Semiconductor device and power conversion apparatus

Abstract

A semiconductor device 1 comprises: a collector layer 5; a drift layer 4 stacked on the collector layer 5; a base layer 32 stacked on the drift layer 4; first gates 21 arranged side by side on the drift layer 4 in the gate length direction; and second gates 22 which are arranged side by side with some of the first gates 21 and which can be driven independently of the first gates 21. The semiconductor device is partitioned into a first region Hc and a third region Ts where the first gates 21 are disposed, and a second region Hs where the first gates 21 and the second gates 22 are disposed. The semiconductor device is disposed such that the third region Ts is disposed between the first region Hc and the second region Hs in the gate length direction. In the collector layer 5, the carrier concentration in the second region Hs and the third region Ts is lower than the carrier concentration in the first region Hc.

Description

Semiconductor device and power conversion device

[0001] The present invention relates to a semiconductor device and a power conversion device including the same.

[0002] The global trend toward a decarbonized society is driving robust growth in the mobility sector, including electric vehicles (EVs) and railways, and the power grid. These applications utilize power conversion devices that convert DC power supplied from a DC power source into AC power to control loads such as electric motors. To achieve compactness and high efficiency in power conversion devices, their key components, semiconductor switching elements, are required to reduce losses (reduction of conduction loss and switching loss). To achieve this, insulated gate bipolar transistors (IGBTs), which are capable of switching large currents at high speed, are widely used as semiconductor switching elements. Furthermore, to ensure the reliability of power conversion devices, semiconductor switching elements must be able to interrupt large currents without breaking down, i.e., must ensure the maximum current that can be successfully interrupted during turn-off switching (i.e., turn-off interruption capability).

[0003] As a technique for reducing conduction loss and switching loss (turn-off loss) of an IGBT, a technique related to a dual-gate IGBT is disclosed in Patent Document 1. Furthermore, a technique for increasing the breakdown resistance of a dual-gate IGBT is disclosed in Patent Document 2.

[0004] A dual-gate IGBT has a circuit structure shown in Fig. 5. The IGBTs described in Patent Documents 1 and 2 have an active region divided into a region where a first gate and a second gate, which can be driven independently of each other, are arranged, and a region where only the first gate is arranged. When the IGBT is conductive, one region accumulates a lower concentration of carriers than the other region. When transitioning from a conductive state to a non-conductive state, the IGBTs described in Patent Documents 1 and 2 go through a high-conduction period in which a drive voltage is applied to the first and second gates, a low-conduction period in which the first gate is turned off and a drive voltage is applied only to the second gate, and then the second gate is also turned off to enter a non-conductive state. With this configuration, during the low-conduction period, the region where only the first gate is arranged discharges the accumulated carriers that were concentrated during the high-conduction period, while the region where the first and second gates are arranged forms a low-conduction accumulated carrier due to the application of a voltage to the second gate. As a result, when the second gate is turned OFF (turned OFF), electrons and holes are rapidly discharged from the low concentration stored carriers, so that a reverse blocking voltage is rapidly applied to the IGBT and the current is rapidly reduced, thereby achieving low-loss turn-off switching.

[0005] JP 2022-167435 A JP 2023-115995 A

[0006] In the techniques described in Patent Documents 1 and 2, the carrier injection efficiency of the two regions is different, so when accumulated carriers are discharged in one region during a low conduction period, current concentration occurs at the boundary between these two regions, and the effect of improving turn-off interruption capability is not fully realized, leaving room for improvement.

[0007] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a highly reliable semiconductor device that can improve turn-off interruption tolerance without increasing conduction loss and switching loss, and a power conversion device using the same.

[0008] In order to achieve the above object, a semiconductor device of the present invention includes a collector layer, a drift layer stacked on the collector layer, a base layer stacked on the drift layer, first gates arranged in parallel in a gate length direction on the drift layer, and second gates arranged in parallel to a part of the first gates and drivable independently of the first gates, the semiconductor device being partitioned into a first region and a third region in which the first gates are arranged, and a second region in which the first gates and the second gates are arranged, one or more of the first region, the second region, and the third region are arranged so that the third region is arranged between the first region and the second region in the gate length direction, the base layer is provided in each of the first region, the second region, and the third region and is spaced apart from one another, and the collector layer has a carrier concentration in the second region and the third region that is lower than the carrier concentration in the first region.

[0009] According to the present invention, it is possible to realize a highly reliable semiconductor device and power conversion device that can improve turn-off interruption tolerance without increasing conduction loss and switching loss.

[0010] 1 is a diagram showing the overall configuration of an electric motor control system using a power conversion device to which a semiconductor device according to an embodiment of the present invention is applied. It is a plan view of a semiconductor chip constituting the semiconductor device according to an embodiment of the present invention. It is a schematic diagram explaining the structure of a semiconductor device according to an embodiment of the present invention, which is a partial cross-sectional view taken along line A-A in FIG. 2. It is a schematic diagram explaining the arrangement of an emitter layer of a semiconductor device according to an embodiment of the present invention, which is a partially enlarged view of FIG. 2. It is a circuit diagram of a semiconductor device and its drive device according to an embodiment of the present invention. It is a time chart of a drive signal of a semiconductor device according to an embodiment of the present invention. It is a diagram conceptually showing carrier distribution in a high conduction period of the semiconductor device shown in FIG. 3. It is a diagram conceptually showing carrier distribution in a low conduction period of the semiconductor device shown in FIG. 3. It is a diagram conceptually showing carrier distribution in a low conduction period of a conventional semiconductor device. It is a graph showing the relationship between the turn-off loss of an IGBT and the ratio of the length of a third region to the thickness of the drift layer of the IGBT, obtained by semiconductor device simulation. It is a graph showing the relationship between the length of the third region of an IGBT and the thickness of the drift layer, based on the simulation results shown in FIG. 9. It is a schematic diagram explaining the structure of a semiconductor device according to a modification of an embodiment of the present invention, which is a partial cross-sectional view taken along line A-A in FIG. 2. It is a schematic diagram explaining the structure of a semiconductor device according to a modification of an embodiment of the present invention, which is a partial cross-sectional view taken along line A-A in FIG. FIG. 10 is a plan view of a semiconductor chip constituting a semiconductor device according to a modified example of the embodiment of the present invention.

[0011] Hereinafter, embodiments of the present invention (hereinafter referred to as "embodiments") will be described with reference to the accompanying drawings. Elements of the same or similar structure will be designated by the same reference numerals, and descriptions thereof will be omitted where appropriate.

[0012] [Power Conversion Device] Fig. 1 is a diagram showing the overall configuration of an electric motor control system 100 using a power conversion device according to an embodiment of the present invention. The power conversion device is a device that converts electric power using power semiconductor devices. In this embodiment, an electric motor control system 100 using an inverter circuit that applies IGBTs as the power semiconductor devices will be described as an example. The electric motor control system 100 is a control system for an inductive load using a three-phase inverter, and includes a direct current power source DC, an inverter circuit 90, and an electric motor M as the inductive load.

[0013] The inverter circuit 90 includes a smoothing capacitor 91, inverter units 9 for three phases, UVW (U-phase inverter unit 9U, V-phase inverter unit 9V, and W-phase inverter unit 9W), and a command logic unit 96. The inverter circuit 90 outputs AC power based on DC power supplied from a DC power supply to drive the electric motor M. The smoothing capacitor 91 is provided between the DC power supply DC (power supply voltage = Vcc) and the positive electrode connecting wire 93 and negative electrode connecting wire 94 of the inverter circuit 90.

[0014] The inverter unit 9 is composed of upper and lower arms, and has a series circuit of semiconductor devices 1. The semiconductor devices 1 of each of the upper and lower arms constitute the semiconductor switching elements of that arm. In this example, the semiconductor devices 1 are composed of IGBTs. A gate signal is transmitted to the IGBTs from a gate drive device 80. The high-potential terminal of the IGBT of the upper arm is connected to a first end (positive electrode connection line 93) of a smoothing capacitor 91. The low-potential terminal of the IGBT of the upper arm is connected to a high-potential terminal of the IGBT of the lower arm. The low-voltage terminal of the IGBT of the lower arm is connected to a second end (negative electrode connection line 94) of the smoothing capacitor 91.

[0015] In each phase, a connection point 95 between the low potential side terminal of the IGBT in the upper arm and the high potential side terminal of the IGBT in the lower arm is connected to one end of a winding of the motor M. The other end of the winding of each phase is connected to a neutral point. The motor M is, for example, an induction motor.

[0016] Each IGBT is connected in anti-parallel to a freewheeling diode 92. As the freewheeling diode 92, various diodes can be used, such as a pn junction diode, a Schottky barrier diode, or a diode that uses both a pn junction and a Schottky junction.

[0017] The command logic unit 96 outputs an ON command instructing an ON state or an OFF command instructing an OFF state to the gate drive device 80 as a drive command signal P for the semiconductor device 1. As a result, the command logic unit 96 alternately turns on the semiconductor device 1 of the upper arm and the semiconductor device 1 of the lower arm in each phase to control the control variable of the electric motor M to the command value. The control variable is, for example, the torque of the electric motor.

[0018] The gate drive device 80 is provided for each semiconductor device 1, acquires a drive command signal P from the command logic unit 96, and turns the semiconductor device 1 on or off based on the acquired drive command signal P.

[0019] [Semiconductor Device] Fig. 2 is a plan view of a semiconductor chip constituting the semiconductor device 1 according to an embodiment of the present invention. Fig. 2 shows a semiconductor chip constituting the semiconductor device of the lower arm of the U-phase in the inverter circuit 90 shown in Fig. 1. The other semiconductor devices of the upper arm of the U-phase and the upper and lower arms of the V-phase and W-phase have the same configuration. The semiconductor device 1 may be in the form of a power module (IGBT module) in which a plurality of semiconductor (IGBT) chips as shown in Fig. 2 are mounted in parallel. Each element of the semiconductor chip will be described in detail below.

[0020] The semiconductor device (semiconductor chip) 1 is composed of an inactive region including a termination region (also called a guard ring) Ter arranged around the periphery of the chip for electric field relaxation, and an active region inside the termination region Ter. The active region of the semiconductor device 1 is further divided into a first region Hc, a third region Ts, and a second region Hs in the longitudinal direction of the planar view of the chip. The inactive region is a region through which no current flows, and includes the termination region Ter as well as gate finger regions in which gate wirings 71 and 72 that supply power to gate electrodes 21 and 22 are disposed, and pad regions for the gate wirings 71 and 72. The active region is a region through which current flows, for example, a region in which an electrode 73 (see FIG. 3, not shown in FIG. 2) connected to an emitter layer 33 is formed. The first region Hc is a high-conductivity region, i.e., a region capable of accumulating a high concentration of carriers when the semiconductor device 1 is conductive. The second region Hs is a low-conductivity region that can accumulate a lower concentration of carriers than the first region Hc when the semiconductor device 1 is conductive. The third region Ts is a boundary region sandwiched between the first region Hc and the second region Hs, and can accumulate carriers at a concentration equivalent to that of the second region Hs when the semiconductor device 1 is conductive.

[0021] In the first region Hc and the third region Ts, first gate electrodes 21 extending across the entire width of the region in the gate width direction are arranged side by side in the gate length direction (horizontal direction in FIG. 2 ). In the second region Hs, first gate electrodes 21 and second gate electrodes 22 extending in the same manner as above are arranged side by side in two rows. In other words, the first gate electrodes 21 are arranged side by side across the entire active region, but in the second region Hs they are spaced apart more widely than in the regions Hc and Ts, and in the second region Hs, the second gate electrodes 22 are arranged side by side with each first gate electrode 21.

[0022] 3 is a partial cross-sectional view taken along line A-A in FIG. 2, and specifically shows the third region Ts and the first region Hc and second region Hs in the vicinity of both sides thereof. In FIG. 3 and subsequent cross-sectional views, the p-type semiconductor layer is denoted by "p" and "p + " or "p - " and "n" and "n + " or "n -" is added. In order of increasing carrier concentration, "p + ", "p", "p - " and "n + ", "n", "n - " is expressed as ".

[0023] The semiconductor device 1 is a dual-gate trench gate IGBT. - On one main surface side (upper side in FIG. 3) of the n-type semiconductor substrate, a p-well layer including a floating layer 31 and a base layer 32, as well as a first gate electrode 21 and a second gate electrode 22 that can be controlled independently of each other, are formed. - On one main surface of the n-type semiconductor substrate + An emitter layer 33 is formed of a p-type semiconductor layer. A gate oxide film 61 is formed inside the drift layer 4 in contact with the base layer 32 and the emitter layer 33. Gate electrodes 21 and 22 are provided inside the drift layer 4 via the gate oxide film 61 and are insulated from an emitter electrode 73 by an interlayer insulating film 62. The emitter electrode 73 is formed on one main surface side of the drift layer 4 in contact with the p-well layer in the region with the narrower gate spacing, i.e., the base layer 32 and the emitter layer 33. The p-well layer in the region with the wider gate spacing, i.e., the floating layer 31, is insulated from the emitter electrode 73 by the interlayer insulating film 62. A collector layer 5 made of a p-type semiconductor layer is formed on the other main surface side of the drift layer 4 (the lower side in FIG. 3 ). - 3, the semiconductor device 1 includes, in order from the bottom (back side) in FIG. 3, a collector electrode 74, a collector layer 5, a drift layer 4, and a well layer including a floating layer 31 and a base layer 32 stacked thereon, gate electrodes 21 and 22 embedded between the floating layer 31 and the base layer 32 and covered with a gate oxide film 61, an emitter layer 33 stacked on a partial region on the base layer 32, an emitter electrode 73 commonly connected to all of the emitter layers 33 and the base layer 32, and gate wirings 71 and 72 (see FIG. 2) connected to the gate electrodes 21 and 22, respectively.

[0024] The collector layer 5 and the drift layer 4 are provided throughout the entire semiconductor device 1, including the inactive region. The drift layer 4 is made of an n-type semiconductor layer. The collector layer 5 is made of a p-type semiconductor layer. The collector layer 5 is a hole injection layer that injects holes into the drift layer 4 when the semiconductor device 1 is conductive. The collector layer 5 further includes a high-concentration carrier layer 51 in the first region Hc and a low-concentration carrier layer 52 in the second region Hs and the third region Ts, the low-concentration carrier layer 52 having a lower carrier concentration than the high-concentration carrier layer 51. As shown in FIG. 2 , the semiconductor device 1 includes the high-concentration carrier layer 51 in the first region Hc and the low-concentration carrier layer 52 in other regions, including the inactive region. When the semiconductor device 1 is conductive, holes are injected from the collector layer 5 into the drift layer 4, but the high-concentration carrier layer 51 and the low-concentration carrier layer 52 are formed so that the amount of holes injected from the low-concentration carrier layer 52 is sufficiently smaller than that of the high-concentration carrier layer 51. For example, the concentration ratio of p-type impurities in the high-concentration carrier layer 51 and the low-concentration carrier layer 52 is about 10:1 to 100:1. - After irradiating the entire rear surface of the semiconductor substrate with a low concentration of p-type impurities, a mask is provided that leaves open the region (first region Hc) to be the high-concentration carrier layer 51, and then the high-concentration p-type impurities are irradiated.

[0025] The first gate electrode 21 is a carrier control gate and extends in the gate width direction across the entire width of the active region in each of the regions Hc, Hs, and Ts, with one end connected to a contact 71c (FIG. 4) of the first gate wiring 71. The second gate electrode 22 is a switching gate and extends in the gate width direction in the second region Hs, similar to the first gate electrode 21, with one end connected to a contact (not shown) of the second gate wiring 72. Therefore, the first gate electrode 21 and the second gate electrode 22 can be controlled independently of each other. The side and bottom surfaces of the gate electrodes 21 and 22 are covered with a gate oxide film 61, and their top surfaces, excluding the connection portions with the contacts of the gate wirings 71 and 72, are covered with an interlayer insulating film 62. The first gate electrode 21, together with the gate oxide film 61, the adjacent emitter layer 33, and the power supply layer of the adjacent base layer 32, with the gate oxide film 61 interposed therebetween, constitute the first switching element 11. The second gate electrode 22 constitutes the second switching element 12 together with the gate oxide film 61 , the emitter layer 33 adjacent thereto with the gate oxide film 61 interposed therebetween, and the power supply layer of the base layer 32 adjacent thereto.

[0026] The floating layer 31 and the base layer 32 are made of p-type well layers. The base layers 32 are arranged separately from each other in each of the regions Hc, Hs, and Ts. In the first region Hc and the third region Ts, the base layer 32 is sandwiched between the first gate electrodes 21, 21 on both sides, and in the second region Hs, it is sandwiched between the first gate electrode 21 and the second gate electrode 22. An emitter layer 33 is stacked on a portion of the base layer 32, and the portion of the base layer 32 that is sandwiched between the emitter layers 33 from the sides and does not have the emitter layer serves as a power supply layer, connecting the base layer 32 and the emitter layer 33 to the emitter electrode 73. The floating layers 31 and the base layers 32 are arranged alternately, with the first gate electrode 21 or the second gate electrode 22 sandwiched between them, and their upper surfaces are covered with an interlayer insulating film 62.

[0027] The emitter layer 33 is a high-concentration n-type semiconductor layer. The emitter layer 33 is a region that injects electrons into the drift layer 4 when the semiconductor device 1 is conductive. The emitter layer 33 is layered so as to be embedded in a portion of the base layer 32. Specifically, the emitter layer 33 is provided separated from the base layer 32 by a power supply layer in the center of the gate length direction, and is adjacent to the first gate electrode 21 or the second gate electrode 22 on both sides of the base layer 32, respectively, via a gate oxide film 61. The emitter layer 33 may be provided continuously in the gate width direction along the gate electrodes 21 and 22, or may be arranged intermittently as shown in FIG. 4. Specifically, the emitter layer 33 is regularly arranged in the gate width direction with a length w1 and a period a1 (gap (a1-w1)). If the length per period (intermittency ratio) (w1 / a1) of the emitter layer 33 is small, the saturation current of the IGBT decreases, resulting in an increase in on-state voltage. Conversely, a large interruption ratio (w1 / a1) of the emitter layers 33 increases the saturation current of the IGBT, resulting in a decrease in short-circuit resistance. Therefore, it is desirable to design the ratio appropriately. Furthermore, the interruption ratio of the emitter layers 33 in the third region Ts is preferably equal to or greater than those in the regions Hc and Hs. In FIG. 4 , the emitter layers 33 are arranged in the third region Ts with a length w2 and a period a2. For example, by designing w1 = w2 and a1 > a2, the emitter layers 33 in the third region Ts are arranged at a relatively high density. This configuration promotes electron injection into the drift layer 4 in the third region Ts when the semiconductor device 1 is conductive, thereby reducing the on-voltage of the IGBT.

[0028] The collector electrode 74 is provided over the entire back surface of the semiconductor device 1 and is in contact with the collector layer 5. The emitter electrode 73 is provided over the entire active region on the front surface of the semiconductor device 1 and is in contact with the power supply layers of all of the emitter layers 33 and all of the base layers 32. The collector electrode 74 and the emitter electrode 73 form a pair of electrodes and supply current to the semiconductor device 1, with the collector electrode 74 being positive. The first gate wiring 71 and the second gate wiring 72 are disposed in the inactive region on the front surface of the semiconductor device 1, extend in the gate length direction, and have pads formed at one end for connection to the outside. The first gate wiring 71 is connected to one end of each of the first gate electrodes 21. The second gate wiring 72 is connected to one end of each of the second gate electrodes 22.

[0029] The semiconductor chips constituting the semiconductor device 1 include n - A p-well layer including a floating layer 31 and a base layer 32 is formed on one main surface side (upper side in FIG. 3) of the n-type semiconductor substrate (drift layer 4). - On one main surface of the n-type semiconductor substrate + An emitter layer 33 is formed of a p-type semiconductor layer. A gate oxide film 61 is formed inside the drift layer 4 in contact with the base layer 32 and the emitter layer 33. Gate electrodes 21 and 22 are provided inside the drift layer 4 via the gate oxide film 61, and are insulated from an emitter electrode 73 by an interlayer insulating film 62. The emitter electrode 73 is formed on one main surface side of the drift layer 4 in contact with the p-well layer in the region with the narrower gate spacing, i.e., the base layer 32 and the emitter layer 33. The p-well layer in the region with the wider gate spacing, i.e., the floating layer 31, is insulated from the emitter electrode 73 by the interlayer insulating film 62.

[0030] Here, a region including one base layer 32 and two rows of first gate electrodes 21 on both sides thereof (the first gate electrodes 21 and the second gate electrodes 22 in the second region Hs) is called a unit cell, and the pitch L c The semiconductor device 1 has unit cells arranged in the active region at a constant pitch L cIn the second region Hs, the unit cells are arranged side by side, inverted one by one, so that the first gate electrodes 21, 21 and the second gate electrodes 22, 22 face each other with the floating layer 31 interposed therebetween. The first gate electrode 21 is preferably disposed at the end of the second region Hs on the third region Ts side.

[0031] In the semiconductor device 1, the third region Ts is shorter in the gate length direction than the first region Hc and the second region Hs, and the number of first gate electrodes 21 arranged therein is smaller than both the number (number of columns) of first gate electrodes 21 in the first region Hc and the total number of gate electrodes 21, 22 in the second region Hs. The third region Ts includes at least one base layer 32 and two columns of first gate electrodes 21 on both sides of the base layer 32. As shown in FIG. 3, the third region Ts preferably includes two base layers 32 sandwiching a floating layer 31 in the gate length direction and a total of four columns of first gate electrodes 21 on both sides of each base layer 32. That is, the length Δ of the third region Ts in the gate length direction is equal to the cell length L. c or the cell length L c The length Δ of the third region Ts in the gate length direction is twice the cell length L c The length Δ' is twice as long as L, which is sufficient to further improve the turn-off interruption capability. Furthermore, as described above, by arranging the first gate electrode 21 at the end of the second region Hs on the third region Ts side, the region of the second region Hs where the first gate electrode 21 is arranged has the same structure as the third region Ts, so it can be said that the third region Ts is expanded. The expanded length Δ' is L c On the other hand, even if the third region Ts has three or more base layers 32 and the length Δ is further increased (Δ≧3L c ), it is difficult to further improve the effect, and if it is longer, the conduction loss (on-state voltage) increases. Details of the preferred range of the length Δ of the third region Ts in the gate length direction will be described later.

[0032] In the semiconductor device 1, the area ratio between the first region Hc and the second region Hs, and the relationship between the number of first gate electrodes 21 in the first region Hc and the total number of gate electrodes 21 and 22 in the second region Hs are not particularly defined. The planar shape of the semiconductor device 1 and the number of gate electrodes 21 and 22 arranged in each of the regions Hc, Hs, and Ts shown in FIG. 2 are merely examples. Because the first region Hc has a larger area and a larger number of gate columns than the second region Hs, the high-concentration carrier layer 51 in the collector layer 5 has a larger area than the low-concentration carrier layer 52, effectively reducing conduction loss (IGBT on-voltage). This configuration is suitable for power conversion devices for power grid applications, which have a relatively low switching frequency and a high rate of conduction loss. Conversely, since the second region Hs has a larger area and a larger number of gate columns than the first region Hc, the area of ​​the low-concentration carrier layer 52 is larger than that of the high-concentration carrier layer 51, and as a result of this, the number of stored carriers is reduced, and switching loss (turn-off loss of the IGBT) can be effectively reduced. This configuration is suitable for power conversion devices for mobility applications such as railways and EVs, which have a relatively high switching frequency and a relatively high proportion of switching loss.

[0033] (Operation of the Semiconductor Device) The operation of the semiconductor device according to this embodiment will be described. FIG. 5 is a circuit diagram of the semiconductor device 1 and its drive device. FIG. 6 is a time chart of the drive signals of the semiconductor device. The semiconductor device 1 operates with low loss due to drive signals from gate drivers 81 and 82 that drive the first gate electrode 21 and the second gate electrode 22, respectively. The period before time t2 (t≦t2) is the conduction period of the IGBT, and the period after time t2 (t≧t2) is the non-conduction period. The conduction period is divided into a high conduction period (t≦t1) before time t1 and a low conduction period (t1≦t≦t2) before transitioning to the non-conduction period. The low conduction period is called the switching preparation period t pre_off It is also called (= t2 - t1).

[0034] During the high conduction period, a voltage V th equal to or higher than the threshold voltage V th that forms an inversion layer in the base layer 32 of the semiconductor device 1 is applied to the first gate electrode 21 and the second gate electrode 22 . Gc , V Gs1 is applied to the gate electrodes 21 and 22 of the semiconductor device 1 via the gate wirings 71 and 72. A voltage V th equal to or higher than the threshold voltage Vth of the semiconductor device 1 is supplied to the collector electrode 74 (FIG. 3) of the semiconductor device 1. A positive voltage is applied to the emitter electrode 73 of the semiconductor device 1. FIG. 7A conceptually shows the carrier distribution in the high conduction period of the semiconductor device 1. When a positive voltage is applied to the collector electrode 74 (FIG. 3) of the semiconductor device 1 with respect to the emitter electrode 73, power is supplied from the gate driver 80 of FIG. 1 to the gate electrodes 21 and 22 of the semiconductor device 1 via the gate wirings 71 and 72. Gc , V Gs When a voltage Vcc is applied between the first gate electrode 21 and the emitter electrode 73 and between the second gate electrode 22 and the emitter electrode 73, the semiconductor surface of the base layer 32 in contact with the gate oxide film 61 is strongly inverted, increasing the electron carrier concentration and forming an n-type inversion layer. This connects the emitter layer 33 and the drift layer 4 via the n-type inversion layer, and electron carriers are injected from the emitter layer 33 into the drift layer 4. Electrons are injected from the emitter electrode 73 into the drift layer 4 via the emitter layer 33 and the electron channel, and holes are injected from the collector layer 5, causing conductivity modulation. The resistance of the drift layer 4 is reduced by the large number of stored carriers, and the semiconductor device 1 becomes conductive. In particular, in the first region Hc, holes are injected at a high concentration from the high-concentration carrier layer 51, increasing the concentration of stored carriers. On the other hand, in the regions Hs and Ts where the low-concentration carrier layer 52 is provided, the stored carrier concentration is sufficiently lower than that of the first region Hc.

[0035] At time t1, only the first gate electrode 21 is turned off and biased to a voltage lower than the threshold voltage (Vth), while the second gate electrode 22 remains on. Fig. 7B conceptually shows the carrier distribution in the low conduction period (switching preparation period) of the semiconductor device 1.

[0036] Switching preparation period t pre_offis the period from when the first gate electrode 21 is turned off to when the second gate electrode 22 is turned off. Because the first gate electrode 21 is turned off, an n-type inversion layer is not formed in the first region Hc and the third region Ts, and injection of electrons from the emitter electrode 73 into the drift layer 4 stops. As a result, the accumulated holes are discharged to the emitter electrode 73 via the base layer 32, and the accumulated holes and electrons are annihilated by recombination, resulting in a decrease in the accumulated carrier concentration. On the other hand, in the second region Hs, only the second gate electrode 22 is in the on state, and the accumulated carrier concentration, which was low during the high conduction period as described above, becomes even lower.

[0037] At time t2, the second gate electrode 22 is also turned off and biased to a voltage lower than the threshold voltage (Vth). This causes the semiconductor device 1 to transition to a turn-off operation. pre_off Therefore, the concentration of accumulated carriers in the first region Hc and the third region Ts, particularly in the first region Hc, is sufficiently low, and the concentration of accumulated carriers in the second region Hs is sufficiently low. Therefore, the rate of depletion of the drift layer 4 at turn-off, i.e., the rate of increase in the collector voltage (dV / dt), becomes high, and the tail current at turn-off of the semiconductor device 1 is reduced, resulting in a reduction in switching loss (turn-off loss).

[0038] Here, a conventional semiconductor device (IGBT) without a third region Ts and in which the first region Hc and the second region Hs are adjacent will be compared with the semiconductor device of the present invention. Figure 8 conceptually illustrates the carrier distribution during the low conduction period of the conventional semiconductor device. During the low conduction period, in the first region Hc and the adjacent second region Hs where the first gate electrode 21 is provided, holes are not injected from the collector layer 5, as in the present invention ( Figure 7B ). Carriers accumulated during conduction are annihilated by hole-electron recombination and reduced over a period equivalent to the carrier lifetime. However, in the second region Hs where the second gate electrode 22 is provided, electrons are injected from the emitter layer 33 into the drift layer 4, as in the high conduction period. Furthermore, a certain amount of holes continues to be injected from the collector layer 5, particularly from the high-concentration carrier layer 51 near the second region Hs. As a result, the accumulated carriers remain insufficiently reduced, particularly in the region 4b near the boundary between the first region Hc and the second region Hs. The accumulated carriers remaining in the region 4b near the boundary cause an increase in the tail current when the IGBT is turned off, resulting in an increase in switching loss (turn-off loss).

[0039] The semiconductor device 1 according to this embodiment is pre_off 7B , some of the holes remaining at a high concentration in the first region Hc may migrate and accumulate in a region 4b near the boundary between the second region Hs and the third region Ts due to electron carriers injected from the emitter layer 33 into the drift layer 4 by the second gate electrode 22, which is continuously on in the second region Hs. However, because the third region Ts provides a sufficient distance from the first region Hc to the second gate electrode 22 closest to the second region Hs, the number of carriers accumulating in region 4b is sufficiently small. Furthermore, in the third region Ts adjacent to the second region Hs, the accumulated carriers during the high conduction period are sufficiently low, so the number of carriers accumulating in region 4b is also sufficiently small. As a result, the tail current generated by the accumulated carriers in region 4b during turn-off is sufficiently small, preventing an increase in switching loss (turn-off loss).

[0040] Furthermore, the semiconductor device 1 includes an emitter layer 33 in the third region Ts, similar to the regions Hc and Hs. During conduction, electrons are injected from the emitter layer 33 into the drift layer 4 in the third region Ts via the electron channel. Therefore, holes are injected from the high-concentration carrier layer 51 in the adjacent first region Hc, causing conductivity modulation, and the large number of accumulated carriers reduces the resistance of the drift layer 4. As a result, conduction loss (on-state voltage) is reduced compared to a structure in which the emitter layer 33 is not provided in the third region Ts, in other words, a distance is provided between the first region Hc and the second region Hs only by the floating layer 31 or the like.

[0041] As described above, the semiconductor device according to this embodiment has the collector layer 5 as the low-concentration carrier layer 52, and the third region Ts having the first gate electrode 21 and the emitter layer 33 is provided between the first region Hc and the second region Hs, thereby improving the turn-off interruption capability without increasing the conduction loss and the switching loss.

[0042] The appropriate length of the third region Ts will be explained. If the third region Ts is sufficiently long and the distance from the first region Hc to the second region Hs is sufficiently long, the effect of improving the turn-off interruption capability is high. However, if the third region Ts with a low carrier concentration is long and occupies a large proportion of the chip, the conduction loss (on-state voltage) increases. Figure 9 shows the turn-off loss E of an IGBT by semiconductor device simulation. off 10 is a graph showing an example of the relationship between the ratio of the length Δ of the third region to the thickness D of the drift layer of the IGBT and the turn-off loss E generated in the entire chip (active region: first region Hc, second region Hs, and third region Ts). off Turn-off loss E occurring in the third region Ts off The vertical axis represents the ratio of the turn-off loss (Ts). Figure 9 shows the dependency of the ratio of the turn-off loss occurring in the third region Ts on the ratio (Δ / D) of the length Δ of the third region to the thickness D of the drift layer. In the simulation, a driver with the following drift layer thickness D and resistivity ρ was used, and the length Δ of the third region was changed. In addition, in this simulation, the turn-off loss E off The following switching preparation period t pre_off6.5 kV device: D = 630 μm, ρ = 550 Ωcm, t pre_off =70μs 3.3kV device: D=350μm, ρ=250Ωcm, t pre_off =30μs 1.2kV device: D=120μm, ρ=55Ωcm, t pre_off = 10 μs

[0043] As shown in FIG. 9, regardless of the rated voltage of the IGBT, the larger Δ / D is, the more the switching loss (turn-off loss) can be suppressed. This is because the switching preparation period t pre_off In this case, the larger Δ / D becomes, the more the accumulated carriers remaining near the boundary between the first region Hc and the second region Hs are suppressed by ensuring a distance between the first region Hc and the second region Hs, preventing an increase in the tail current when the IGBT is turned off, and as a result, reducing the turn-off loss that occurs in the third region.

[0044] From the results shown in FIG. 9, it is possible to determine the minimum value (Δ) of the length Δ of the third region Ts required to suppress the ratio of turn-off loss occurring in the third region Ts to that occurring in the entire active region to 5% or less. min ) and the thickness D of the drift layer. The relational expression can be expressed by the following equation (1'). a, b, and c in equation (1) are constants determined by device design. Equation (1') can be expressed by the graph shown in FIG. 10. (a, b, c are constants. 0<c≦1)

[0045] The rated breakdown voltage of an IGBT is determined by the drift layer thickness D and the resistivity ρ of the drift layer, and can be expressed by substituting D on the right side of equation (1') for equation (2') below. Equation (2') can be expressed by substituting ρ for the horizontal axis of the graph shown in FIG. (a, b, c are constants. 0<c≦1)

[0046] The formulas (1') and (2') can be expressed as the following formulas (1) and (2), respectively. (a, b, c are constants. 0<c≦1)

[0047] A long third region Ts increases the conduction loss (on-state voltage) in the semiconductor device 1. To suppress this, an upper limit value of Δ / D was obtained by semiconductor device simulation, and it was found that the length Δ of the third region Ts in the gate length direction is preferably three times or less the thickness D of the drift layer 4, as expressed by the following formula (3):

[0048] By appropriately changing the length Δ of the third region Ts depending on the thickness D or resistivity ρ of the drift layer 4, it is possible to universally improve the turn-off interruption capability while suppressing an increase in switching loss, regardless of the rated withstand voltage of the IGBT.

[0049] (Modification) In the semiconductor device 1, the collector layer 5 including the high-concentration carrier layer 51 and the low-concentration carrier layer 52 can be configured as follows. As shown in FIG. 11 , the semiconductor device 1 can have the low-concentration carrier layer 52 formed by alternately and intermittently arranging the high-concentration carrier layer 51 and the low-concentration carrier layer 52a. In this modification, the low-concentration carrier layer 52 has a locally formed region with a high carrier concentration, thereby reducing the back surface electric field during a short circuit in the semiconductor device 1, relatively improving the short-circuit resistance, and improving reliability. As in the above embodiment, such a collector layer 5 can have an n - The low-concentration carrier layer 52 can be formed by irradiating the entire back surface of the semiconductor substrate with low-concentration p-type impurities, then providing a mask with a large number of holes in the region to be the high-concentration carrier layer 51 and irradiating the mask with high-concentration p-type impurities. The arrangement pattern of the alternating high-concentration carrier layers 51 in the low-concentration carrier layer 52 is not particularly specified, and may be formed, for example, using a mesh-shaped mask, or may be a stripe-like arrangement arranged intermittently only in one dimension. Furthermore, the length (diameter) of each of the alternating high-concentration carrier layers 51 in the low-concentration carrier layer 52 is preferably in the range of 0.01 to 1 times the thickness D of the drift layer 4. A sufficiently long length of each of the alternating high-concentration carrier layers 51 can reduce the on-voltage, while an excessively long length reduces the effect of improving the turn-off interruption capability.

[0050] The semiconductor device 1 may selectively suppress the carrier lifetime in a specific region. In this case, it is preferable to suppress the carrier lifetime in the third region Ts. With this configuration, the switching preparation period t pre_off In this case, the number of accumulated carriers remaining near the boundaries of the third region Ts with the first region Hc and the second region Hs is effectively reduced. As a result, current concentration at the boundary during turn-off is suppressed, and local heat generation in the boundary is suppressed, so that the turn-off interruption capability can be more effectively improved. Such a semiconductor device 1 has n - A light ion or electron beam is irradiated from the rear or front surface of the semiconductor substrate through an absorber having a third region Ts opened, to form crystal defects in the drift layer 4 to form a carrier lifetime killer layer 41 .

[0051] The semiconductor device 1 may suppress the carrier lifetime in part or all of the second region Hs as well as the third region Ts. Specifically, this is the region in the second region Hs where the second gate electrode 22 is formed, or the entire second region Hs. With this configuration, the switching preparation period t pre_off In this case, since the accumulated carriers remaining in not only the third region Ts but also the second region Hs can be suppressed, the turn-off loss can be suppressed more effectively. pre_off In this case, the lifetime of only the portion of the second gate electrode 22, which is a factor in increasing the turn-off loss due to electron injection, is selectively suppressed (=switching preparation period t pre_off By doing so, the turn-off loss can be more effectively suppressed while preventing an increase in on-state voltage, which is a detrimental effect caused by reducing the lifetime of the portion of the first gate electrode 21, while also preventing the portion of the first gate electrode 21 into which electrons are not injected from reducing its lifetime.

[0052] As shown in FIG. 13 , the semiconductor device 1 may have two or more regions Hc, Hs, and Ts, with the third region Ts located between the first region Hc and the second region Hs. In particular, by separating the first region Hc into two or more locations on the chip, the temperature within the chip can be uniformized. When the semiconductor device 1 is conductive, holes injected from the collector layer 5 are particularly abundant from the high-concentration carrier layer 51, so the first region Hc is the primary heat source of the semiconductor device 1. Furthermore, to improve turn-off interruption capability, it is preferable to locate the first region Hc closer to the periphery of the chip than the second region Hs. For example, the order of the first region Hc, the third region Ts, the second region Hs, the third region Ts, the first region Hc, the third region Ts, the second region Hs, the third region Ts, the first region Hc, the third region Ts, the second region Hs, the third region Ts, the first region Hc, the first region Hc, the first region Hc, the first region Hc, the first region Hc, the first region Hs ...

[0053] The present invention is not limited to the above-described embodiments, and includes other modifications and applications as long as they do not deviate from the gist of the present invention as set forth in the claims. For example, the above-described embodiments have been described in detail to facilitate understanding of the present invention, and the present invention is not necessarily limited to those including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another example, or to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is possible to add, delete, or replace part of the configuration of each embodiment with other configurations.

[0054] REFERENCE SIGNS LIST 100 Electric motor control system 1 Semiconductor device 21 First gate electrode (first gate) 22 Second gate electrode (second gate) 32 Base layer 33 Emitter layer 4 Drift layer 41 Carrier lifetime killer layer 5 Collector layer 51 High concentration carrier layer 52 Low concentration carrier layer Hc First region Hs Second region Ts Third region

Claims

1. A semiconductor device comprising a collector layer, a drift layer stacked on the collector layer, a base layer stacked on the drift layer, first gates arranged in parallel in the gate length direction on the drift layer, and second gates arranged in parallel to some of the first gates and drivable independently of the first gates, wherein the semiconductor device is partitioned into a first region and a third region in which the first gates are arranged, and a second region in which the first gates and the second gates are arranged, and one or more of each of the first region, the second region, and the third region are arranged so that the third region is arranged between the first region and the second region in the gate length direction; the base layer is provided in each of the first region, the second region, and the third region, and is spaced apart from one another; and the carrier concentration in the collector layer in the second region and the third region is lower than the carrier concentration in the first region.

2. The semiconductor device according to claim 1, wherein the first region, the third region, the second region, the third region, and the first region are repeated in this order in the gate length direction.

3. The semiconductor device according to claim 1 or 2, further comprising an emitter layer stacked on the base layer and adjacent to the first gate or the second gate with a gate oxide film interposed therebetween, wherein the emitter layer is provided intermittently at a predetermined period in a direction perpendicular to the gate length direction in a plan view, and the ratio of the length of the emitter layer to the period is such that the first region and the second region are equal to or shorter than the third region.

4. The semiconductor device according to claim 1 or 2, wherein, of the first gate and the second gate in the second region, the first gate is arranged closest to the third region.

5. The semiconductor device according to claim 1 or 2, characterized in that the length of said third region in the gate length direction depends on at least one of the thickness and resistivity of said drift layer.

6. The semiconductor device according to claim 5, wherein the length Δ of the third region in the gate length direction satisfies formula (1) in which the thickness D of the drift layer is a variable, or formula (2) in which the thickness D of the drift layer and resistivity ρ are variables. (a, b, c are constants. 0<c≦1) 7. The semiconductor device according to claim 5, wherein the length of said third region in the gate length direction is three times or less the thickness of said drift layer.

8. A semiconductor device according to claim 1 or 2, characterized in that the third region, or further in at least the region of the second region where the second gate is provided, has a carrier lifetime killer layer in the drift layer.

9. A semiconductor device according to claim 1 or 2, characterized in that the collector layer in the second region and the third region is formed by two regions with different carrier concentrations arranged alternately and repeatedly.

10. A power conversion device comprising the semiconductor device according to claim 1 or 2.

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