Light detection device and electronic apparatus

Abstract

To enable miniaturization of a pixel without increasing a chip area. A light detection device includes a first substrate having a pixel array region in which light receiving elements are two-dimensionally disposed in a matrix and a second substrate having a pixel array lower region corresponding to the pixel array region, the first substrate and the second substrate being stacked, in which the pixel array lower region is configured with a plurality of unit regions being disposed in a row direction or a column direction, each unit region including one or more pixels, and includes one or more pixel readout circuits in which a circuit arrangement is common in the respective unit regions, and a first logic circuit in which a circuit is disposed across the unit regions. The technology of the present disclosure can be applied to, for example, a distance measuring device or the like that measures a distance to an object to be measured.

Description

LIGHT DETECTION DEVICE AND ELECTRONIC APPARATUS

[0001] The present disclosure relates to a light detection device and an electronic apparatus, and in particular relates to a light detection device and an electronic apparatus capable of miniaturizing a pixel without enlarging a chip area.

[0002] <CROSS REFERENCE TO RELATED APPLICATIONS> This application claims the benefit of Japanese Priority Patent Application JP 2024-032736 filed on March 5, 2024, the entire contents of which are incorporated herein by reference.

[0003] A direct time-of-flight (ToF) light receiving device is known (see, for example, PTL 1). The direct ToF light receiving device measures the distance to the object to be measured by measuring the time from when the object to be measured is irradiated with light to when the reflected light reflected by the object to be measured is received. The light receiving device includes, for example, a light receiving element such as a single photon avalanche diode (SPAD) that detects photons, a TDC that measures a time until the light receiving element detects light and reacts, and a histogram generation unit that generates a histogram based on the measured time. For example, the TDC and the histogram generation unit may be disposed in each pixel in the pixel array (for example, see PTL 2) or may be disposed outside the pixel array.

[0004] JP 2021-110697 AJP 2020-504299 W

[0005] In a case where the TDC and the histogram generation unit are disposed in each pixel in the pixel array, a mounting area is increased, and thus, it is difficult to miniaturize the pixel. On the other hand, when the TDC and the histogram generation unit are disposed outside the pixel array, the chip area increases.

[0006] The present disclosure has been made in view of such a situation, and enables miniaturization of pixels without enlarging a chip area.

[0007] A light detection device according to a first aspect of the present disclosure includes a first substrate having a pixel array region in which light receiving elements are two-dimensionally disposed in a matrix and a second substrate having a pixel array lower region corresponding to the pixel array region, the first substrate and the second substrate being stacked, in which the pixel array lower region is configured with a plurality of unit regions being disposed in a row direction or a column direction, each unit region including one or more pixels, and includes one or more pixel readout circuits in which a circuit arrangement is common in the respective unit regions, and a first logic circuit in which a circuit is disposed across the unit regions.

[0008] An electronic apparatus according to a second aspect of the present disclosure includes a light source device that outputs radiation light, and a light detection device that receives reflected light obtained by reflecting the radiation light by an object, in which the light detection device includes a first substrate having a pixel array region in which light receiving elements are two-dimensionally disposed in a matrix and a second substrate having a pixel array lower region corresponding to the pixel array region, the first substrate and the second substrate being stacked, the pixel array lower region is configured with a plurality of unit regions being disposed in a row direction or a column direction, each unit region including one or more pixels, and includes one or more pixel readout circuits in which a circuit arrangement is common in the respective unit regions, and a first logic circuit in which a circuit is disposed across the unit regions.

[0009] In the first and second aspects of the present disclosure, a first substrate having a pixel array region in which light receiving elements are two-dimensionally disposed in a matrix and a second substrate having a pixel array lower region corresponding to the pixel array region are stacked, and the pixel array lower region is configured with a plurality of unit regions being disposed in a row direction or a column direction, each unit region including one or more pixels, and includes one or more pixel readout circuits in which a circuit arrangement is common in the respective unit regions, and a first logic circuit in which a circuit is disposed across the unit regions.

[0010] The light detection device and the electronic apparatus may be independent devices or may be modules incorporated in another device.

[0011] Fig. 1 is a block diagram depicting a configuration example of an electronic apparatus on which a light detection device of the present disclosure is mounted.Fig. 2 is a perspective view depicting a substrate configuration example of the light detection device of Fig. 1.Fig. 3 is a diagram depicting a configuration example of a pixel sensor unit and a pixel readout circuit.Fig. 4 is a diagram for describing the operation of the SPAD of Fig. 3.Fig. 5 is a cross-sectional view of a pixel portion of a first substrate and a second substrate.Fig. 6 is a block diagram depicting a configuration example of the second substrate.Fig. 7 is a diagram for describing a series of processes until distance information is generated.Fig. 8 is a diagram depicting an arrangement sharing example of a logic circuit disposed in a pixel array lower region and a logic circuit disposed outside the pixel array lower region.Fig. 9 is a plan view depicting the first arrangement example of the pixel array lower region.Fig. 10 is a plan view depicting the second arrangement example of the pixel array lower region.Fig. 11 is a plan view depicting the third arrangement example of the pixel array lower region.Fig. 12 is a plan view depicting the fourth arrangement example of the pixel array lower region.Fig. 13 is a plan view depicting the fifth arrangement example of the pixel array lower region.Fig. 14 is a diagram depicting the first modification of the pixel readout circuit.Fig. 15 is a diagram depicting the second modification of the pixel readout circuit.Fig. 16 is a diagram depicting another connection example of the pixel sensor unit and the pixel readout circuit.Fig. 17 is a diagram depicting another connection example of the pixel sensor unit and the pixel readout circuit.Fig. 18 is a perspective view depicting an example in which the light detection device has a stacked structure of three substrates.Fig. 19 is a block diagram depicting an example of schematic configuration of a vehicle control system.Fig. 20 is an explanatory diagram depicting an example of installation positions of an outside-vehicle information detecting section and imaging sections.

[0012] Hereinafter, modes for carrying out the technique of the present disclosure (hereinafter, it is referred to as embodiments) will be described with reference to the accompanying drawings. Note that, in the present specification and the drawings, components having substantially the same functional configurations are denoted by the same reference signs, and redundant descriptions are omitted. The description is given in the following order. 1. Configuration example of electronic apparatus 2. Substrate configuration example of light detection device 3. Configuration example of pixel sensor unit and pixel readout circuit 4. Pixel cross-sectional view 5. Configuration block diagram of second substrate 6. Arrangement sharing example of in-array logic circuit and out-of-array logic circuit 7. Circuit arrangement example in pixel array lower region 8. Another configuration example of pixel readout circuit 9. Another connection example of pixel sensor unit and pixel readout circuit 10. Configuration example of stacked structure of three substrates 11. Example of application to mobile object

[0013] <1. Configuration example of electronic apparatus> Fig. 1 is a block diagram depicting a configuration example of an electronic apparatus on which a light detection device of the present disclosure is mounted.

[0014] An electronic apparatus 1 includes a distance measuring device 11 and an application unit 12. The distance measuring device 11 measures the distance to the object to be measured (object to be measured) 30 by the direct ToF method to output distance information which is a measurement result to the application unit 12. The distance information includes, for example, a depth image in which a depth value indicating the distance to the subject is stored as a pixel value of each pixel. The application unit 12 is realized, for example, by a program operating on a central processing unit (CPU), requests the distance measuring device 11 to execute distance measurement, and acquires distance information which is a distance measurement result from the distance measuring device 11. The electronic apparatus 1 is assumed to be, for example, a smartphone, a tablet, a wearable device, a camera such as an in-vehicle camera, a digital still camera, or a digital video camera, a mounted device mounted on a vehicle such as an automobile, a mobile object such as a drone, or the like.

[0015] The distance measuring device 11 includes a control section 21, a light source device 22, and a light detection device 23. The control section 21 includes a control circuit and a processor such as a field programmable gate array (FPGA) or a digital signal processor (DSP), for example, and controls the entire operation of the distance measuring device 11. For example, the control section 21 generates a reference clock signal serving as a reference of a clock signal used by each unit of the distance measuring device 11, and supplies the reference clock signal to the light source device 22 and the light detection device 23. In addition, the control section 21 instructs the light detection device 23 to execute distance measurement in response to a request for distance measurement execution from the application unit 12, acquires distance information which is a distance measurement result from the light detection device 23, and outputs the distance information to the application unit 12.

[0016] The light source device 22 includes, for example, a light emitting element that emits light having a wavelength in an infrared region, and a drive circuit that drives the light emitting element. As a light emitting element that emits light having a wavelength in the infrared region, for example, a light emitting diode (LED) can be applied. The light emitting element is not limited thereto, and for example, a vertical cavity surface emitting laser (VCSEL) in which a plurality of light emitting elements is formed in an array can also be applied. The light source device 22 outputs radiation light 31 on the basis of the light emission timing signal supplied from the light detection device 23. The light emission timing signal is, for example, a pulse signal modulated into a rectangular wave having a predetermined duty ratio. Hereinafter, unless otherwise specified, “the light emitting element of the light source device 22 emits light” will be described as “the light source device 22 emits light” or the like.

[0017] The light detection device 23 includes, for example, a light receiving element capable of detecting light having a wavelength in an infrared region, and a signal processing circuit that outputs a signal corresponding to the light detected by the light receiving element. For example, a single photon avalanche diode (SPAD) can be applied as the light receiving element included in the light detection device 23. Hereinafter, unless otherwise specified, “the light receiving element of the light detection device 23 detects light” will be described as “the light detection device 23 receives light” or the like.

[0018] The light detection device 23 executes distance measurement processing in response to an instruction to execute distance measurement from the control section 21. For example, the light detection device 23 generates a light emission timing signal indicating a timing at which the light source device 22 emits light, and supplies the light emission timing signal to the light source device 22. Furthermore, the light detection device 23 performs a light receiving operation in synchronization with the light emission timing signal, and measures a count value serving as a basis for calculating the depth value. The count value is a value obtained by counting a time from when the light source device 22 outputs the radiation light 31 to when the light detection device 23 receives reflected light 32 obtained by the radiation light 31 being reflected by an object 30. For example, the light detection device 23 supplies the count value to the control section 21 as distance information. Alternatively, the light detection device 23 may calculate and generate a distance D to the object 30 from the count value, and supply the depth image stored as the depth value to the control section 21 as the distance information. The generation processing of the depth image based on the count value may be performed by the control section 21.

[0019] <2. Substrate configuration example of light detection device> Fig. 2 is a perspective view depicting a substrate configuration example of the light detection device 23.

[0020] For example, as depicted in Fig. 2, the light detection device 23 is configured by a semiconductor chip having a stacked structure in which a first substrate 51 and a second substrate 52 are stacked. An upper face of the first substrate 51 is a light incident face, and the reflected light 32 is incident on the first substrate 51 from above the first substrate 51.

[0021] The first substrate 51 includes at least a pixel array region 72 in which the pixel sensor units 71 are two-dimensionally disposed in a matrix in the row direction and the column direction. The pixel sensor unit 71 includes a light receiving element capable of detecting incident light of a predetermined wavelength (for example, a wavelength in an infrared region) to output a detection signal indicating a result of detecting the incident light. In the present embodiment, the pixel sensor unit 71 includes an SPAD as a light receiving element.

[0022] The second substrate 52 includes at least a pixel array lower region 82 in which the pixel readout circuits 81 are two-dimensionally disposed in a matrix in the row direction and the column direction. The pixel readout circuit 81 is provided in one-to-one correspondence with the pixel sensor unit 71 of the first substrate 51, and is electrically connected to the upper pixel sensor unit 71. The pixel readout circuit 81 is disposed in a region overlapping the upper pixel sensor unit 71 in plan view, and the pixel array lower region 82 is also a region overlapping the pixel array region 72 of the first substrate 51 in plan view. The pixel readout circuit 81 is a circuit that reads a detection signal generated by the pixel sensor unit 71.

[0023] <3. Configuration example of pixel sensor unit and pixel readout circuit> Fig. 3 is a diagram depicting a configuration example of the pixel sensor unit 71 and the pixel readout circuit 81 provided in a one-to-one correspondence.

[0024] The pixel sensor unit 71 includes an SPAD 101 which is a light receiving element. The pixel readout circuit 81 includes a transistor 102, an inverter 103 (input amplifier), and a level down unit 104.

[0025] A cathode of the SPAD 101 is connected to a drain of the transistor 102 and is connected to an input terminal of the inverter 103. An anode of the SPAD 101 is connected to a power supply voltage VA (hereinafter, also referred to as an anode voltage VA). When incident light is incident, the SPAD 101 avalanche amplifies the generated electrons to output a signal of a cathode voltage VS.

[0026] The SPAD 101 has a characteristic that electrons generated in response to incidence of one photon cause avalanche multiplication so that a large current flows when a large negative voltage that generates the avalanche multiplication is applied to a cathode. When this characteristic of the SPAD 101 is used, the incidence of one photon can be detected with high sensitivity. The power supply voltage VA supplied to the anode of the SPAD 101 is a negative voltage corresponding to the breakdown voltage VBD, and is, for example, a negative bias of about -20 V.

[0027] The transistor 102 is a constant current source that operates in a saturation region, and performs passive quenching by acting as a quenching resistor. The source of the transistor 102 is connected to the power supply voltage VE, and the drain is connected to the cathode of the SPAD 101 and the input terminal of the inverter 103. As a result, the power supply voltage VE is also supplied to the cathode of the SPAD 101. A bias voltage BIAS is supplied to the gate of the transistor 102.

[0028] In order to detect photons with sufficient efficiency, a voltage (hereinafter referred to as excess bias (ExcessBias)) larger than the breakdown voltage VBD of the SPAD 101 is applied to the SPAD 101. For example, assuming that the breakdown voltage VBD of the SPAD 101 is 20 V and a voltage larger than that by 3 V is applied, the power supply voltage VE supplied to the source of the transistor 102 is 3 V.

[0029] Note that the breakdown voltage VBD of the SPAD 101 greatly changes depending on the temperature or the like. Therefore, the applied voltage applied to the SPAD 101 is controlled (adjusted) according to the change in the breakdown voltage VBD. For example, when the power supply voltage VE is a fixed voltage, the anode voltage VA is controlled (adjusted).

[0030] The inverter 103 compares the signal of the cathode voltage VS from the SPAD 101 with a threshold value voltage Vth to output a detection signal PFout inverted every time the signal exceeds the threshold value voltage Vth in the positive direction or the negative direction. The inverter 103 includes a thick film MOS transistor.

[0031] Fig. 4 depicts a relationship between the signal of the cathode voltage VS input from the SPAD 101 to the inverter 103 and the detection signal PFout output by the inverter 103.

[0032] The inverter 103 inverts the detection signal PFout at time point t0 when the cathode voltage VS exceeds the threshold value voltage Vth in a voltage drop due to avalanche multiplication in response to incidence of photons on the SPAD 101. Next, the SPAD 101 is charged by the recharge operation, and the cathode voltage VS increases. The inverter 103 inverts the detection signal PFout again at time t1 when the rising cathode voltage VS exceeds the threshold value voltage Vth. The width in the time direction between time point t0 and time point t1 is an output pulse according to the incidence of photons on the SPAD 101. The inverter 103 shapes the output pulse to output the shaped output pulse to the level down unit 104.

[0033] Returning to Fig. 3, the level down unit 104 is a voltage conversion unit that converts the detection signal PFout input from the inverter 103 into a voltage level at which the TDC provided at the subsequent stage operates. For example, when the power supply voltage VE is 3 V, the level down unit 104 converts the detection signal PFout having a voltage amplitude of 0 V to 3 V into a signal having a voltage amplitude of 0 V to 1 V.

[0034] <4. Pixel cross-sectional view> Fig. 5 depicts a cross-sectional view of a pixel portion of the first substrate 51 and the second substrate 52. Fig. 5 depicts a cross-sectional view of a portion in which two pixels PX each including a pair of the pixel sensor unit 71 and the pixel readout circuit 81 are disposed in the row direction or the column direction.

[0035] In Fig. 5, the first substrate 51 and the second substrate 52 are bonded to each other at a bonding face indicated by a dotted line. The first substrate 51 includes a semiconductor substrate 141 including a silicon substrate or the like, and a wiring layer 142. Hereinafter, the wiring layer 142 is referred to as a sensor-side wiring layer 142 for easy distinction from a wiring layer 212 of the second substrate 52 described later. The wiring layer 212 of the second substrate 52 is referred to as a logic-side wiring layer 212. A face on which the sensor-side wiring layer 142 is formed is a front face of the semiconductor substrate 141, and in the drawing, a face on which an on-chip lens 143 on the upper side is formed is a back face of the semiconductor substrate 141 and is a light receiving face on which reflected light is incident.

[0036] The pixel region of the semiconductor substrate 141 includes an N well 151, a P-type diffusion layer 152, an N-type diffusion layer 153, a hole accumulation layer 154, and a high-concentration P-type diffusion layer 155. Then, an avalanche multiplication region 156 includes the depletion layer formed in the region where the P-type diffusion layer 152 and the N-type diffusion layer 153 are connected.

[0037] The N well 151 is formed by controlling the impurity concentration of the semiconductor substrate 141 to n-type, and forms an electric field that transfers electrons generated by photoelectric conversion in the pixel PX to the avalanche multiplication region 156. Instead of the N well 151, a P-well formed by controlling the impurity concentration of the semiconductor substrate 141 to p-type may be formed.

[0038] The P-type diffusion layer 152 is a dense P-type diffusion layer (P+) formed over substantially the entire surface of the pixel region in the planar direction. The N-type diffusion layer 153 is a thick N-type diffusion layer (N+) formed in the vicinity of the surface of the semiconductor substrate 141 over substantially the entire surface of the pixel region, as in the P-type diffusion layer 152. The N-type diffusion layer 153 is a contact layer connected to a contact electrode 181 as a cathode electrode for supplying a negative voltage for forming the avalanche multiplication region 156, and has a convex shape in which part thereof is formed up to the contact electrode 181 on the surface of the semiconductor substrate 141.

[0039] The hole accumulation layer 154 is a P-type diffusion layer (P) formed so as to surround the side face and the bottom face of the N well 151, and accumulates holes. In addition, the hole accumulation layer 154 is connected to the high-concentration P-type diffusion layer 155 electrically connected to a contact electrode 182 as an anode electrode of the SPAD 101.

[0040] The high-concentration P-type diffusion layer 155 is a dense P-type diffusion layer (P++) formed so as to surround the outer periphery of the N well 151 in the vicinity of the surface of the semiconductor substrate 141, and constitutes a contact layer for electrically connecting the hole accumulation layer 154 to the contact electrode 182 of the SPAD 101.

[0041] The contact electrodes 181 and 182, metal wires 183 and 184, contact electrodes 185 and 186, and metal wires 187 and 188 are formed in the sensor-side wiring layer 142.

[0042] The contact electrode 181 connects the N-type diffusion layer 153 and the metal wire 183, and the contact electrode 182 connects the high-concentration P-type diffusion layer 155 and the metal wire 184.

[0043] The metal wire 183 is formed to be wider than the avalanche multiplication region 156 so as to cover at least the avalanche multiplication region 156 in the planar region. In addition, the metal wire 183 may have a structure in which light transmitted through a pixel region of the semiconductor substrate 141 is reflected toward the semiconductor substrate 141.

[0044] The metal wire 184 is formed so as to overlap the high-concentration P-type diffusion layer 155 so as to surround the outer periphery of the metal wire 183 in the planar region.

[0045] The contact electrode 185 connects the metal wire 183 and the metal wire 187, and the contact electrode 186 connects the metal wire 184 and the metal wire 188.

[0046] On the other hand, the second substrate 52 includes a semiconductor substrate 211 including a silicon substrate or the like, and the wiring layer 212 (logic-side wiring layer 212).

[0047] In the drawing, a plurality of MOS transistors Tr and the logic-side wiring layer 212 are formed on a front face of the semiconductor substrate 211, the front face being the upper side. The plurality of MOS transistors Tr includes an N-type MOS transistor Tr1 and a P-type MOS transistor Tr2.

[0048] The logic-side wiring layer 212 includes metal wires 231 and 232, metal wires 233 and 234, and contact electrodes 235 and 236.

[0049] The metal wire 231 is electrically connected to the metal wire 187 of the sensor-side wiring layer 142 by metal bonding of Cu-Cu or the like. The metal wire 232 is electrically connected to the metal wire 188 of the sensor-side wiring layer 142 by metal bonding of Cu-Cu or the like.

[0050] The contact electrode 235 connects the metal wire 231 and the metal wire 233, and the contact electrode 236 connects the metal wire 232 and the metal wire 234.

[0051] The logic-side wiring layer 212 further includes a plurality of layers of metal wires 241 between a layer with the metal wires 233 and 234 and the semiconductor substrate 211.

[0052] On the second substrate 52, a pixel readout circuit 81 and logic circuits 301 and 311 to be described later include a plurality of MOS transistors Tr and a plurality of layers of metal wires 241 formed on the front face of the semiconductor substrate 211.

[0053] In the pixel PX including the pixel sensor unit 71 and the pixel readout circuit 81 configured as described above, the metal wire 187 and the metal wire 231 and the metal wire 188 and the metal wire 232 electrically connecting the first substrate 51 and the second substrate 52 by metal bonding of Cu-Cu or the like constitute a connection unit of the pixel region.

[0054] <5. Configuration block diagram of second substrate> Fig. 6 is a block diagram depicting a configuration example of the second substrate 52.

[0055] The second substrate 52 includes a plurality of pixel readout circuits 81 and a logic circuit 301 in the pixel array lower region 82 formed at a position corresponding to the pixel array region 72 of the first substrate 51. A rectangular region divided in a lattice pattern in the pixel array lower region 82 indicated by a broken line represents a pixel region of one pixel, and the pixel readout circuit 81 is provided for each pixel region. The logic circuit 301 includes a plurality of logic circuits 301-1 to 301-R (R>1). The logic circuits 301-1 to 301-R are dispersedly disposed in a region excluding the region of the pixel readout circuit 81 in the pixel array lower region 82. The adjacent logic circuits 301-P and Q (P and Q are different integers equal to or less than R) are electrically connected by connection wiring. Therefore, in each pixel region, the pixel readout circuit 81 provided for a pixel unit and part of the logic circuit 301 are disposed.

[0056] In addition, the second substrate 52 includes a logic circuit 311, an array driving unit 312, a distance measurement control section 313, a clock generation unit 314, an I / F unit 315, a memory 316, a reference current source 317, a thermometer 318, and the like in a region outside the pixel array lower region 82.

[0057] The logic circuit 311 is a circuit that executes a function different from that of the logic circuit 301 disposed in the pixel array lower region 82. Specific circuit examples of the logic circuit 301 disposed in the pixel array lower region 82 and the logic circuit 311 disposed outside the pixel array lower region 82 will be described later with reference to Figs. 7 and 8. Hereinafter, in order to facilitate distinction between the logic circuit 301 and the logic circuit 311, the logic circuit 301 disposed in the pixel array lower region 82 will be referred to as a first logic circuit 301, and the logic circuit 311 disposed outside the pixel array lower region 82 will be referred to as a second logic circuit 311. However, as will be described later with reference to Fig. 13, the logic circuit 311 may be disposed in the pixel array lower region 82.

[0058] The array driving unit 312 controls the pixel readout circuits 81 disposed in the pixel array lower region 82 in a matrix. The array driving unit 312 may individually control the validity and invalidity of the operation of each pixel readout circuit 81.

[0059] The distance measurement control section 313 controls the entire operation of the light detection device 23 according to, for example, a program incorporated in advance. The distance measurement control section 313 controls operations of the first logic circuit 301, the second logic circuit 311, the array driving unit 312, and the like on the basis of the clock signal supplied from the clock generation unit 314. Furthermore, the distance measurement control section 313 generates a light emission timing signal indicating a timing at which the light source device 22 emits light, and supplies the light emission timing signal to the light source device 22.

[0060] The clock generation unit 314 generates one or more clock signals to be used in the light detection device 23 on the basis of a reference clock signal supplied from the outside (for example, the control section 21 of the distance measuring device 11), and supplies the generated clock signals to the distance measurement control section 313 and the like.

[0061] The I / F unit 315 converts the distance information generated by the first logic circuit 301 into a format of a predetermined communication interface to output the converted information to the outside (for example, the control section 21 of the distance measuring device 11). As the communication interface, for example, a mobile industry processor interface (MIPI) can be applied.

[0062] The memory 316 is a storage unit that stores various types of setting information such as an operation mode and temporarily stores data that is necessary during operation.

[0063] The reference current source 317 generates an original reference current used in each circuit in the light detection device 23, and supplies the generated reference current to each unit.

[0064] The thermometer 318 measures the temperature in the light detection device 23. The measured temperature is used, for example, for control (adjustment) of the anode voltage VA of the SPAD 101.

[0065] As described above, the second substrate 52 of the light detection device 23 has a configuration in which the logic circuit is divided into the first logic circuit 301 of the pixel array lower region 82 and the second logic circuit 311 outside the pixel array lower region 82 and disposed.

[0066] <6. Arrangement sharing example of in-array logic circuit and out-of-array logic circuit> Next, a function sharing example of the logic circuits of the first logic circuit 301 and the second logic circuit 311 will be described.

[0067] First, a series of processes until the distance information is generated on the basis of the detection signal PFout output by the pixel readout circuit 81 will be described with reference to Fig. 7.

[0068] An MUX 331, a plurality of TDCs 332, a TDC result calculation unit 333, a histogram generation unit 334, and a distance calculation unit 335 depicted in Fig. 7 are disposed in either the first logic circuit 301 or the second logic circuit 311. The TDC result calculation unit 333 and the distance calculation unit 335 indicated by broken lines in Fig. 7 may be omitted. The histogram generation unit 334 includes a decoder unit 351, a counter unit 352, and a readout unit 353.

[0069] The multiplexer (MUX) 331 switches connection of each pixel PX disposed in the pixel array lower region 82 in a matrix to the pixel readout circuit 81 and connection to a plurality of TDCs 332. The MUX 331 appropriately switches the plurality of pixel readout circuits 81 disposed in a matrix in a predetermined order, and acquires the detection signal PFout output by the pixel readout circuit 81 of each pixel PX. Further, the MUX 331 outputs the detection signal PFout acquired from the predetermined pixel readout circuit 81 to any of the plurality of TDCs 332.

[0070] Each time to digital converter (TDC) 332 converts the time at which the SPAD 101 of the pixel PX reacts into time information. The TDC 332 generates a count value indicating a time from when the light source device 22 emits light to when the SPAD 101 of the pixel PX receives light and reacts, on the basis of the pixel signal (detection signal PFout) of the predetermined pixel PX supplied from the MUX 73 and the light emission timing signal generated by the distance measurement control section 313. The TDC 332 supplies the count value generated for each pixel to the TDC result calculation unit 333 as a TDC result. A multiplexer (MUX) that switches connection between the plurality of TDCs 332 and the TDC result calculation unit 333 may also be provided at a subsequent stage of each TDC 332.

[0071] The TDC result calculation unit 333 performs a predetermined calculation on the count value supplied as the TDC result from the TDC 332 as necessary. For example, for the purpose of correcting the distance measurement result, the TDC result calculation unit 333 performs a process of subtracting a correction value for correcting the distance information from the count value from the TDC 332. Furthermore, for example, the TDC result calculation unit 333 performs a process of merging (summing) count values of a plurality of pixels for the purpose of improving the count rate per distance measurement point and increasing the SN ratio. The TDC result calculation unit 333 supplies the calculated count value to the decoder unit 351 of the histogram generation unit 334. In a case where the calculation by the TDC result calculation unit 333 is unnecessary, the TDC result calculation unit 333 is omitted.

[0072] The decoder unit 351 generates a signal for counting up the bin of the histogram corresponding to the count value from the TDC 332 or the TDC result calculation unit 333, and supplies the signal to the counter unit 352.

[0073] The counter unit 352 counts up the frequency value of the bin of the predetermined count value of the histogram on the basis of the signal supplied from the decoder unit 351. In the direct ToF distance measurement, light emission by the light source device 22 and reception of reflected light by the light detection device 23 are repeatedly performed a predetermined number of times (for example, thousands to tens of thousands of times). The frequency value of the bin of the count value corresponding to the time until the reflected light is received is counted up, and a histogram is generated for each pixel.

[0074] The readout unit 353 reads out histogram data (histogram data) generated for each pixel in the counter unit 352 to output the histogram data to the distance calculation unit 335. In a case where the distance calculation unit 335 is omitted, the histogram data of each pixel is output to the control section 21 as distance information.

[0075] The distance calculation unit 335 detects a bin having the maximum frequency value for each pixel on the basis of the histogram data of each pixel supplied from the readout unit 353 to output the bin as distance information to the control section 21. Alternatively, the distance calculation unit 335 calculates the distance D corresponding to the bin having the maximum frequency value, generates a depth image stored as a depth value, and outputs the depth image as distance information to the control section 21. Note that the distance calculation unit 335 may calculate the distance D using not only the bin having the maximum frequency value but also a plurality of bins around the bin. For example, the distance calculation unit may perform centroid calculation on the count values of a plurality of bins including the peak position to output the distance D with a resolution equal to or lower than the bin. In a case where the distance calculation unit 335 is omitted, calculation corresponding to that by the distance calculation unit 335 can be performed by the control section 21.

[0076] Fig. 8 is a diagram depicting an arrangement sharing example of the first logic circuit 301 and the second logic circuit 311 of each unit depicted in Fig. 7.

[0077] As depicted in Fig. 8, for example, the TDC result calculation unit 333, the histogram generation unit 334, and the distance calculation unit 335 are disposed in the first logic circuit 301 in the pixel array lower region 82. More specifically, the TDC result calculation unit 333, the histogram generation unit 334, and the distance calculation unit 335 are appropriately distributed and disposed in the first logic circuits 301-1 to 301-R. As to how the TDC result calculation unit 333, the histogram generation unit 334, and the distance calculation unit 335 are disposed in the first logic circuits 301-1 to 301-R, for example, an automatic arrangement wiring tool of a circuit can be used.

[0078] On the other hand, the MUX 331 and the plurality of TDCs 332 are disposed in the second logic circuit 311 outside the pixel array lower region 82. Note that circuits other than the MUX 331 and the TDC 332 may be further disposed in the second logic circuit 311. For example, a plurality of clock generation circuits for generating a clock signal used for the counting operation of the TDC 332 may be disposed in the second logic circuit 311, and the individual clock generation circuit may be used for each region obtained by dividing the pixel array lower region 82.

[0079] In the flow of the signal (data), the detection signal PFout output by the pixel readout circuit 81 of each pixel region in the pixel array lower region 82 is input to the second logic circuit 311 outside the pixel array lower region 82. In the second logic circuit 311 outside the pixel array lower region 82, the MUX 331 appropriately switches the connection with the pixel readout circuit 81 and the connection with the plurality of TDCs 332, and each TDC 332 generates a count value corresponding to the time from when the light source device 22 emits light to when the pixel PX receives light. The count value generated by each TDC 332 is output to the first logic circuit 301 (any one of 301-1 to 301-R) in the pixel array lower region 82. Then, in the first logic circuit 301 in the pixel array lower region 82, a histogram is generated, the distance D to the object 30 is calculated on the basis of the generated histogram, and is output to the outside as distance information. In this manner, the signal (data) temporarily goes out of the pixel array lower region 82 from the inside of the pixel array lower region 82, and is returned into the pixel array lower region 82 again.

[0080] Note that a control section 336 may be further disposed in the first logic circuit 301 in the pixel array lower region 82. The control section 336 can have the following functions, for example. The control section 336 controls validity / invalidity of each pixel readout circuit 81 and validity / invalidity of each TDC 332 on the basis of a signal from the control section 21 outside the light detection device 23 and a signal from the memory 316. Furthermore, for example, the control section 336 generates a control signal that designates the bias voltage BIAS input to the gate of the transistor 102 as the current source of each pixel readout circuit 81. For example, in a case where the range of the radiation light 31 output by the light source device 22 is limited and it is not necessary to drive all the pixels of the pixel array region 72 in the light detection device 23, part of the pixel readout circuit 81 and the TDC 332 can be stopped according to the pixels that are not driven.

[0081] As described above, in the light detection device 23, the logic circuits that process the detection signal PFout output by each pixel readout circuit 81 can be dispersedly disposed in the first logic circuit 301 in the pixel array lower region 82 and the second logic circuit 311 outside the pixel array lower region 82.

[0082] <7. Circuit arrangement example in pixel array lower region> As described with reference to Fig. 6, part of the pixel readout circuit 81 and the first logic circuit 301 is disposed in each pixel region of the pixel array lower region 82 of the second substrate 52. An arrangement example of the pixel readout circuit 81 and the first logic circuit 301 will be described with reference to Figs. 9 to 12.

[0083] (First arrangement example) Fig. 9 is a plan view depicting the first arrangement example of the pixel array lower region 82 of the second substrate 52.

[0084] Fig. 9 depicts a plan view of a 4x4 pixel region in the pixel array lower region 82. In Fig. 9, a rectangular region divided by a broken line represents a pixel region of one pixel. The same applies to Figs. 10 and 11.

[0085] In the first arrangement example of Fig. 9, the pixel readout circuit 81 is disposed at the central portion of the pixel region, and a connection unit 401 is disposed in the region of the pixel readout circuit 81 and at the central portion of the pixel region. The connection unit 401 is a wiring electrically connected to the SPAD 101 of the pixel sensor unit 71 of the first substrate 51. The connection unit 401 corresponds to, for example, the metal wires 231 and 232 connected to the sensor-side wiring layer 142 of the first substrate 51 by metal bonding depicted in the cross-sectional view of Fig. 5. A region other than the pixel readout circuit 81 in the pixel region is any region of the first logic circuits 301-1 to 301-R.

[0086] Assuming that a region of the unit of NxM pixels (N and M are integers of one or more) is a unit region 411, the pixel array lower region 82 of the first arrangement example has a configuration in which the unit region 411 of 1×1 pixel indicated by a bold solid line is repeatedly disposed in the row direction and the column direction with N, M=1. The unit region 411 of 1×1 pixel includes the pixel readout circuit 81 in which the arrangement of the transistor and the metal wire is common in the unit region 411 and (part of) the first logic circuit 301 in which the arrangement of the transistor and the metal wire is different (non-common) in the unit region 411.

[0087] Regarding the region of each pixel readout circuit 81 in the pixel array lower region 82, the transistors of the unit region 411 each including one pixel readout circuit 81 are regularly disposed in the pixel array lower region 82. Therefore, the pixel array lower region 82 includes a region (first transistor region) of the plurality of pixel readout circuits 81 in which the transistors of the unit region 411 are regularly disposed and a region (second transistor region) of the first logic circuit 301 in which the transistors are irregularly disposed.

[0088] The connection unit 401 is disposed in the pixel readout circuit 81. For example, assuming that the connection unit 401 is the metal wire 231 in the cross-sectional view depicted in Fig. 5, the arrangement of a contact electrode 235 and a contact electrode 235 connected to the metal wire 231 is also the same in the unit region 411. By disposing the connection unit 401 in the pixel readout circuit 81, the coupling capacitance of the wiring connected to up to the pixel readout circuit 81 can be equalized in the pixel array lower region 82.

[0089] Furthermore, in the first arrangement example, since the position of the connection unit 401 is the same in all the pixels, the optical characteristics of the pixels can be made uniform for all the pixels.

[0090] (Second arrangement example) Fig. 10 is a plan view depicting the second arrangement example of the pixel array lower region 82 of the second substrate 52.

[0091] In the first arrangement example depicted in Fig. 9, the pixel readout circuits 81 are disposed at the central portion of the pixel region, but in the second arrangement example of Fig. 10, the pixel readout circuits 81 are disposed on one side of the pixel region so that two adjacent rows of the pixel readout circuits 81 are in contact with each other. Specifically, in one of the odd-numbered row and the even-numbered row, the pixel readout circuit 81 is disposed at the lower part of the pixel region in the column direction, and in the other one, the pixel readout circuit 81 is disposed at the upper part of the pixel region in the column direction. As in the first arrangement example, the connection unit 401 is disposed in the pixel readout circuit 81.

[0092] The pixel array lower region 82 of the second arrangement example has a configuration in which assuming that N=1 and M=2 for the unit region 411 of NxM pixels, the unit region 411 of 1×2 pixels indicated by a bold solid line is repeatedly disposed in the row direction and the column direction. The unit region 411 of 1×2 pixels includes two pixel readout circuits 81 in which the arrangement of transistors and metal wires is common in the unit region 411, and (part of) the first logic circuit 301 in which the arrangement of transistors and metal wires is different (non-common) in the unit region 411.

[0093] Regarding the region of each pixel readout circuit 81 in the pixel array lower region 82, the transistors of the unit region 411 including the two pixel readout circuits 81 are regularly disposed in the pixel array lower region 82. Therefore, the pixel array lower region 82 includes a region (first transistor region) of the plurality of pixel readout circuits 81 in which the transistors of the unit region 411 are regularly disposed and a region (second transistor region) of the first logic circuit 301 in which the transistors are irregularly disposed.

[0094] Also in the second arrangement example, since the connection unit 401 is disposed in the pixel readout circuit 81, the coupling capacitance of the wiring connected to up to the pixel readout circuit 81 can be equalized in the pixel array lower region 82.

[0095] Furthermore, in the second arrangement example, by disposing the pixel readout circuits 81 so that two adjacent rows of the pixel readout circuits 81 are in contact with each other, the area efficiency of the pixel readout circuits 81 can be improved.

[0096] (Third arrangement example) Fig. 11 is a plan view depicting the third arrangement example of the pixel array lower region 82 of the second substrate 52.

[0097] In the third arrangement example depicted in Fig. 11, as in the second arrangement example of Fig. 10, the pixel readout circuit 81 is disposed on one side of the pixel region so that two adjacent rows of the pixel readout circuits are in contact with each other. On the other hand, the third arrangement example is different from the second arrangement example depicted in Fig. 10 in that the connection unit 401 is disposed in the pixel readout circuit 81 in the second arrangement example, but the connection unit 401 is disposed in the region of the first logic circuit 301 and at the central portion of the pixel region in the third arrangement example.

[0098] The pixel array lower region 82 of the third arrangement example has a configuration in which assuming that N=1 and M=2 for the unit region 411 of NxM pixels, the unit region 411 of 1×2 pixels indicated by a bold solid line is repeatedly disposed in the row direction and the column direction. The unit region 411 of 1×2 pixels includes two pixel readout circuits 81 in which the arrangement of transistors and metal wires is common in the unit region 411, and (part of) the first logic circuit 301 in which the arrangement of transistors and metal wires is different (non-common) in the unit region 411.

[0099] Regarding the region of each pixel readout circuit 81 in the pixel array lower region 82, the transistors of the unit region 411 including the two pixel readout circuits 81 are regularly disposed in the pixel array lower region 82. Therefore, the pixel array lower region 82 includes a region (first transistor region) of the plurality of pixel readout circuits 81 in which the transistors of the unit region 411 are regularly disposed and a region (second transistor region) of the first logic circuit 301 in which the transistors are irregularly disposed.

[0100] In the third arrangement example, by disposing the pixel readout circuit so that two adjacent rows of the pixel readout circuits 81 are in contact with each other, the area efficiency of the pixel readout circuits 81 can be improved.

[0101] Furthermore, in the third arrangement example, since the position of the connection unit 401 is the same in all the pixels, the optical characteristics of the pixels can be made uniform in all the pixels.

[0102] (Fourth arrangement example) In the example described above, the first logic circuit 301 is disposed in the pixel array lower region 82. However, part of the first logic circuit 301 may be formed outside the pixel array lower region 82.

[0103] Fig. 12 is a plan view depicting the fourth arrangement example of the pixel array lower region 82 of the second substrate 52, and depicts an example in which the first logic circuit 301 is also disposed outside the pixel array lower region 82.

[0104] The fourth arrangement example of Fig. 12 is similar to the first arrangement example of Fig. 9 except that part of the first logic circuit 301 (first logic circuit 301-R) is disposed outside the pixel array lower region 82. In the example of Fig. 12, an example is depicted in which the first logic circuit 301 extends to the outside of the pixel array lower region 82 only in the direction of one side of the pixel array lower region 82 of the rectangular region, but may extend to the outside in the directions of two or more sides of the pixel array lower region 82.

[0105] (Fifth arrangement example) In the above-described example, the second logic circuit 311 is disposed outside the pixel array lower region 82. However, the second logic circuit 311 may be disposed in the pixel array lower region 82.

[0106] Fig. 13 is a plan view depicting the fifth arrangement example of the pixel array lower region 82 of the second substrate 52, and depicts an example in which the second logic circuit 311 is disposed in the pixel array lower region 82.

[0107] In this manner, it is also possible to dispose the second logic circuit 311 in the pixel array lower region 82. In addition, the second logic circuit 311 may be disposed across both the inside of the pixel array lower region 82 and the outside of the pixel array lower region 82.

[0108] (Summary of circuit arrangement in pixel array lower region) The pixel array lower region 82 of the second substrate 52 is configured by disposing a plurality of unit regions 411 including one or more pixels in the row direction or the column direction, and includes one or more pixel readout circuits 81 in which the circuit arrangement of transistors and metal wires is common in the respective unit regions 411, and a first logic circuit 301 in which a circuit including transistors and metal wires is disposed across the unit regions 411. In other words, the pixel array lower region 82 of the second substrate 52 includes the first transistor region including the plurality of pixel readout circuits 81 in which the transistors of the unit region 411 are regularly disposed and the second transistor region in which the transistors are irregularly disposed to form the first logic circuit 301. The first logic circuit 301 includes at least the histogram generation unit 334 that generates a histogram of count values based on the detection signal PFout output by the pixel readout circuit 81.

[0109] By disposing the first logic circuit 301 including at least the histogram generation unit 334 in the pixel array lower region 82 of the second substrate 52, the area of the second logic circuit 311 outside the pixel array lower region 82 can be reduced, and the chip area can be reduced. By disposing the histogram generation unit 334 in the pixel array lower region 82, the bit depth of the histogram and the number of bits of the count value can be largely secured without depending on the distance measurement point size, so that the distance measurement range can be extended.

[0110] Furthermore, by disposing the second logic circuit 311 including the plurality of TDCs 332 outside the pixel array lower region 82, the distance measurement point size (pixel size) can be reduced, and the distance measurement point density can be improved. Since the bit depth of the count value of the TDC 332 can be increased without being restricted by the distance measurement point size, the distance measurement range can be extended. By increasing the wiring width and using a wiring layer having a small sheet resistance, the band of signal transmission can be improved, the resolution of the TDC 332 can be improved, and the distance measurement accuracy can be improved.

[0111] That is, according to the light detection device 23 including the second substrate 52, it is possible to miniaturize the pixel without enlarging the chip area.

[0112] <8. Another configuration example of pixel readout circuit> Another configuration example of the pixel readout circuit 81 will be described.

[0113] Fig. 14 is a diagram depicting the first modification of the pixel readout circuit 81.

[0114] In the first modification depicted in Fig. 14, a circuit 105 that executes a predetermined function is added to the basic configuration of the pixel readout circuit 81 depicted in Fig. 3. The circuit 105 is disposed at a subsequent stage of the level down unit 104. The circuit 105 can be, for example, a buffer circuit or a short pulse circuit.

[0115] Fig. 15 is a diagram depicting the second modification of the pixel readout circuit 81.

[0116] In the second modification depicted in Fig. 15, a latch circuit 111, an inverter 112, and a switch 113 are added to the basic configuration of the pixel readout circuit 81 depicted in Fig. 3.

[0117] The pixel readout circuit 81 of the second modification has a configuration capable of performing ON / OFF control of photon detection for a pixel unit.

[0118] The switch 113 has one end of at both ends connected to the cathode of the SPAD 101, the input terminal of the inverter 103, and the drain of the transistor 102, and the other end connected to the ground (GND). The switch 113 can include, for example, an N-type MOS transistor, and is turned on and off according to a gating inversion signal VG_I obtained by inverting a gating control signal VG, which is an output of the latch circuit 111, by the inverter 112.

[0119] The latch circuit 111 supplies the gating control signal VG for controlling the pixel PX to be either valid or invalid to the inverter 112 on the basis of the trigger signal SET supplied from the array driving unit 312 and address data DEC. The inverter 112 generates a gating inversion signal VG_I obtained by inverting the gating control signal VG, and supplies the gating inversion signal VG_I to the switch 113.

[0120] The trigger signal SET is a timing signal indicating a timing at which the gating control signal VG is switched, and the address data DEC is data indicating the address of the pixel PX to be set as the valid pixel among the plurality of pixels PX disposed in a matrix. The trigger signal SET and the address data DEC are supplied from the array driving unit 312.

[0121] The latch circuit 111 reads the address data DEC at a predetermined timing indicated by the trigger signal SET. Then, in a case where the pixel address indicated by the address data DEC includes the pixel address of (the pixel PX) thereof, the latch circuit 111 outputs the gating control signal VG of Hi(1) for setting the pixel PX thereof as a valid pixel. On the other hand, in a case where the pixel address indicated by the address data DEC does not include the pixel address of (the pixel PX) thereof, the circuit outputs the gating control signal VG of Lo(0) for setting the pixel PX thereof as an invalid pixel. Accordingly, in a case where the pixel PX is set as a valid pixel, the gating inversion signal VG_I of Lo(0) inverted by the inverter 112 is supplied to the switch 113. On the other hand, in a case where the pixel PX is set as an invalid pixel, the gating inversion signal VG_I of Hi(1) is supplied to the switch 113. The switch 113 is turned off (disconnected) in a case where the pixel PX is set as a valid pixel, and is turned on (connected) in a case where the pixel PX is set as an invalid pixel. In a case where the switch 113 is turned on and the pixel PX is set as an invalid pixel, the cathode voltage VS of the SPA 101 is 0 V (GND), and the anode-cathode voltage of the SPAD 101 is equal to or lower than the breakdown voltage VBD, so that no reaction occurs even when photons enter the SPAD 101.

[0122] <9. Another connection example of pixel sensor unit and pixel readout circuit> Another connection example of the pixel sensor unit 71 and the pixel readout circuit 81 will be described.

[0123] In Fig. 3, the pixel sensor unit 71 and the pixel readout circuit 81 are provided on a one-to-one basis. However, one pixel readout circuit 81 may be provided for the plurality of pixel sensor units 71.

[0124] Fig. 16 depicts a configuration example in which one pixel readout circuit 81 is provided for the SPADs 101 of the four pixel sensor units 71. By connecting a plurality of SPADs 101 to one pixel readout circuit 81, variations in the breakdown voltage VBD can be reduced.

[0125] Alternatively, instead of being connected to one pixel readout circuit 81 via one wire as depicted in Fig. 16, a plurality of SPADs 101 may be connected to one pixel readout circuit 81 via a plurality of wires as depicted in Fig. 17. In Fig. 17, two SPADs 101 are connected to one wire, and two wires are connected to one pixel readout circuit 81, so that one pixel readout circuit 81 is connected to a total of four SPADs 101. The number of wires connected to the pixel readout circuit 81 may be three or more. The number of SPADs 101 of the pixel sensor unit 71 connected to one wire may be 3 or more. In this manner, by connecting a plurality of wires to one pixel readout circuit 81 and connecting a plurality of SPADs 101 to each wire, it is possible to optimize the wiring RC load in addition to reducing the variation in the breakdown voltage VBD.

[0126] <10. Configuration example of stacked structure of three substrates> In the above-described example, as depicted in Fig. 2, the light detection device 23 has a stacked structure of two substrates in which the first substrate 51 and the second substrate 52 are stacked.

[0127] However, the light detection device 23 may have a stacked structure of three or more substrates.

[0128] Fig. 18 is a perspective view depicting an example in which the light detection device 23 has a stacked structure of three substrates.

[0129] The light detection device 23 includes a semiconductor chip having a stacked structure of three substrates obtained by adding a third substrate 53 in addition to the first substrate 51 and the second substrate 52 described above.

[0130] The third substrate 53 includes at least a pixel array lower region 92 in which predetermined processing circuits 91 are two-dimensionally disposed in a matrix in the row direction and the column direction. The processing circuit 91 may be provided in a one-to-one correspondence with the pixel sensor unit 71 of the first substrate 51 and the pixel readout circuit 81 of the second substrate 52, or may not be provided in a one-to-one correspondence. The processing circuit 91 is electrically connected to the pixel readout circuit 81 above. What kind of circuit is provided as the processing circuit 91 of the third substrate 53 is not particularly limited. Part of the pixel readout circuit 81 of the second substrate 52 may be disposed on the third substrate 53, or part or all of the first logic circuit 301 and the second logic circuit 311 may be disposed. In addition, the clock generation unit 314, the I / F unit 315, the memory 316, and the like other than the first logic circuit 301 and the second logic circuit 311 may be disposed on the third substrate 53.

[0131] By configuring the light detection device 23 with a stacked structure of three substrates, a margin can be provided in the circuit arrangement of the second substrate 52, and it is possible to further reduce the chip area and extend the distance measurement range. In addition, it is possible to further miniaturize the pixel without increasing the chip area.

[0132] <11. Example of application to mobile object> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology of the present disclosure may be achieved in the form of a device to be mounted on a mobile object of any kind, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility, an airplane, a drone, a vessel, or a robot.

[0133] Fig. 19 is a block diagram depicting a schematic configuration example of a vehicle control system as an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0134] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. In the example depicted in Fig. 19, the vehicle control system 12000 includes a driving system control unit 12010, a body system control unit 12020, an outside-vehicle information detecting unit 12030, an in-vehicle information detecting unit 12040, and an integrated control unit 12050. In addition, a microcomputer 12051, a sound / image output section 12052, and a vehicle-mounted network interface (I / F) 12053 are illustrated as a functional configuration of the integrated control unit 12050.

[0135] The driving system control unit 12010 controls the operation of devices related to the driving system of the vehicle in accordance with various kinds of programs. For example, the driving system control unit 12010 functions as a control device for a driving force generating device for generating the driving force of the vehicle, such as an internal combustion engine, a driving motor, or the like, a driving force transmitting mechanism for transmitting the driving force to wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating the braking force of the vehicle, and the like.

[0136] The body system control unit 12020 controls the operation of various kinds of devices provided to a vehicle body in accordance with various kinds of programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various kinds of lamps such as a headlamp, a backup lamp, a brake lamp, a turn signal, a fog lamp, or the like. In this case, radio waves transmitted from a mobile device as an alternative to a key or signals of various kinds of switches can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals, and controls a door lock device, the power window device, the lamps, or the like of the vehicle.

[0137] The outside-vehicle information detecting unit 12030 detects information about the outside of the vehicle including the vehicle control system 12000. For example, the outside-vehicle information detecting unit 12030 is connected with an imaging section 12031. The outside-vehicle information detecting unit 12030 makes the imaging section 12031 image an image of the outside of the vehicle, and receives the imaged image. On the basis of the received image, the outside-vehicle information detecting unit 12030 may perform processing of detecting an object such as a human, a vehicle, an obstacle, a sign, a character on a road surface, or the like, or processing of detecting a distance thereto.

[0138] The imaging section 12031 is an optical sensor that receives light, and which outputs an electric signal corresponding to a received light amount of the light. The imaging section 12031 can output the electric signal as an image, or can output the electric signal as information about a measured distance. In addition, the light received by the imaging section 12031 may be visible light, or may be invisible light such as infrared rays or the like.

[0139] The in-vehicle information detecting unit 12040 detects information about the inside of the vehicle. The in-vehicle information detecting unit 12040 is, for example, connected with a driver state detecting section 12041 that detects the state of a driver. The driver state detecting section 12041, for example, includes a camera that images the driver. On the basis of detection information input from the driver state detecting section 12041, the in-vehicle information detecting unit 12040 may calculate a degree of fatigue of the driver or a degree of concentration of the driver, or may determine whether the driver is dozing.

[0140] The microcomputer 12051 can calculate a control target value for the driving force generating device, the steering mechanism, or the braking device on the basis of the information about the inside or outside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030 or the in-vehicle information detecting unit 12040, and output a control command to the driving system control unit 12010. For example, the microcomputer 12051 can perform cooperative control intended to implement functions of an advanced driver assistance system (ADAS) which functions include collision avoidance or shock mitigation for the vehicle, following driving based on a following distance, vehicle speed maintaining driving, a warning of collision of the vehicle, a warning of deviation of the vehicle from a lane, or the like.

[0141] In addition, the microcomputer 12051 can perform cooperative control intended for automated driving, which makes the vehicle to travel automatedly without depending on the operation of the driver, or the like, by controlling the driving force generating device, the steering mechanism, the braking device, or the like on the basis of the information about the outside or inside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030 or the in-vehicle information detecting unit 12040.

[0142] In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 on the basis of the information about the outside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030. For example, the microcomputer 12051 can perform cooperative control intended to prevent a glare by controlling the headlamp so as to change from a high beam to a low beam, for example, in accordance with the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detecting unit 12030.

[0143] The sound / image output section 12052 transmits an output signal of at least one of a sound and an image to an output device capable of visually or auditorily notifying information to an occupant of the vehicle or the outside of the vehicle. In the example of Fig. 19, an audio speaker 12061, a display section 12062, and an instrument panel 12063 are depicted as the output device. The display section 12062 may, for example, include at least one of an on-board display and a head-up display.

[0144] Fig. 20 is a diagram depicting an example of an installation position of the imaging section 12031.

[0145] In Fig. 20, the imaging section 12031 includes imaging sections 12101, 12102, 12103, 12104, and 12105.

[0146] The imaging sections 12101, 12102, 12103, 12104, and 12105 are, for example, disposed at positions on a front nose, sideview mirrors, a rear bumper, and a back door of the vehicle 12100 as well as a position on an upper portion of a windshield within the interior of the vehicle. The imaging section 12101 provided to the front nose and the imaging section 12105 provided to the upper portion of the windshield within the interior of the vehicle obtain mainly an image of the front of the vehicle 12100. The imaging sections 12102 and 12103 provided to the sideview mirrors obtain mainly an image of the sides of the vehicle 12100. The imaging section 12104 provided to the rear bumper or the back door obtains mainly an image of the rear of the vehicle 12100. The imaging section 12105 provided to the upper portion of the windshield within the interior of the vehicle is used mainly to detect a preceding vehicle, a pedestrian, an obstacle, a signal, a traffic sign, a lane, or the like.

[0147] Note that Fig. 20 depicts an example of an imaging range of the imaging section 12101 to 12104. An imaging range 12111 represents the imaging range of the imaging section 12101 provided to the front nose. Imaging ranges 12112 and 12113 respectively represent the imaging ranges of the imaging sections 12102 and 12103 provided to the sideview mirrors. An imaging range 12114 represents the imaging range of the imaging section 12104 provided to the rear bumper or the back door. A bird's-eye image of the vehicle 12100 when viewed from above is obtained by superimposing image data imaged by the imaging sections 12101 to 12104, for example.

[0148] At least one of the imaging sections 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging sections 12101 to 12104 may be a stereo camera constituted of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0149] For example, the microcomputer 12051 can determine a distance to each three-dimensional object within the imaging ranges 12111 to 12114 and a temporal change in the distance (relative speed with respect to the vehicle 12100) on the basis of the distance information obtained from the imaging sections 12101 to 12104 to extract, as a preceding vehicle, a nearest three-dimensional object in particular that is present on a traveling path of the vehicle 12100 and which travels in substantially the same direction as the vehicle 12100 at a predetermined speed (for example, equal to or more than 0 km / hour). Further, the microcomputer 12051 can set a following distance to be maintained in front of a preceding vehicle in advance, and perform automatic brake control (including following stop control), automatic acceleration control (including following start control), or the like. It is thus possible to perform cooperative control intended for automated driving that makes the vehicle travel automatedly without depending on the operation of the driver or the like.

[0150] For example, the microcomputer 12051 can classify three-dimensional object data on three-dimensional objects into three-dimensional object data of a two-wheeled vehicle, a standard-sized vehicle, a large-sized vehicle, a pedestrian, a utility pole, and other three-dimensional objects on the basis of the distance information obtained from the imaging sections 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic avoidance of an obstacle. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that the driver of the vehicle 12100 can recognize visually and obstacles that are difficult for the driver of the vehicle 12100 to recognize visually. Then, the microcomputer 12051 determines a collision risk indicating a risk of collision with each obstacle. In a situation in which the collision risk is equal to or higher than a set value and there is thus a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display section 12062, and performs forced deceleration or avoidance steering via the driving system control unit 12010. The microcomputer 12051 can thereby assist in driving to avoid collision.

[0151] At least one of the imaging sections 12101 to 12104 may be an infrared camera that detects infrared rays. The microcomputer 12051 can, for example, recognize a pedestrian by determining whether or not there is a pedestrian in imaged images of the imaging sections 12101 to 12104. Such recognition of a pedestrian is, for example, performed by a procedure of extracting characteristic points in the imaged images of the imaging sections 12101 to 12104 as infrared cameras and a procedure of determining whether or not it is the pedestrian by performing pattern matching process on a series of characteristic points representing the contour of the object. When the microcomputer 12051 determines that there is a pedestrian in the imaged images of the imaging sections 12101 to 12104, and thus recognizes the pedestrian, the sound / image output section 12052 controls the display section 12062 so that a square contour line for emphasis is displayed so as to be superimposed on the recognized pedestrian. The sound / image output section 12052 may also control the display section 12062 so that an icon or the like representing the pedestrian is displayed at a desired position.

[0152] An example of the vehicle control system to which the technology according to the present disclosure can be applied is described above. The technique according to the present disclosure can be applied to the imaging section 12031 and the like in the configuration described above. Specifically, the electronic apparatus 1 or the distance measuring device 11 in Fig. 1 can be applied as the imaging section 12031. The imaging section 12031 is, for example, an LIDAR, and is used for detecting an object around the vehicle 12100 and a distance to the object. By applying the technology according to the present disclosure to the imaging section 12031, detection accuracy of an object and a distance to the object around the vehicle 12100 is improved. As a result, for example, a vehicle collision warning can be performed at an appropriate timing, and a traffic accident can be prevented.

[0153] In the above-described example, the pixel cross-sectional structure in which the first conductivity type is the P-type, the second conductivity type is the N-type, and electrons are signal charges is described, but the present disclosure can also be applied to a pixel cross-sectional structure in which positive holes are signal charges. That is, the first conductivity type may be the N-type, the second conductivity type may be the P-type, and the conductivity types of the above-described respective semiconductor regions may be reversed.

[0154] Note that, in the present specification, a system means an assembly of a plurality of components (devices, modules (parts), and the like), and it does not matter whether or not all the components are located in the same housing. Therefore, a plurality of devices housed in separate housings and connected to each other via a network and one device in which a plurality of modules is housed in one housing are both systems.

[0155] The embodiment of the technology of the present disclosure is not limited to the above-described embodiments and various modifications may be made without departing from the gist of the technology of the present disclosure.

[0156] The effects described in the present specification are merely examples and are not limited, and effects other than those described in the present specification may be provided.

[0157] Note that the technology of the present disclosure can have the following configurations.

[0158] It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.

[0159] 1 Electronic apparatus 11 Distance measuring device 21 Control section 22 Light source device 23 Light detection device 30 Object 31 Radiation light 32 Reflected light 51 First substrate 52 Second substrate 53 Third substrate 71 Pixel sensor unit 72 Pixel array region 81 Pixel readout circuit 82 Pixel array lower region 91 Processing circuit 92 Pixel array lower region 102 Transistor 103 Inverter 104 Level down unit 105 Circuit 111 Latch circuit 112 Inverter 113 Switch 141 Semiconductor substrate 142 Wiring layer 143 On-chip lens 151 N well 152 P-type diffusion layer 153 N-type diffusion layer 154 Hole accumulation layer 155 High-concentration P-type diffusion layer 156 Avalanche multiplication region 301 (301-1 to 301-R) Logic circuit (first logic circuit) 311 Logic circuit (second logic circuit) 312 Array driving unit 313 Distance measurement control section 314 Clock generation unit 315 I / F unit 316 Memory 317 Reference current source 318 Thermometer 333 TDC result calculation unit 334 Histogram generation unit 335 Distance calculation unit 336 Control section 341 Metal wire 351 Decoder unit 352 Counter unit 353 Readout unit 401 Connection unit 411 Repeating unit

Claims

1. A light detection device comprising: a plurality of pixels that are two-dimensionally arranged in a first matrix and in a pixel region, the plurality of pixels is configured to detect light; a plurality of logic circuits; and a plurality of readout circuits that are two-dimensionally arranged in a second matrix, wherein, in a plan view, a first logic circuit of the plurality of logic circuits overlaps at least one pixel of the plurality of pixels of the pixel region, and wherein, in the plan view, a second logic circuit of the plurality of logic circuits is arranged outside of the pixel region.

2. The light detection device according to claim 1, wherein, in the plan view, two or more logic circuits of the plurality of logic circuits is outside of the pixel region, the two or more logic circuits include the second logic circuit.

3. The light detection device according to claim 1, wherein the second logic circuit of the plurality of logic circuits includes a multiplexer, a time to digital converter (TDC), or a combination thereof, and wherein the first logic circuit of the plurality of logic circuits includes a TDC result calculation circuitry, a histogram generation circuitry, a distance calculation circuitry, a control circuitry, or a combination thereof.

4. The light detection device according to claim 3, wherein the histogram generation circuitry includes a decoder circuitry, a counter circuitry, and a readout circuitry.

5. The light detection device according to claim 1, wherein the plurality of pixels disposed on a first substrate, and wherein the plurality of logic circuits and the plurality of readout circuits are disposed on a second substrate that is distinct from the first substrate.

6. The light detection device according to claim 1, wherein each readout circuit of the plurality of readout circuits is centered in at least one of the two dimensions with respect to one pixel of the plurality of pixels.

7. The light detection device according to claim 1, wherein each readout circuit of the plurality of readout circuits is offset from a center in at least one of the two dimensions with respect to one pixel of the plurality of pixels.

8. The light detection device according to claim 1, wherein each readout circuit of the plurality of readout circuits is directly adjacent to a second readout circuit of the plurality of readout circuits in a first one of the two dimensions.

9. The light detection device according to claim 8, wherein a first portion of the plurality of readout circuits is directly adjacent to the second readout circuit and a third readout circuit of the plurality of readout circuits in the first one of the two dimensions.

10. The light detection device according to claim 9, wherein a second portion of the first portion is directly adjacent to a fourth readout circuit of the plurality of readout circuits in a second one of the two dimensions.

11. The light detection device according to claim 1, further comprising: a plurality of connection units that are two-dimensionally arranged in a third matrix, wherein each connection unit of the plurality of connection units is centered in both of the two dimensions with respect to one pixel of the plurality of pixels.

12. The light detection device according to claim 1, further comprising: a plurality of connection units that are two-dimensionally arranged in a third matrix, wherein each connection unit of the plurality of connection units is centered in only one of the two dimensions with respect to one pixel of the plurality of pixels.

13. The light detection device according to claim 1, wherein four pixels of the plurality of pixels corresponds to only one of the plurality of readout circuits.

14. The light detection device according to claim 13, wherein the four pixels are connected in series with each other.

15. The light detection device according to claim 13, wherein a first pair of the four pixels are connected in series with each other, wherein a second pair of the four pixels are connected in series with each other, and wherein the first pair is connected in parallel to the second pair.

16. The light detection device according to claim 1, further comprising: a third logic circuit that is distinct from the plurality of logic circuits and is arranged in the pixel region, wherein the plurality of logic circuits includes a first plurality of first logic circuits and a second plurality of first logic circuits, and wherein the first plurality and the second plurality are symmetrical with each other relative to the third logic circuit.

17. A light detection device comprising: a plurality of pixels that are two-dimensionally arranged in a first matrix and in a pixel region, the plurality of pixels is configured to detect light; a plurality of logic circuits, wherein a first portion of the plurality of logic circuits is within the pixel region, and wherein a second portion of the plurality of logic circuits is outside of the pixel region; and a plurality of readout circuits that are two-dimensionally arranged in a second matrix.

18. The light detection device according to claim 17, further comprising: a third logic circuit that is distinct from the plurality of logic circuits and is arranged in the pixel region, wherein the first portion and the second portion are symmetrical with each other relative to the third logic circuit.

19. A distance measuring device comprising: a light source device configured to emit light; and a light detection device including a plurality of pixels that are two-dimensionally arranged in a first matrix and in a pixel region, the plurality of pixels is configured to detect the light that is emitted by the light source device; a plurality of logic circuits; and a plurality of readout circuits that are two-dimensionally arranged in a second matrix, wherein, in a plan view, a first logic circuit of the plurality of logic circuits overlaps at least one pixel of the plurality of pixels of the pixel region, and wherein, in the plan view, a second logic circuit of the plurality of logic circuits is arranged outside of the pixel region.

20. The distance measuring device according to claim 19, wherein, in the plan view, two or more logic circuits of the plurality of logic circuits is outside of the pixel region, the two or more logic circuits include the second logic circuit.

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