Thin film capacitor
Patent Information
- Application Number
- PCT/JP2025/007872
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2024-03-08
- Filing Date
- 2025-03-05
- Publication Date
- 2025-10-02
AI Technical Summary
Existing thin film capacitors that divide input voltage by stacking multiple layers face the challenge of increasing thickness with the number of layers, compromising reliability and requiring a more compact design.
A thin film capacitor design with a laminated structure of conductor layers and dielectric film, incorporating overhanging portions and resin layers to enhance adhesion and dielectric strength, allowing for voltage division across multiple capacitors without significant thickness increase.
The design achieves high reliability and reduced overall thickness while effectively dividing input voltage across multiple capacitors, improving dielectric strength and maintaining a compact form factor.
Smart Images
Figure JP2025007872_02102025_PF_FP_ABST
Abstract
Description
thin film capacitor
[0001] The present disclosure relates to a thin film capacitor capable of dividing an input voltage.
[0002] Japanese Patent Application Laid-Open No. 2003-144222 discloses a voltage dividing capacitor that can divide an input voltage by stacking a plurality of thin film capacitors.
[0003] International Publication No. WO2024 / 177052
[0004] The voltage dividing capacitor disclosed in Patent Document 1 is formed by stacking a plurality of thin film capacitors, and therefore the greater the number of layers, the thicker the overall thickness becomes.
[0005] In this disclosure, a thin film capacitor is described that can divide an input voltage, has high reliability, and has a small overall thickness.
[0006] A thin film capacitor according to one aspect of the present disclosure includes a substrate including an insulating layer, a capacitor layer provided on the surface of the substrate, and a wiring layer including a resin layer provided on the surface of the substrate so as to embed the capacitor layer. The capacitor layer includes a first capacitance electrode layer located on the substrate side, a second capacitance electrode layer located on the wiring layer side, and a dielectric film located between the first capacitance electrode layer and the second capacitance electrode layer. The first capacitance electrode layer has a laminated structure including a first conductor layer located on the substrate side and a second conductor layer located on the dielectric film side. The second conductor layer has an overhanging portion that protrudes above the surface of the substrate without being laminated on the first conductor layer. A resin layer is embedded in a gap formed between the overhanging portion of the second metal layer and the substrate.
[0007] According to the present disclosure, a thin-film capacitor is provided that is capable of dividing an input voltage, has high reliability, and has a small overall thickness.
[0008] FIG. 1 is an equivalent circuit diagram of a thin film capacitor 100 according to a first embodiment of the technology disclosed herein. FIG. 2A is a schematic plan view of the thin film capacitor 100 according to the first embodiment. FIG. 2B is a schematic cross-sectional view of the thin film capacitor 100. FIGS. 3A to 3L are process diagrams for explaining a manufacturing method of the thin film capacitor 100 according to this embodiment. FIG. 4 is an equivalent circuit diagram of a thin film capacitor 200 according to a second embodiment of the technology disclosed herein. FIG. 5 is a schematic plan view of the thin film capacitor 200 according to the second embodiment.
[0009] Hereinafter, embodiments of the technology according to the present disclosure will be described in detail with reference to the accompanying drawings.
[0010] FIG. 1 is an equivalent circuit diagram of a thin film capacitor 100 according to a first embodiment of the technique of the present disclosure.
[0011] As shown in Figure 1, the thin film capacitor 100 according to the first embodiment has a circuit configuration in which capacitors C1 and C2 are connected in series between terminal electrodes P1 and P0, and capacitors C3 and C4 are connected in series between the terminal electrode P0 and a connection point P2 between capacitors C1 and C2. The terminal electrode P1 is an input terminal (IN), and the terminal electrode P0 is a ground terminal (GND). The connection point between capacitors C3 and C4 forms a terminal electrode P3 (OUT). A power supply IC 11 is connected between the terminal electrodes P1 and P0. An input capacitor 12 may be connected between the terminal electrodes P1 and P0.
[0012] The voltage V1 appearing at the connection point P2 is the level of the input voltage Vin divided by the capacitors C1 and C2. The output voltage V appearing at the terminal electrode P3, which is the output terminal (OUT), is ＤＩＶ is the level of voltage V1 further divided by capacitors C3 and C4. Therefore, if the capacitance is designed so that C1<C2, Vin / 2>V1, and it becomes possible to further reduce voltage V1. Also, if the capacitance is designed so that C3<C4, V1 / 2>V ＤＩＶ and the output voltage V ＤＩＶ It is possible to further reduce
[0013] Fig. 2A is a schematic plan view of the thin film capacitor 100 according to the first embodiment, and Fig. 2B is a schematic cross-sectional view of the thin film capacitor 100.
[0014] As shown in FIG. 2B, the thin film capacitor 100 according to this embodiment includes a substrate 170, a capacitor layer 180 provided on the surface of the substrate 170, and a wiring layer 190 covering the substrate 170 so as to embed the capacitor layer 180.
[0015] The substrate 170 includes an insulating layer 171 made of a prepreg or the like, and a copper foil 172 provided on the back surface of the insulating layer 171. The capacitor layer 180 includes capacitive electrode layers E0, E1, and E2, and a dielectric film D located between the capacitive electrode layers E1 and E2. The dielectric film D is made of a perovskite-based dielectric material such as barium titanate, and the capacitive electrode layers E0 and E1 are arranged on one surface D1, and the capacitive electrode layer E2 is arranged on the other surface D2.
[0016] The capacitive electrode layers E0 and E1 constitute the lower electrode of the capacitor. Of these, the capacitive electrode layer E0 constitutes a first conductor layer located on the substrate 170 side (insulating layer 171 side), and the capacitive electrode layer E1 constitutes a second conductor layer located on the dielectric film D side. In other words, the lower electrode of the capacitor has a laminated structure of the capacitive electrode layer E0, which is a first conductor layer, and the capacitive electrode layer E1, which is a second conductor layer. The capacitive electrode layer E2 constitutes the upper electrode of the capacitor. The capacitive electrode layers E0 and E2 are made of, for example, copper. The capacitive electrode layer E1 is made of, for example, nickel. Of the capacitive electrode layers E0 and E1, which are conductor layers that constitute the lower electrode of the capacitor, the capacitive electrode layer E0 is located on the substrate 170 side and is in contact with the resin layer 171. Of the capacitive electrode layers E0 and E1, which are conductor layers that constitute the lower electrode of the capacitor, the capacitive electrode layer E1 is located on the dielectric film D side and is in contact with the dielectric film D. The capacitive electrode layer E0 may be thinner than the capacitive electrode layer E1. For example, the thickness of the capacitive electrode layer E0 is 1 μm, and the thickness of the capacitive electrode layer E1 is 15 μm.
[0017] The wiring layer 190 includes a resin layer 191, a wiring pattern 192, and via conductors 193 and 194 embedded in the resin layer 191. A terminal electrode P1 (IN), a terminal electrode P3 (OUT), and a terminal electrode P0 (GND) are provided on the surface of the resin layer 191 that constitutes the wiring layer 190.
[0018] The electrode pattern 111a included in the capacitive electrode layer E0 and the electrode pattern 111b included in the capacitive electrode layer E1 constitute the electrode pattern 111, which is the lower electrode of the capacitor C1. The electrode pattern 112 included in the capacitive electrode layer E2 constitutes the upper electrode of the capacitor C1. The electrode patterns 111 and 112 and the dielectric film D located between them constitute the capacitor C1.
[0019] The electrode pattern 121a included in the capacitive electrode layer E0 and the electrode pattern 121b included in the capacitive electrode layer E1 constitute an electrode pattern 121, which is the lower electrode of capacitors C2 and C4. The electrode pattern 122 included in the capacitive electrode layer E2 constitutes the upper electrode of capacitor C2. The electrode pattern 124 included in the capacitive electrode layer E2 constitutes the upper electrode of capacitor C4. The electrode patterns 121 and 122 and the dielectric film D located between them constitute capacitor C2. The electrode patterns 121 and 142 and the dielectric film D located between them constitute capacitor C4.
[0020] The electrode pattern 131a included in the capacitive electrode layer E0 and the electrode pattern 131b included in the capacitive electrode layer E1 constitute an electrode pattern 131, which is the lower electrode of the capacitor C3. The electrode pattern 132 included in the capacitive electrode layer E2 constitutes the upper electrode of the capacitor C3. The electrode patterns 131 and 132 and the dielectric film D located between them constitute the capacitor C3.
[0021] The electrode patterns 111, 121, and 131 are separated from one another on the surface D1 of the dielectric film D. The electrode pattern 121 is a first electrode pattern, the electrode pattern 111 is a second electrode pattern, and the electrode pattern 131 is a fifth electrode pattern. The electrode patterns 112, 122, 132, and 142 are separated from one another on the surface D2 of the dielectric film D. The electrode pattern 112 is a third electrode pattern, the electrode pattern 122 is a fourth electrode pattern, the electrode pattern 132 is a sixth electrode pattern, and the electrode pattern 142 is a seventh electrode pattern.
[0022] 2A, electrode pattern 111, which is the lower electrode of capacitor C1, is surrounded by electrode patterns 121, which are the lower electrodes of capacitors C2 and C4, and is separated from electrode pattern 121 by a slit SL1. Also, electrode pattern 131, which is the lower electrode of capacitor C3, is surrounded by electrode patterns 121, which are the lower electrodes of capacitors C2 and C4, and is separated from electrode pattern 121 by a slit SL3.
[0023] 2A , the entire electrode pattern 112 overlaps with the electrode pattern 111, and the entire electrode pattern 122 overlaps with the electrode pattern 121. This allows the capacitance of capacitor C1 to be adjusted by the area of electrode pattern 112, and the capacitance of capacitor C2 to be adjusted by the area of electrode pattern 122. In the example shown in FIG. 2A , the area of electrode pattern 122 is larger than the area of electrode pattern 112, and therefore the capacitance of capacitor C2 is larger than the capacitance of capacitor C1.
[0024] 2A , the entire electrode pattern 132 overlaps with the electrode pattern 131, and the entire electrode pattern 142 overlaps with the electrode pattern 121. This allows the capacitance of capacitor C3 to be adjusted by the area of electrode pattern 132, and the capacitance of capacitor C4 to be adjusted by the area of electrode pattern 142. In the example shown in FIG. 2A , the area of electrode pattern 142 is larger than the area of electrode pattern 132, and therefore the capacitance of capacitor C4 is larger than the capacitance of capacitor C3.
[0025] Electrode pattern 112, which is the upper electrode of capacitor C1, is connected to terminal electrode P1 (IN) via via conductor 193, wiring pattern 192, and via conductor 194. Electrode pattern 111, which is the lower electrode of capacitor C1, is connected to electrode pattern 122, which is the upper electrode of capacitor C2, and to electrode pattern 132, which is the upper electrode of capacitor C3, via connection point P2. Electrode pattern 131, which is the lower electrode of capacitor C3, is connected to electrode pattern 142, which is the upper electrode of capacitor C4, and to terminal electrode P3 (OUT) via via conductor 193, wiring pattern 192, and via conductor 194. Electrode pattern 121, which is the lower electrode of capacitors C2 and C4, is connected to terminal electrode P0 (GND) via via conductor 193, wiring pattern 192, and via conductor 194.
[0026] The above configuration realizes the circuit shown in Fig. 1. When the terminal electrode P0 is connected to the ground and the input voltage Vin is supplied to the terminal electrode P1, the voltage V1 obtained by dividing the input voltage Vin appears at the connection point P2, and the output voltage V1 obtained by dividing the voltage V1 appears at the terminal electrode P3. ＤＩＶ appears.
[0027] In this way, the thin film capacitor 100 according to the present embodiment divides the input voltage Vin using two capacitors C1 and C2, and further divides the voltage V1 using another two capacitors C3 and C4. Therefore, even if the input voltage Vin is high, a low output voltage V ＤＩＶMoreover, since the four capacitors C1 to C4 are arranged horizontally, the total thickness is the same as that of a single capacitor.
[0028] 2B , in the capacitive electrode layer E1, ends of the electrode patterns 111b and 121b constituting the slit SL1 are not laminated on the capacitive electrode layer E0, but form an overhanging portion H1 that protrudes above the surface of the insulating layer 171 that constitutes the substrate 170. As a result, a gap G1 is formed between the overhanging portion H1 of the capacitive electrode layer E1 and the insulating layer 171 that constitutes the substrate 170. When the width W1a of the slit SL1 between the electrode patterns 111a and 121a located on the capacitive electrode layer E0 is taken as W1a and the width W1b between the electrode patterns 111b and 121b located on the capacitive electrode layer E1 is taken as W1a, W1a > W1b.
[0029] Similarly, in the capacitive electrode layer E1, ends of the electrode patterns 121b and 131b constituting the slit SL3 are not laminated on the capacitive electrode layer E0, but form an overhanging portion H3 that protrudes above the surface of the insulating layer 171 constituting the substrate 170. As a result, a gap G3 is formed between the overhanging portion H3 of the capacitive electrode layer E1 and the insulating layer 171 constituting the substrate 170. When the width W3a of the slit SL3 between the electrode patterns 121a and 131a located on the capacitive electrode layer E0 and the width W3b between the electrode patterns 121b and 131b located on the capacitive electrode layer E1 are set to W3a > W3b.
[0030] The gaps G1 and G3 are filled with a resin layer 191. The resin layer 191 filled in the gaps G1 and G3 provides an anchor effect, which improves the adhesion between the capacitor layer 180 and the wiring layer 190.
[0031] The widths W1a and W1b of the slit SL1 may be wider than the widths W3a and W3b of the slit SL3. The widths W1a and W1b of the slit SL1 and the widths W3a and W1b of the slit SL3 may be defined by the minimum width or the average width.
[0032] Here, when terminal electrode P0 is grounded and input voltage Vin is supplied to terminal electrode P1, ground potential (GND) is applied to electrode pattern 121, which is the lower electrode of capacitors C2 and C4, voltage V1 is applied to electrode pattern 111, which is the lower electrode of capacitor C1, and output voltage V2 is applied to electrode pattern 131, which is the lower electrode of capacitor C3. Therefore, a voltage equivalent to V1-GND is generated between electrode pattern 111 and electrode pattern 121, and a voltage equivalent to V2-GND is generated between electrode pattern 131 and electrode pattern 121. Here, since V1 > V2, the voltage generated between electrode pattern 111 and electrode pattern 121 is greater than the voltage generated between electrode pattern 131 and electrode pattern 121.
[0033] Taking this into consideration, the widths W1a and W1b of the slit SL1 separating the electrode pattern 111 and the electrode pattern 121 may be designed to be larger than the widths W3a and W3b of the slit SL3 separating the electrode pattern 131 and the electrode pattern 121. This increases the dielectric strength between the electrode pattern 111 and the electrode pattern 121, thereby improving product reliability. In particular, when the electrode pattern 111 is surrounded by the electrode pattern 121, as in the example shown in FIG. 2A , the section in which the electrode pattern 111 and the electrode pattern 121 are close to each other becomes longer. Therefore, increasing the widths W1a and W1b of the slit SL1, as in this embodiment, significantly improves reliability. On the other hand, by designing the widths W3a and W1b of the slit SL3 separating the electrode pattern 131 and the electrode pattern 121 to be smaller than the widths W1a and W1b of the slit SL1, the planar size of the product can be reduced.
[0034] 3A to 3L are process diagrams illustrating a method for manufacturing the thin film capacitor 100 according to this embodiment.
[0035] First, as shown in Fig. 3A, a capacitor layer 180 having a structure in which capacitive electrode layers E0 and E1, a dielectric film D, and a capacitive electrode layer E2 are stacked is prepared. Next, as shown in Fig. 3B, an insulating layer 171 made of prepreg or the like is sandwiched between the capacitor layer 180 and copper foil 172. As a result, the capacitive electrode layers E0 and E1 of the capacitor layer 180 are covered with the base material 170, as shown in Fig. 3C.
[0036] Next, as shown in Fig. 3D, a laminate of substrate 170 and capacitor layer 180 is fixed to support 101 made of ceramic or the like via adhesive layer 102. Next, as shown in Fig. 3E, capacitive electrode layer E2 is patterned to divide it into electrode patterns 112, 122, 132, and 142 shown in Fig. 2A. Next, as shown in Fig. 3F, dielectric film D is patterned.
[0037] Next, as shown in FIG. 3G, the capacitive electrode layers E0 and E1 are patterned to divide the capacitive electrode layers E0 and E1 into the electrode patterns 111, 121, and 131 shown in FIG. 2A. The capacitive electrode layers E0 and E1 are patterned under conditions in which the etching rate for the capacitive electrode layer E0 made of, for example, copper is higher than the etching rate for the capacitive electrode layer E1 made of, for example, nickel. As a result, the etching amount in the planar direction is greater for the capacitive electrode layer E0 made of, for example, copper than for the capacitive electrode layer E1 made of, for example, nickel. As a result, an overhanging portion H1 is formed in the capacitive electrode layer E1 that constitutes the slit SL1, and an overhanging portion H3 is formed in the capacitive electrode layer E1 that constitutes the slit SL3. In other words, a structure in which W1a > W1b and W3a > W3b is obtained.
[0038] Next, as shown in FIG. 3H, the capacitor layer 180 is covered with a resin layer 191a. The resin layer 191a is part of the resin layer 191 shown in FIG. 2B. As a result, the gaps G1 and G3 formed between the overhanging portions H1 and H3 and the insulating layer 171 constituting the base material 170 are filled with the resin layer 191a. Next, as shown in FIG. 3I, via conductors 193 that penetrate the resin layer 191a and are connected to the capacitive electrode layers E0 to E2, and wiring patterns 192 connected to the via conductors 193 are formed.
[0039] Next, as shown in FIG. 3J, the surface of the resin layer 191a on which the wiring pattern 192 is provided is covered with another resin layer 191b, and then another via conductor 194 that penetrates the other resin layer 191b and is connected to the wiring pattern 192, and terminal electrodes P0, P1, and P3 that are connected to the other via conductor 194, are formed. The resin layer 191b is another part of the resin layer 191 shown in FIG. 2B. Next, as shown in FIG. 3K, the support 101 is peeled off, and gold plating M is applied to the surfaces of the terminal electrodes P0, P1, and P3. Then, as shown in FIG. 3L, the laminate consisting of the base material 170, the capacitor layer 180, and the wiring layer 190 is cut along the dicing lines L, thereby completing the thin-film capacitor 100 according to this embodiment.
[0040] FIG. 4 is an equivalent circuit diagram of a thin film capacitor 200 according to the second embodiment of the technique of the present disclosure.
[0041] 4, the thin film capacitor 200 according to the second embodiment differs from the thin film capacitor 100 according to the first embodiment in that capacitors C5 and C6 connected in series between the connection point P3 and the terminal electrode P0 are further added. The other circuit configurations are the same as those of the thin film capacitor 100 according to the first embodiment.
[0042] Capacitors C1 and C2 are connected in series between terminal electrode P1, which is the input terminal (IN), and terminal electrode P0, which is the ground terminal (GND). As a result, the voltage V1 appearing at node P2 between capacitors C1 and C2 is at a level obtained by dividing the input voltage Vin by capacitors C1 and C2. Capacitors C3 and C4 are connected in series between node P2 and terminal electrode P0, which is the ground terminal (GND). As a result, the voltage V2 appearing at node P3 between capacitors C3 and C4 is at a level obtained by further dividing voltage V1 by capacitors C3 and C4. Capacitors C5 and C6 are connected in series between node P3 and terminal electrode P0, which is the ground terminal (GND). As a result, the output voltage V ＤＩＶis at a level obtained by further dividing the voltage V2 by the capacitors C5 and C6.
[0043] When the voltage division ratio between capacitors C1 and C2, the voltage division ratio between capacitors C3 and C4, and the voltage division ratio between capacitors C5 and C6 are all N, the total voltage division ratio is N ３ Therefore, the output voltage V ＤＩＶ is Vin / N ３ That is, voltage V1=Vin / N, voltage V2=V1 / N, output voltage V ＤＩＶ = V2 / N.
[0044] Here, if the voltage division ratio between the capacitors C1 and C2 is N1, the voltage division ratio between the capacitors C3 and C4 is N2, and the voltage division ratio between the capacitors C5 and C6 is N3, some or all of the voltage division ratios N1, N2, and N3 may be different. ＤＩＶ is Vin / (N1·N2·N3). That is, voltage V1=Vin / N1, voltage V2=V1 / N2, and output voltage V ＤＩＶ = V2 / N3.
[0045] Therefore, if the capacitance is designed so that C1<C2, the capacitance is designed so that C3<C3, and the capacitance is designed so that C5<C6, then the output voltage V ＤＩＶ It is possible to further reduce the
[0046] FIG. 5 is a schematic plan view of a thin film capacitor 200 according to the second embodiment.
[0047] 5 , in the thin film capacitor 200 according to the second embodiment, the capacitive electrode layers E0 and E1 further include an electrode pattern 151, and the capacitive electrode layer E2 further includes electrode patterns 152 and 162. The electrode patterns 151 and 152 and the dielectric film D located between the electrode patterns 151 and 152 form a capacitor C5. The electrode patterns 121 and 162 and the dielectric film D located between the electrode patterns 121 and 162 form a capacitor C6. The electrode patterns 111, 121, 131, and 151 are separated from one another on the surface D1 of the dielectric film D. The electrode patterns 112, 122, 132, 142, 152, and 162 are separated from one another on the surface D2 of the dielectric film D. The electrode pattern 151 is the eighth electrode pattern, the electrode pattern 152 is the ninth electrode pattern, and the electrode pattern 162 is the tenth electrode pattern.
[0048] 5, electrode pattern 111, which is the lower electrode of capacitor C1, is surrounded by electrode patterns 121, which are the lower electrodes of capacitors C2, C4, and C6, and is separated from electrode pattern 121 by slit SL1. Electrode pattern 131, which is the lower electrode of capacitor C3, is surrounded by electrode patterns 121, which are the lower electrodes of capacitors C2, C4, and C6, and is separated from electrode pattern 121 by slit SL3. Electrode pattern 151, which is the lower electrode of capacitor C5, is surrounded by electrode patterns 121, which are the lower electrodes of capacitors C2, C4, and C6, and is separated from electrode pattern 121 by slit SL5.
[0049] The ends of the electrode patterns 111 and 121 that form the slit SL1 have the overhanging portions H1 shown in Fig. 2B. The ends of the electrode patterns 121 and 131 that form the slit SL3 have the overhanging portions H3 shown in Fig. 2B. The ends of the electrode patterns 121 and 151 that form the slit SL5 have overhanging portions (not shown).
[0050] The width W1 of the slit SL1 may be wider than the width W3 of the slit SL3 and may be wider than the width W5 of the slit SL5. The width W5 of the slit SL5 may be the same as the width W3 of the slit SL3, or may be narrower than the width W3 of the slit SL3. The width W1 of the slit SL1, the width W3 of the slit SL3, and the width W5 of the slit SL5 may be defined by a minimum width or an average width.
[0051] 5, the entire electrode pattern 152 overlaps with the electrode pattern 151, and the entire electrode pattern 162 overlaps with the electrode pattern 161. This allows the capacitance of capacitor C5 to be adjusted by the area of electrode pattern 152, and the capacitance of capacitor C6 to be adjusted by the area of electrode pattern 162. In the example shown in Fig. 5, the area of electrode pattern 162 is larger than the area of electrode pattern 152, and therefore the capacitance of capacitor C6 is larger than the capacitance of capacitor C5.
[0052] Electrode pattern 112, which is the upper electrode of capacitor C1, is connected to terminal electrode P1 (IN). Electrode pattern 111, which is the lower electrode of capacitor C1, is connected to electrode pattern 122, which is the upper electrode of capacitor C2, and to electrode pattern 132, which is the upper electrode of capacitor C3, via connection point P2. Electrode pattern 131, which is the lower electrode of capacitor C3, is connected to electrode pattern 142, which is the upper electrode of capacitor C4, and to electrode pattern 152, which is the upper electrode of capacitor C5, via connection point P3. Electrode pattern 151, which is the lower electrode of capacitor C5, is connected to electrode pattern 162, which is the upper electrode of capacitor C6, and to terminal electrode P4 (OUT). Electrode pattern 121, which is the lower electrode of capacitors C2, C4, and C6, is connected to terminal electrode P0 (GND).
[0053] The above configuration realizes the circuit shown in Fig. 4. When the terminal electrode P0 is connected to the ground and the input voltage Vin is supplied to the terminal electrode P1, the voltage V1 obtained by dividing the input voltage Vin appears at the connection point P2, the voltage V2 obtained by dividing the voltage V1 appears at the connection point P3, and the output voltage V2 obtained by dividing the voltage V2 appears at the terminal electrode P4. ＤＩＶ appears.
[0054] In this way, the thin film capacitor 200 according to the present embodiment divides the input voltage Vin using two capacitors C1 and C2, further divides the voltage V1 using two other capacitors C3 and C4, and further divides the voltage V2 using two other capacitors C5 and C6. Therefore, even if the input voltage Vin is higher, a lower output voltage V ＤＩＶ Moreover, since the six capacitors C1 to C6 are arranged horizontally, the total thickness is the same as that of a single capacitor.
[0055] Furthermore, when terminal electrode P0 is grounded and input voltage Vin is supplied to terminal electrode P1, ground potential (GND) is applied to electrode pattern 121, which is the lower electrode of capacitors C2, C4, and C6, voltage V1 is applied to electrode pattern 111, which is the lower electrode of capacitor C1, output voltage V2 is applied to electrode pattern 131, which is the lower electrode of capacitor C3, and output voltage V3 is applied to electrode pattern 151, which is the lower electrode of capacitor C5. Therefore, a voltage equivalent to V1-GND is generated between electrode pattern 111 and electrode pattern 121, a voltage equivalent to V2-GND is generated between electrode pattern 131 and electrode pattern 121, and a voltage equivalent to V3-GND is generated between electrode pattern 151 and electrode pattern 121. Here, since V1>V2>V3, the voltage generated between electrode pattern 111 and electrode pattern 121 is greater than the voltage generated between electrode pattern 131 and electrode pattern 121, and is also greater than the voltage generated between electrode pattern 151 and electrode pattern 121.
[0056] Taking this into consideration, the width W1 of the slit SL1 separating the electrode pattern 111 from the electrode pattern 121 may be designed to be larger than the width W3 of the slit SL3 separating the electrode pattern 131 from the electrode pattern 121 and the width W5 of the slit SL5 separating the electrode pattern 151 from the electrode pattern 121. This increases the dielectric strength between the electrode pattern 111 and the electrode pattern 121, thereby improving product reliability. In particular, when the electrode pattern 111 is surrounded by the electrode pattern 121, as in the example shown in FIG. 5 , the section in which the electrode pattern 111 and the electrode pattern 121 are close to each other becomes longer. Therefore, increasing the width W1 of the slit SL1, as in this embodiment, significantly improves reliability. On the other hand, the width W3 of the slit SL3 separating the electrode pattern 131 from the electrode pattern 121 and the width W5 of the slit SL5 separating the electrode pattern 151 from the electrode pattern 121 can be designed to be smaller than the width W1 of the slit SL1, thereby enabling the planar size of the product to be reduced.
[0057] The above describes embodiments of the technology according to the present disclosure, but the technology according to the present disclosure is not limited to the above embodiments, and various modifications are possible within the scope of the gist of the technology, and it goes without saying that these modifications are also included within the scope of the technology according to the present disclosure.
[0058] The technology according to the present disclosure includes, but is not limited to, the following configuration examples.
[0059] A thin film capacitor according to one aspect of the present disclosure includes a substrate including an insulating layer, a capacitor layer provided on the surface of the substrate, and a wiring layer including a resin layer provided on the surface of the substrate so as to embed the capacitor layer. The capacitor layer includes a first capacitance electrode layer located on the substrate side, a second capacitance electrode layer located on the wiring layer side, and a dielectric film located between the first capacitance electrode layer and the second capacitance electrode layer. The first capacitance electrode layer has a laminated structure including a first conductor layer located on the substrate side and a second conductor layer located on the dielectric film side. The second conductor layer has an overhanging portion that protrudes above the surface of the substrate without being stacked on the first conductor layer. A resin layer is embedded in the gap formed between the overhanging portion of the second metal layer and the substrate. This enhances adhesion between the capacitor layer and the wiring layer due to the anchor effect.
[0060] In the above-mentioned thin film capacitor, the wiring layer further includes a wiring pattern at least a portion of which is embedded in the resin layer, the first capacitance electrode layer includes a first electrode pattern and a second electrode pattern separated from the first electrode pattern by a first slit, the second capacitance electrode layer includes a third electrode pattern overlapping the second electrode pattern via a dielectric film and a fourth electrode pattern overlapping the first electrode pattern via the dielectric film, the second electrode pattern is connected to the fourth electrode pattern via a wiring pattern, and ends of the first electrode pattern and the second electrode pattern that form the first slit may have overhanging shapes. This enables voltage division of an input voltage by the first capacitor including the second and third electrode patterns and the second capacitor including the first and fourth electrode patterns.
[0061] In the above-described thin film capacitor, the fourth electrode pattern may be larger than the third electrode pattern, which makes it possible to increase the voltage division ratio.
[0062] In the above-mentioned thin film capacitor, the first capacitive electrode layer further includes a fifth electrode pattern separated from the first electrode pattern by a second slit, the second capacitive electrode layer further includes a sixth electrode pattern overlapping the fifth electrode pattern via a dielectric film and a seventh electrode pattern overlapping the first electrode pattern via a dielectric film, the second electrode pattern is further connected to the sixth electrode pattern via a wiring pattern, the fifth electrode pattern is connected to the seventh electrode pattern via a wiring pattern, and ends of the first electrode pattern and the fifth electrode pattern constituting the second slit may have overhanging shapes. This allows an input voltage to be divided in one stage by the first capacitor including the second and third electrode patterns and the second capacitor including the first and fourth electrode patterns, and allows the internal voltage divided in one stage to be further divided into two stages by the third capacitor including the fifth and sixth electrode patterns and the fourth capacitor including the first and seventh electrode patterns.
[0063] The thin film capacitor may further include a first terminal electrode provided on the resin layer and connected to the third electrode pattern, a second terminal electrode provided on the resin layer and connected to the seventh electrode pattern, and a third terminal electrode provided on the resin layer and connected to the first electrode pattern. In this way, by applying an input voltage between the first terminal electrode and the third terminal electrode, it is possible to obtain a divided output voltage from the second terminal electrode.
[0064] In the above-described thin film capacitor, the fourth electrode pattern may be larger than the third electrode pattern. This increases the voltage division ratio, thereby enabling a further reduction in the output voltage output from the second terminal electrode. In this case, the seventh electrode pattern may be larger than the sixth electrode pattern. This increases the voltage division ratio, thereby enabling a further reduction in the output voltage output from the second terminal electrode.
[0065] In the above thin film capacitor, the slit width of the first slit may be wider than the slit width of the second slit, thereby increasing the dielectric strength between the first electrode pattern and the second electrode pattern.
[0066] In the above-mentioned thin film capacitor, the first capacitive electrode layer further includes an eighth electrode pattern separated from the first electrode pattern via a third slit, the second capacitive electrode layer further includes a ninth electrode pattern overlapping the eighth electrode pattern via a dielectric film and a tenth electrode pattern overlapping the first electrode pattern via a dielectric film, the fifth electrode pattern is further connected to the ninth electrode pattern via a wiring pattern, the eighth electrode pattern is connected to the tenth electrode pattern via a wiring pattern, and the ends of the first electrode pattern and the eighth electrode pattern that form the third slit may have overhanging portions. According to this, the input voltage can be divided into one stage by the first capacitor including the second and third electrode patterns and the second capacitor including the first and fourth electrode patterns, and the internal voltage divided into one stage can be further divided into two stages by the third capacitor including the fifth and sixth electrode patterns and the fourth capacitor including the first and seventh electrode patterns, and further the internal voltage divided into two stages can be further divided into three stages by the fifth capacitor including the eighth and ninth electrode patterns and the sixth capacitor including the first and tenth electrode patterns.
[0067] In the above thin film capacitor, the slit width of the first slit may be wider than the slit width of the third slit, thereby increasing the dielectric strength between the first electrode pattern and the second electrode pattern.
[0068] The thin film capacitor may further include a first terminal electrode provided on the resin layer and connected to the third electrode pattern, a second terminal electrode provided on the resin layer and connected to the tenth electrode pattern, and a third terminal electrode provided on the resin layer and connected to the first electrode pattern. In this way, by applying an input voltage between the first terminal electrode and the third terminal electrode, it is possible to obtain a divided output voltage from the second terminal electrode.
[0069] In the above-described thin film capacitor, the fourth electrode pattern may be larger than the third electrode pattern. This increases the voltage division ratio, thereby enabling a further reduction in the output voltage output from the second terminal electrode. In this case, the seventh electrode pattern may be larger than the sixth electrode pattern. This increases the voltage division ratio, thereby enabling a further reduction in the output voltage output from the second terminal electrode. In this case, the tenth electrode pattern may be larger than the ninth electrode pattern. This increases the voltage division ratio, thereby enabling a further reduction in the output voltage output from the second terminal electrode.
[0070] This application claims the benefit of U.S. Provisional Application No. 63 / 563,153, filed March 8, 2024, the entire disclosure of which is incorporated herein by reference.
[0071] 11 Power supply IC 12 Input capacitor 100, 200 Thin film capacitor 101 Support 102 Adhesive layer 111, 111a, 111b, 112, 121, 121a, 121b, 122, 131, 131a, 131b, 132, 142, 151, 152, 162 Electrode pattern 170 Base material 171 Insulating layer 172 Copper foil 180 Capacitor layer 190 Wiring layer 191, 191a, 191b Resin layer 192 Wiring pattern 193, 194 Via conductor C1 to C6 Capacitor D Dielectric film D1, D2 Surface E0, E1, E2 Capacitor electrode layer G1, G3 Gap H1, H3 Overhang shape portion L Dicing line M Gold plating P0, P1, P4 Terminal electrode P2 Connection point P3 Terminal electrode (connection point) SL1, SL3, SL5 Slit
Claims
1. A thin film capacitor comprising: a substrate including an insulating layer; a capacitor layer provided on the surface of the substrate; and a wiring layer including a resin layer provided on the surface of the substrate so as to embed the capacitor layer, wherein the capacitor layer includes a first capacitance electrode layer located on the substrate side, a second capacitance electrode layer located on the wiring layer side, and a dielectric film located between the first capacitance electrode layer and the second capacitance electrode layer, the first capacitance electrode layer having a layered structure including a first conductor layer located on the substrate side and a second conductor layer located on the dielectric film side, the second conductor layer having an overhanging portion protruding above the surface of the substrate without being layered on the first conductor layer, and the resin layer being embedded in a gap formed between the overhanging portion of the second metal layer and the substrate.
2. The thin film capacitor according to claim 1, wherein the wiring layer further includes a wiring pattern at least a portion of which is embedded in the resin layer, the first capacitance electrode layer includes a first electrode pattern and a second electrode pattern separated from the first electrode pattern by a first slit, the second capacitance electrode layer includes a third electrode pattern overlapping the second electrode pattern via the dielectric film and a fourth electrode pattern overlapping the first electrode pattern via the dielectric film, the second electrode pattern being connected to the fourth electrode pattern via the wiring pattern, and the ends of the first electrode pattern and the second electrode pattern which form the first slit have the overhanging portion.
3. The thin film capacitor according to claim 2, wherein the fourth electrode pattern is larger than the third electrode pattern.
4. The thin film capacitor of claim 2, wherein the first capacitive electrode layer further includes a fifth electrode pattern separated from the first electrode pattern via a second slit, the second capacitive electrode layer further includes a sixth electrode pattern overlapping the fifth electrode pattern via the dielectric film and a seventh electrode pattern overlapping the first electrode pattern via the dielectric film, the second electrode pattern is further connected to the sixth electrode pattern via the wiring pattern, the fifth electrode pattern is connected to the seventh electrode pattern via the wiring pattern, and the ends of the first electrode pattern and the fifth electrode pattern that form the second slit have the overhanging portion.
5. The thin film capacitor according to claim 4, further comprising: a first terminal electrode provided on the resin layer and connected to the third electrode pattern; a second terminal electrode provided on the resin layer and connected to the seventh electrode pattern; and a third terminal electrode provided on the resin layer and connected to the first electrode pattern.
6. The thin film capacitor according to claim 5, wherein the fourth electrode pattern is larger than the third electrode pattern.
7. The thin film capacitor according to claim 6, wherein the seventh electrode pattern is larger than the sixth electrode pattern.
8. The thin film capacitor according to claim 4, wherein the slit width of the first slit is wider than the slit width of the second slit.
9. The thin film capacitor of claim 4, wherein the first capacitive electrode layer further includes an eighth electrode pattern separated from the first electrode pattern via a third slit, the second capacitive electrode layer further includes a ninth electrode pattern overlapping the eighth electrode pattern via the dielectric film and a tenth electrode pattern overlapping the first electrode pattern via the dielectric film, the fifth electrode pattern is further connected to the ninth electrode pattern via the wiring pattern, the eighth electrode pattern is connected to the tenth electrode pattern via the wiring pattern, and the ends of the first electrode pattern and the eighth electrode pattern that form the third slit have the overhanging portion.
10. The thin film capacitor according to claim 9, wherein the slit width of the first slit is wider than the slit width of the third slit.
11. The thin film capacitor according to claim 9, further comprising: a first terminal electrode provided on the resin layer and connected to the third electrode pattern; a second terminal electrode provided on the resin layer and connected to the tenth electrode pattern; and a third terminal electrode provided on the resin layer and connected to the first electrode pattern.
12. A thin film capacitor according to any one of claims 9 to 11, wherein the fourth electrode pattern is larger than the third electrode pattern.
13. The thin film capacitor according to claim 12, wherein the seventh electrode pattern is larger than the sixth electrode pattern.
14. The thin film capacitor according to claim 13, wherein the tenth electrode pattern is larger than the ninth electrode pattern.