Non-invasive cache node power reduction

Abstract

Methods, systems, and apparatus for a computing device comprising; a caching subsystem comprising more than one cache nodes and a routing subsystem configured to operate in an intermediate dual hash mode while the caching subsystem modifies a subset of operational cache nodes.

Description

[0001] NON-INVASIVE CACHE NODE POWER REDUCTION

[0002] BACKGROUND

[0003] This specification relates to computational devices that employ a caching subsystem. Caching subsystems, which temporarily store frequently accessed data closer to the central processing unit (CPU), are often divided into multiple, semi-independent cache slices. Each cache slice holds a portion of the data stored in the caching subsystem and can increase the scalability and reduce the latency of memory' requests to the caching subsystem by executing memory requests directed at more than one cache slice in parallel.

[0004] The division of the caching subsystem into slices allows for an efficient distribution of data, but if the full capacity of the caching subsystem is underutilized, the caching subsy stem consumes more power than necessary' by operating a surplus of cache slices. In addition, the process of enabling and disabling cache slices requires a stoppage of memory access to the caching subsystem, leading to a degradation of overall system performance.

[0005] SUMMARY

[0006] This specification describes systems and methods for modifying a distribution of memory' requests to a set of cache slices (e.g., cache nodes) within a caching subsystem while minimizing disruption of memory requests to the caching subsystem from one or more processors. By operating in an intermediate mode during which a subset of cache nodes is flushing the respective stored data, the caching subsystem can minimize disruption to incoming memory requests. The caching subsystem can include more than one cache node, where each cache node stores a portion of cached data and multiple cache nodes can process memory requests simultaneously. Each cache node can require a certain amount of power to operate, and the ability to selectively power up and power down a subset of cache nodes according to a required amount of cache storage while minimizing disruption to memory' access can lead to a power-efficient and high-performing caching subsystem.

[0007] In some cases, the required amount of cache storage can change depending on requirements of the one or more processors that rely on the caching subsystem for quick access to stored data. For example, a particular program running on the one or more processors may require a subset of available cache nodes to operate efficiently. As another example, a particular program may require a full set of available cache nodes to operate efficiently. The caching subsystem can include a routing subsystem that can receive memory requests from the one or more processors. The routing subsystem can implement a hash function that can identify a target cache node for each incoming memory request, where the memory request can request data stored on the target cache node or the memory request can request to write data to the target cache node.

[0008] In some cases, the required amount of cache storage to service the one or more processors can change, and a cache mode controller can instruct the routing subsystem to temporarily operate in an intermediate dual hash mode while the caching subsystem modifies the subset of cache nodes that are available to store data and receive memory requests. While operating in the intermediate dual hash mode, the routing subsystem can reissue each incoming memory request to a cache node that will remain operational after the caching subsystem is finished modifying the subset of available cache nodes.

[0009] Particular embodiments of the subject matter described in this specification can be implemented as to realize one or more of the following advantages. By operating in an intermediate dual hash mode while modifying the set of operational cache nodes of a caching subsystem, the caching subsystem can transition to a lower power consumption mode while minimizing the amount of time that memory requests to the caching subsystem are stalled which speeds up the overall system performance.

[0010] The details of one or more embodiments of the subject matter of this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, the drawings, and the claims.

[0011] BRIEF DESCRIPTION OF THE DRAWINGS

[0012] FIG. 1 is an overview of an example system implementation.

[0013] FIG. 2 is an example process where a caching subsystem enters a partial single hash mode.

[0014] FIG. 3 depicts a caching subsystem that transitions from a full single hash mode to a partial single hash mode through an intermediate dual hash mode.

[0015] FIG. 4 is an example caching subsystem in a full single hash mode.

[0016] FIG. 5 is an example caching subsystem in an intermediate dual hash mode.

[0017] FIG. 6 is an example caching subsystem in a partial single hash mode. FIG. 7 illustrates a command protocol for a caching subsystem.

[0018] FIG. 8 depicts a detailed view of a caching subsystem.

[0019] FIG. 9 is an example process where a caching subsystem enters a full single hash mode. Like reference numbers and designations in the various drawings indicate like elements.

[0020] DETAILED DESCRIPTION

[0021] This specification describes a system that processes memory' requests between processors, e.g., central processing units (CPUs), and a caching subsystem. In some examples, the caching subsystem can include a single cache divided into multiple cache slices (e.g., cache nodes), where each cache slice stores a portion of the cached data. In some cases, the multiple cache slices can be underutilized, where an application may only require a subset of the cache slices to accommodate the memory requests from the CPUs. It can be desirable to power down a subset of cache slices to save power. The powering dow n or powering up of a subset of cache slices can be highly disruptive because memory' requests to the caching subsy stem must be paused during the powering down and powering up.

[0022] FIG. 1 is an overview of an example system that can distribute memory requests to multiple cache nodes, where the cache nodes can include one or more operational cache nodes, one or more transitioning cache nodes, and one or more non-operational cache nodes. The number of operational cache nodes can be modified by a cache mode controller while minimizing disruption to memory requests. An operational cache node is a cache node that accepts memory requests. A non-operational cache node is a powered-down cache node that does not accept memory requests. A transitioning cache node is a cache node that is transitioning between an operational state to anon-operational state or between a non- operational state to an operational state.

[0023] The system is an example of a system that includes N processors 100-106, a caching subsystem 110, and a cache mode controller 130. The caching subsystem 1 10 includes M cache nodes 112-1 18 and a data processing apparatus (i.e., a routing subsystem 120). Each of the N processors 100-106 (e.g., processor 100) can issue memory' requests to the caching subsy stem 110 over a communication channel (e.g., communication channel 108).

[0024] The routing subsystem 120 can process the memory requests from the N processors 100-106 and implement a hash function, or any other appropriate function for distributing memory requests, to determine which of the M cache nodes 112-118 should receive the memory' request. In some implementations, a processor can generate a memory address that corresponds to the location of the data to retrieve or to store in an underlying memory device beyond the caching subsystem 110. In some implementations, the routing subsystem 120 can process the memory address with the hash function to convert the memory address to a cache node identifier. The result of the hash function is an index or identifier that indicates which cache node the memory7address is associated with or which cache node the data associated with the corresponding memory address should be stored if it is not already stored in a cache node. In some implementations, in the case of a cache hit. e.g., the memory address is represented in a cache node, the data located at the memory^ address is retrieved through a communication line (e.g., communication line 122) and returned to the requesting processor. In the case of a cache miss, the data corresponding to the memory7address can be retrieved from a lower-level memory, e.g., the main memory, and then stored in the cache node identified by the hash function to service future requests for the data without re-reading from memory.

[0025] In some implementations, the M cache nodes 112-118 can include one or more non- operational cache nodes, one or more transitioning cache nodes, and one or more operational cache nodes. The cache mode controller 130 can send a request to the routing subsystem 120 to route to a different subset of cache nodes. In this case, the cache mode controller 130 can reconfigure the routing subsystem 120 to use a different hash function in order to direct incoming requests to a new subset of cache nodes. In other words, the cache mode controller 130 can reconfigure the routing subsystem 120 to use a hash function to target the new subset of cache nodes present in the caching subsystem 110.

[0026] FIG. 2 is a flow diagram of an example process that results in a reduction in the number of operational cache nodes. For convenience, the process will be described as being performed by a routing subsystem (e.g., the routing subsystem 120) configured to operate in accordance with this specification.

[0027] The routing subsystem can process (202) memory^ requests in a full single hash mode using a primary7hash function, or any other appropriate function for distributing memoryrequests. The routing subsystem, operating in the full single hash mode, can implement the primary hash function that routes each incoming memory request to one of the cache nodes of a caching subsystem (e.g., caching subsystem 110).

[0028] The routing subsystem can receive (204) a request to enter a partial single hash mode in which at least one cache node of the set of all cache nodes present in the caching subsystem is non-operational. This may occur if the caching subsystem is determined to be underutilized, leading to an opportunity for pow er savings. In some implementations, the request can be sent by a processor acting as a cache mode controller (e.g., cache mode controller 130).

[0029] The routing subsystem can enter (206) an intermediate dual hash mode during which each memory request is routed to a cache node with the primary hash function then reissued and routed with a secondary hash function, or any other appropriate function for distributing memory requests. While operating in the intermediate dual hash mode, the routing subsystem can convert each incoming memory request to two separate subsets of cache node identifiers using the appropriate hash function which can be the primary hash function or the secondary hash function. The primary hash function routes each memory request to the full set of cache nodes. The secondary' hash function routes each memory request to the subset of cache nodes corresponding to the request in relation to 204.

[0030] When the routing subsystem receives a memory request, the routing subsystem routes the memory request to the corresponding cache node. The corresponding cache node returns a resend message to the routing subsystem or issuing processor directing the processor to reissue the same memory’ request to one of the cache nodes that will remain operational after the transition using the secondary hash function. If the data corresponding to the memory request is not stored in the cache node corresponding to the route by the secondary hash function, the system can fetch the data from a lower-level memory' resource and store it in the corresponding cache node as defined by the secondary hash function for future use.

[0031] The routing subsystem can flush (208) the cache nodes while operating in the intermediate dual hash mode. The process of flushing all cache nodes is performed in the background, independent of any incoming memory requests. In addition, the system performs an immediate flush of a cache line when a corresponding memory' request is received.

[0032] The routing subsystem can enter (210) the partial single hash mode during which allocation of memory requests to cache nodes uses the secondary hash function as a primary hash function moving forward. Every memory' request from a processor can be converted to an identifier corresponding to one of the cache nodes that remain operational after the transition from the full single hash mode to the partial single hash mode.

[0033] In general, an operational cache node is a cache node that is powered up and available to store data and return data in response to memory requests. A non-operational cache node is a cache node that is powered down. A transitioning cache node is a cache node in the process of being powered down or being powered up and not accepting memory' requests. In some implementations, a powered down cache node is a cache node that has no power supplied to it, or a cache node that has reduced power supplied to it relative to a powered up cache node. If the routing subsystem operates in a single hash mode, e.g., the full single hash mode or the partial single hash mode, a non-operational cache node is fully or partially powered down and does not accept memory requests. If the routing subsystem operates in an intermediate dual hash mode, a transitioning cache node is powered up, but it does not sen e memory requests. Instead, each operational and transitioning cache node directs the processor to reissue the memory request to one of the cache nodes that will remain operational after the transition.

[0034] FIG. 3 illustrates a set of hash modes that can define how a routing subsystem (e.g., routing subsystem 120) routes memory requests to a set of cache nodes in a caching subsystem (e.g., caching subsystem 110).

[0035] In this example, a routing subsystem can operate in a first single hash mode 302. The first single hash mode 302 targets a first set of cache nodes that includes the full set of cache nodes, e.g., cache node 0 through cache node 7 for a caching subsystem that includes 8 cache nodes. In other words, all of the data stored in the caching subsystem is distributed across all of the available cache nodes, and each memory' request is converted to a cache node identifier by a primary hash function that outputs a cache node identifier corresponding to one of the cache nodes 0 through 7.

[0036] To further this example, the routing subsystem can receive a request to enter a second single hash mode 306, that targets a second set, e.g., cache nodes 4-7, of cache nodes of the caching subsystem. The system first transitions to an intermediate dual hash mode 304 while the cache nodes are drained of their stored data. While operating in the intermediate dual hash mode 304, the routing subsystem introduces a secondary hash function, or any other appropriate function for distributing memory requests, that converts incoming memory' requests into a cache node identifier corresponding to one of the cache nodes of the second set of cache nodes. For example, the second set of cache nodes can include cache node 4 through cache node 7. The primary hash function during the intermediate dual hash mode 304 continues to convert incoming memory requests to the first set of cache nodes (e.g., cache nodes 0-7).

[0037] While operating in the intermediate dual hash mode 304, the routing subsystem first converts each memory request to a cache node identifier with the primary' hash function. Each cache node returns a resend message for the issuing processor to reissue the memory request. The secondary' hash function converts the reissued memory' request to a cache node identifier corresponding to the second set of cache nodes. In addition, the routing subsystem issues an instruction to flush each cache node. To further this example, when each cache node is completely flushed, the routing subsystem enters the second single hash mode 306. The second single hash mode 306 uses the secondary hash function which targets the second set of cache nodes 4-7 as the primary hash function. Each new memory request is converted to an identifier of one of the cache nodes that are included in the second set of cache nodes (e.g., cache nodes 4-7) using the secondary hash function.

[0038] FIG. 4 is an overview of an example system that can distribute a memory request 402 from a processor 400 with a routing subsystem 420. A cache mode controller 430 configures the routing subsystem 420 to operate in a full single hash mode. The routing subsystem 420, the subsystem operating in the full single hash mode, can route the memory request to a set of cache nodes 412-418. The memory request 402 issued by the processor 400 can be distributed to any of the cache nodes 412-418 in the caching subsystem 410 using a primary hash function, or any other appropriate function for distributing memory requests.

[0039] In some implementations, the processor 400 can issue the memory request 402 to the caching subsystem 410. The routing subsystem 420 can process the memory request, where the cache mode controller 430 configures the routing subsystem 420 to operate in the full single hash mode. The routing subsystem 420 can convert the memory request 402 into an identifier to determine which cache node (e.g., one of cache nodes 412-418) stores the requested memory object associated with the memory request 402. The routing subsystem 420 can read or write the memory request through one of the channels 422-428 from or to an appropriate cache node (e.g., one of the cache nodes 412-418).

[0040] FIG. 5 is an overview of an example system that can distribute memory' requests from a processor 500 through a routing subsystem 520. A cache mode controller 530 configures the routing subsystem 520 to operate in an intermediate dual hash mode. In this example, the routing subsystem 520 operates in the intermediate dual hash mode when one or more cache nodes are transitioning between an operational state to a non-operational state. In this example, cache node 512 and cache node 514 are transitioning from an operational state to a non-operational state and are considered to be transitioning cache nodes.

[0041] The processor 500 can issue a first memory request 502 to a caching subsystem 510. The caching subsystem 510 includes the routing subsystem 520, where the routing subsystem 520 converts the incoming memory request 502 to a cache node identifier with a primary' hash function, or any other appropriate function for distributing memory requests. The cache node identifier corresponds to one of the cache nodes 512-518, which includes the transitioning cache nodes and the operational cache nodes. For example, if a target cache node is one of the transitioning cache nodes (e.g., cache node 512), the routing subsystem 520 issues the memory request 522 to cache node 512. The cache node 512 subsequently flushes the cache line, e.g., the portion of the cache node 512 that pertains to the memory request, to a lower-level memory and returns a resend message 524 to the routing subsystem 520 which sends a corresponding resend message 504 to the processor 500. The processor 500 can reissue the same memory request 506 with the resend message to the routing subsystem 520. In this case, the routing subsystem 520 can implement a secondary hash function that targets the set of cache nodes that will remain operational after the transition (e.g., cache node 518). For example, the routing subsystem 520 can issue the memory' request 528 to the cache node 518. If the object is not stored, e.g., a cache miss in the cache node 518, the system can retrieve the object from a lower-level memory. If the object is found in the cache node 518, e.g., a cache hit, the cache node 518 can return the memory object 526 to the routing subsystem 520 and the routing subsystem 520 can return the memory' object 506 to the processor 500. A copy of the memory' object can be stored in the cache node 518 for future retrieval. In this example, the use of the dual hash mode effectively transferred the memory' object from the cache node 512 which is transitioning from operational to non-operational to cache node 518 which is to remain operational.

[0042] FIG. 6 is an overview of an example system that can distribute a memory' request 602 from a processor 600 through a routing subsystem 620. A cache mode controller 630 configures the routing subsystem 620 to operate in a single hash mode. A caching subsystem 610 includes the routing subsystem 620 and a first set of operational cache nodes 16-618 and a second set of non-operational cache nodes 612-614. Each memory' request (e.g., memory' request 602) issued by the processor 600 can be distributed to any of the operational cache nodes 616-618 in the caching subsystem 610 using a primary hash function, or any other appropriate function for distributing memory requests. The primary hash function converts each incoming memory' request into a cache node identifier, where the cache node identifier can identify one of the cache nodes of the first set of operational cache nodes 616- 618.

[0043] In some implementations, the processor 600 can issue a memory request to the caching subsystem 610. The memory request is processed by the routing system 620 that is configured by the cache mode controller 630 to operate in the single hash mode configured to use the primary' hash function, where the primary hash function targets the first set of operational cache nodes 616-618. The routing subsystem 620 can convert the memory request into an identifier to determine which operational cache node (e.g., one of operational cache nodes 616-618) stores the requested memory object. The routing subsystem can issue the memory request through one of the channels 622 and 626 to an appropriate cache node (e.g., one of the cache nodes 616-618) and receive the response from the operational cache node through one of the corresponding channels 624 and 628.

[0044] FIG. 7 illustrates a communication protocol when a routing subsystem (e.g., the routing subsystem 120) is configured to be in an intermediate dual hash mode, a processor 702, a set of cache nodes 704-706. and a bus node 708 which represents a lower level memory apparatus. In this example, the cache node 704 is a transitioning cache node that is transitioning from an operational state to a non-operational state, and the cache node 706 is an operational cache node (i.e., cache node 706 will remain operational).

[0045] In some implementations, a memory read request 720 can be issued by the processor 702 which reaches the transitioning cache node 704, e.g., a routing subsystem can convert the memory read request 720 to a cache node identifier with a primary hash function, or any other appropriate function for distributing memory requests. The system is configured to transition the transitioning cache node 704 into a non-operational node: therefore, the system can direct the transitioning cache node 704 to flush the cache line 722 that pertains to the memory request 720 in the transitioning cache node 704. The data stored in the flushed cache line of the transitioning cache node 704 is written back 726 to the main bus 708 after the cache line 722 is flushed, where it can be accessed by future memory requests in a lower level memory apparatus.

[0046] After the transitioning cache node 704 flushes the cache line, e.g., the object corresponding to memory' request 720 is no longer stored in the transitioning cache node 704, the main bus 708 can send a message 724 back to the transitioning cache node 704 that indicates the flush is complete. The transitioning cache node 704 can issue a resend message 728 to the processor 702, instructing the processor 702 to resend a read request 730 that will be directed to a set of operational cache nodes, e.g., operational cache node 706.

[0047] The processor 702 can issue a read request 730 targeting the same object in memory7as the read request 720. In this case, the processor 702 sends the read request 730 along with an indicator to the routing subsystem to implement a secondary hash function, or any other appropriate function for distributing memory requests, that converts the memory request to a cache node identifier for one of the operational cache nodes (e.g., the operational cache node 706).

[0048] In some implementations, the processor 702 can issue the read request 730 to the operational cache node 706. In some cases, the target object in memory' that corresponds to the read request 720 and the read request 730 was previously stored in the transitioning cache node 704 and subsequently written back to the main bus node 708. In this case, the read request 730 can result in a cache miss in the operational cache node 706. In the case of a cache miss, a read request 732 is sent to the main bus node 708 to read the object from a lower level memory7. The main bus node 708 can retrieve the object from memory7and return the object as a message 736 to the processor 702 and as a message 734 to the operational cache node 706. The object in memory can be stored in the operational cache node 706 as well as the lower level main bus node 708. The data object corresponding to the memory request 720 is effectively transferred from the transitioning cache node 704 to the operational cache node 706.

[0049] In some implementations, as part of the communication protocol of the intermediate dual hash mode, the processor 702 can issue a confirmation message 738 to the operational cache node 706 confirming the successful read request. Similarly, the operational cache node 706 can issue a confirmation message 740 to the main bus node 708 confirming the successful read request.

[0050] FIG. 8 illustrates a detailed view of an example caching subsystem, where the caching subsystem receives memory requests from multiple processors (e.g., processor 802). The caching subsystem can include an array of switch nodes, each switch node (e.g., switch node 810) directing a memory request from one or more processors to a target cache node (e.g., cache node 820 or cache node 822) as defined by a hash function, or any other appropriate function for distributing memory7requests.

[0051] The caching subsystem can include more than one cache nodes, each cache node storing a portion of the data stored in the caching subsystem. One or more cache nodes (e.g., cache node 820) can be powered up or down with a corresponding power gate 840, where the caching subsystem can implement power gating on each non-operational cache node.

[0052] One or more bus nodes (e.g., bus node 850) which communicates with a lower level memory7apparatus can also communicate with the one or more cache nodes of the caching subsystem through the array of switch nodes. A memory request that enters the caching subsystem through a switch node 810 or a bus node 850 is processed with a corresponding hashing module (e.g., hashing module 830 or hashing module 860) that converts the memory' request into a cache node identifier to determine which cache node will receive the memory' request.

[0053] FIG. 9 is a flow diagram of an example process that results in an increase in the number of operational cache nodes. For convenience, the process will be described as being performed by a routing subsystem (e.g., the routing subsystem 120) configured to operate in accordance wi th this specification.

[0054] The routing subsystem can process (902) memory requests in a partial single hash mode using a primary hash function, or any other appropriate function for distributing memory requests, where the primary hash function can convert each incoming memory' request to a cache node identifier for one of the cache nodes of a subset of all the cache nodes, where the subset of cache nodes includes all operational cache nodes. In this example, the set of all cache nodes in the caching subsystem that is configured to operate in the partial single hash mode includes at least one non-operational cache node.

[0055] The routing subsystem can receive (904) a request to enter a full single hash mode in which all of the cache nodes present in the caching subsystem are operational. This may occur if the caching subsystem is determined to require more cache memory. In some implementations, the request can be sent by a processor acting as a cache mode controller (e.g., cache mode controller 130).

[0056] The routing subsystem can enable (906) the one or more non-operational cache nodes, such that the one or more non-operational cache nodes become operational. The cache nodes can begin accepting memory' requests.

[0057] The routing subsystem can enter (908) an intermediate dual hash mode during which each memory request is routed to a cache node with a primary hash function then reissued and routed with a secondary hash function, or any other appropriate function for distributing memory requests. The secondary' hash function converts each memory request into a cache node identifier that targets the full set of cache nodes of the caching subsystem. The formerly non-operational cache nodes can receive memory requests.

[0058] The routing subsystem can enter (910) the full single hash mode during which allocation of memory requests to cache nodes can use the secondary hash function as a primary hash function moving forward, where the primary hash function targets all of the cache nodes of the caching subsystem.

[0059] In some implementations, the routing subsystem can implement a hash function, or any other appropriate function for distnbuting memory requests, in a dual hash mode to transition between a configuration with a first number of operational cache nodes and a second number of operational cache nodes. The first number of operational cache nodes can include any number between one and the number of cache nodes in the caching subsystem. The second number of operational cache nodes can include any number between zero and one less than the number of cache nodes in the caching subsystem. In other words, the caching subsystem can include at least one operational cache node and it can transition between any number of operational cache nodes greater than one with the processes described in relation to FIG. 2 and FIG. 9.

[0060] Embodiments of the subject matter and the functional operations described in this specification can be implemented in digital electronic circuitry7, in tangibly-embodied computer software or firmware, in computer hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them.

[0061] The term “data processing apparatus” refers to data processing hardware and encompasses all kinds of apparatus, devices, and machines for processing data, including by way of example a programmable processor, a computer, or multiple processors or computers. The apparatus can also be. or further include, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit). The apparatus can optionally include, in addition to hardware, code that creates an execution environment for computer programs, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.

[0062] In addition to the embodiments described above, the following embodiments are also innovative:

[0063] Embodiment 1 is a system comprising: a plurality of processors; a plurality of cache nodes of a caching subsystem configured to cache memory requests from the plurality7of processors; wherein the caching subsystem comprises a data processing apparatus configured to perform operations comprising: processing memory requests in a full single hash mode during which allocation of memory requests to cache nodes uses a primary hash function; receiving a request to enter a partial single hash mode in which one or more first cache nodes are non-operational cache nodes and one or more second cache nodes are operational cache nodes that continue to process memory requests; entering an intermediate dual hash mode during which memory requests are routed to cache nodes with the primary7hash function then reissued and routed using a secondary7hash function that allocates memory7requests to the operational cache nodes; flushing the cache nodes; and entering a partial single hash mode during which allocation of memory requests to cache nodes uses the secondary’ hash function.

[0064] Embodiment 2 is the system of embodiment 1 , wherein the operations further comprise power gating the one or more non-operational cache nodes.

[0065] Embodiment 3 is the system of any of embodiments 1-2, wherein the operations further comprise: receiving a request to enter a full single hash mode in which all of the plurality of cache nodes are operational cache nodes; enabling the one or more non-operational cache nodes; entering an intermediate dual hash mode during which memory requests are routed to cache nodes with a primary hash function then reissued and routed using a secondary hash function that allocates memory' requests to all of the plurality of cache nodes; and entering the full single hash mode during which allocation of memory' requests to cache nodes uses the secondary' hash function.

[0066] Embodiment 4 is the system of any of embodiments 1-3, wherein the operations further comprise flushing a cache line corresponding to a memory request when the memory request is issued.

[0067] Embodiment 5 is the system of any of embodiments 1-4, wherein the operations further comprise the data processing apparatus configured in a first partial single hash mode receiving a request to enter a second partial single hash mode.

[0068] Embodiment 6 is a method performed by a data processing apparatus, the method comprising: processing memory requests in a full single hash mode during which allocation of memory requests to cache nodes uses a primary hash function; receiving a request to enter a partial single hash mode in which one or more first cache nodes are non-operational cache nodes and one or more second cache nodes are operational cache nodes that continue to process memory requests; entering an intermediate dual hash mode during which memory requests are routed to cache nodes with the primary’ hash function then reissued and routed using a secondary hash function that allocates memory requests to the operational cache nodes; flushing the cache nodes: and entering a partial single hash mode during which allocation of memory requests to cache nodes uses the secondary' hash function. Embodiment 7 is the method of embodiment 6, wherein the operations further comprise power gating the one or more non-operational cache nodes.

[0069] Embodiment 8 is the method of any of embodiments 6-7, wherein the operations further comprise: receiving a request to enter a full single hash mode in which all of the plurality of cache nodes are operational cache nodes; enabling the one or more non-operational cache nodes; entering a second intermediate dual hash mode during which memory requests are routed to cache nodes with the primary hash function then reissued and routed using the secondary' hash function that allocates the memory' requests to all of the plurality of cache nodes; and entering the full single hash mode during which allocation of memory' requests to cache nodes uses the primary hash function.

[0070] Embodiment 9 is the method of any of embodiments 6-8, wherein the operations further comprise flushing a cache line corresponding to a memory’ request when the memory request is issued.

[0071] Embodiment 10 is the method of any of embodiments 6-9, wherein the operations further comprise the data processing apparatus configured in a first partial single hash mode receiving a request to enter a second partial single hash mode.

[0072] While this specification contains many specific implementation details, these should not be construed as limitations on the scope of any invention or on the scope of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments of particular inventions. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially be claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

[0073] Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system modules and components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0074] Particular embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. For example, the actions recited in the claims can be performed in a different order and still achieve desirable results. As one example, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In certain implementations, multitasking and parallel processing may be advantageous.

[0075] What is claimed is:

Claims

CLAIMS1. A system comprising: a plurality of processors; a plurality of cache nodes of a caching subsystem configured to cache memory requests from the plurality7of processors; wherein the caching subsystem comprises a data processing apparatus configured to perform operations comprising: processing memory7requests in a full single hash mode during which allocation of memory requests to cache nodes uses a primary hash function; receiving a request to enter a partial single hash mode in which one or more first cache nodes are non-operational cache nodes and one or more second cache nodes are operational cache nodes that continue to process memory requests; entering an intermediate dual hash mode during which memory requests are routed to cache nodes with the primary7hash function then reissued and routed using a secondary7hash function that allocates memory7requests to the operational cache nodes; flushing the cache nodes; and entering a partial single hash mode during which allocation of memory requests to cache nodes uses the secondary7hash function.

2. The system of claim 1, wherein the operations further comprise power gating the one or more non-operational cache nodes.

3. The system of any of claims 1-2. wherein the operations further comprise: receiving a request to enter a full single hash mode in which all of the plurality of cache nodes are operational cache nodes; enabling the one or more non-operational cache nodes; entering an intermediate dual hash mode during which memory requests are routed to cache nodes with a primary hash function then reissued and routed using a secondary hash function that allocates memory7requests to all of the plurality of cache nodes; and entering the full single hash mode during which allocation of memory7requests to cache nodes uses the secondary7hash function.

4. The system of any of claims 1-3. wherein the operations further comprise flushing a cache line corresponding to a memory request when the memory request is issued.

5. The system of any of claims 1-4, wherein the operations further comprise the data processing apparatus configured in a first partial single hash mode receiving a request to enter a second partial single hash mode.

6. A method performed by a data processing apparatus, the method comprising: processing memory requests in a full single hash mode during which allocation of memory requests to cache nodes uses a primary hash function; receiving a request to enter a partial single hash mode in which one or more first cache nodes are non-operational cache nodes and one or more second cache nodes are operational cache nodes that continue to process memory requests; entering an intermediate dual hash mode during which memory requests are routed to cache nodes with the primary hash function then reissued and routed using a secondary hash function that allocates memory requests to the operational cache nodes; flushing the cache nodes; and entering a partial single hash mode during which allocation of memory requests to cache nodes uses the secondary hash function.

7. The method of claim 6, wherein the operations further comprise power gating the one or more non-operational cache nodes.

8. The method of any of claims 6-7, wherein the operations further comprise: receiving a request to enter a full single hash mode in which all of the plurality of cache nodes are operational cache nodes; enabling the one or more non-operational cache nodes; entering a second intermediate dual hash mode during which memory requests are routed to cache nodes with the primary' hash function then reissued and routed using the secondary' hash function that allocates the memory' requests to all of the plurality of cache nodes; andentering the full single hash mode during which allocation of memory' requests to cache nodes uses the primary’ hash function.

9. The method of any of claims 6-8, wherein the operations further comprise flushing a cache line corresponding to a memory request when the memory’ request is issued.

10. The method of any of claims 6-9, wherein the operations further comprise the data processing apparatus configured in a first partial single hash mode receiving a request to enter a second partial single hash mode.

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