Pixel circuit, pixel unit, and driving method

Abstract

A pixel circuit (100, 200, 300, 400, 500, 600), a pixel unit, and a driving method for the pixel circuit (100, 200, 300, 400, 500, 600). The pixel circuit (100, 200, 300, 400, 500, 600) comprises a drive circuit (110, 210), a write circuit (120, 220), a light-emission control circuit (130, 230), a first compensation circuit (140, 240), and a second compensation circuit (150, 250). The first compensation circuit (140, 240) is connected between a control end (N2) of the drive circuit (110, 210) and a first end (N1) of the drive circuit (110, 210) and is connected to a second control signal end (G2) of the pixel circuit (100, 200, 300, 400, 500, 600), and the first compensation circuit (140, 240) is used for controlling the electrical connection and disconnection between the control end (N2) of the drive circuit (110, 210) and the first end (N1) of the drive circuit (110, 210) on the basis of the signal of the second control signal end (G2). The second compensation circuit (150, 250) is connected between the control end (N2) of the drive circuit (110, 210) and an output signal end (OUT) and is connected to a first voltage end (Vini), a third control signal end (G3) and a fourth control signal end (G4) of the pixel circuit (100, 200, 300, 400, 500, 600), and the second compensation circuit (150, 250) is used for providing the voltage of the first voltage end (Vini) to the output signal end (OUT) under the control of the third control signal end (G3), and controlling the electrical connection and disconnection between the output signal end (OUT) and the control end (N2) of the drive circuit (110, 210) on the basis of the signal of the fourth control signal end (G4).

Description

Pixel circuit, pixel unit and driving method Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a pixel circuit, a pixel unit, and a driving method. Background Art

[0002] In the display field, oxide processes are often used due to their high uniformity. However, threshold voltage shifts in pixel circuits can adversely affect display performance. This problem can be alleviated through internal compensation in the pixel circuit, but this brings significant challenges to pixel circuit design.

[0003] Summary of the Invention

[0004] According to one aspect of the present disclosure, a pixel circuit is provided, comprising: a driving circuit having a control terminal, a first terminal, and a second terminal, the driving circuit being configured to generate a driving current flowing through the second terminal; a writing circuit connected to a data signal terminal, a first control signal terminal, and the second terminal of the driving circuit of the pixel circuit, the writing circuit being configured to provide a signal from the data signal terminal to the second terminal of the driving circuit under the control of the first control signal terminal; a light-emitting control circuit connected to a first light-emitting signal terminal, a second light-emitting signal terminal, a power signal terminal, an output signal terminal, and the first and second terminals of the driving circuit, the light-emitting control circuit being configured to electrically connect the first terminal of the driving circuit to the power signal terminal under the control of the first light-emitting signal terminal, and to electrically connect the first terminal of the driving circuit to the power signal terminal under the control of the second light-emitting signal terminal. The second end of the driving circuit is electrically connected to the output signal end; a first compensation circuit is connected between the control end and the first end of the driving circuit and is connected to the second control signal end of the pixel circuit, and the first compensation circuit is used to control the electrical connection and disconnection between the control end and the first end of the driving circuit according to the signal of the second control signal end; a second compensation circuit is connected between the control end and the output signal end of the driving circuit and is connected to the first voltage end, the third control signal end and the fourth control signal end of the pixel circuit, and the second compensation circuit is used to provide the voltage of the first voltage end to the output signal end under the control of the third control signal end, and to control the electrical connection and disconnection between the output signal end and the control end of the driving circuit according to the signal of the fourth control signal end.

[0005] For example, the second compensation circuit includes: a first sub-circuit, connecting the first voltage terminal, the output signal terminal and the third control signal terminal, the first sub-circuit being used to provide the voltage of the first voltage terminal to the output signal terminal under the control of the third control signal terminal; a second sub-circuit, connected between the control terminal of the drive circuit and the output signal terminal and connected to the fourth control signal terminal, the second sub-circuit being used to control the electrical connection and disconnection between the output signal terminal and the control terminal of the drive circuit according to the signal of the fourth control signal terminal.

[0006] For example, the second sub-circuit includes a first transistor and a first capacitor, the first transistor and the first capacitor are connected in series between the control terminal and the output signal terminal of the driving circuit, and the gate of the first transistor is connected to the fourth control signal terminal.

[0007] For example, the first electrode of the first transistor is connected to the control terminal of the driving circuit, the second electrode of the first transistor is connected to the first electrode of the first capacitor, and the second electrode of the first capacitor is connected to the output signal terminal.

[0008] For example, a first electrode of the first capacitor is connected to the control terminal of the driving circuit, a second electrode of the first capacitor is connected to the first electrode of the first transistor, and a second electrode of the first transistor is connected to the output signal terminal.

[0009] For example, the first sub-circuit includes a second transistor, a gate of the second transistor is connected to the third control signal terminal, a first electrode of the second transistor is connected to the first voltage terminal, and a second electrode of the second transistor is connected to the output signal terminal.

[0010] For example, the second electrode of the second transistor is connected to the output signal end through the first transistor, wherein the second electrode of the second transistor is connected to the first electrode of the first transistor, the second electrode of the first transistor is connected to the output signal end, the first electrode of the first capacitor is connected to the control end of the driving circuit, and the second electrode of the first capacitor is connected to the first electrode of the first transistor.

[0011] For example, the pixel circuit also includes: a third compensation circuit, which is connected to the second voltage terminal, the fifth control signal terminal and the first terminal of the driving circuit of the pixel circuit, and the third compensation circuit is used to provide the voltage of the second voltage terminal to the first terminal of the driving circuit under the control of the fifth control signal terminal.

[0012] For example, the third compensation circuit includes a third transistor, a gate of the third transistor is connected to the fifth control signal terminal, a first electrode of the third transistor is connected to the second voltage terminal, and a second electrode of the third transistor is connected to the first terminal of the driving circuit.

[0013] For example, the third control signal terminal and the fourth control signal terminal are independent of each other to receive the third control signal and the fourth control signal respectively, or the third control signal terminal and the fourth control signal terminal are connected to receive the third control signal.

[0014] For example, the first compensation circuit includes a fourth transistor, the gate of the fourth transistor is connected to the second control signal terminal, the first electrode of the fourth transistor is connected to the first terminal of the driving circuit, and the second electrode of the fourth transistor is connected to the control terminal of the driving circuit.

[0015] For example, the light-emitting control circuit includes a fifth transistor and a sixth transistor; the gate of the fifth transistor is connected to the first light-emitting signal end, the first electrode of the fifth transistor is connected to the power signal end, and the second electrode of the fifth transistor is connected to the first end of the driving circuit; the gate of the sixth transistor is connected to the second light-emitting signal end, the first electrode of the sixth transistor is connected to the second end of the driving circuit, and the second electrode of the sixth transistor is connected to the output signal end.

[0016] For example, the write circuit includes a seventh transistor, a gate of the seventh transistor is connected to the first control signal terminal, a first electrode of the seventh transistor is connected to the data signal terminal, and a second electrode of the seventh transistor is connected to the second terminal of the drive circuit.

[0017] For example, the driving circuit includes a driving transistor and a second capacitor, the gate of the driving transistor serves as the control end of the driving circuit, the first electrode of the driving transistor serves as the first end of the driving circuit, and the second electrode of the driving transistor serves as the second end of the driving circuit; the first electrode of the second capacitor is connected to the gate of the driving transistor, and the second electrode of the second capacitor is connected to the second electrode of the driving transistor.

[0018] According to another aspect of the present disclosure, a pixel unit is provided, including: the pixel circuit as described above; and a light emitting unit.

[0019] According to another aspect of the present disclosure, a driving method for the pixel circuit as described above is also provided, including: in a compensation stage, the light-emitting control circuit electrically connects the second end of the driving circuit with the output signal end, the first compensation circuit electrically connects the control end and the first end of the driving circuit, the second compensation circuit provides the voltage of the first voltage end to the output signal end, and electrically connects the output signal end to the control end of the driving circuit; in a writing stage, the first compensation circuit disconnects the control end and the first end of the driving circuit, the light-emitting control circuit disconnects the second end of the driving circuit with the output signal end, and the writing circuit provides the signal of the data signal end to the second end of the driving circuit; in a light-emitting stage, the second compensation circuit disconnects the first voltage end from the output signal end, disconnects the output signal end from the control end of the driving circuit, the light-emitting control circuit electrically connects the first end of the driving circuit with the power signal end, and electrically connects the second end of the driving circuit with the output signal end, and the driving circuit generates a driving current flowing through the second end.

[0020] For example, the method also includes: in a reset stage before the compensation stage, the light-emitting control circuit electrically connects the second end of the driving circuit to the output signal end, the first compensation circuit electrically connects the control end and the first end of the driving circuit, and the second compensation circuit provides the voltage of the first voltage end to the output signal end and electrically connects the output signal end to the control end of the driving circuit.

[0021] For example, the method further includes: in a reset phase, the light emitting control circuit electrically connects the power signal terminal to the first terminal of the driving circuit.

[0022] For example, the pixel circuit also includes a third compensation circuit, and the method also includes: in the reset stage, the light-emitting control circuit disconnects the power signal end from the first end of the driving circuit, and the third compensation circuit provides the voltage of the second voltage end to the first end of the driving circuit.

[0023] For example, the third control signal terminal and the fourth control signal terminal are independent of each other to receive the third control signal and the fourth control signal, respectively, wherein, in the light-emitting stage, the second compensation circuit disconnects the first voltage terminal from the output signal terminal according to the third control signal, and disconnects the output signal terminal from the control terminal of the driving circuit according to the fourth control signal.

[0024] For example, in the light-emitting stage, the second compensation circuit disconnects the output signal terminal from the control terminal of the driving circuit before disconnecting the first voltage terminal from the output signal terminal.

[0025] For example, the third control signal terminal and the fourth control signal terminal are connected to receive a third control signal, wherein, in the light-emitting stage, the second compensation circuit disconnects the first voltage terminal from the output signal terminal according to the third control signal, and disconnects the output signal terminal from the control terminal of the driving circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] FIG1 shows a schematic block diagram of a pixel circuit according to an embodiment of the present disclosure.

[0027] FIG. 2 shows a circuit diagram of a pixel circuit according to an embodiment of the present disclosure.

[0028] FIG3 shows a circuit diagram of a pixel circuit according to another embodiment of the present disclosure.

[0029] FIG4 shows a circuit diagram of a pixel circuit according to another embodiment of the present disclosure.

[0030] FIG5 shows a circuit diagram of a pixel circuit according to another embodiment of the present disclosure.

[0031] FIG6 shows a circuit diagram of a pixel circuit according to another embodiment of the present disclosure.

[0032] FIG7 shows a flowchart of a method for driving a pixel circuit according to an embodiment of the present disclosure.

[0033] FIG8 shows a signal timing diagram of a pixel circuit according to an embodiment of the present disclosure.

[0034] FIG. 9 shows a signal timing diagram of a pixel circuit according to another embodiment of the present disclosure.

[0035] FIG. 10 shows a signal timing diagram of a pixel circuit according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] While the present disclosure will be fully described with reference to the accompanying drawings that contain preferred embodiments of the present disclosure, it should be understood before this description that one of ordinary skill in the art may modify the disclosure described herein while still achieving the technical benefits of the present disclosure. Therefore, it should be understood that the above description is intended to be a broad disclosure for one of ordinary skill in the art and is not intended to limit the exemplary embodiments described herein.

[0037] In addition, in the following detailed description, for ease of explanation, numerous specific details are set forth to provide a comprehensive understanding of the disclosed embodiments. However, it is apparent that one or more embodiments can be practiced without these specific details. In other cases, well-known structures and devices are shown in diagrammatic form to simplify the accompanying drawings.

[0038] FIG1 shows a schematic block diagram of a pixel circuit according to an embodiment of the present disclosure.

[0039] As shown in FIG. 1 , the pixel circuit 100 includes a driving circuit 110 , a writing circuit 120 , a light emitting control circuit 130 , a first compensation circuit 140 , and a second compensation circuit 150 .

[0040] The driving circuit 110 has a control terminal N2, a first terminal N1, and a second terminal N3. The driving circuit 110 can generate a driving current flowing through the second terminal N3.

[0041] The writing circuit 120 is connected to the data signal terminal Vdata of the pixel circuit, the first control signal terminal G1 and the second terminal N3 of the driving circuit 110. The writing circuit 120 can provide the signal of the data signal terminal Vdata to the second terminal N3 of the driving circuit 110 under the control of the first control signal terminal G1.

[0042] The light emission control circuit 130 is connected to the first light emission signal terminal EM1, the second light emission signal terminal EM2, the power signal terminal ELVDD, the output signal terminal OUT of the pixel circuit, and the first terminal N1 and the second terminal N3 of the driver circuit 110. The light emission control circuit 130 can electrically connect the first terminal N1 of the driver circuit 110 to the power signal terminal ELVDD under the control of the first light emission signal terminal EM1, and electrically connect the second terminal N3 of the driver circuit 110 to the output signal terminal OUT under the control of the second light emission signal terminal EM2.

[0043] The first compensation circuit 140 is connected between the control terminal N2 and the first terminal N1 of the driving circuit 110 and is connected to the second control signal terminal G2 of the pixel circuit. The first compensation circuit 140 can control the electrical connection and disconnection between the control terminal N2 and the first terminal N1 of the driving circuit 110 according to the signal of the second control signal terminal G2.

[0044] The second compensation circuit 150 is connected between the control terminal N2 of the driving circuit 110 and the output signal terminal OUT and is connected to the first voltage terminal Vini, the third control signal terminal G3, and the fourth control signal terminal G4 of the pixel circuit. The second compensation circuit 150 can provide the voltage of the first voltage terminal Vini to the output signal terminal OUT under the control of the third control signal terminal G3, and control the electrical connection and disconnection between the output signal terminal OUT and the control terminal N2 of the driving circuit 110 according to the signal of the fourth control signal terminal G4. In some embodiments, the second compensation circuit 150 may include a first sub-circuit and a second sub-circuit. The first sub-circuit connects the first voltage terminal, the output signal terminal, and the third control signal terminal, and the first sub-circuit can provide the signal of the first voltage terminal to the output signal terminal under the control of the third control signal terminal. The second sub-circuit is connected between the control terminal and the output signal terminal of the driving circuit and is connected to the fourth control signal terminal. The second sub-circuit can control the electrical connection and disconnection between the output signal terminal and the control terminal of the driving circuit according to the signal of the fourth control signal terminal.

[0045] In some embodiments, the pixel circuit may further include a third compensation circuit. The third compensation circuit is connected to the second voltage terminal of the pixel circuit, the fifth control signal terminal, and the first terminal of the driving circuit. The third compensation circuit may provide the voltage of the second voltage terminal to the first terminal of the driving circuit under the control of the fifth control signal terminal.

[0046] In some embodiments, the third control signal terminal G3 and the fourth control signal terminal G4 can be independent of each other to receive the third control signal and the fourth control signal, respectively. In other embodiments, the third control signal terminal G3 and the fourth control signal terminal G4 can be connected to receive the same control signal, such as the third control signal.

[0047] Embodiments of the present disclosure provide a pixel circuit that, by providing a first compensation circuit and a second compensation circuit, can achieve rapid compensation for threshold voltage loss. The second compensation circuit also allows the voltage at the first voltage terminal to be used to reset the output signal terminal before the light-emitting phase, disconnecting the output signal terminal from the driver circuit during the light-emitting phase. This prevents the voltage at the output signal terminal from affecting the output of the driver circuit during the light-emitting phase.

[0048] FIG. 2 shows a circuit diagram of a pixel circuit according to an embodiment of the present disclosure.

[0049] As shown in FIG2 , the pixel circuit 200 includes a driving circuit 210, a writing circuit 220, a light-emitting control circuit 230, a first compensation circuit 240, and a second compensation circuit 250. The description of the driving circuit 110, the writing circuit 120, the light-emitting control circuit 130, the first compensation circuit 140, and the second compensation circuit 150 in the above embodiment also applies to this embodiment.

[0050] The driving circuit 210 may include a driving transistor DT and a second capacitor C2. For example, the gate of the driving transistor DT may serve as the control terminal N2 of the driving circuit 210, the first electrode of the driving transistor DT may serve as the first terminal N1 of the driving circuit 210, and the second electrode of the driving transistor DT may serve as the second terminal N3 of the driving circuit 210. The first electrode of the second capacitor C2 may be connected to the gate of the driving transistor DT, and the second electrode of the second capacitor C2 may be connected to the second electrode of the driving transistor DT. The driving transistor DT may be an N-type transistor, the first electrode of the driving transistor DT may be a source electrode, and the second electrode may be a drain electrode. However, the embodiments of the present disclosure are not limited thereto. In some embodiments, the driving transistor may also be a P-type transistor. The driving transistor DT may generate a driving current based on its gate-source voltage, and the magnitude of the generated driving current may be determined.

[0051] The writing circuit 220 may include a seventh transistor T7. As shown in FIG2 , the gate of the seventh transistor T7 is connected to the first control signal terminal G1, the first electrode of the seventh transistor T7 is connected to the data signal terminal Vdata, and the second electrode of the seventh transistor T7 is connected to the second terminal N3 of the driving circuit.

[0052] The light-emitting control circuit 230 may include a fifth transistor T5 and a sixth transistor T6. As shown in FIG2 , the gate of the fifth transistor T5 is connected to the first light-emitting signal terminal EM1, the first electrode of the fifth transistor T5 is connected to the power supply signal terminal ELVDD, and the second electrode of the fifth transistor T5 is connected to the first terminal N1 of the driving circuit. The gate of the sixth transistor T6 is connected to the second light-emitting signal terminal EM2, the first electrode of the sixth transistor T6 is connected to the second terminal N3 of the driving circuit, and the second electrode of the sixth transistor T6 is connected to the output signal terminal OUT.

[0053] The first compensation circuit 240 may include a fourth transistor T4. As shown in FIG2 , the gate of the fourth transistor T4 is connected to the second control signal terminal G2, the first electrode of the fourth transistor T4 is connected to the first terminal N1 of the drive circuit, and the second electrode of the fourth transistor T4 is connected to the control terminal N2 of the drive circuit. When the fourth transistor T4 is turned on, the control terminal N2 of the drive circuit is electrically connected to the first terminal N1. When the fourth transistor T4 is turned off, the control terminal N2 of the drive circuit is disconnected from the first terminal.

[0054] The second compensation circuit 250 may include a first sub-circuit 2501 and a second sub-circuit 2502 .

[0055] As shown in FIG2 , the first sub-circuit 2501 can be connected to the first voltage terminal Vini, the output signal terminal OUT, and the third control signal terminal G3. The first sub-circuit 2501 can provide a signal from the first voltage terminal Vini to the output signal terminal OUT under the control of the third control signal terminal G3. For example, the first sub-circuit 2501 may include a second transistor T2, the gate of the second transistor T2 being connected to the third control signal terminal G3, a first electrode of the second transistor T2 being connected to the first voltage terminal Vini, and a second electrode of the second transistor T2 being connected to the output signal terminal OUT.

[0056] As shown in FIG2 , the second sub-circuit 2502 is connected between the control terminal N2 of the drive circuit and the output signal terminal OUT and is connected to the fourth control signal terminal G4. The second sub-circuit 2502 can control the electrical connection and disconnection between the output signal terminal OUT and the control terminal N2 of the drive circuit based on the signal of the fourth control signal terminal G4. For example, the second sub-circuit 2502 may include a first transistor T1 and a first capacitor C1, wherein the first transistor T1 and the first capacitor C1 are connected in series between the control terminal N2 of the drive circuit and the output signal terminal OUT, and the gate of the first transistor T1 is connected to the fourth control signal terminal G4. In FIG2 , the first electrode of the first capacitor C1 is connected to the control terminal N2 of the drive circuit, the second electrode of the first capacitor C1 is connected to the first electrode of the first transistor T1, and the second electrode of the first transistor T1 is connected to the output signal terminal OUT.

[0057] When the first transistor T1 is on, the output signal terminal OUT1 is connected to the control terminal N2 of the driving circuit via the first capacitor C1. When the first transistor T1 is off, the path between the output signal terminal OUT and the control terminal N2 of the driving circuit is disconnected. When the second transistor T2 is on, the voltage of the first voltage terminal Vini is provided to the output signal terminal OUT. When the second transistor T2 is off, the path between the first voltage terminal Vini and the output signal terminal OUT is disconnected, facilitating subsequent light emission control.

[0058] In FIG2 , the third control signal terminal G3 and the fourth control signal terminal G4 are independent of each other to receive the third control signal and the fourth control signal, respectively. However, the embodiments of the present disclosure are not limited thereto. In some embodiments, the third control signal terminal G3 and the fourth control signal terminal G4 may be connected to receive the third control signal, as will be described in detail below.

[0059] FIG3 shows a circuit diagram of a pixel circuit according to another embodiment of the present disclosure. The pixel circuit 300 of FIG3 is similar to the pixel circuit 200 of FIG2 , differing at least in the structure of the second compensation circuit. For ease of description, the following will primarily describe the differences in detail.

[0060] As shown in FIG3 , in the pixel circuit 300, the second sub-circuit 3502 of the second compensation circuit includes a first transistor T1 and a first capacitor C1. Unlike FIG2 , the positions of the first transistor T1 and the first capacitor C1 are interchanged, i.e., the first transistor T1 is connected to the control terminal N2 of the drive circuit, while the first capacitor C1 is connected to the output signal terminal OUT. As shown in FIG3 , the first electrode of the first transistor T1 is connected to the control terminal N2 of the drive circuit, the second electrode of the first transistor T1 is connected to the first electrode of the first capacitor C1, and the second electrode of the first capacitor C1 is connected to the output signal terminal OUT.

[0061] FIG4 shows a circuit diagram of a pixel circuit according to another embodiment of the present disclosure. The pixel circuit 400 of FIG4 is similar to the pixel circuit 200 of FIG2 , differing at least in the structure of the second compensation circuit. For ease of description, the following will primarily describe the differences in detail.

[0062] As shown in FIG4 , in the pixel circuit 400, the first compensation circuit 4501 includes a second transistor T2, and the second compensation circuit 4502 includes a first transistor T1 and a first capacitor C1. Unlike FIG2 , in the pixel circuit 400, the second electrode of the second transistor T2 is connected to the output signal terminal OUT through the first transistor T1. As shown in FIG4 , the second electrode of the second transistor T2 is connected to the first electrode of the first transistor T1, the second electrode of the first transistor T1 is connected to the output signal terminal OUT, the first electrode of the first capacitor C1 is connected to the control terminal N2 of the drive circuit, and the second electrode of the first capacitor C1 is connected to the first electrode of the first transistor T1.

[0063] When both the first transistor T1 and the second transistor T2 are turned on, the voltage at the first voltage terminal Vini is provided to the output signal terminal OUT. Simultaneously, the conduction of the first transistor T1 electrically connects the output signal terminal OUT to the control terminal N2 of the drive circuit via the first capacitor C1. When the first transistor T1 is turned off, the path between the output signal terminal OUT and the control terminal N2 of the drive circuit is disconnected. When the second transistor T2 is turned off, the path between the first voltage terminal Vini and the output signal terminal OUT is disconnected.

[0064] FIG5 shows a circuit diagram of a pixel circuit according to another embodiment of the present disclosure. The pixel circuit 500 of FIG5 is similar to the pixel circuit 200 of FIG2 , differing at least in the connection method of the control terminal of the second compensation circuit. For ease of description, the following will primarily describe the differences in detail.

[0065] As shown in FIG5 , unlike the independent design of the third control signal terminal G3 and the fourth control signal terminal G4 in FIG2 , in pixel circuit 500, the third control signal terminal and the fourth control signal terminal connected to the second compensation circuit 550 can be electrically connected, thereby serving as the same control signal terminal to receive the same control signal, such as the third control signal. In FIG5 , both the third control signal terminal and the fourth control signal terminal are represented by G3, indicating that the third control signal terminal and the fourth control signal terminal can be implemented as the same control signal terminal to receive the same control signal.

[0066] FIG6 shows a circuit diagram of a pixel circuit according to another embodiment of the present disclosure. The pixel circuit 600 of FIG6 is similar to the pixel circuit 200 of FIG2 , except that it further includes a third compensation circuit. For ease of description, the following will focus on the differences.

[0067] As shown in FIG6 , in addition to the driver circuit, write circuit, light emission control circuit, first compensation circuit, and second compensation circuit described above, the pixel circuit 600 may further include a third compensation circuit 660. The third compensation circuit 660 is connected to the second voltage terminal Vref of the pixel circuit, the fifth control signal terminal G5, and the first terminal N1 of the driver circuit. The third compensation circuit is configured to provide the voltage of the second voltage terminal Vref to the first terminal N1 of the driver circuit under the control of the fifth control signal terminal G5. For example, the third compensation circuit 660 may include a third transistor T3, wherein the gate of the third transistor T3 is connected to the fifth control signal terminal G5, the first electrode of the third transistor T3 is connected to the second voltage terminal Vref, and the second electrode of the third transistor T3 is connected to the first terminal N1 of the driver circuit.

[0068] The various transistors mentioned in the above embodiments may be N-type transistors. When the transistor is an N-type transistor, the effective control level of the transistor is a high level, that is, when the control terminal is a high level (for example, 5V, 10V or other suitable voltages), the transistor is turned on, and when the control terminal is a low level (for example, 0V, -5V, -10V or other suitable voltages), the transistor is turned off. However, the embodiments of the present disclosure are not limited thereto, and the various transistors in the above embodiments may also be P-type transistors. When the transistor is a P-type transistor, the effective control level of the transistor is a low level, that is, when the control terminal is a low level (for example, 0V, -5V, -10V or other suitable voltages), the transistor is turned on, and when the control terminal is a high level (for example, 5V, 10V or other suitable voltages), the transistor is turned off. When the type of transistor changes, the same function can be achieved by adjusting the connection relationship or control signal in the circuit accordingly.

[0069] An embodiment of the present disclosure further provides a pixel unit, comprising a pixel circuit and a light-emitting unit. The pixel circuit can be implemented by the pixel circuit in any of the above embodiments. The light-emitting unit can be connected to the output end of the pixel circuit. For example, with reference to Figures 2 to 6, the first pole (e.g., anode) of the light-emitting unit EL can be connected to the output signal terminal OUT of the pixel circuit, and the second pole (e.g., cathode) of the light-emitting unit EL can be connected to the reference signal terminal ELVSS. The light-emitting unit EL can be an organic light-emitting diode (OLED). The light-emitting unit EL can emit light under the drive current provided by the pixel circuit.

[0070] FIG7 shows a flowchart of a method for driving a pixel circuit according to an embodiment of the present disclosure.

[0071] In operation S110, in the compensation stage, the light-emitting control circuit electrically connects the second end of the driving circuit to the output signal end, the first compensation circuit electrically connects the control end and the first end of the driving circuit, and the second compensation circuit provides the voltage of the first voltage end to the output signal end, and electrically connects the output signal end to the control end of the driving circuit.

[0072] In operation S120, in the writing phase, the first compensation circuit disconnects the control terminal and the first terminal of the driving circuit, the light emitting control circuit disconnects the second terminal of the driving circuit from the output signal terminal, and the writing circuit provides the signal of the data signal terminal to the second terminal of the driving circuit.

[0073] In operation S130, during the light-emitting stage, the second compensation circuit disconnects the first voltage terminal from the output signal terminal, and disconnects the output signal terminal from the control terminal of the driving circuit. The light-emitting control circuit electrically connects the first terminal of the driving circuit to the power signal terminal, and electrically connects the second terminal of the driving circuit to the output signal terminal. The driving circuit generates a driving current flowing through the second terminal.

[0074] In some embodiments, a reset phase may be included before the compensation phase. During the reset phase, the light emitting control circuit electrically connects the second terminal of the driving circuit to the output signal terminal, the first compensation circuit electrically connects the control terminal and the first terminal of the driving circuit, and the second compensation circuit provides the voltage of the first voltage terminal to the output signal terminal and electrically connects the output signal terminal to the control terminal of the driving circuit.

[0075] In some embodiments, the method may further include: in a reset phase, the light emitting control circuit electrically connecting the power signal terminal to the first terminal of the driving circuit.

[0076] In some embodiments, when the pixel circuit also includes a third compensation circuit, the method may further include: in the reset stage, the light-emitting control circuit disconnects the power signal terminal from the first terminal of the driving circuit, and the third compensation circuit provides the voltage of the second voltage terminal to the first terminal of the driving circuit.

[0077] In some embodiments, when the third control signal terminal and the fourth control signal terminal are independent of each other to receive the third control signal and the fourth control signal, respectively, during the light-emitting phase, the second compensation circuit may disconnect the first voltage terminal from the output signal terminal according to the third control signal, and disconnect the output signal terminal from the control terminal of the driver circuit according to the fourth control signal. For example, under the control of the third control signal and the fourth control signal, the second compensation circuit may disconnect the output signal terminal from the control terminal of the driver circuit before disconnecting the first voltage terminal from the output signal terminal.

[0078] In some embodiments, when the third control signal terminal and the fourth control signal terminal are connected to receive the third control signal, during the light-emitting phase, the second compensation circuit can disconnect the first voltage terminal from the output signal terminal and disconnect the output signal terminal from the control terminal of the driving circuit according to the third control signal. For example, under the control of the third control signal, the second compensation circuit can disconnect the first voltage terminal from the output signal terminal and simultaneously disconnect the output signal terminal from the control terminal of the driving circuit.

[0079] FIG8 shows a signal timing diagram of a pixel circuit according to an embodiment of the present disclosure. This timing diagram is applicable to the pixel circuit of the above embodiment, such as the pixel circuit described above with reference to FIG2 . The operation process of the pixel circuit 200 will be described below in conjunction with FIG2 and FIG8 .

[0080] During the reset phase, the signals at the first and second emission signal terminals EM1 and EM2 are high, the signals at the second, third, and fourth control signal terminals G2, G3, and G4 are high, and the signal at the first control signal terminal G1 is low. The low level at the first control signal terminal G1 turns off the seventh transistor T7, preventing data from being written to the node N3. The high level at the first emission signal terminal EM1 turns on the fifth transistor T5, thereby supplying the signal at the power supply signal terminal ELVDD to the node N1 (i.e., the first electrode N1 of the drive transistor DT). The signal at the power supply signal terminal ELVDD can be a constant high level, such as 5V, 10V, or other suitable voltages. The high level at the second control signal terminal G2 turns on the fourth transistor T4, thereby setting the node N2 (i.e., the gate N2 of the drive transistor DT) to the voltage at the power supply signal terminal ELVDD. The high level at the third control signal terminal G3 turns on the second transistor T2, thereby supplying the voltage at the first voltage terminal Vini to the output signal terminal OUT. The voltage at the first voltage terminal Vini is less than the voltage at the power signal terminal ELVDD. This causes the light-emitting unit EL to be in a non-luminous state when applied to the light-emitting unit EL. A high level at the fourth control signal terminal G4 turns on the first transistor T1, connecting the output signal terminal OUT to the node N2 via the first capacitor C1. A high level at the second light-emitting signal terminal EM2 turns on the sixth transistor T6, thereby supplying the voltage at the output signal terminal OUT to the node N3 (i.e., the second electrode N3 of the drive transistor DT). Through the above process, nodes N1 and N2 are set to the voltage of the power signal terminal ELVDD, and node N3 and the output signal terminal OUT are set to the voltage of the first voltage terminal Vini.

[0081] In the compensation phase, the first light emitting signal EM1 changes to a low level, and the fifth transistor T5 is turned off. Since the second light emitting signal EM2 and the third control signal G3 remain at a high level, the sixth transistor T6 and the second transistor T2 remain on, and the potential of the node N3 and the output signal terminal OUT remains at V INI , where V INI When the fifth transistor T5 is turned off, the potentials of the nodes N1 and N2 are V ELVDD , the potential of node N3 is V INI , and V ELVDD >V INI , so nodes N1 and N2 discharge to node N3 until the potential of node N2 becomes V INI +V TH , where V ELVDD Indicates the voltage of the power signal terminal ELVDD, V TH represents the threshold voltage of the driving transistor DT.

[0082] During the write phase, the second control signal terminal G2 and the second light emitting signal terminal EM2 become low levels, and the first control signal terminal G1 becomes high. The high level of the first control signal terminal G1 turns on the seventh transistor T7, thereby writing the voltage of the data signal terminal Vdata into the node N3. The low level of the second control signal terminal G2 turns off the fourth transistor T4, and the low level of the second light emitting signal terminal EM2 turns off the first transistor T1. The node N2 becomes V due to the voltage divider effect of the first capacitor C1 and the second capacitor C2. INI +V TH +(V DATA -V IN I)*C1 / (C1+C2), where V DATA represents the voltage of the data signal terminal Vdata, C1 represents the capacitance value of the first capacitor C1, and C2 represents the capacitance value of the second capacitor C2. In some embodiments, during the write phase, the high-level duration of the signal at the first control signal terminal G1 can be within the low-level duration of the signal at the second light-emitting signal terminal EM2, so that the entire process of the seventh transistor T7 writing the data voltage to the node N3 is performed during the off-state period of the sixth transistor T6.

[0083] During the light-emitting phase, the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are both at a high level, while the first control signal terminal G1, the second control signal terminal G2, the third control signal terminal G3, and the fourth control signal terminal G4 are all at a low level. The seventh transistor T7, the fourth transistor T4, the second transistor T2, and the first transistor T1 are all turned off, while the fifth transistor T5 and the sixth transistor T6 are turned on. The voltage of the power supply signal terminal ELVDD is supplied to the first terminal N1 of the driving transistor DT. The driving transistor DT generates a driving current under the action of the voltages of the first terminal N1, the gate N2, and the second terminal N3. The generated driving current is supplied to the light-emitting element EL via the output signal terminal OUT, thereby driving the light-emitting element EL to emit light.

[0084] The driving current generated by the driving transistor DT is:

[0085] I=K*(Vgs-Vth) 2 Equation (1)

[0086] Wherein K represents the conductivity coefficient of the driving transistor DT, and Vgs represents the gate-source voltage of the driving transistor DT, that is, the voltage difference between the gate and the source.

[0087] As mentioned above, at the beginning of the light emitting phase, the voltage of the gate N1 of the driving transistor DT is V INI +V TH +(V DATA -V INI)*C1 / (C1+C2), the voltage of the source (the second electrode N3 in this embodiment) is V DATA , the threshold voltage of the driving transistor DT is V TH , so the gate-source voltage Vgs=V INI +V TH +(V DATA -V IN I)*C1 / (C1+C2)-V DATA -V TH , substituting into the above equation (1), we get:

[0088] I=K*(V INI +V TH +(V DATA -V INI )*C1 / (C1+C2)-V DATA -V TH ) 2 =K*((V INI -V DATA )*C2 / (C1+C2)) 2 Equation (2)

[0089] According to the above equation (2), the driving current I flowing through the light emitting unit EL is no longer related to the threshold voltage V TH related, thereby eliminating the threshold voltage V TH In this way, even if the threshold voltage V TH The threshold voltage drift will not affect the driving current, thereby improving the display effect of the pixel unit where the pixel circuit is located.

[0090] In the above process, the presence of the first transistor T1 can further stabilize the output of the driving transistor DT. For example, in conjunction with FIG2 , if there is no first transistor T1, the output signal terminal OUT and the first capacitor C1 will always remain connected. Then the following situation will occur: in the light-emitting phase, at the moment when the sixth transistor T6 is turned on, since the voltage of the node N3 is V DATA , the voltage of the output signal terminal OUT is V INI, there is a difference between the voltage of node N3 and the voltage of the output signal terminal OUT, which causes the potential of the output signal terminal OUT to be instantly pulled up by the node N3. At this time, since the output signal terminal OUT is connected to the first capacitor C1, the voltage of the output signal terminal OUT will affect the voltage of the node N3 through the coupling effect of the first capacitor C1 and the second capacitor C2, thereby causing the voltage of N3 to deviate from the expected value, thereby affecting the output of the driving transistor DT. The embodiment of the present disclosure provides a first transistor T1 controlled by the fourth control signal terminal G4. In the light-emitting stage, the signal of the fourth control signal terminal G4 can be used to turn off the first transistor T1, thereby preventing the voltage of the output signal terminal OUT from affecting the voltage of the node N3, which is beneficial to the stability of the driving signal output by the driving transistor DT.

[0091] In FIG8 , the signal of the third control signal terminal G3 (hereinafter referred to as the third control signal) and the signal of the fourth control signal terminal G4 (hereinafter referred to as the fourth control signal) are the same, however, the embodiments of the present disclosure are not limited thereto, and the third control signal and the fourth control signal may also be different. For example, in the write phase, the fourth control signal of the fourth control signal terminal G4 may become a low level before the third control signal of the third control signal terminal G3. In conjunction with FIG2 , this causes the first transistor T1 to be turned off before the second transistor T3 is turned off. In this way, the output signal terminal OUT is disconnected from the node N2 before the first voltage terminal Vini is disconnected from the output signal terminal OUT, thereby further stabilizing the voltage of the node N2.

[0092] In some embodiments, during the light-emitting phase, the second control signal at the second control signal terminal EM2 and the first control signal at the first control signal terminal EM1 can simultaneously change from a low level to a high level, thereby turning on the fifth transistor T5 and the sixth transistor T6 at the same time, thereby causing the driving transistor DT to generate a driving current. However, the embodiments of the present disclosure are not limited thereto. In other embodiments, as shown in FIG8 , the second control signal terminal EM2 can change to a high level before the first control signal terminal EM1, thereby causing the sixth transistor T6 to turn on before the fifth transistor T5, thereby connecting the node N3 to the output signal terminal OUT before the driving transistor DT generates a driving current, thereby avoiding flickering of the light-emitting unit EL caused by simultaneous conduction.

[0093] In some embodiments, during the light-emitting stage, the signals of the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 may become high level after the third control signal terminal G3 and the fourth control signal terminal G4 become low level for a period of time, thereby ensuring that the first transistor T1 and the second transistor T2 are turned off before turning on the fifth transistor T5 and the sixth transistor T6, thereby further stabilizing the output of the driving transistor DT.

[0094] The timing diagram of Figure 8 is also applicable to the pixel circuit 300 of Figure 3. The working process of the pixel circuit 300 is the same as the process described above and will not be repeated here. Compared with the pixel circuit 200 of Figure 2, the first transistor T1 and the first capacitor C1 in the pixel circuit 300 are interchanged to further stabilize the voltage of the node N2. For example, in combination with Figure 3 and Figure 8, if the first transistor T1 and the first capacitor C1 adopt the connection method shown in Figure 2, then in the light-emitting phase, the first transistor T1 is turned off and the first capacitor C1 remains connected to the node N2, which will cause the node N2 to be connected to a floating first capacitor C1 in the light-emitting phase. The presence of the floating capacitor will affect the voltage of the node N2. The pixel circuit 300 of Figure 3 connects the first capacitor C1 to the output signal terminal OUT side and the first transistor T1 to the node N2 side, so that when the first transistor T1 is turned off in the light-emitting phase, the connection between the first capacitor C1 and the node N2 is also disconnected, thereby avoiding the influence of the floating capacitor on the node N2, which is further beneficial to the output stability of the driving transistor DT.

[0095] The timing diagram of FIG8 is also applicable to the pixel circuit 400 of FIG4. The operation process of the pixel circuit 400 is similar to the process described above. The operation process of the pixel circuit 400 will be described below in conjunction with FIG4 and FIG8. For the sake of simplicity, the differences will be mainly described in detail.

[0096] During the reset phase, the signals at the first and second emission signal terminals EM1 and EM2 are high, the signals at the second, third, and fourth control signal terminals G2, G3, and G4 are high, and the signal at the first control signal terminal G1 is low. The low level at the first control signal terminal G1 turns off the seventh transistor T7, preventing data from being written to the node N3. The high level at the first emission signal terminal EM1 turns on the fifth transistor T5, thereby supplying the signal at the power supply signal terminal ELVDD to the node N1 (i.e., the first electrode N1 of the driver transistor DT). The signal at the power supply signal terminal ELVDD can be a constant high level, such as 5V, 10V, or other suitable voltages. The high level at the second control signal terminal G2 turns on the fourth transistor T4, thereby setting the node N2 (i.e., the gate N2 of the driver transistor DT) to the voltage at the power supply signal terminal ELVDD. The high levels at the third and fourth control signal terminals G3 and G4, respectively, turn on the second and first transistors T2 and T1, thereby supplying the voltage at the first voltage terminal Vini to the output signal terminal OUT. The voltage at the first voltage terminal Vini is lower than the voltage at the power signal terminal ELVDD, thereby rendering the light-emitting unit EL non-luminous when applied to the light-emitting unit EL. The conduction of the first transistor T1 also connects the output signal terminal OUT to the node N2 via the first capacitor C1. The high level at the second light-emitting signal terminal EM2 turns on the sixth transistor T6, thereby supplying the voltage at the output signal terminal OUT to the node N3 (i.e., the second electrode N3 of the drive transistor DT). Through the above process, nodes N1 and N2 are set to the voltage of the power signal terminal ELVDD, and node N3 and the output signal terminal OUT are set to the voltage of the first voltage terminal Vini.

[0097] In the compensation phase, the first light emitting signal EM1 changes to a low level, and the fifth transistor T5 is turned off. Since the second light emitting signal EM2, the third control signal G3, and the fourth control signal terminal G4 remain at a high level, the sixth transistor T6, the second transistor T2, and the first transistor T1 remain in a conducting state, and the potential of the node N3 and the output signal terminal OUT remains at V INI , where V INI When the fifth transistor T5 is turned off, the potentials of the nodes N1 and N2 are V ELVDD , the potential of node N3 is V INI , and V ELVDD >V INI , so nodes N1 and N2 discharge to node N3 until the potential of node N2 becomes V INI +V TH , where V ELVDD Indicates the voltage of the power signal terminal ELVDD, V TH represents the threshold voltage of the driving transistor DT.

[0098] During the write phase, the second control signal terminal G2 and the second light emitting signal terminal EM2 become low levels, and the first control signal terminal G1 becomes high. The high level of the first control signal terminal G1 turns on the seventh transistor T7, thereby writing the voltage of the data signal terminal Vdata into the node N3. The low level of the second control signal terminal G2 turns off the fourth transistor T4, and the low level of the second light emitting signal terminal EM2 turns off the first transistor T1. The node N2 becomes V due to the voltage divider effect of the first capacitor C1 and the second capacitor C2. INI +V TH +(V DATA -V INI )*C1 / (C1+C2), where V DATA represents the voltage of the data signal terminal Vdata, C1 represents the capacitance value of the first capacitor C1, and C2 represents the capacitance value of the second capacitor C2. In some embodiments, during the write phase, the high-level duration of the signal at the first control signal terminal G1 can be within the low-level duration of the signal at the second light-emitting signal terminal EM2, so that the entire process of the seventh transistor T7 writing the data voltage to the node N3 is performed during the off-state period of the sixth transistor T6.

[0099] In the light-emitting stage, the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 both become high levels, and the first control signal terminal G1, the second control signal terminal G2, the third control signal terminal G3 and the fourth control signal terminal G4 are all low levels. The seventh transistor T7, the fourth transistor T4, the second transistor T2 and the first transistor T1 are all turned off, and the fifth transistor T5 and the sixth transistor T6 are turned on. The voltage of the power supply signal terminal ELVDD is provided to the first electrode N1 of the driving transistor DT. Under the action of the voltage of the first electrode N1, the gate N2 and the second electrode N3, the driving transistor DT generates a driving current. The generated driving current is provided to the light-emitting unit EL through the output signal terminal OUT, thereby driving the light-emitting unit EL to emit light. According to the above equations (1) and (2), the driving current generated by the driving transistor DT is no longer related to the threshold voltage V TH related, thereby eliminating the threshold voltage V TH The impact on the driving current is used to compensate for the pixel circuit.

[0100] In the above process, the presence of the first transistor T1 can also further stabilize the output of the driving transistor DT. For example, in conjunction with Figure 4, during the light-emitting phase, the signal of the fourth control signal terminal G4 can be used to turn off the first transistor T1, thereby preventing the voltage of the output signal terminal OUT from affecting the voltage of the node N3, which is conducive to stabilizing the driving signal output by the driving transistor DT.

[0101] Figure 9 shows a signal timing diagram of a pixel circuit according to another embodiment of the present disclosure. The signal timing of Figure 9 is applicable to the pixel circuit of the above embodiment, such as the pixel circuit shown in Figure 5. The working process of the pixel circuit 500 will be described below in conjunction with Figures 5 and 9. By comparing Figures 9 and 8, it can be seen that the working process of the pixel circuit 500 of Figure 5 is similar to the working process of the pixel circuit 200 of Figure 2, and the difference is at least that the third control signal terminal and the fourth control signal terminal are implemented as the same control signal terminal G3 (hereinafter referred to as the third control signal terminal G3 for ease of description). For the sake of brevity, the difference will be mainly described.

[0102] During the reset phase, the signals at the first and second emission signal terminals EM1 and EM2 are high, the second and third control signal terminals G2 and G3 are high, and the signal at the first control signal terminal G1 is low. The low level at the first control signal terminal G1 turns off the seventh transistor T7, preventing data from being written to the node N3. The high level at the first emission signal terminal EM1 turns on the fifth transistor T5, thereby supplying the signal at the power supply signal terminal ELVDD to the node N1 (i.e., the first electrode N1 of the driver transistor DT). The signal at the power supply signal terminal ELVDD can be a constant high level, such as 5V, 10V, or other suitable voltages. The high level at the second control signal terminal G2 turns on the fourth transistor T4, thereby setting the node N2 (i.e., the gate N2 of the driver transistor DT) to the voltage at the power supply signal terminal ELVDD. The high level at the third control signal terminal G3 turns on both the first and second transistors T1 and T2, thereby supplying the voltage at the first voltage terminal Vini to the output signal terminal OUT, which is then connected to the node N2 via the first capacitor C1. The voltage at the first voltage terminal Vini is lower than the voltage at the power signal terminal ELVDD, thereby rendering the light-emitting unit EL non-luminous when applied to the light-emitting unit EL. The high level at the second light-emitting signal terminal EM2 turns on the sixth transistor T6, thereby supplying the voltage at the output signal terminal OUT to the node N3 (i.e., the second electrode N3 of the drive transistor DT). Through the above process, nodes N1 and N2 are set to the voltage of the power signal terminal ELVDD, and node N3 and the output signal terminal OUT are set to the voltage of the first voltage terminal Vini.

[0103] In the compensation phase, the first light emitting signal EM1 changes to a low level, and the fifth transistor T5 is turned off. Since the second light emitting signal EM2 and the third control signal G3 remain at a high level, the sixth transistor T6, the first transistor T1, and the second transistor T2 remain in a conducting state, and the potential of the node N3 and the output signal terminal OUT remains at V INI , where V INIWhen the fifth transistor T5 is turned off, the potentials of the nodes N1 and N2 are V ELVDD , the potential of node N3 is V INI , and V ELVDD >V INI , so nodes N1 and N2 discharge to node N3 until the potential of node N2 becomes V INI +V TH , where V ELVDD Indicates the voltage of the power signal terminal ELVDD, V TH represents the threshold voltage of the driving transistor DT.

[0104] During the write phase, the second control signal terminal G2 and the second light emitting signal terminal EM2 become low levels, and the first control signal terminal G1 becomes high. The high level of the first control signal terminal G1 turns on the seventh transistor T7, thereby writing the voltage of the data signal terminal Vdata into the node N3. The low level of the second control signal terminal G2 turns off the fourth transistor T4, and the low level of the second light emitting signal terminal EM2 turns off the first transistor T1. The node N2 becomes V due to the voltage divider effect of the first capacitor C1 and the second capacitor C2. INI +V TH +(V DATA -V INI )*C1 / (C1+C2), where V DATA represents the voltage of the data signal terminal Vdata, C1 represents the capacitance value of the first capacitor C1, and C2 represents the capacitance value of the second capacitor C2. In some embodiments, during the write phase, the high-level duration of the signal at the first control signal terminal G1 can be within the low-level duration of the signal at the second light-emitting signal terminal EM2, so that the entire process of the seventh transistor T7 writing the data voltage to the node N3 is performed during the off-state period of the sixth transistor T6.

[0105] During the light-emitting phase, the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are both at a high level, while the first control signal terminal G1, the second control signal terminal G2, and the third control signal terminal G3 are all at a low level. The seventh transistor T7, the fourth transistor T4, the second transistor T2, and the first transistor T1 are all turned off, while the fifth transistor T5 and the sixth transistor T6 are turned on. The voltage of the power supply signal terminal ELVDD is supplied to the first terminal N1 of the driving transistor DT. The driving transistor DT generates a driving current under the action of the voltages of the first terminal N1, the gate N2, and the second terminal N3. The generated driving current is supplied to the light-emitting element EL via the output signal terminal OUT, thereby driving the light-emitting element EL to emit light.

[0106] According to the above equations (1) and (2), the driving current generated by the driving transistor DT is no longer proportional to the threshold voltage VTH related, thereby eliminating the threshold voltage V TH The impact on the driving current is used to compensate for the pixel circuit.

[0107] In the above process, the presence of the first transistor T1 can also further stabilize the output of the driving transistor DT. For example, with reference to FIG5 , during the light-emitting phase, the signal (e.g., the third control signal) at the third control signal terminal G3 shared by the first transistor T1 and the second transistor T2 turns off both the first transistor T1 and the second transistor T2, thereby preventing the voltage at the output signal terminal OUT from affecting the voltage at the node N3, which is beneficial to stabilizing the driving signal output by the driving transistor DT.

[0108] Figure 10 shows a signal timing diagram of a pixel circuit according to another embodiment of the present disclosure. The signal timing of Figure 10 is applicable to the pixel circuit of the above embodiment, such as the pixel circuit of Figure 6. The working process of the pixel circuit 600 will be described below in conjunction with Figures 6 and 10. By comparing the signal timings of Figures 10 and 8, it can be seen that the working process of the pixel circuit 600 of Figure 6 is similar to the working process of the pixel circuit 200 of Figure 2, and the difference lies at least in the operation of the reset phase. For the sake of brevity, the difference will be mainly described in detail.

[0109] During the reset phase, the first light-emitting signal terminal EM1 is at a low level, the signal at the second light-emitting signal terminal EM2 is at a high level, the signals at the second control signal terminal G2, the third control signal terminal G3, the fourth control signal terminal G4, and the fifth control signal terminal G5 are at a high level, and the signal at the first control signal terminal G1 is at a low level. The low level of the first control signal terminal G1 turns off the seventh transistor T7, thereby preventing data from being written to the node N3. The low level of the first light-emitting signal terminal EM1 turns off the fifth transistor T5, thereby disconnecting the power supply signal terminal ELVDD from the node N1. The high level of the fifth control signal terminal G5 turns on the third transistor T3, thereby supplying the voltage of the second voltage terminal Vref to the node N1. The signal at the power supply signal terminal ELVDD can be a constant high level, such as 5V, 10V, or other suitable voltages. The high levels of the second control signal terminal G2, the third control signal terminal G3, and the fourth control signal terminal G4 respectively turn on the fourth transistor T4, the second transistor T2, and the first transistor T1, thereby setting node N2 to the voltage of the second voltage terminal Vref. The voltage of the first voltage terminal Vini is provided to the output signal terminal OUT, which is connected to node N2 via the first capacitor C1. The high level of the second light-emitting signal terminal EM2 turns on the sixth transistor T6, thereby providing the voltage of the output signal terminal OUT to node N3. Through the above process, nodes N1 and N2 are set to the voltage of the second voltage terminal Vref, and node N3 and the output signal terminal OUT are set to the voltage of the first voltage terminal Vini.

[0110] In the compensation phase, the fifth control signal terminal G5 becomes low level and the third transistor T3 is turned off. Since the second luminous signal EM2 and the third control signal G3 remain high level, the sixth transistor T6 and the second transistor T2 remain on state, and the potential of the node N3 and the output signal terminal OUT remains at V INI When the third transistor T3 is turned off, the potentials of nodes N1 and N2 are V REF , the potential of node N3 is V INI , and V REF >V INI , so nodes N1 and N2 discharge to node N3 until the potential of node N2 becomes V INI +V TH , where V REF Represents the voltage of the second voltage terminal Vref, V TH represents the threshold voltage of the driving transistor DT.

[0111] During the write phase, the second control signal terminal G2 and the second light emitting signal terminal EM2 become low levels, and the first control signal terminal G1 becomes high. The high level of the first control signal terminal G1 turns on the seventh transistor T7, thereby writing the voltage of the data signal terminal Vdata into the node N3. The low level of the second control signal terminal G2 turns off the fourth transistor T4, and the low level of the second light emitting signal terminal EM2 turns off the first transistor T1. The node N2 becomes V due to the voltage divider effect of the first capacitor C1 and the second capacitor C2. INI +V TH +(V DATA -V INI )*C1 / (C1+C2), where V DATA represents the voltage of the data signal terminal Vdata, C1 represents the capacitance value of the first capacitor C1, and C2 represents the capacitance value of the second capacitor C2. In some embodiments, during the write phase, the high-level duration of the signal at the first control signal terminal G1 can be within the low-level duration of the signal at the second light-emitting signal terminal EM2, so that the entire process of the seventh transistor T7 writing the data voltage to the node N3 is performed during the off-state period of the sixth transistor T6.

[0112] During the light-emitting phase, the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are both at a high level, while the first control signal terminal G1, the second control signal terminal G2, the third control signal terminal G3, the fourth control signal terminal G4, and the fifth control signal terminal G5 are all at a low level. The seventh transistor T7, the fourth transistor T4, the second transistor T2, the first transistor T1, and the third transistor T1 are all turned off, while the fifth transistor T5 and the sixth transistor T6 are turned on. The voltage of the power supply signal terminal ELVDD is supplied to the first terminal N1 of the driving transistor DT. The driving transistor DT generates a driving current under the action of the voltages of the first terminal N1, the gate N2, and the second terminal N3. The generated driving current is supplied to the light-emitting element EL via the output signal terminal OUT, thereby driving the light-emitting element EL to emit light.

[0113] According to the above equations (1) and (2), the driving current generated by the driving transistor DT is no longer proportional to the threshold voltage V TH related, thereby eliminating the threshold voltage V TH In the above process, the presence of the first transistor T1 can also further stabilize the output of the driving transistor DT, which will not be described in detail here.

[0114] In this embodiment, the presence of the third compensation circuit 660 allows the reset of nodes N1 and N2 to be independent of the voltage of the power signal terminal ELVDD. The voltage of the second voltage terminal Vref can be set as needed to reset nodes N1 and N2 to a desired level.

[0115] Those skilled in the art will appreciate that the embodiments described above are exemplary and that they may be improved upon. The structures described in the various embodiments may be freely combined without causing any conflict in structure or principle.

[0116] After describing the preferred embodiments of the present disclosure in detail, those skilled in the art will clearly understand that various changes and modifications may be made without departing from the scope and spirit of the appended claims, and that the present disclosure is not limited to the exemplary embodiments described in the specification.

Claims

1. A pixel circuit comprising: A driving circuit having a control terminal, a first terminal and a second terminal, wherein the driving circuit is configured to generate a driving current flowing through the second terminal; a writing circuit connected to the data signal terminal of the pixel circuit, the first control signal terminal, and the second terminal of the driving circuit, the writing circuit being configured to provide the signal of the data signal terminal to the second terminal of the driving circuit under the control of the first control signal terminal; a light-emitting control circuit connected to a first light-emitting signal terminal, a second light-emitting signal terminal, a power signal terminal, an output signal terminal of the pixel circuit, and a first terminal and a second terminal of the driving circuit, the light-emitting control circuit being configured to electrically connect the first terminal of the driving circuit to the power signal terminal under the control of the first light-emitting signal terminal, and to electrically connect the second terminal of the driving circuit to the output signal terminal under the control of the second light-emitting signal terminal; a first compensation circuit connected between the control terminal and the first terminal of the driving circuit and connected to the second control signal terminal of the pixel circuit, the first compensation circuit being configured to control electrical connection and disconnection between the control terminal and the first terminal of the driving circuit according to a signal at the second control signal terminal; A second compensation circuit is connected between the control terminal of the driving circuit and the output signal terminal and is connected to the first voltage terminal, the third control signal terminal and the fourth control signal terminal of the pixel circuit. The second compensation circuit is used to provide the voltage of the first voltage terminal to the output signal terminal under the control of the third control signal terminal, and to control the electrical connection and disconnection between the output signal terminal and the control terminal of the driving circuit according to the signal of the fourth control signal terminal.

2. The pixel circuit according to claim 1, wherein: The second compensation circuit includes: a first sub-circuit connected to the first voltage terminal, the output signal terminal, and the third control signal terminal, the first sub-circuit being configured to provide a voltage from the first voltage terminal to the output signal terminal under control of the third control signal terminal; The second sub-circuit is connected between the control terminal of the driving circuit and the output signal terminal and is connected to the fourth control signal terminal. The second sub-circuit is used to control the electrical connection and disconnection between the output signal terminal and the control terminal of the driving circuit according to the signal of the fourth control signal terminal.

3. The pixel circuit according to claim 2, wherein: The second sub-circuit includes a first transistor and a first capacitor, the first transistor and the first capacitor are connected in series between the control terminal of the driving circuit and the output signal terminal, and the gate of the first transistor is connected to the fourth control signal terminal.

4. The pixel circuit according to claim 3, wherein: A first electrode of the first transistor is connected to the control end of the driving circuit, a second electrode of the first transistor is connected to the first electrode of the first capacitor, and a second electrode of the first capacitor is connected to the output signal end.

5. The pixel circuit according to claim 3, wherein: A first electrode of the first capacitor is connected to the control end of the driving circuit, a second electrode of the first capacitor is connected to the first electrode of the first transistor, and a second electrode of the first transistor is connected to the output signal end.

6. The pixel circuit according to any one of claims 2 to 5, wherein: The first sub-circuit includes a second transistor, a gate of the second transistor is connected to the third control signal terminal, a first electrode of the second transistor is connected to the first voltage terminal, and a second electrode of the second transistor is connected to the output signal terminal.

7. The pixel circuit according to claim 6, wherein: The second electrode of the second transistor is connected to the output signal end through the first transistor, wherein the second electrode of the second transistor is connected to the first electrode of the first transistor, the second electrode of the first transistor is connected to the output signal end, the first electrode of the first capacitor is connected to the control end of the driving circuit, and the second electrode of the first capacitor is connected to the first electrode of the first transistor.

8. The pixel circuit according to any one of claims 1 to 7, further comprising: A third compensation circuit is connected to the second voltage terminal of the pixel circuit, the fifth control signal terminal and the first terminal of the driving circuit, and the third compensation circuit is used to provide the voltage of the second voltage terminal to the first terminal of the driving circuit under the control of the fifth control signal terminal.

9. The pixel circuit according to claim 8, wherein: The third compensation circuit includes a third transistor, a gate of the third transistor is connected to the fifth control signal terminal, a first electrode of the third transistor is connected to the second voltage terminal, and a second electrode of the third transistor is connected to the first terminal of the driving circuit.

10. The pixel circuit according to any one of claims 1 to 9, wherein: The third control signal terminal and the fourth control signal terminal are independent of each other to receive the third control signal and the fourth control signal respectively, or the third control signal terminal and the fourth control signal terminal are connected to receive the third control signal.

11. The pixel circuit according to any one of claims 1 to 10, wherein: The first compensation circuit includes a fourth transistor, a gate of the fourth transistor is connected to the second control signal terminal, a first electrode of the fourth transistor is connected to the first terminal of the drive circuit, and a second electrode of the fourth transistor is connected to the control terminal of the drive circuit.

12. The pixel circuit according to any one of claims 1 to 11, wherein: The light emitting control circuit includes a fifth transistor and a sixth transistor; The gate of the fifth transistor is connected to the first light emitting signal terminal, the first electrode of the fifth transistor is connected to the power signal terminal, and the second electrode of the fifth transistor is connected to the first terminal of the driving circuit; The gate of the sixth transistor is connected to the second light-emitting signal terminal, the first electrode of the sixth transistor is connected to the second terminal of the driving circuit, and the second electrode of the sixth transistor is connected to the output signal terminal.

13. The pixel circuit according to any one of claims 1 to 12, wherein: The write circuit includes a seventh transistor, a gate of the seventh transistor is connected to the first control signal terminal, a first electrode of the seventh transistor is connected to the data signal terminal, and a second electrode of the seventh transistor is connected to the second terminal of the drive circuit.

14. The pixel circuit according to any one of claims 1 to 13, wherein: The driving circuit includes a driving transistor and a second capacitor, The gate of the driving transistor serves as the control terminal of the driving circuit, the first electrode of the driving transistor serves as the first terminal of the driving circuit, and the second electrode of the driving transistor serves as the second terminal of the driving circuit; A first electrode of the second capacitor is connected to the gate of the driving transistor, and a second electrode of the second capacitor is connected to the second electrode of the driving transistor.

15. A pixel unit, comprising: The pixel circuit according to any one of claims 1 to 14; as well as Light-emitting unit.

16. A method for driving a pixel circuit according to any one of claims 1 to 14, comprising: During the compensation phase, the light emitting control circuit electrically connects the second terminal of the driving circuit to the output signal terminal, the first compensation circuit electrically connects the control terminal and the first terminal of the driving circuit, and the second compensation circuit provides the voltage of the first voltage terminal to the output signal terminal and electrically connects the output signal terminal to the control terminal of the driving circuit; During the writing phase, the first compensation circuit disconnects the control terminal and the first terminal of the driving circuit, the light emitting control circuit disconnects the second terminal of the driving circuit from the output signal terminal, and the writing circuit provides the signal from the data signal terminal to the second terminal of the driving circuit; During the light-emitting stage, the second compensation circuit disconnects the first voltage terminal from the output signal terminal, and disconnects the output signal terminal from the control terminal of the driving circuit. The light-emitting control circuit electrically connects the first terminal of the driving circuit to the power signal terminal, and electrically connects the second terminal of the driving circuit to the output signal terminal. The driving circuit generates a driving current flowing through the second terminal.

17. The method according to claim 16, further comprising: In the reset stage before the compensation stage, the light-emitting control circuit electrically connects the second end of the driving circuit to the output signal end, the first compensation circuit electrically connects the control end and the first end of the driving circuit, and the second compensation circuit provides the voltage of the first voltage end to the output signal end and electrically connects the output signal end to the control end of the driving circuit.

18. The method according to claim 17, further comprising: In the reset phase, the light emitting control circuit electrically connects the power signal terminal to the first terminal of the driving circuit.

19. The method according to claim 17, wherein The pixel circuit also includes a third compensation circuit, and the method also includes: in the reset stage, the light-emitting control circuit disconnects the power signal end from the first end of the driving circuit, and the third compensation circuit provides the voltage of the second voltage end to the first end of the driving circuit.

20. The method according to any one of claims 16 to 19, wherein The third control signal terminal and the fourth control signal terminal are independent of each other to receive the third control signal and the fourth control signal respectively. In the light-emitting stage, the second compensation circuit disconnects the first voltage terminal from the output signal terminal according to the third control signal, and disconnects the output signal terminal from the control terminal of the driving circuit according to the fourth control signal.

21. The method according to claim 20, wherein In the light-emitting stage, the second compensation circuit disconnects the output signal terminal from the control terminal of the driving circuit before disconnecting the first voltage terminal from the output signal terminal.

22. The method according to any one of claims 16 to 19, wherein The third control signal terminal and the fourth control signal terminal are connected to receive a third control signal, In the light-emitting stage, the second compensation circuit disconnects the first voltage terminal from the output signal terminal and disconnects the output signal terminal from the control terminal of the driving circuit according to the third control signal.

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