Drive backplane, display substrate, and display device

Abstract

The present disclosure provides a drive backplane, a display substrate, and a display device. The drive backplane comprises a base substrate; the base substrate has a plurality of connecting areas; the drive backplane further comprises a plurality of data lines, a plurality of gate lines, and a plurality of voltage lines, and a plurality of conductive pad groups, and the conductive pad groups are arranged in the corresponding connecting areas; each conductive pad group comprises a plurality of conductive pads; the plurality of conductive pads comprise a first-type conductive pad for transmitting data voltage, a second-type conductive pad for transmitting a gate drive signal, and a third-type conductive pad for transmitting a voltage signal; each voltage line comprises a first voltage line part extending in a first direction; the first direction intersects with a second direction; the first-type conductive pad is electrically connected to the data line, the second-type conductive pad is electrically connected to the gate line, and the third-type conductive pad is electrically connected to the voltage line. The present disclosure can reduce the cost.

Description

Driving backplane, display substrate and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a driving backplane, a display substrate, and a display device. Background Art

[0002] In the related art, the driving backplane includes multiple rows and columns of connection areas and multiple rows and columns of micro driving ICs (integrated circuits). The micro driving ICs are used to provide driving signals for pixel circuits arranged in corresponding connection areas. The cost of the related driving backplane is high.

[0003] Summary of the Invention

[0004] In one aspect, an embodiment of the present disclosure provides a driving backplane, comprising a base substrate having a plurality of connection regions; the driving backplane further comprising a plurality of data lines, a plurality of gate lines, a plurality of voltage lines, and a plurality of conductive pad groups, the conductive pad groups being disposed in corresponding connection regions; the conductive pad groups comprising a plurality of conductive pads;

[0005] The plurality of conductive pads include a first type of conductive pad for transmitting a data voltage, a second type of conductive pad for transmitting a gate driving signal, and a third type of conductive pad for transmitting a voltage signal;

[0006] One of the data line and the gate line extends along a first direction, and the other of the data line and the gate line extends along a second direction; the voltage line includes a first voltage line portion extending in the first direction; the first direction intersects the second direction;

[0007] The first type of conductive pads are electrically connected to the data lines, the second type of conductive pads are electrically connected to the gate lines, and the third type of conductive pads are electrically connected to the voltage lines.

[0008] Optionally, the voltage line further includes a second voltage line portion extending along a second direction; the second voltage line portion is electrically connected to the first voltage line portion;

[0009] The first voltage line portion and the second voltage line portion are disposed in different conductive layers.

[0010] Optionally, the line width of the first voltage line portion is greater than the line width of the data line.

[0011] Optionally, the driving backplane according to at least one embodiment of the present disclosure further includes a driving module and a power supply voltage lead provided on the base substrate; the voltage line includes a power supply voltage line; the power supply voltage line includes a first power supply voltage line portion extending along the first direction and a second power supply voltage line portion extending along the second direction;

[0012] The driving module includes a power supply voltage output terminal, and the power supply voltage output terminal is electrically connected to the power supply voltage lead;

[0013] The driving module is used to provide a power supply voltage signal through the power supply voltage output terminal;

[0014] The power supply voltage lead is electrically connected to the first power supply voltage line portion.

[0015] Optionally, the driving backplane according to at least one embodiment of the present disclosure further includes a driving module and a reset voltage lead provided on the base substrate; the voltage line includes a reset voltage line; the reset voltage line includes a first reset voltage line portion extending along the first direction and a second reset voltage line portion extending along the second direction;

[0016] The driving module includes a reset voltage output terminal, and the reset voltage output terminal is electrically connected to the reset voltage lead;

[0017] The driving module is used to provide a reset voltage signal through the reset voltage output terminal;

[0018] The reset voltage lead is electrically connected to the first reset voltage line portion.

[0019] Optionally, the driving backplane according to at least one embodiment of the present disclosure further comprises a plurality of control voltage lines; the control voltage lines comprise a first control voltage line portion extending along the first direction; the plurality of conductive pads comprise a fourth type of conductive pad for transmitting a control voltage;

[0020] The fourth type conductive pad is electrically connected to the control voltage line.

[0021] Optionally, the control voltage line further includes a second control voltage line portion extending along the second direction; the first control voltage line portion is electrically connected to the second control voltage line portion;

[0022] The first control voltage line portion and the second control voltage line portion are disposed in different conductive layers.

[0023] Optionally, the line width of the first control voltage line portion is greater than the line width of the data line.

[0024] Optionally, the driving backplane according to at least one embodiment of the present disclosure further includes a driving module disposed on the substrate; the driving module includes a first control voltage output terminal, and the driving module is configured to provide a control voltage through the first control voltage output terminal;

[0025] The first control voltage output terminal is electrically connected to at least one first control voltage line portion.

[0026] Optionally, the driving module further includes a second control voltage output terminal, and the driving module is configured to provide a control voltage through the second control voltage output terminal;

[0027] The second control voltage output terminal is electrically connected to a first end portion of a second control voltage line portion closest to the driving module, and the first control voltage output terminal is electrically connected to a second end portion of the second control voltage line portion closest to the driving module.

[0028] Optionally, the driving backplane according to at least one embodiment of the present disclosure further includes a plurality of driving control lines; the plurality of conductive pads include a fifth type of conductive pad for transmitting driving control signals;

[0029] The driving control line extends along the second direction;

[0030] The fifth type of conductive pad is electrically connected to the driving control line.

[0031] Optionally, the data line and the gate line are provided in different conductive layers;

[0032] The first voltage line portion and the gate line are provided in different conductive layers;

[0033] The second voltage line portion and the data line are arranged in different conductive layers;

[0034] The data line is provided in the same layer as the first voltage line portion, and the gate line is provided in the same layer as the second voltage line portion.

[0035] Optionally, the first control voltage line portion and the gate line are provided in different conductive layers; the second control voltage line portion and the data line are provided in different conductive layers;

[0036] The data line is provided in the same layer as the first control voltage line portion, and the gate line is provided in the same layer as the second control voltage line portion.

[0037] Optionally, the orthographic projection of the data line on the base substrate is arranged between the orthographic projections of two first voltage line portions on the base substrate.

[0038] Optionally, the orthographic projection of the data line on the base substrate is arranged between the orthographic projection of the first control voltage line portion on the base substrate and the orthographic projection of at least one first voltage line portion on the base substrate.

[0039] Optionally, an orthographic projection of the first voltage line portion on the base substrate does not overlap with an orthographic projection of the data line on the base substrate;

[0040] An orthographic projection of the first control voltage line portion on the base substrate does not overlap with an orthographic projection of the data line on the base substrate.

[0041] Optionally, the driving backplane according to at least one embodiment of the present disclosure further includes a gate driving unit provided on the base substrate;

[0042] The gate driving unit is used to generate a multi-level gate driving signal.

[0043] Optionally, the driving backplane according to at least one embodiment of the present disclosure further includes a gate driving module, wherein the gate driving module includes a plurality of gate driving circuits connected in cascade to each other; the gate driving circuit is configured to generate and output a corresponding level gate driving signal through its output terminal;

[0044] The output end of the gate driving circuit is electrically connected to the input end of the adjacent next-stage gate driving circuit, and is used to provide an input signal to the adjacent next-stage gate driving circuit.

[0045] In a second aspect, an embodiment of the present disclosure provides a display substrate comprising the aforementioned driving backplane.

[0046] Optionally, the display substrate according to at least one embodiment of the present disclosure includes a plurality of light-emitting components disposed on the backplane; the light-emitting components include a substrate, and at least one pixel circuit disposed on the substrate, the pixel circuit including a light-emitting unit and a pixel driving circuit for driving the light-emitting unit; the at least one pixel circuit includes a first pixel circuit;

[0047] The first pixel circuit receives a data voltage through a first first-type conductive pad;

[0048] In the second direction, the first first-type conducting pad is disposed between the second-type conducting pad and at least one third-type conducting pad.

[0049] Optionally, the at least one pixel circuit further includes a second pixel circuit; the second pixel circuit receives a data voltage through a second first-type conductive pad;

[0050] In the second direction, the second first-type conducting pad is disposed between the second-type conducting pad and at least one third-type conducting pad.

[0051] Optionally, the at least one pixel circuit further includes a third pixel circuit; the second pixel circuit receives a data voltage through a third first-type conductive pad;

[0052] The third first-type conducting pad and at least one third-type conducting pad are arranged along the first direction, or the third first-type conducting pad and the second-type conducting pad are arranged along the first direction.

[0053] Optionally, along the second direction, a first third-category conducting pad and a second third-category conducting pad are disposed on two opposite sides of the first first-category conducting pad.

[0054] Optionally, the display substrate according to at least one embodiment of the present disclosure includes a plurality of light-emitting components disposed on the backplane; the light-emitting components include a substrate, and at least one pixel circuit disposed on the substrate, the pixel circuit including a light-emitting unit and a pixel driving circuit for driving the light-emitting unit; the pixel driving circuit including a driving transistor and a data writing circuit;

[0055] The gate of the driving transistor is electrically connected to the control node, the first electrode of the driving transistor is electrically connected to the first node, and the second electrode of the driving transistor is electrically connected to the second node. The driving transistor is used to generate a driving current under the control of the potential of the control node;

[0056] The control end of the data writing circuit is electrically connected to the gate line, the first end of the data writing circuit is electrically connected to the data line, and the second end of the data writing circuit is electrically connected to the first node. The data writing circuit is used to control the writing of the display data voltage provided by the data line into the first node under the control of the gate drive signal provided by the gate line.

[0057] Optionally, the pixel driving circuit further includes a first light emitting control circuit;

[0058] A control terminal of the first light-emitting control circuit is electrically connected to a light-emitting control line, a first terminal of the first light-emitting control circuit is electrically connected to a power supply voltage line, and a second terminal of the first light-emitting control circuit is electrically connected to the first node, wherein the first light-emitting control circuit is configured to control communication between the power supply voltage line and the first node under control of a light-emitting control signal provided by the light-emitting control line;

[0059] The power voltage line is electrically connected to the first third-type conductive pad.

[0060] Optionally, the pixel driving circuit further includes a second light emitting control circuit and a first control circuit;

[0061] The second light-emitting control circuit is electrically connected to the first control terminal, the second node, and the first electrode of the light-emitting unit, respectively, and is configured to control the second node to be connected to the first electrode of the light-emitting unit under the control of the potential of the first control terminal; the second electrode of the light-emitting unit is electrically connected to the first voltage line; and the first voltage line is electrically connected to the second third-category conductive pad;

[0062] The first control circuit is electrically connected to the first control terminal, the second control terminal, and the data line, respectively. The first input terminal of the first control circuit is electrically connected to the light-emitting control line, the second input terminal of the first control circuit is electrically connected to the control voltage line, and the control terminal of the first control circuit is electrically connected to the reset control line. The first control circuit is configured to write a control data voltage provided by the data line into the second control terminal under the control of a reset control signal provided by the reset control line, maintain the potential of the second control terminal, and control the connection between the first control terminal and the light-emitting control line or the control voltage line under the control of the potential of the second control terminal.

[0063] The light emitting control line is electrically connected to the first fifth type conductive pad, the reset control line is electrically connected to the second fifth type conductive pad, and the control voltage line is electrically connected to the fourth type conductive pad.

[0064] Optionally, the light-emitting component includes a first pixel circuit, a second pixel circuit, and a third pixel circuit; the plurality of conductive pads include a first first-category conductive pad, a second first-category conductive pad, a third first-category conductive pad, a second-category conductive pad, a first third-category conductive pad, a second third-category conductive pad, a fourth-category conductive pad, a first fifth-category conductive pad, and a second fifth-category conductive pad;

[0065] A first end of the data writing circuit in the first pixel circuit is electrically connected to a first first-type conductive pad, a first end of the data writing circuit in the second pixel circuit is electrically connected to a second first-type conductive pad, and a first end of the data writing circuit in the third pixel circuit is electrically connected to a third first-type conductive pad;

[0066] The control end of the data writing circuit in the first pixel circuit, the control end of the data writing circuit in the second pixel circuit, and the control end of the data writing circuit in the third pixel circuit are all electrically connected to the second type of conductive pad;

[0067] The first end of the first light emitting control circuit in the first pixel circuit, the first end of the first light emitting control circuit in the second pixel circuit, and the first end of the first light emitting control circuit in the third pixel circuit are all electrically connected to a first third-type conductive pad;

[0068] The second electrode of the light-emitting element in the first pixel circuit, the second electrode of the light-emitting element in the second pixel circuit, and the second electrode of the light-emitting element in the third pixel circuit are all electrically connected to the second third-type conductive pad;

[0069] The second input terminal of the first control circuit in the first pixel circuit, the second input terminal of the first control circuit in the second pixel circuit, and the second input terminal of the first control circuit in the third pixel circuit are all electrically connected to the fourth type of conductive pad;

[0070] The control end of the first light emitting control circuit in the first pixel circuit, the control end of the first light emitting control circuit in the second pixel circuit, and the control end of the first light emitting control circuit in the third pixel circuit are all electrically connected to the first fifth-category conductive pad;

[0071] The control end of the first light emitting control circuit in the first pixel circuit, the control end of the first light emitting control circuit in the second pixel circuit, and the control end of the first light emitting control circuit in the third pixel circuit are all electrically connected to the first fifth-category conductive pad;

[0072] The control end of the first control circuit in the first pixel circuit, the control end of the first control circuit in the second pixel circuit, and the control end of the first control circuit in the third pixel circuit are all electrically connected to the second fifth-category conducting pad.

[0073] Optionally, the display substrate according to at least one embodiment of the present disclosure includes a light-emitting component disposed on the driving backplane and electrically connected to the conductive pad;

[0074] The light emitting component comprises:

[0075] a light-emitting unit, the light-emitting unit comprising: a first electrode, a second electrode, and a light-emitting portion electrically connected to the first electrode and the second electrode respectively;

[0076] A driving unit having the pixel driving circuit, the driving unit comprising: a third electrode, a fourth electrode, and a driving circuit, the third electrode and the fourth electrode being located on a side of the driving unit facing the light-emitting unit, the third electrode and the fourth electrode being electrically connected to the driving circuit respectively, the third electrode being electrically connected to the first electrode, and the fourth electrode being electrically connected to the second electrode;

[0077] a first substrate, located on a side of the light emitting unit away from the driving unit. Optionally, the light emitting assembly includes a plurality of light emitting units;

[0078] The plurality of light emitting units include a first color light emitting unit, a second color light emitting unit and a third color light emitting unit;

[0079] The first color, the second color and the third color are different from each other.

[0080] Optionally, the light-emitting unit includes a color filter layer, a color conversion layer, and a light-emitting layer stacked in sequence in a direction away from the first substrate; the light-emitting layer emits blue light;

[0081] The light-emitting layer includes a first semiconductor layer, a multi-quantum well layer and a second semiconductor layer that are stacked, wherein the first semiconductor layer is electrically connected to the first electrode, the second semiconductor layer is electrically connected to the second electrode, and the light-emitting layer includes a first light-emitting portion, a second light-emitting portion and a third light-emitting portion.

[0082] Optionally, the driving circuit includes a plurality of thin film transistors, each of which includes a gate, a source and a drain.

[0083] Optionally, the driving unit further includes a substrate; the driving circuit includes a buffer layer, an active layer, a first gate insulating layer, a first gate layer, an interlayer dielectric layer, a source and drain layer, and a planar layer, which are located on one side of the substrate and stacked in sequence; the third electrode and the fourth electrode are located on a side of the planar layer away from the substrate;

[0084] The active layer includes a plurality of active patterns corresponding to the plurality of thin film transistors, and each of the active patterns includes a source region, a drain region, and a channel region;

[0085] The source electrode and the drain electrode of the thin film transistor are located in the source-drain electrode layer, the source electrode of the thin film transistor is connected to the source region, and the drain electrode of the thin film transistor is connected to the drain region;

[0086] The first gate layer includes a plurality of gate patterns corresponding to the plurality of thin film transistors, and the channel region is an overlapping region of an orthographic projection of the gate pattern on the substrate and an orthographic projection of the active pattern on the substrate.

[0087] Optionally, the pixel driving circuit includes a driving transistor and a data writing circuit; at least one of the driving transistor and the data writing circuit includes the thin film transistor.

[0088] Optionally, the pixel driving circuit further includes a first light emitting control circuit, a second light emitting control circuit and a first control circuit;

[0089] At least one of the first light emission control circuit, the second light emission control circuit, and the first control circuit includes the thin film transistor.

[0090] Optionally, the light-emitting component further includes a plurality of pins;

[0091] The plurality of pins are located on a side of the driving circuit away from the light-emitting unit and are electrically connected to the driving circuit. The plurality of pins are connected to the plurality of conductive pads in one conductive pad group in a one-to-one correspondence.

[0092] Optionally, the driving unit further includes a substrate and a connection structure, the substrate has a connection via, the connection structure is located in the connection via, and the driving circuit is located on one side of the substrate;

[0093] The pin is located on a side of the substrate away from the driving circuit, and the pin is in contact with the connection structure. The pin and the driving circuit are connected via the connection structure.

[0094] Optionally, the driving circuit includes a plurality of thin film transistors, each of which includes a gate, a source and a drain;

[0095] One of the plurality of pins is connected to a source electrode of a thin film transistor among the plurality of thin film transistors, and is used for providing the driving circuit with a data driving signal transmitted from a display backplane in a display panel.

[0096] In a third aspect, an embodiment of the present disclosure provides a display device comprising the above-mentioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0097] FIG1 is a structural diagram of a driving backplane according to at least one embodiment of the present disclosure;

[0098] FIG2A is a structural diagram of a driving backplane according to at least one embodiment of the present disclosure;

[0099] FIG2B is a structural diagram of a driving backplane according to at least one embodiment of the present disclosure;

[0100] FIG2C is a structural diagram of a driving backplane according to at least one embodiment of the present disclosure;

[0101] FIG2D is a structural diagram of a driving backplane according to at least one embodiment of the present disclosure;

[0102] FIG3 is a structural diagram of a driving backplane according to at least one embodiment of the present disclosure;

[0103] FIG4 is a schematic diagram showing the positions of the conductive pads included in the driving backplane according to at least one embodiment of the present disclosure;

[0104] FIG5 is a structural diagram of at least one embodiment of a pixel circuit;

[0105] FIG6 is a circuit diagram of at least one embodiment of a pixel circuit;

[0106] FIG7 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG6 ;

[0107] FIG8 is a circuit diagram of three pixel circuits included in an LED chip;

[0108] FIG9 is a structural diagram of at least one embodiment of an LED chip;

[0109] FIG10 is a circuit diagram of at least one embodiment of a pixel circuit;

[0110] FIG11A is a schematic structural diagram of a light-emitting assembly provided by an embodiment of the present disclosure;

[0111] FIG11B is a schematic diagram of the connection relationship between a light-emitting component and a driving backplane provided by an embodiment of the present disclosure;

[0112] FIG12 is a schematic structural diagram of a light-emitting unit provided in an embodiment of the present disclosure;

[0113] FIG13 is a schematic structural diagram of a light-emitting unit provided in an embodiment of the present disclosure;

[0114] FIG14 is a schematic structural diagram of a driving unit provided by an embodiment of the present disclosure;

[0115] FIG15 is a schematic diagram illustrating a combination of at least one embodiment of the driving unit shown in FIG14 and at least one embodiment of the light-emitting unit shown in FIG12 ;

[0116] FIG16 is a flow chart of the steps of the preparation process used in preparing at least one embodiment shown in FIG15;

[0117] FIG. 17 is a structural diagram of a display substrate according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0118] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0119] The transistors used in all embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor except the gate, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0120] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0121] The driving backplane according to the embodiment of the present disclosure includes a base substrate having a plurality of connection areas; the driving backplane further includes a plurality of data lines, a plurality of gate lines, a plurality of voltage lines, and a plurality of conductive pad groups; the conductive pad groups are arranged in corresponding connection areas; the conductive pad groups include a plurality of conductive pads;

[0122] The plurality of conductive pads include a first type of conductive pad for transmitting a data voltage, a second type of conductive pad for transmitting a gate driving signal, and a third type of conductive pad for transmitting a voltage signal;

[0123] One of the data line and the gate line extends along a first direction, and the other of the data line and the gate line extends along a second direction; the voltage line includes a first voltage line portion extending in the first direction; the first direction intersects the second direction;

[0124] The first type of conductive pads are electrically connected to the data lines, the second type of conductive pads are electrically connected to the gate lines, and the third type of conductive pads are electrically connected to the voltage lines.

[0125] In at least one embodiment of the present disclosure, the data line may extend along a first direction, and the gate line may extend along a second direction; or, the data line may extend along the second direction, and the gate line may extend along the first direction.

[0126] In at least one embodiment of the present disclosure, the voltage line may be a DC voltage line for providing a DC voltage signal, but the present invention is not limited thereto.

[0127] The driver backplane described in the embodiment of the present disclosure includes a base substrate, a plurality of data lines, a plurality of gate lines, and a plurality of voltage lines disposed on the base substrate, and a plurality of conductive pads disposed in a connection region of the base substrate. The plurality of conductive pads include a first type of conductive pad electrically connected to the data lines, a second type of conductive pad electrically connected to the gate lines, and a third type of conductive pad electrically connected to the voltage lines. The first type of conductive pad is used to transmit data voltages, the second type of conductive pad is used to transmit gate drive signals, and the third type of conductive pad is used to transmit voltage signals. The driver backplane described in the embodiment of the present disclosure can be a passive backplane, which can effectively reduce the cost of the driver backplane.

[0128] The driving mode of the driving backplane described in the embodiment of the present disclosure is PM (passive matrix) driving. Multiple LED (light-emitting diode) chips can be set in the connection area. The driving backplane only needs to provide the connection of multiple signals required by the LED chips. The signals can be provided by the driving integrated circuit and the gate driving integrated circuit (or gate driving module). The multiple signals may include: gate driving signals, data voltages, and voltage signals; the voltage signals may include power supply voltage signals and reset voltage signals. The driving integrated circuit is used to provide data voltages and voltage signals, and the gate driving integrated circuit (or gate driving module) is used to provide gate driving signals.

[0129] Optionally, the first direction may be a vertical direction, and the second direction may be a horizontal direction, but is not limited thereto.

[0130] In at least one embodiment of the present disclosure, the voltage signal may include a power voltage signal and a reset voltage signal, and the voltage line may include a power voltage line and a reset voltage line; but the present invention is not limited thereto.

[0131] Optionally, the reset voltage line may be used to provide a reset voltage signal, and the reset voltage signal may be a low voltage signal.

[0132] In a specific implementation, the pixel circuit may include a reset transistor for resetting the potential of the gate of the driving transistor, the gate of the reset transistor may be electrically connected to a reset control line, the first electrode of the reset transistor may be electrically connected to a reset voltage line, and the second electrode of the reset transistor may be electrically connected to the gate of the driving transistor. When the reset transistor is turned on, the gate of the driving transistor is reset by a reset voltage signal provided by the reset voltage line.

[0133] In related technologies, the cost of MLED (micro-light-emitting diode) direct display products primarily includes the cost of the LED (light-emitting diode) chip, the LED component, and the driver backplane, which includes the driver IC. This cost can be reduced by using the lowest-cost blue LED chip and implementing color conversion. Alternatively, the LED component cost can be reduced by using a single LED chip with three blue light-emitting regions.

[0134] In the related art, the driving backplane includes multiple rows and columns of connection areas and multiple rows and columns of micro-driving ICs (integrated circuits). The micro-driving ICs are used to provide driving signals for pixel circuits arranged in the corresponding connection areas. However, the driving backplane described in the embodiment of the present disclosure does not need to be provided with the multiple rows and columns of micro-driving ICs. By providing wiring and conductive pads for providing data voltages, gate driving signals, and voltage signals, plus a driving integrated circuit and a gate driving integrated circuit (or gate driving module), the display control of the pixel circuit can be achieved, thereby reducing the cost of using many micro-driving ICs.

[0135] In at least one embodiment of the present disclosure, the voltage line further includes a second voltage line portion extending along a second direction; the second voltage line portion is electrically connected to the first voltage line portion;

[0136] The first voltage line portion and the second voltage line portion are disposed in different conductive layers.

[0137] In a specific implementation, the voltage line may include a first voltage line portion extending along a first direction, and a second voltage line portion extending along a second direction; the first voltage line portion and the second voltage line portion are arranged in different conductive layers and are electrically connected to each other.

[0138] In actual operation, the driving backplane may include at least two routing layers, and the first voltage line portion may be made through one of the routing layers, and the second voltage line portion may be made through another routing layer. An insulating layer is provided between one of the routing layers and the other routing layer, and the first voltage line portion may be electrically connected to the second voltage line portion through a via hole passing through the insulating layer.

[0139] In at least one embodiment of the present disclosure, multiple first voltage line portions and multiple second voltage line portions are arranged in a grid pattern to reduce the resistance and capacitance of the voltage lines, thereby reducing the IR voltage drop (IR voltage drop refers to a phenomenon in which the voltage drops or rises on the power supply and ground networks in an integrated circuit) and RC delay (RC delay is a signal delay caused by the process of controlling the charging and discharging of a capacitor by a resistor). Compared to related solutions using multiple micro-integrated circuits and related PM drive solutions based on PCBs (printed circuit boards), at least one embodiment of the present disclosure has a low dependence on DC voltage signals (DC voltage signals do not directly affect the generated current and pulse width), can be made larger in size and achieve a small pixel pitch, further reducing the cost of splicing and the cost of peripheral driver ICs.

[0140] Optionally, the line width of the first voltage line portion is greater than the line width of the data line.

[0141] In a specific implementation, the line width of the first voltage line portion extending along the first direction (the first direction may be a vertical direction) may be set to be wider to reduce the resistance and capacitance of the voltage line.

[0142] In at least one embodiment of the present disclosure, the line width of the first voltage line portion may be greater than the line width of the second voltage line portion, and the line width of the first voltage line portion may be greater than the line width of the gate line.

[0143] Optionally, the line width of the first voltage line portion may satisfy at least one of the following three conditions:

[0144] The line width of the first voltage line portion is greater than the line width of the data line;

[0145] The line width of the first voltage line portion may be greater than the line width of the second voltage line portion;

[0146] A line width of the first voltage line portion may be greater than a line width of the gate line.

[0147] In at least one embodiment of the present disclosure, a line width of the first power voltage line portion is greater than a line width of the data line, and a line width of the first reset voltage line portion is greater than a line width of the data line.

[0148] The driving backplane according to at least one embodiment of the present disclosure further comprises a driving module and a power supply voltage lead provided on the substrate; the voltage line comprises a power supply voltage line; the power supply voltage line comprises a first power supply voltage line portion extending along a first direction and a second power supply voltage line portion extending along a second direction;

[0149] The driving module includes a power supply voltage output terminal, and the power supply voltage output terminal is electrically connected to the power supply voltage lead;

[0150] The driving module is used to provide a power supply voltage signal through the power supply voltage output terminal;

[0151] The power supply voltage lead is electrically connected to the first power supply voltage line portion.

[0152] Optionally, the driving module may be a source driver IC (integrated circuit).

[0153] In a specific implementation, the driving module can output a power supply voltage signal through a power supply voltage output terminal, and the driving backplane can include a power supply voltage lead extending in a horizontal direction. The power supply voltage lead can be arranged on the opposite side of the driving module, and the power supply voltage lead is electrically connected to multiple vertical first power supply voltage lines to reduce the number of power supply voltage output terminals used by the driving module.

[0154] Optionally, the power supply voltage lead may extend along the second direction, but is not limited thereto.

[0155] In at least one embodiment of the present disclosure, the driving module may be at least one of a driving circuit board, a driving chip, and a driving circuit structure directly manufactured on a substrate through a semiconductor process.

[0156] The driving backplane according to at least one embodiment of the present disclosure further comprises a driving module and a reset voltage lead provided on the substrate; the voltage line comprises a reset voltage line; the reset voltage line comprises a first reset voltage line portion extending along a first direction and a second reset voltage line portion extending along a second direction;

[0157] The driving module includes a reset voltage output terminal, and the reset voltage output terminal is electrically connected to the reset voltage lead;

[0158] The driving module is used to provide a reset voltage signal through the reset voltage output terminal;

[0159] The reset voltage lead is electrically connected to the first reset voltage line portion.

[0160] In a specific implementation, the driving module can output a reset voltage signal through a reset voltage output terminal, and the driving backplane can include a reset voltage lead extending in a horizontal direction. The reset voltage lead can be arranged on the opposite side of the driving module, and the reset voltage lead is electrically connected to multiple vertical first reset voltage line portions to reduce the number of reset voltage output terminals used by the driving module.

[0161] Optionally, the reset voltage lead may extend along the second direction, but is not limited thereto.

[0162] The driving backplane according to at least one embodiment of the present disclosure further comprises a plurality of control voltage lines; the control voltage lines comprise a first control voltage line portion extending along a first direction; the plurality of conductive pads comprise a fourth type of conductive pad for transmitting a control voltage;

[0163] The fourth type conductive pad is electrically connected to the control voltage line.

[0164] In a specific implementation, the driving backplane may also include multiple control voltage lines, which are used to provide control voltage, and the control voltage may be a high-frequency pulse voltage signal; the control voltage line may include a first control voltage line portion extending along a first direction, and the multiple conductive pads may include a fourth type of conductive pad electrically connected to the control voltage line for transmitting the control voltage.

[0165] In at least one embodiment of the present disclosure, when it is necessary to control the pixel circuit to operate in a low grayscale mode, a control voltage can be provided to the first control terminal in the first control circuit in the pixel circuit through a control voltage line, so that in the light-emitting stage, the second light-emitting control circuit in the pixel circuit operates under the control of a high-frequency pulse signal, and the brightness is adjusted by controlling the duty cycle of the control voltage to achieve low grayscale display.

[0166] In at least one embodiment of the present disclosure, the control voltage line further includes a second control voltage line portion extending along a second direction; the first control voltage line portion is electrically connected to the second control voltage line portion;

[0167] The first control voltage line portion and the second control voltage line portion are disposed in different conductive layers.

[0168] In a specific implementation, the control voltage line may further include a second control voltage line portion electrically connected to the first control voltage line portion and extending along a second direction, with the first control voltage line portion and the second control voltage line portion being disposed on different conductive layers. In at least one embodiment of the present disclosure, the plurality of first control voltage line portions and the plurality of second control voltage line portions are arranged in a grid-like manner to reduce the resistance and capacitance of the control voltage line, thereby reducing the IR drop (IR drop refers to a phenomenon in which the voltage drops or rises on the power supply and ground networks in an integrated circuit) and RC delay (RC delay is a signal delay caused by the charging and discharging process of the capacitor controlled by the resistor) of the control voltage line.

[0169] During specific implementation, the load on the control voltage line affects the low grayscale uniformity, so the load on the control voltage line needs to be reduced.

[0170] Optionally, the line width of the first control voltage line portion is greater than the line width of the data line.

[0171] In a specific implementation, the line width of the first control voltage line portion extending along the first direction (the first direction may be a vertical direction) may be set to be wider to reduce the resistance of the control voltage line and reduce the load of the control voltage line.

[0172] In at least one embodiment of the present disclosure, the line width of the first control voltage line portion may be greater than the line width of the second control voltage line portion, and the line width of the first control voltage line portion may be greater than the line width of the gate line.

[0173] In at least one embodiment of the present disclosure, the line width of the first control voltage line portion may satisfy at least one of the following three conditions:

[0174] The line width of the first control voltage line portion is greater than the line width of the data line;

[0175] The line width of the first control voltage line portion may be greater than the line width of the second control voltage line portion;

[0176] A line width of the first control voltage line portion may be greater than a line width of the gate line.

[0177] The driving backplane according to at least one embodiment of the present disclosure further includes a driving module disposed on the substrate; the driving module includes a first control voltage output terminal, and the driving module is configured to provide a control voltage through the first control voltage output terminal;

[0178] The first control voltage output terminal is electrically connected to at least one first control voltage line portion.

[0179] In a specific implementation, the driving module can provide the control voltage to the vertical first control voltage line portion through the first control voltage output terminal, so as to reduce the number of output terminals used by the driving module to output the control voltage.

[0180] In at least one embodiment of the present disclosure, the driving module further includes a second control voltage output terminal electrically connected, and the driving module is configured to provide the second control voltage output terminal with a control voltage;

[0181] The second control voltage output terminal is electrically connected to the first end of the second control voltage line portion closest to the driving module, and the first control voltage output terminal is electrically connected to the second end of the second control voltage line portion closest to the driving module.

[0182] In a specific implementation, the driving module may further include a second control voltage output terminal for providing a control voltage, the second control voltage output terminal being electrically connected to the first end of the second control voltage line portion closest to the driving module, and the first control voltage output terminal being electrically connected to the second end of the second control voltage line portion closest to the driving module, so as to improve the uniformity of the control voltage on the second control voltage line in the horizontal direction, reduce the lead distance between the second control voltage output terminal and the first end of the second control voltage line portion, and reduce the resistance of the lead.

[0183] The driving backplane according to at least one embodiment of the present disclosure further includes a plurality of driving control lines; the plurality of conductive pads include a fifth type of conductive pad for transmitting driving control signals;

[0184] The driving control line extends along the second direction;

[0185] The fifth type of conductive pad is electrically connected to the driving control line.

[0186] Optionally, the drive control line may include a light-emitting control line and a reset control line, the drive control signal may include a light-emitting control signal and a reset control signal, the light-emitting control line and the reset control line may extend along the second direction, and the multiple conductive pads may include a first fifth-category conductive pad electrically connected to the light-emitting control line, and a second fifth-category conductive pad electrically connected to the reset control line.

[0187] Optionally, the data line and the gate line are provided in different conductive layers;

[0188] The first voltage line portion and the gate line are provided in different conductive layers;

[0189] The second voltage line portion and the data line are arranged in different conductive layers;

[0190] The data line is provided in the same layer as the first voltage line portion, and the gate line is provided in the same layer as the second voltage line portion.

[0191] In a specific implementation, the data line and the gate line can be set in a different conductive layer, the first voltage line portion and the gate line can be set in a different conductive layer, and the second voltage line portion and the data line can be set in a different conductive layer.

[0192] Optionally, the first control voltage line portion and the gate line are provided in different conductive layers; the second control voltage line portion and the data line are provided in different conductive layers;

[0193] The data line is provided in the same layer as the first control voltage line portion, and the gate line is provided in the same layer as the second control voltage line portion.

[0194] In a specific implementation, the first control voltage line portion and the gate line may be provided in a different conductive layer; the second control voltage line portion and the data line may be provided in a different conductive layer.

[0195] In a specific implementation, the first control voltage line portion and the light emitting control line may be provided in a different conductive layer; the first control voltage line portion and the reset control line may be provided in a different conductive layer;

[0196] The second control voltage line portion may be provided on the same layer as the light emitting control line, and the second control voltage line portion may be provided on the same layer as the reset control line.

[0197] In at least one embodiment of the present disclosure, the driving backplane may include a first routing layer and a second routing layer, wherein the gate line, the second power supply voltage line portion, the second reset voltage line portion, the second control voltage line portion, and the driving control line may all be arranged in the first routing layer, and the first power supply voltage line portion, the first reset voltage line portion, the first control voltage line portion, and the data line may all be arranged in the second routing layer;

[0198] The first routing layer and the second routing layer are conductive layers.

[0199] Optionally, the first wiring layer may be a gate metal layer, and the second wiring layer may be a source / drain metal layer, but is not limited thereto.

[0200] In at least one embodiment of the present disclosure, an orthographic projection of the data line on the base substrate is disposed between orthographic projections of two first voltage line portions on the base substrate.

[0201] In a specific implementation, the orthographic projection of the data line on the base substrate can be arranged between the orthographic projections of the two first voltage line portions on the base substrate, so that the data line is arranged between the two first voltage line portions, which is convenient for increasing the line width of the first voltage line portion extending in the vertical direction in the horizontal direction, thereby helping to reduce the resistance of the voltage line.

[0202] In at least one embodiment of the present disclosure, the orthographic projection of the data line on the base substrate is disposed between the orthographic projection of the first control voltage line portion on the base substrate and the orthographic projection of at least one first voltage line portion on the base substrate.

[0203] In a specific implementation, the orthographic projection of the data line on the base substrate can be set between the orthographic projection of the first control voltage line portion on the base substrate and the orthographic projection of at least one first voltage line portion on the base substrate, so as to set the data line between the first voltage line portion and the first control voltage line portion, thereby facilitating the increase of the line width of the first voltage line portion extending in the vertical direction in the horizontal direction and the line width of the first control voltage line portion extending in the vertical direction in the horizontal direction, thereby helping to reduce the resistance of the voltage line and the resistance of the control voltage line.

[0204] In at least one embodiment of the present disclosure, the orthographic projection of the first voltage line portion on the base substrate does not overlap with the orthographic projection of the data line on the base substrate;

[0205] An orthographic projection of the first control voltage line portion on the base substrate does not overlap with an orthographic projection of the data line on the base substrate.

[0206] In a specific implementation, by arranging the data line in the middle and the first voltage line portion and the first control voltage line portion on either side of the data line, the orthographic projection of the first voltage line portion on the substrate is controlled to not overlap with the orthographic projection of the data line on the substrate, and the orthographic projection of the first control voltage line portion on the substrate is controlled to not overlap with the orthographic projection of the data line on the substrate, thereby reducing the coupling capacitance between the data line and the voltage line, and reducing the coupling capacitance between the data line and the control voltage line. The coupling capacitance includes stacked capacitance and lateral capacitance.

[0207] The driving backplane according to at least one embodiment of the present disclosure further includes a gate driving unit provided on the base substrate;

[0208] The gate driving unit is used to generate a multi-level gate driving signal.

[0209] In a specific implementation, the driving backplane may include a gate driving IC bound to the left side of the base substrate and / or the right side of the base substrate, and the gate driving signal is provided by the gate driving IC.

[0210] In actual operation, the gate driver IC may also be used to provide a light emitting control signal and a reset control signal.

[0211] In at least one embodiment of the present disclosure, the gate driving unit may be at least one of a gate driving chip and a gate driving circuit structure directly fabricated on a substrate through a semiconductor process.

[0212] The driving backplane according to at least one embodiment of the present disclosure further includes a gate driving module, wherein the gate driving module includes a plurality of gate driving circuits connected in cascade to each other; the gate driving circuit is configured to generate and output corresponding level gate driving signals through its output terminal;

[0213] The output end of the gate driving circuit is electrically connected to the input end of the adjacent next-stage gate driving circuit to provide an input signal to the adjacent next-stage gate driving circuit.

[0214] The driving backplane described in at least one embodiment of the present disclosure may also include a light-emitting control signal generating module and a reset control signal generating module. The light-emitting control signal generating module may include a multi-level light-emitting control signal generating circuit, and the reset control signal generating module may include a multi-level reset control signal generating circuit. The light-emitting control signal generating circuit is used to generate a light-emitting control signal, and the reset control signal generating circuit is used to generate a reset control signal.

[0215] As shown in FIG1 , the driving backplane according to at least one embodiment of the present disclosure includes a first conductive pad Y1, a second conductive pad Y2, a third conductive pad Y3, a fourth conductive pad Y4, a fifth conductive pad Y5, a sixth conductive pad Y6, a seventh conductive pad Y7, an eighth conductive pad Y8, and a ninth conductive pad Y9;

[0216] The first conducting pad Y1, the second conducting pad Y2, the third conducting pad Y3, the fourth conducting pad Y4, the fifth conducting pad Y5, the sixth conducting pad Y6, the seventh conducting pad Y7, the eighth conducting pad Y8 and the ninth conducting pad Y9 are disposed in the same connection area A0;

[0217] The first conductive pad Y1 is used to provide a reset control signal, the second conductive pad Y2 is used to provide a gate driving signal, the third conductive pad Y3 is used to provide a light emitting control signal, the fourth conductive pad Y4 is used to provide a control voltage, the fifth conductive pad Y5 is used to provide a green data voltage, the sixth conductive pad Y6 is used to provide a power supply voltage signal, the seventh conductive pad Y7 is used to provide a red data voltage, the eighth conductive pad Y8 is used to provide a blue data voltage, and the ninth conductive pad Y9 is used to provide a reset voltage signal;

[0218] Wherein, the first conductive pad Y1 may be the first conductive pad of the fifth category, the second conductive pad Y2 may be the conductive pad of the second category, the third conductive pad Y3 may be the second conductive pad of the fifth category, the fourth conductive pad Y4 may be the conductive pad of the fourth category, the fifth conductive pad Y5 may be the first conductive pad of the first category, the sixth conductive pad Y6 may be the first conductive pad of the third category, the seventh conductive pad Y7 may be the second conductive pad of the first category, the eighth conductive pad Y8 may be the third conductive pad of the first category, and the ninth conductive pad Y9 may be the second conductive pad of the third category;

[0219] The driving backplane according to at least one embodiment of the present disclosure includes a red data line DTR, a green data line DTG, a blue data line DTB, a first power supply voltage line portion LVDD1, a second power supply voltage line portion LVDD2, a first reset voltage line portion LVSS1, a second reset voltage line portion LVSS2, a first control voltage line portion HF1, a second control voltage line portion HF2, a gate line GT, a light emitting control line EM, and a reset control line RST;

[0220] The first power voltage line portion LVDD1, the first reset voltage line portion LVSS1, the first control voltage line portion HF1, the red data line DTR, the green data line DTG, and the blue data line DTB extend in a vertical direction;

[0221] The second power supply voltage line portion LVDD2, the second reset voltage line portion LVSS2, the second control voltage line portion HF2, the gate line GT, the emission control line EM and the reset control line RST extend in the horizontal direction;

[0222] The first power supply voltage line portion LVDD1, the first control voltage line portion HF1, the red data line DTR, the green data line DTG, the blue data line DTB and the first reset voltage line portion LVSS1 are arranged in sequence from left to right along the horizontal direction;

[0223] The reset control line RST, the gate line GT, the second power voltage line portion LVDD2, the emission control line EM, the second control voltage line portion HF2, and the second reset voltage line portion LVSS2 are sequentially arranged from top to bottom along the vertical direction.

[0224] In at least one embodiment shown in FIG. 1 , the first power supply voltage line portion LVDD1 and the second power supply voltage line portion LVDD2 are disposed on different conductive layers, and the first power supply voltage line portion LVDD1 and the second power supply voltage line portion LVDD2 are electrically connected to each other;

[0225] The first reset voltage line portion LVSS1 and the second reset voltage line portion LVSS2 are provided in different conductive layers, and the first reset voltage line portion LVSS1 and the second reset voltage line portion LVSS2 are electrically connected to each other;

[0226] The first control voltage line portion HF1 and the second control voltage line portion HF2 are provided in different conductive layers, and the first control voltage line portion HF1 and the second control voltage line portion HF2 are electrically connected to each other.

[0227] As shown in FIG1 , the red data line DTR, the green data line DTG, and the blue data line DTB are provided between the first control voltage line portion HF1 and the first reset voltage line portion LVSS1;

[0228] The first power supply voltage line portion LVDD1 is arranged at the leftmost side, and the first reset voltage line portion LVSS1 is arranged at the rightmost side, which is conducive to increasing the line width of the first power supply voltage line portion LVDD1 in the horizontal direction and increasing the line width of the first reset voltage line portion LVSS1 in the horizontal direction, thereby facilitating reducing the resistance of LVDD1 and LVSS1, and facilitating reducing the load of the power supply voltage line and reducing the load of the reset voltage line;

[0229] The orthographic projection of DTR on the substrate substrate does not overlap with the orthographic projection of LVDD1 on the substrate substrate; the orthographic projection of DTG on the substrate substrate does not overlap with the orthographic projection of LVDD1 on the substrate substrate; the orthographic projection of DTB on the substrate substrate does not overlap with the orthographic projection of LVDD1 on the substrate substrate;

[0230] The orthographic projection of DTR on the substrate does not overlap with the orthographic projection of LVSS1 on the substrate; the orthographic projection of DTG on the substrate does not overlap with the orthographic projection of LVSS1 on the substrate; the orthographic projection of DTB on the substrate does not overlap with the orthographic projection of LVSS1 on the substrate;

[0231] The orthographic projection of DTR on the substrate does not overlap with the orthographic projection of HF1 on the substrate; the orthographic projection of DTG on the substrate does not overlap with the orthographic projection of HF1 on the substrate; the orthographic projection of DTB on the substrate does not overlap with the orthographic projection of HF1 on the substrate;

[0232] With the above configuration, the coupling capacitance between each data line and the first power supply voltage line portion LVDD1, the coupling capacitance between each data line and the first reset voltage line portion LVSS1, and the coupling capacitance between each data line and the first control voltage line portion HF1 can be reduced.

[0233] In at least one embodiment shown in FIG. 1 , when HF1 and LVDD1 are disposed in different conductive layers, the line width of HF1 along the horizontal direction can be increased, the resistance of HF1 can be reduced, and the load of the control voltage line can be reduced.

[0234] As shown in FIG. 2A to FIG. 2D , the driving backplane according to at least one embodiment of the present disclosure includes a base substrate, wherein the base substrate includes a plurality of rows and columns of connection regions;

[0235] In FIG2A , the connection region labeled A11 is the first row and first column, the connection region labeled A12 is the first row and second column, the connection region labeled A13 is the first row and third column, the connection region labeled A1m-1 is the first row and m-1 column, and the connection region labeled A1m-1 is the first row and m column;

[0236] The connection area labeled An-11 is the n-1th row and first column, the connection area labeled An-12 is the n-1th row and second column, the connection area labeled An-13 is the nth row and third column, the connection area labeled An-1m-1 is the n-1th row and m-1th column, and the connection area labeled An-1m-1 is the n-1th row and m-1th column.

[0237] The connection area labeled An1 is the nth row and first column, the connection area labeled An2 is the nth row and second column, the connection area labeled An3 is the nth row and third column, the connection area labeled Anm-1 is the nth row and m-1 column, and the connection area labeled Anm-1 is the nth row and m column;

[0238] n and m are positive integers;

[0239] As shown in FIG. 2A to FIG. 2D , the driving backplane according to at least one embodiment of the present disclosure further includes a driving module 20 , a gate driving module, a light emitting control signal generating module, and a reset control signal generating module;

[0240] The gate driving module includes a multi-stage gate driving circuit, the light emitting control signal generating module includes a multi-stage light emitting control signal generating circuit, and the reset control signal generating module includes a multi-stage reset control signal generating circuit;

[0241] In FIG. 2A to FIG. 2D , the first-stage gate driving circuit is labeled GA1, the n-1-th-stage gate driving circuit is labeled GAn-1, and the n-th-stage gate driving circuit is labeled GAn;

[0242] The circuit labeled EA1 is the first-stage light emitting control signal generating circuit, the circuit labeled EAn-1 is the n-1th-stage light emitting control signal generating circuit, and the circuit labeled EAn is the nth-stage light emitting control signal generating circuit;

[0243] The circuit labeled RA1 is the first-stage reset control signal generating circuit, the circuit labeled RAn-1 is the n-1th-stage reset control signal generating circuit, and the circuit labeled RAn is the nth-stage reset control signal generating circuit;

[0244] In FIG2B and FIG2D , the power supply voltage lead is labeled LVDY, and the reset voltage lead is labeled LVSY. LVDY and LVSY are provided on the upper side of each connection region.

[0245] In FIG2B , LVDD11 is the first power supply voltage line portion in the first column, HF11 is the first control voltage line portion in the first column, DTR1 is the first red data line portion in the first column, DTG1 is the first green data line portion in the first column, DTB1 is the first blue data line portion in the first column, and LVSS11 is the first reset voltage line portion in the first column.

[0246] The first power supply voltage line portion in the second column is labeled LVDD21, the first control voltage line portion in the second column is labeled HF21, the red data line in the second column is labeled DTR2, the green data line in the second column is labeled DTG2, the blue data line in the second column is labeled DTB2, and the first reset voltage line portion in the second column is labeled LVSS21;

[0247] The third column is labeled LVDD31 for the first power supply voltage line portion, the third column is labeled HF31 for the first control voltage line portion, the third column is labeled DTR3 for the red data line, the third column is labeled DTG3 for the green data line, the third column is labeled DTB3 for the blue data line, and the third column is labeled LVSS31 for the first reset voltage line portion;

[0248] LVDDm-11 is the first power supply voltage line portion of the m-1th column, HFm-11 is the first control voltage line portion of the m-1th column, DTRm-1 is the red data line of the m-1th column, DTGm-1 is the green data line of the m-1th column, DTBm-1 is the blue data line of the m-1th column, and LVSSm-11 is the first reset voltage line portion of the m-1th column.

[0249] The first power supply voltage line portion labeled LVDDm1 is the m-th column, the first control voltage line portion labeled HFm1 is the m-th column, the red data line labeled DTRm is the m-th column, the green data line labeled DTGm is the m-th column, the blue data line labeled DTBm is the m-th column, and the first reset voltage line portion labeled LVSSm1 is the m-th column.

[0250] As shown in FIG2C , RST1 is the first row reset control line, GT1 is the first row gate line, LVDD12 is the first row second power supply voltage line portion, EM1 is the first row light emitting control line, HF12 is the first row second control voltage line portion, and LVSS12 is the first row second reset voltage line portion.

[0251] The line labeled RSTn-1 is the reset control line in the n-1th row, the line labeled GTn-1 is the gate line in the n-1th row, the line labeled LVDDn-12 is the second power supply voltage line portion in the n-1th row, the line labeled EMn-1 is the light emitting control line in the n-1th row, the line labeled HFn-12 is the second control voltage line portion in the n-1th row, and the line labeled LVSSn-12 is the second reset voltage line portion in the n-1th row.

[0252] The n-th row is labeled RSTn for the reset control line, the n-th row is labeled GTn for the gate line, the n-th row is labeled LVDDn2 for the second power supply voltage line portion, the n-th row is labeled EMn for the emission control line, the n-th row is labeled HFn2 for the second control voltage line portion, and the n-th row is labeled LVSSn2 for the second reset voltage line portion.

[0253] As shown in FIG2D , VDDT1 is the first power supply voltage output terminal of the driving module 20, VDDT2 is the second power supply voltage output terminal of the driving module 20, VSST1 is the first reset voltage output terminal of the driving module 20, and VSST2 is the second reset voltage output terminal of the driving module 20; HFT1 is the first control voltage output terminal of the driving module 20, and HFT2 is the second control voltage output terminal of the driving module 20;

[0254] VDDT1 is electrically connected to LVDDY through HF11, and VDDT2 is electrically connected to LVDDn2;

[0255] VSST1 is electrically connected to LVSSn2, and VSST2 is electrically connected to LVSSY through LVSSm1;

[0256] HFT2 is electrically connected to HF11, and HFT1 is electrically connected to HFn2;

[0257] HFT1 is electrically connected to the left end of HFn2, and HFT2 is electrically connected to the right end of HFn2.

[0258] In at least one embodiment shown in Figures 2A-2D, the left side, right side, upper side, and lower side of the drive backplane are all relative. When the drive backplane is rotated 90 degrees to the left, 90 degrees to the right, or 180 degrees, the sides of the drive backplane change accordingly.

[0259] As shown in FIG. 2A-2D , each first power supply voltage line portion is electrically connected to the corresponding second power supply voltage line portion, each first reset voltage line portion is electrically connected to the corresponding second reset voltage line portion, and each first control voltage line portion is electrically connected to the corresponding second control voltage line portion.

[0260] In at least one embodiment shown in FIG. 2A to FIG. 2D , LVDDY and LVSSY extend in a horizontal direction, LVDDY and LVSSY are disposed on the upper side of each connection region, and the driving module 20 is disposed on the upper side of each connection region;

[0261] Each vertical first power supply voltage line portion is electrically connected to LVDDY, so as to reduce the number of terminals for outputting power supply voltage signals used by the driving module 20;

[0262] Each vertical first reset voltage line portion is electrically connected to LVSSY, so as to reduce the number of terminals for outputting reset voltage signals used by the driving module 20;

[0263] In at least one embodiment shown in FIG. 2D , the upper end of Y0 is electrically connected to the right end of HFn2 , and Y0 does not extend upward from the right end of HFn2 .

[0264] In at least one embodiment shown in FIG2D , HFT1 is electrically connected to the left end of HFn2, and HFT2 is electrically connected to the right end of HFn2. HFT1 and HFT2 simultaneously provide a control voltage to HFn2 to improve the uniformity of the control voltage on HFn2. HFT2 is electrically connected to HFn2, and HFn2 is the second control voltage line portion closest to the driving module 20, so as to reduce the length of the lead Y0 between HFT2 and the right end of HFn2 and reduce the resistance of the lead Y0.

[0265] In at least one embodiment shown in FIG. 2D , VDDT2 is electrically connected to the right end of LVDDn2, and VDDT1 is connected to the left end of LVDDn2. VDDT1 and VDDT2 simultaneously provide a control voltage to LVDDn2 to improve the uniformity of the control voltage on LVDDn2. LVDDn2 is the second power supply voltage line portion closest to the driver module 20, so as to reduce the length of the lead YX0 between VDDT2 and the right end of LVDDn2 and reduce the resistance of the lead YX0.

[0266] 2D , the length of the lead wire YX0 between the right end portions of VDDT2 and LVDDn2 is smaller than the distance between the n-th row gate line GTn and the driving module 20, so that the lead wire YX0 between the right end portions of VDDT2 and LVDDn2 avoids the n-th row gate line GTn, and does not affect the wiring of GTn, as well as the connection between GTn and GAn.

[0267] Referring to Figure 2D, the length of the lead Y0 between HFT2 and the right end portion of the second control voltage line portion HFn2 of the nth row is less than the distance between the gate line GTn of the nth row and the driving module 20, so that the lead Y0 between HFT2 and the right end portion of the second control voltage line portion HFn2 of the nth row avoids the gate line GTn of the nth row, and does not affect the wiring of GTn, as well as the connection between GTn and GAn.

[0268] As configured above, the arrangement of GA1-GAn whose edges are arranged at the edge of the driving backplane and the leads electrically connected thereto is conducive to forming a visually narrow frame when the gate driving circuits of each level and the connection area are located on the same side of the substrate.

[0269] Specifically, the cascade line JL0 between GAn-1 and GAn, the lead YX0 between VDDT2 and the right end of LVDDn2, and the lead Y0 between HFT2 and the right end of the second control voltage line portion HFn2 of the nth row are located on the same conductor layer. This design can achieve the effect of allowing the lead YX0 between VDDT2 and the right end of LVDDn2, and the lead Y0 between HFT2 and the right end of the second control voltage line portion HFn2 of the nth row to avoid the cascade line JL0 between GAn-1 and GAn.

[0270] Specifically, in the extension direction of lead YX0 and lead Y0, the distance between the lead closest to GAn among lead YX0 and lead Y0 and GAn can be less than or equal to the distance between the connection node between the cascade line JL0 between GAn and GAn-1 and the nth row gate line GTn and GAn.

[0271] In at least one embodiment of the present invention, the cascade line JL0 between GAn and GAn-1 is a connection line between the output terminal of GAn and the input terminal of GAn-1, and is used to provide an input signal to the input terminal of GAn-1.

[0272] As shown in FIG2B , each data line, each first power voltage line portion, each first reset voltage line portion, and each first control voltage line portion extend in a vertical direction;

[0273] DTR1, DTG1 and DTB1 are arranged between LVDD11 and LVSS11 to increase the line width of LVDD11 and the line width of LVSS11, thereby reducing the resistance of LVDD11 and the resistance of LVSS11;

[0274] DTR2, DTG2, and DTB2 are provided between LVDD21 and LVSS21 to increase the line width of LVDD21 and the line width of LVSS21, thereby reducing the resistance of LVDD21 and the resistance of LVSS21;

[0275] DTR3, DTG3, and DTB3 are provided between LVDD31 and LVSS31 to increase the line width of LVDD31 and the line width of LVSS31, thereby reducing the resistance of LVDD31 and the resistance of LVSS31;

[0276] DTRm-1, DTGm-1, and DTBm-1 are disposed between LVDDm-11 and LVSSm-11 to increase the line width of LVDDm-11 and the line width of LVSSm-11, thereby reducing the resistance of LVDDm-11 and the resistance of LVSSm-11.

[0277] DTRm, DTGm, and DTBm are disposed between LVDDm1 and LVSSm1 to increase the line width of LVDDm1 and the line width of LVSSm1, thereby reducing the resistance of LVDDm1 and the resistance of LVSSm1.

[0278] The orthographic projection of DTR1 on the substrate substrate does not overlap with the orthographic projection of LVDD11 on the substrate substrate, the orthographic projection of DTR1 on the substrate substrate does not overlap with the orthographic projection of LVSS11 on the substrate substrate, and the orthographic projection of DTR1 on the substrate substrate does not overlap with the orthographic projection of HF11 on the substrate substrate, so as to reduce the coupling capacitance between DTR1 and LVDD11, reduce the coupling capacitance between DTR1 and LVSS11, and reduce the coupling capacitance between DTR1 and HF11;

[0279] The orthographic projection of DTG1 on the substrate substrate does not overlap with the orthographic projection of LVDD11 on the substrate substrate, the orthographic projection of DTG1 on the substrate substrate does not overlap with the orthographic projection of LVSS11 on the substrate substrate, and the orthographic projection of DTG1 on the substrate substrate does not overlap with the orthographic projection of HF11 on the substrate substrate, so as to reduce the coupling capacitance between DTG1 and LVDD11, reduce the coupling capacitance between DTG1 and LVSS11, and reduce the coupling capacitance between DTG1 and HF11;

[0280] The orthographic projection of DTB1 on the substrate does not overlap with the orthographic projection of LVDD11 on the substrate, the orthographic projection of DTB1 on the substrate does not overlap with the orthographic projection of LVSS11 on the substrate, and the orthographic projection of DTB1 on the substrate does not overlap with the orthographic projection of HF11 on the substrate, so as to reduce the coupling capacitance between DTB1 and LVDD11, reduce the coupling capacitance between DTB1 and LVSS11, and reduce the coupling capacitance between DTB1 and HF11;

[0281] The orthographic projection of DTR2 on the substrate substrate does not overlap with the orthographic projection of LVDD21 on the substrate substrate, the orthographic projection of DTR2 on the substrate substrate does not overlap with the orthographic projection of LVSS21 on the substrate substrate, and the orthographic projection of DTR2 on the substrate substrate does not overlap with the orthographic projection of HF21 on the substrate substrate, so as to reduce the coupling capacitance between DTR2 and LVDD21, reduce the coupling capacitance between DTR2 and LVSS21, and reduce the coupling capacitance between DTR2 and HF21;

[0282] The orthographic projection of DTG2 on the substrate substrate does not overlap with the orthographic projection of LVDD21 on the substrate substrate, the orthographic projection of DTG2 on the substrate substrate does not overlap with the orthographic projection of LVSS21 on the substrate substrate, and the orthographic projection of DTG2 on the substrate substrate does not overlap with the orthographic projection of HF21 on the substrate substrate, so as to reduce the coupling capacitance between DTG2 and LVDD21, reduce the coupling capacitance between DTG2 and LVSS21, and reduce the coupling capacitance between DTG2 and HF21;

[0283] The orthographic projection of DTB2 on the substrate does not overlap with the orthographic projection of LVDD21 on the substrate, the orthographic projection of DTB2 on the substrate does not overlap with the orthographic projection of LVSS21 on the substrate, and the orthographic projection of DTB2 on the substrate does not overlap with the orthographic projection of HF21 on the substrate, so as to reduce the coupling capacitance between DTB2 and LVDD21, reduce the coupling capacitance between DTB2 and LVSS21, and reduce the coupling capacitance between DTB2 and HF21;

[0284] The orthographic projection of DTR3 on the substrate substrate does not overlap with the orthographic projection of LVDD31 on the substrate substrate, the orthographic projection of DTR3 on the substrate substrate does not overlap with the orthographic projection of LVSS31 on the substrate substrate, and the orthographic projection of DTR3 on the substrate substrate does not overlap with the orthographic projection of HF31 on the substrate substrate, so as to reduce the coupling capacitance between DTR3 and LVDD31, reduce the coupling capacitance between DTR3 and LVSS31, and reduce the coupling capacitance between DTR3 and HF31;

[0285] The orthographic projection of DTG3 on the substrate substrate does not overlap with the orthographic projection of LVDD31 on the substrate substrate, the orthographic projection of DTG3 on the substrate substrate does not overlap with the orthographic projection of LVSS31 on the substrate substrate, and the orthographic projection of DTG3 on the substrate substrate does not overlap with the orthographic projection of HF31 on the substrate substrate, so as to reduce the coupling capacitance between DTG3 and LVDD31, reduce the coupling capacitance between DTG3 and LVSS31, and reduce the coupling capacitance between DTG3 and HF31;

[0286] The orthographic projection of DTB3 on the substrate substrate does not overlap with the orthographic projection of LVDD31 on the substrate substrate, the orthographic projection of DTB3 on the substrate substrate does not overlap with the orthographic projection of LVSS31 on the substrate substrate, and the orthographic projection of DTB3 on the substrate substrate does not overlap with the orthographic projection of HF31 on the substrate substrate, so as to reduce the coupling capacitance between DTB3 and LVDD31, reduce the coupling capacitance between DTB3 and LVSS31, and reduce the coupling capacitance between DTB3 and HF31;

[0287] The orthographic projection of DTRm-1 on the substrate substrate does not overlap with the orthographic projection of LVDDm-11 on the substrate substrate, the orthographic projection of DTRm-1 on the substrate substrate does not overlap with the orthographic projection of LVSSm-11 on the substrate substrate, and the orthographic projection of DTR m-1 on the substrate substrate does not overlap with the orthographic projection of HFm-11 on the substrate substrate, so as to reduce the coupling capacitance between DTRm-1 and LVDDm-11, reduce the coupling capacitance between DTR m-1 and LVSS m-11, and reduce the coupling capacitance between DTRm-1 and HFm-11;

[0288] The orthographic projection of DTGm-1 on the substrate substrate does not overlap with the orthographic projection of LVDDm-11 on the substrate substrate, the orthographic projection of DTGm-1 on the substrate substrate does not overlap with the orthographic projection of LVSSm-11 on the substrate substrate, and the orthographic projection of DTGm-1 on the substrate substrate does not overlap with the orthographic projection of HFm-11 on the substrate substrate, so as to reduce the coupling capacitance between DTGm-1 and LVDDm-11, reduce the coupling capacitance between DTGm-1 and LVSS m-11, and reduce the coupling capacitance between DTGm-1 and HFm-11;

[0289] The orthographic projection of DTBm-1 on the base substrate does not overlap with the orthographic projection of LVDDm-11 on the base substrate, the orthographic projection of DTBm-1 on the base substrate does not overlap with the orthographic projection of LVSSm-11 on the base substrate, and the orthographic projection of DTBm-1 on the base substrate does not overlap with the orthographic projection of HFm-11 on the base substrate, so as to reduce the coupling capacitance between DTBm-1 and LVDDm-11, reduce the coupling capacitance between DTB m-1 and LVSS m-11, and reduce the coupling capacitance between DTBm-1 and HFm-11;

[0290] The orthographic projection of DTRm on the substrate does not overlap with the orthographic projection of LVDDm1 on the substrate, the orthographic projection of DTRm on the substrate does not overlap with the orthographic projection of LVSSm1 on the substrate, and the orthographic projection of DTRm on the substrate does not overlap with the orthographic projection of HFm1 on the substrate, so as to reduce the coupling capacitance between DTRm and LVDDm1, reduce the coupling capacitance between DTRm and LVSSm1, and reduce the coupling capacitance between DTRm and HFm1;

[0291] The orthographic projection of DTGm on the substrate substrate does not overlap with the orthographic projection of LVDDm1 on the substrate substrate, the orthographic projection of DTGm on the substrate substrate does not overlap with the orthographic projection of LVSSm1 on the substrate substrate, and the orthographic projection of DTGm on the substrate substrate does not overlap with the orthographic projection of HFm1 on the substrate substrate, so as to reduce the coupling capacitance between DTGm and LVDDm1, reduce the coupling capacitance between DTGm and LVSSm1, and reduce the coupling capacitance between DTGm and HFm1;

[0292] The orthographic projection of DTBm on the substrate does not overlap with the orthographic projection of LVDDm1 on the substrate, the orthographic projection of DTBm on the substrate does not overlap with the orthographic projection of LVSSm1 on the substrate, and the orthographic projection of DTBm on the substrate does not overlap with the orthographic projection of HFm1 on the substrate, so as to reduce the coupling capacitance between DTBm and LVDDm1, reduce the coupling capacitance between DTBm and LVSSm1, and reduce the coupling capacitance between DTBm and HFm1.

[0293] In at least one embodiment shown in Figures 2A-2D, the power supply voltage line adopts grid wiring, the reset voltage line adopts grid wiring, and the control voltage line adopts grid wiring, which is beneficial to reducing the load of the power supply voltage line, reducing the load of the reset voltage line, and reducing the load of the control voltage line.

[0294] As shown in FIG2A to FIG2D , VGH is a high-level signal, VGL is a low-level signal, RCK is a first clock signal, RCB is a second clock signal, ECK is a third clock signal, ECB is a fourth clock signal, RSTV is a first starting voltage, ESTV is a second starting voltage, GCK is a fifth clock signal, GCB is a sixth clock signal, and GSTV is a third starting voltage;

[0295] The driving module 20 is used to provide a high level signal VGH, a low level signal VGL, a first clock signal RCK, a second clock signal RCB, a third clock signal ECK, a fourth clock signal ECB, a fifth clock signal GCK, a sixth clock signal GCB, a first starting voltage RSTV, a second starting voltage ESTV and a third starting voltage GSTV.

[0296] In at least one embodiment shown in Figures 2A-2D, gate drive signals at various levels, light-emitting control signals at various levels, and reset control signals at various levels are generated respectively by a gate drive module, a light-emitting control signal generation module, and a reset control signal generation module. The gate drive module includes gate drive circuits at various levels, the light-emitting control signal generation module includes multi-level light-emitting control signal generation circuits, and the reset control signal generation module includes multi-level reset control signal generation circuits.

[0297] In at least one embodiment shown in FIG. 2A to FIG. 2D , the output terminal of RAn is electrically connected to the input terminal of RAn- 1 to provide an input signal to Ran- 1 ;

[0298] The output terminal of EAn is electrically connected to the input terminal of EAn-1, and is used to provide an input signal to EAn-1;

[0299] The output terminal of GAn is electrically connected to the input terminal of GAn- 1 and is used to provide an input signal to GAn- 1 .

[0300] In at least one embodiment shown in Figures 2A-2D, EAn is connected to ESTV, RAn is connected to RSTV, and GAn is connected to GSTV; in the gate drive module, scanning is performed from GAn to GA1; in the light-emitting control signal generation module, scanning is performed from EAn to EA1; in the reset control signal generation module, scanning is performed from RAn to RA1.

[0301] In a specific implementation, the display substrate may include LED chips arranged in each connection area, the pixel pitch is greater than or equal to 0.9 mm and less than or equal to 4 mm, and the size of the LED chip is generally greater than or equal to 200 μm and less than or equal to 1 mm. The distance between adjacent LED chips is relatively large, so the line width of the first power supply voltage line portion and the line width of the first reset voltage line portion close to the edge can be set to be larger to reduce the resistance of the power supply voltage line and the resistance of the reset voltage line, and reduce the voltage drop on the power supply voltage line and the voltage drop on the reset voltage line.

[0302] In a specific implementation, the first control voltage line portion may also be arranged at the leftmost or rightmost portion of the connection area to increase the line width of the first control voltage line portion, reduce the resistance of the control voltage line, and reduce the voltage drop on the control voltage line.

[0303] On the substrate, the size of the LED chip is much smaller than the pixel pitch, and the remaining space after the LED is mounted on the backplane can be used to widen the width of the signal line.

[0304] The difference between at least one embodiment shown in FIG3 and at least one embodiment shown in FIG2A is that: the gate driving module, the light emitting control signal generating module and the reset control signal generating module are not included, but the gate driving signal of each level, the light emitting control signal of each level and the reset control signal of each level are provided by the gate driving unit 30;

[0305] The gate driving unit 30 is disposed on the right side of each connection area.

[0306] In a specific implementation, when the driving backplane includes a gate driving module, a light emitting control signal generating module and a reset control signal generating module, a buffer layer, a semiconductor layer, a gate insulating layer, a gate metal layer, an interlayer dielectric layer, a source-drain metal layer, a flat layer and a PAD (metal electrode) layer can be sequentially arranged on the base substrate; each voltage line can be made through the gate metal layer and the source-drain metal layer; the transistors and capacitors in the gate driving module, the transistors and capacitors in the light emitting control signal generating module, and the transistors and capacitors in the reset control signal generating module can be made through the semiconductor layer, the gate metal layer and the source-drain metal layer, and each conductive pad can be made on the PAD layer.

[0307] In a specific implementation, when the driving backplane includes a gate driving integrated circuit, a gate metal layer, an interlayer dielectric layer, a source-drain metal layer, a planar layer and a PAD layer can be sequentially arranged on the base substrate, and only five mask processes are required; each voltage line can be made through the gate metal layer and the source-drain metal layer, and each conductive pad can be made on the PAD layer.

[0308] Optionally, the PAD layer may be made of Cu to meet the metal requirements when LED components are formed, but the present invention is not limited thereto.

[0309] The display substrate described in the embodiment of the present disclosure includes the above-mentioned driving backplane.

[0310] The display substrate according to at least one embodiment of the present disclosure includes a plurality of light-emitting components disposed on the backplane and electrically connected to the conductive pads; the light-emitting components include a substrate, and at least one pixel circuit disposed on the substrate, the pixel circuit including a light-emitting unit and a pixel driving circuit for driving the light-emitting unit; the at least one pixel circuit includes a first pixel circuit;

[0311] The first pixel circuit receives a data voltage through a first first-type conductive pad;

[0312] In the second direction, the first first-type conducting pad is disposed between the second-type conducting pad and at least one third-type conducting pad.

[0313] In a specific implementation, the first type of conductive pad can be a conductive pad for transmitting data voltage, and the orthographic projection of the first first type of conductive pad on the substrate can be set at the center of the light-emitting component to be staggered with the voltage line and the control voltage line, thereby reducing the coupling capacitance between the first data line (the first data line is a data line electrically connected to the first first type of conductive pad) and the voltage line, and reducing the coupling capacitance between the first data line and the control voltage line.

[0314] In at least one embodiment of the present disclosure, the first direction is a direction in which the data line extends, and the second direction is a direction intersecting with the first direction.

[0315] Optionally, the light-emitting component may be a light-emitting chip, and the light-emitting chip may be an LED (light-emitting diode) chip.

[0316] In at least one embodiment of the present disclosure, the light emitting component may have pins, and the pins may be electrically connected to the conductive pads by welding; or,

[0317] The light emitting component may have at least one of a pin and a contact, and the pin or the contact may be electrically connected to the conductive pad via an anisotropic conductive film (ACF).

[0318] In at least one embodiment of the present disclosure, the at least one pixel circuit further includes a second pixel circuit; the second pixel circuit receives a data voltage through a second first-type conductive pad;

[0319] In the second direction, the second first-type conducting pad is disposed between the second-type conducting pad and at least one third-type conducting pad.

[0320] In a specific implementation, the light-emitting component may further include a second pixel circuit. In the second direction, a second first-class conductive pad for providing data voltage to the second pixel circuit may be arranged between the second-class conductive pad and at least one third-class conductive pad, so that the second first-class conductive pad is arranged at the center position in the second direction of the light-emitting component, reducing the coupling capacitance between the second data line (the second data line is a data line electrically connected to the second first-class conductive pad) and the voltage line, and reducing the coupling capacitance between the second data line and the control voltage line.

[0321] In at least one embodiment of the present disclosure, the at least one pixel circuit further includes a third pixel circuit; the second pixel circuit receives a data voltage through a third first-type conductive pad;

[0322] The third first-type conducting pad and at least one third-type conducting pad are arranged along the first direction, or the third first-type conducting pad and the second-type conducting pad are arranged along the first direction.

[0323] In a specific implementation, the light-emitting component may include a first pixel circuit, a second pixel circuit and a third pixel circuit. The first type of conductive pad electrically connected to the first pixel circuit and the second pixel circuit may be arranged at the middle position of the light-emitting component along the second direction, and the first type of conductive pad electrically connected to the third pixel circuit among the three pixel circuits may be arranged at the edge position of the light-emitting component along the second direction, so as to facilitate the arrangement of data lines, so that the data lines can be conveniently electrically connected to the corresponding first type of conductive pads.

[0324] In at least one embodiment of the present disclosure, along the second direction, a first third-type conducting pad and a second third-type conducting pad are disposed on opposite sides of the first first-type conducting pad.

[0325] In a specific implementation, the multiple conductive pads may also include a first third-category conductive pad for transmitting a power supply voltage signal, and a second third-category conductive pad for transmitting a reset voltage signal. Along the second direction, the first third-category conductive pad and the second third-category conductive pad are arranged on opposite sides of the first first-category conductive pad. The first third-category conductive pad and the second third-category conductive pad can be arranged at the edge of the substrate, so that the first power supply voltage line portion and the first reset voltage line portion extending in the vertical direction can be set at a position outside the cutting edge of the light-emitting component, so that the first power supply voltage line portion and the first reset voltage line portion can be set using the larger space between adjacent light-emitting components, which is conducive to increasing the line width of the first power supply voltage line portion and the line width of the first reset voltage line portion, reducing the resistance of the power supply voltage line and the resistance of the reset voltage line, and reducing the voltage drop on the power supply voltage line and the voltage drop on the reset voltage line.

[0326] Furthermore, by positioning the third type of conductive pads for transmitting voltage signals near the edges of the light-emitting components and positioning the first type of conductive pads for transmitting data voltages near the center of the light-emitting components, the voltage lines and data lines do not overlap, thereby reducing the coupling capacitance between the data lines and the voltage lines. In a specific implementation, the plurality of conductive pads may further include a fourth type of conductive pad for transmitting control voltages. The fourth type of conductive pads may be positioned near the edges of the substrate, allowing for the vertically extending first control voltage line portion to be positioned outside the cut edges of the light-emitting components. This allows for the larger space between adjacent light-emitting components to be utilized for positioning the first control voltage line portion, thereby increasing the line width of the first control voltage line portion, reducing the resistance of the control voltage line, and lowering the voltage drop across the control voltage line.

[0327] Furthermore, by placing the fourth type of conductive pads that transmit control voltages near the edge of the light-emitting component and the first type of conductive pads that transmit data voltages at the center of the light-emitting component, the control voltage lines and the data lines do not overlap, thereby reducing the coupling capacitance between the data lines and the control voltage lines. As shown in FIG4 , in at least one embodiment of the present disclosure, the driver backplane includes a first conductive pad Y1, a second conductive pad Y2, a third conductive pad Y3, a fourth conductive pad Y4, a fifth conductive pad Y5, a sixth conductive pad Y6, a seventh conductive pad Y7, an eighth conductive pad Y8, and a ninth conductive pad Y9;

[0328] The first conducting pad Y1, the second conducting pad Y2, the third conducting pad Y3, the fourth conducting pad Y4, the fifth conducting pad Y5, the sixth conducting pad Y6, the seventh conducting pad Y7, the eighth conducting pad Y8 and the ninth conducting pad Y9 are disposed in the same connection area A0;

[0329] The first conductive pad Y1 is used to provide a reset control signal, the second conductive pad Y2 is used to provide a gate driving signal, the third conductive pad Y3 is used to provide a light emitting control signal, the fourth conductive pad Y4 is used to provide a control voltage, the fifth conductive pad Y5 is used to provide a green data voltage, the sixth conductive pad Y6 is used to provide a power supply voltage signal, the seventh conductive pad Y7 is used to provide a red data voltage, the eighth conductive pad Y8 is used to provide a blue data voltage, and the ninth conductive pad Y9 is used to provide a reset voltage signal;

[0330] Wherein, the first conductive pad Y1 may be the first conductive pad of the fifth category, the second conductive pad Y2 may be the conductive pad of the second category, the third conductive pad Y3 may be the second conductive pad of the fifth category, the fourth conductive pad Y4 may be the conductive pad of the fourth category, the fifth conductive pad Y5 may be the first conductive pad of the first category, the sixth conductive pad Y6 may be the first conductive pad of the third category, the seventh conductive pad Y7 may be the second conductive pad of the first category, the eighth conductive pad Y8 may be the third conductive pad of the first category, and the ninth conductive pad Y9 may be the second conductive pad of the third category;

[0331] In FIG4 , the LED chip is labeled LD, and the outer contour of the LED chip is the cutting edge of the LED chip.

[0332] In at least one embodiment shown in FIG. 4 , Y5, which provides data voltages for the green pixel circuit, and Y8, which provides data voltages for the blue pixel circuit, are positioned horizontally in the middle of the LED chip, and Y7, which provides data voltages for the red pixel circuit, is positioned near the edge of the LED chip, to facilitate the arrangement of three columns of data lines.

[0333] The sixth conductive pad Y6 providing the power voltage signal is arranged at the edge of the LED chip in the horizontal direction, which is conducive to increasing the line width of the first power voltage line, thereby reducing the resistance of the power voltage line and reducing the voltage drop on the power voltage line;

[0334] The ninth conductive pad Y9 for providing a reset voltage signal is arranged at the edge of the LED chip in the horizontal direction, which is conducive to increasing the line width of the first reset voltage line portion, thereby reducing the resistance of the reset voltage line and reducing the voltage drop on the reset voltage line;

[0335] The fourth conductive pad Y4 for providing control voltage is arranged at the edge of the LED chip in the horizontal direction, which is beneficial to increase the line width of the first control voltage line to reduce the resistance of the control voltage line and reduce the voltage drop on the control voltage line.

[0336] In at least one embodiment of the present disclosure, the voltage drop of DC voltage signals such as the power supply voltage signal and the reset voltage signal will affect the power consumption and brightness uniformity. Grid-type wiring should be selected and the load should be minimized. The conductive pad for transmitting the power supply voltage signal and the reset voltage signal is suitable for the cutting edge position close to the LED chip; the control voltage is a high-frequency pulse signal, and the load of the control voltage affects the low grayscale uniformity. Grid-type wiring should be selected and the load should be minimized. The conductive pad for transmitting the control voltage is suitable for the cutting edge position close to the LED chip.

[0337] In at least one embodiment shown in FIG. 4 , the fifth conducting pad Y5 is disposed at the center of the LED chip; the eighth conducting pad Y8 is disposed below the fifth conducting pad Y5; and in the horizontal direction, the eighth conducting pad Y8 is disposed between the seventh conducting pad Y7 and the ninth conducting pad Y9, such that the eighth conducting pad Y8 is disposed at the center of the LED chip in the horizontal direction.

[0338] The sixth conductive pad Y6 electrically connected to the power voltage line is disposed on the left side of the fifth conductive pad Y5, and the ninth conductive pad Y9 electrically connected to the reset voltage line is disposed on the right side of the eighth conductive pad Y8, so that in the horizontal direction, the fifth conductive pad Y5 and the ninth conductive pad Y9 are disposed at the side.

[0339] The fourth conducting pad Y4 electrically connected to the control voltage line is disposed above the sixth conducting pad Y6 , so that the sixth conducting pad Y6 is disposed at a side position in the horizontal direction.

[0340] In at least one embodiment of the present disclosure, the display substrate includes a plurality of light-emitting components disposed on the backplane; the light-emitting components include a substrate, and at least one pixel circuit disposed on the substrate, the pixel circuit including a light-emitting unit and a pixel driving circuit for driving the light-emitting unit;

[0341] The pixel driving circuit includes a driving transistor and a data writing circuit;

[0342] The gate of the driving transistor is electrically connected to the control node, the first electrode of the driving transistor is electrically connected to the first node, and the second electrode of the driving transistor is electrically connected to the second node. The driving transistor is used to generate a driving current under the control of the potential of the control node;

[0343] The control end of the data writing circuit is electrically connected to the gate line, the first end of the data writing circuit is electrically connected to the data line, and the second end of the data writing circuit is electrically connected to the first node. The data writing circuit is used to control the writing of the display data voltage provided by the data line into the first node under the control of the gate drive signal provided by the gate line.

[0344] In a specific implementation, the pixel driving circuit may include a driving transistor and a data writing circuit. The driving transistor generates a driving current under the control of the potential of the control node; the data writing circuit writes the display data voltage into the first node under the control of the gate driving signal to perform display data voltage writing.

[0345] Optionally, the pixel driving circuit further includes a first light emitting control circuit;

[0346] A control terminal of the first light-emitting control circuit is electrically connected to a light-emitting control line, a first terminal of the first light-emitting control circuit is electrically connected to a power supply voltage line, and a second terminal of the first light-emitting control circuit is electrically connected to the first node, wherein the first light-emitting control circuit is configured to control communication between the power supply voltage line and the first node under control of a light-emitting control signal provided by the light-emitting control line;

[0347] The power voltage line is electrically connected to the first third-type conductive pad.

[0348] In a specific implementation, the pixel driving circuit may further include a first light emitting control circuit. The first light emitting control circuit controls the connection between the power supply voltage line and the first node under the control of the light emitting control signal to perform light emitting control.

[0349] Optionally, the pixel driving circuit further includes a second light emitting control circuit and a first control circuit;

[0350] The second light-emitting control circuit is electrically connected to the first control terminal, the second node, and the first electrode of the light-emitting unit, respectively, and is configured to control the second node to be connected to the first electrode of the light-emitting unit under the control of the potential of the first control terminal; the second electrode of the light-emitting unit is electrically connected to the first voltage line; and the first voltage line is electrically connected to the second third-category conductive pad;

[0351] The first control circuit is electrically connected to the first control terminal, the second control terminal, and the data line, respectively. The first input terminal of the first control circuit is electrically connected to the light-emitting control line, the second input terminal of the first control circuit is electrically connected to the control voltage line, and the control terminal of the first control circuit is electrically connected to the reset control line. The first control circuit is configured to write a control data voltage provided by the data line into the second control terminal under the control of a reset control signal provided by the reset control line, maintain the potential of the second control terminal, and control the connection between the first control terminal and the light-emitting control line or the control voltage line under the control of the potential of the second control terminal.

[0352] The light emitting control line is electrically connected to the first fifth type conductive pad, the reset control line is electrically connected to the second fifth type conductive pad, and the control voltage line is electrically connected to the fourth type conductive pad.

[0353] Optionally, the first voltage line may be a reset voltage line.

[0354] In a specific implementation, the pixel driving circuit may further include a second light-emitting control circuit and a first control circuit, wherein the second light-emitting control circuit controls the connection between the second node and the first pole of the light-emitting unit under the control of the potential of the first control terminal; the first control circuit writes the control data voltage provided by the data line into the second control terminal under the control of the reset control signal, maintains the potential of the second control terminal, and controls the connection between the first control terminal and the light-emitting control line or the control voltage line under the control of the potential of the second control terminal.

[0355] Optionally, the pixel circuit may further include a compensation control circuit, a first reset circuit, a second reset circuit and an energy storage circuit;

[0356] The compensation control circuit is electrically connected to the gate line, the control node and the second node respectively, and is used to control the communication between the control node and the second node under the control of the gate drive signal provided by the gate line;

[0357] The first reset circuit is electrically connected to the reset control line, the reset voltage line and the control node respectively, and is used to control the connection between the control node and the reset voltage line under the control of the reset control signal provided by the reset control line;

[0358] The second reset circuit is electrically connected to the reset control line, the reset voltage line and the first electrode of the light-emitting unit respectively, and is used to control the connection between the first electrode of the light-emitting unit and the reset voltage line under the control of the reset control signal;

[0359] A first end of the energy storage circuit is electrically connected to the control node, a second end of the energy storage circuit is electrically connected to the power supply voltage line, and the energy storage circuit is used to store electrical energy.

[0360] In at least one embodiment of the present disclosure, the light-emitting component includes a first pixel circuit, a second pixel circuit, and a third pixel circuit; the plurality of conductive pads include a first first-type conductive pad, a second first-type conductive pad, a third first-type conductive pad, a second-type conductive pad, a first third-type conductive pad, a second third-type conductive pad, a fourth-type conductive pad, a first fifth-type conductive pad, and a second fifth-type conductive pad;

[0361] A first end of the data writing circuit in the first pixel circuit is electrically connected to a first first-type conductive pad, a first end of the data writing circuit in the second pixel circuit is electrically connected to a second first-type conductive pad, and a first end of the data writing circuit in the third pixel circuit is electrically connected to a third first-type conductive pad;

[0362] The control end of the data writing circuit in the first pixel circuit, the control end of the data writing circuit in the second pixel circuit, and the control end of the data writing circuit in the third pixel circuit are all electrically connected to the second type of conductive pad;

[0363] The first end of the first light emitting control circuit in the first pixel circuit, the first end of the first light emitting control circuit in the second pixel circuit, and the first end of the first light emitting control circuit in the third pixel circuit are all electrically connected to a first third-type conductive pad;

[0364] The second electrode of the light-emitting unit in the first pixel circuit, the second electrode of the light-emitting unit in the second pixel circuit, and the second electrode of the light-emitting unit in the third pixel circuit are all electrically connected to the second third-type conductive pad;

[0365] The second input terminal of the first control circuit in the first pixel circuit, the second input terminal of the first control circuit in the second pixel circuit, and the second input terminal of the first control circuit in the third pixel circuit are all electrically connected to the fourth type of conductive pad;

[0366] The control end of the first light emitting control circuit in the first pixel circuit, the control end of the first light emitting control circuit in the second pixel circuit, and the control end of the first light emitting control circuit in the third pixel circuit are all electrically connected to the first fifth-category conductive pad;

[0367] The control end of the first light emitting control circuit in the first pixel circuit, the control end of the first light emitting control circuit in the second pixel circuit, and the control end of the first light emitting control circuit in the third pixel circuit are all electrically connected to the first fifth-category conductive pad;

[0368] The control end of the first control circuit in the first pixel circuit, the control end of the first control circuit in the second pixel circuit, and the control end of the first control circuit in the third pixel circuit are all electrically connected to the second fifth-category conducting pad.

[0369] As shown in FIG5 , at least one embodiment of a pixel circuit may include a driving transistor T0, a data writing circuit 51, a first light emitting control circuit 52, a second light emitting control circuit 53, a first control circuit 54, a compensation control circuit 55, a first reset circuit 56, a second reset circuit 57, and a tank circuit 50;

[0370] The gate of the driving transistor T0 is electrically connected to the control node, the source of the driving transistor T0 is electrically connected to the first node N1, and the drain of the driving transistor T0 is electrically connected to the second node N2. The driving transistor T0 is used to generate a driving current under the control of the potential of the control node N0;

[0371] The gate of the data writing circuit 51 is electrically connected to the gate line GT, the first end of the data writing circuit 51 is electrically connected to the data line DT, and the second end of the data writing circuit 51 is electrically connected to the first node N1. The data writing circuit 51 is used to control the display data voltage provided by the data line DT to be written into the first node N1 under the control of the gate driving signal provided by the gate line GT;

[0372] The pixel driving circuit further includes a first light emitting control circuit 52;

[0373] A control terminal of the first light emitting control circuit 52 is electrically connected to the light emitting control line EM, a first terminal of the first light emitting control circuit 52 is electrically connected to the power supply voltage line LVDD, and a second terminal of the first light emitting control circuit 52 is electrically connected to the first node N1. The first light emitting control circuit 52 is configured to control communication between the power supply voltage line LVDD and the first node N1 under the control of a light emitting control signal provided by the light emitting control line EM.

[0374] The second light emitting control circuit 53 is electrically connected to the first control terminal S1, the second node N2, and the first electrode of the light emitting unit E1, respectively, and is configured to control the second node N2 to be connected to the first electrode of the light emitting unit E1 under the control of the potential of the first control terminal S1; the second electrode of the light emitting unit E1 is electrically connected to the reset voltage line LVSS;

[0375] The first control circuit 54 is electrically connected to the first control terminal S1, the second control terminal S2, and the data line DT, respectively. A first input terminal of the first control circuit 54 is electrically connected to the light-emission control line EM, a second input terminal of the first control circuit 54 is electrically connected to the control voltage line HF, and a control terminal of the first control circuit 54 is electrically connected to the reset control line RST. The first control circuit 54 is configured to write a control data voltage provided by the data line DT into the second control terminal S2 under the control of a reset control signal provided by the reset control line RST, maintain the potential of the second control terminal S2, and control the connection between the first control terminal S1 and the light-emission control line EM or the control voltage line HF under the control of the potential of the second control terminal S2.

[0376] The compensation control circuit 55 is electrically connected to the gate line GT, the control node N0 and the second node N2 respectively, and is used to control the connection between the control node N0 and the second node N2 under the control of the gate drive signal provided by the gate line GT;

[0377] The first reset circuit 56 is electrically connected to the reset control line RST, the reset voltage line LVSS and the control node N0 respectively, and is used to control the connection between the control node N0 and the reset voltage line LVSS under the control of the reset control signal provided by the reset control line RST;

[0378] The second reset circuit 57 is electrically connected to the reset control line RST, the reset voltage line LVSS and the first electrode of the light emitting unit E1, respectively, and is used to control the connection between the first electrode of the light emitting unit E1 and the reset voltage line LVSS under the control of the reset control signal;

[0379] A first terminal of the energy storage circuit 50 is electrically connected to the control node N0 , and a second terminal of the energy storage circuit 50 is electrically connected to the power supply voltage line LVDD. The energy storage circuit 50 is used to store electrical energy.

[0380] Optionally, the light-emitting unit may be a micro-LED, an organic light-emitting diode, or a mini light-emitting diode, but is not limited thereto. As shown in FIG6 , the first reset circuit may include a first transistor T1, the compensation control circuit may include a second transistor T2, the data write circuit may include a fourth transistor T4, the first light-emitting control circuit may include a fifth transistor T5, the second light-emitting control circuit may include a sixth transistor T6, the second reset circuit may include a seventh transistor T7, the first control circuit may include an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, and a control capacitor C0, and the energy storage circuit may include a storage capacitor Cst; the light-emitting unit is a micro-LED M1;

[0381] The gate of T0 is electrically connected to the control node N0, the source of T0 is electrically connected to the first node N1, and the drain of T0 is electrically connected to the second node N2;

[0382] The gate of T1 is electrically connected to the reset control line RST, the source of T1 is electrically connected to the reset voltage line LVSS, and the drain of T1 is electrically connected to the control node N0;

[0383] The gate of T2 is electrically connected to the gate line GT, the source of T2 is electrically connected to the control node N0, and the drain of T2 is electrically connected to the second node N2;

[0384] The gate of T4 is electrically connected to the gate line GT, the source of T4 is electrically connected to the data line DT, and the drain of T4 is electrically connected to the first node N1;

[0385] The gate of T5 is electrically connected to the light emitting control line EM, the source of T5 is electrically connected to the power supply voltage line LVDD, and the drain of T5 is electrically connected to the first node N1;

[0386] The gate of T6 is electrically connected to the light emitting control line EM, the source of T6 is electrically connected to the second node N2, the drain of T6 is electrically connected to the anode of the micro light emitting diode M1; the cathode of M1 is electrically connected to the reset voltage line LVSS;

[0387] The gate of T7 is electrically connected to the reset control line RST, the source of T7 is electrically connected to the reset voltage line LVSS, the drain of T7 is electrically connected to the anode of M1; the cathode of M1 is electrically connected to the reset voltage line LVSS;

[0388] The gate of T8 is electrically connected to the second control terminal S2, the source of T8 is electrically connected to the light emitting control line EM, and the drain of T8 is electrically connected to the first control terminal S1;

[0389] The gate of T9 is electrically connected to the second control terminal S2, the source of T9 is electrically connected to the control voltage line HF, and the drain of T9 is electrically connected to the first control terminal S1;

[0390] The gate of T10 is electrically connected to the reset control line RST, the source of T10 is electrically connected to the data line DT, and the drain of T10 is electrically connected to the second control terminal S2;

[0391] A first terminal of C0 is electrically connected to the second control terminal S2, and a second terminal of C0 is electrically connected to the reset voltage line LVSS;

[0392] A first end of Cst is electrically connected to the control node N0 , and a second end of Cst is electrically connected to the power supply voltage line LVDD.

[0393] In at least one embodiment of the pixel circuit shown in FIG. 6 , T1 , T7 , T9 , and T10 are n-type transistors, and the other transistors are p-type transistors, but the present invention is not limited thereto.

[0394] As shown in FIG7 , when at least one embodiment of the pixel circuit shown in FIG6 is in operation, a display cycle may include a reset phase t1 , a write phase t2 , and a light emitting phase t3 , which are arranged in sequence;

[0395] In the reset phase t1, EM provides a high voltage signal, RST provides a high voltage signal, GT provides a high voltage signal, DT provides a control data voltage, T1, T7 and T10 are turned on, and the reset voltage signal provided by LVSS is written to the anodes of N1 and M1, so that when the write phase t2 begins, T0 can be turned on and clear the residual charge on the anode of M1; T10 is turned on to write the control data voltage to the second control terminal S2, and C0 maintains the potential of the second control terminal S2; when the control data voltage is a low-level signal, T8 is turned on, and EM is connected to the first control terminal S1; when the control data voltage is a high-level signal, T89 is turned on, and HF is connected to the first control terminal S1; when the gate of T6 is connected to EM, high grayscale display is performed; when the gate of T6 is connected to HF, low grayscale display is performed; wherein the control voltage provided by HF is a high-frequency pulse signal;

[0396] In the writing phase t2, EM provides a high voltage signal, RST provides a low voltage signal, GT provides a low voltage signal, the data line DT provides the display data voltage Vdata, T10 is turned off, T4 is turned on, the display data voltage Vdata is written into N1, and T2 is turned on;

[0397] At the beginning of the write phase t2, T0 is turned on, charging Cst through Vdata, changing the potential of N0 until the potential of N0 becomes Vdata+Vth, T0 is turned off, and charging stops. Vth is the threshold voltage of T0;

[0398] In the light-emitting stage t3, EM provides a low voltage signal, RST provides a low voltage signal, GT provides a high voltage signal, T5 is turned on, and when T6 is turned on, T0 drives M1 to emit light.

[0399] FIG8 is a circuit diagram of three pixel circuits included in an LED chip.

[0400] As shown in FIG8 , the LED chip may include a red pixel circuit, a green pixel circuit, and a blue pixel circuit;

[0401] The red pixel circuit includes a first driving transistor T01, a first first transistor T11, a first second transistor T12, a first fourth transistor T14, a first fifth transistor T15, a first sixth transistor T16, a first seventh transistor T17, a first eighth transistor T18, a first ninth transistor T19, a first tenth transistor T110, a first storage capacitor Cst1, a first control capacitor C01 and a red micro light emitting diode MR;

[0402] The green pixel circuit includes a second driving transistor T02, a second first transistor T21, a second second transistor T22, a second fourth transistor T24, a second fifth transistor T25, a second sixth transistor T26, a second seventh transistor T27, a second eighth transistor T28, a second ninth transistor T29, a second tenth transistor T210, a second storage capacitor Cst2, a second control capacitor C02 and a green micro light emitting diode MG;

[0403] The blue pixel circuit includes a third driving transistor T03, a third first transistor T31, a third second transistor T32, a third fourth transistor T34, a third fifth transistor T35, a third sixth transistor T36, a third seventh transistor T37, a third eighth transistor T38, a third ninth transistor T39, a third tenth transistor T310, a third storage capacitor Cst3, a third control capacitor C03 and a blue micro light emitting diode MB;

[0404] The data line marked DTR is red, the data line marked DTG is green, and the data line marked DTB is blue.

[0405] In at least one embodiment shown in FIG8 , the source of T24 is electrically connected to the first first-type conductive pad, the source of T34 is electrically connected to the second first-type conductive pad, and the source of T14 is electrically connected to the first first-type conductive pad;

[0406] The gate of T14, the gate of T12, the gate of T24, the gate of T22, the gate of T34 and the gate of T32 are all electrically connected to the second type of conductive pad;

[0407] The source of T15, the source of T25 and the source of T35 are all electrically connected to the first third-type conductive pad, and the cathode of MR, the cathode of MG and the cathode of MR are all electrically connected to the second third-type conductive pad;

[0408] The source of T19, the source of T29, and the source of T39 are all electrically connected to the fourth type of conductive pad;

[0409] The gate of T15, the gate of T25, the gate of T35, the source of T18, the source of T28 and the source of T38 are all electrically connected to the first fifth-category conductive pad;

[0410] The gates of T110 , T210 , T310 , T11 , T17 , T21 , T27 , T31 , and T37 are all electrically connected to the second fifth-category conducting pad.

[0411] As shown in FIG9 , in at least one embodiment of the present disclosure, at least one embodiment of the LED chip may include a first pixel circuit P1 , a second pixel circuit P2 , a third pixel circuit P3 , and a timing generation module 120 ;

[0412] The timing generation module 120 receives the high voltage signal VD, the low voltage signal VS, the chip select signal SCS and the clock signal SCLK, and the timing control module 120 is used to generate the reset control signal Rst, the light control signal Em, the first gate drive signal Gt1, the second gate drive signal Gt2 and the third gate drive signal Gt3;

[0413] The first pixel circuit, the second pixel circuit and the third pixel circuit are connected to a high voltage signal VD and a low voltage signal VS;

[0414] The structures of the first pixel circuit, the second pixel circuit, and the third pixel circuit may be as shown in FIG10 ;

[0415] The timing control module 120 is used to provide a first gate driving signal Gt1 for the first pixel circuit, a second gate driving signal Gt2 for the second pixel circuit, and a third gate driving signal Gt3 for the third pixel circuit;

[0416] The timing generation module 120 provides a reset control signal Rst and a light emitting control signal Em to the first pixel circuit, the second pixel circuit, and the third pixel circuit;

[0417] The first pixel circuit, the second pixel circuit and the third pixel circuit are respectively connected to the corresponding display data voltage Vdata, and the first pixel circuit, the second pixel circuit and the third pixel circuit are respectively connected to the control voltage Hf, and the control voltage Hf can be a high-frequency pulse signal.

[0418] In at least one embodiment shown in FIG. 9 , the first pixel circuit may be a red pixel circuit, the second pixel circuit may be a green pixel circuit, and the third pixel circuit may be a blue pixel circuit, but the present invention is not limited thereto.

[0419] As shown in FIG10 , at least one embodiment of a pixel circuit may include a light emitting diode L0, a driving transistor Md, a first light emission control transistor ME1, a second light emission control transistor ME2, a display data voltage supply transistor MDX, a storage capacitor Cst, a first reset transistor MR1, a second reset transistor MR2, a compensation control transistor MC, and a display control circuit;

[0420] The display control circuit includes a first display control transistor MX1, a second display control transistor MX2, a third display control transistor MX3 and a display control capacitor C0;

[0421] The gate of MX1 is connected to the gate drive signal Gt, the source of MX1 is electrically connected to the control data voltage terminal DTC, and the drain of MX1 is electrically connected to the gate of MX2;

[0422] The gate of MX2 is electrically connected to the gate of MX3, the source of MX2 is connected to the control voltage Hf, and the drain of MX3 is electrically connected to the gate of ME2;

[0423] The source of MX3 is electrically connected to the light emitting control line EM, and the drain of MX3 is electrically connected to the gate of ME2;

[0424] The first end of C0 is electrically connected to the gate of MX2, and the second end of C0 is connected to the initial voltage Vini;

[0425] MX1 and MX3 are n-type transistors, and MX2 is a p-type transistor;

[0426] The gate of ME1 is electrically connected to the light emitting control line EM, the source of ME1 is electrically connected to the power supply voltage line LVDD, and the drain of ME1 is electrically connected to the source of Md;

[0427] The gate of Md is electrically connected to the first end of Cst1, and the drain of Md is electrically connected to the source of ME2;

[0428] The second end of Cst1 is electrically connected to the power voltage line LVDD;

[0429] The gate of ME2 is electrically connected to the control terminal TD, the drain of ME2 is electrically connected to the anode of the light emitting diode L0, and the cathode of the light emitting diode L0 is electrically connected to the reset voltage line LVSS;

[0430] The gate of MC is connected to the gate drive signal Gate, the source of MC is electrically connected to the gate of Md, and the drain of MC is electrically connected to the drain of Md;

[0431] The gate of MR1 is connected to the reset control signal Rst, the source of MR1 is connected to the initial voltage Vini, and the drain of MR1 is electrically connected to the gate of Md;

[0432] The gate of MR2 is connected to the reset control signal Rst, the source of MR2 is connected to the initial voltage Vini, and the drain of MR2 is electrically connected to the anode of L0;

[0433] The gate of MDX is connected to the gate drive signal Gate, the source of MDX is connected to the display data voltage Vdata, and the drain of MDX is electrically connected to the source of Md;

[0434] Both MR1 and MR2 are n-type transistors;

[0435] ME1, ME2, Md, MDX and MC are all p-type transistors.

[0436] In at least one embodiment of the present disclosure, a pixel circuit manufactured using an LTPS (low-temperature polycrystalline silicon) process or an LTPO (low-temperature polycrystalline oxide) process provides a driving current through a driving transistor, so there is no strong dependence on the voltage drop of the power supply. Therefore, a large-size display panel can be manufactured, which can be 30 inches, 55 inches or larger, and the splicing cost can be reduced.

[0437] The display substrate according to at least one embodiment of the present disclosure includes a light-emitting component disposed on the driving backplane and electrically connected to the conducting pad;

[0438] The light emitting component comprises:

[0439] a light-emitting unit, the light-emitting unit comprising: a first electrode, a second electrode, and a light-emitting portion electrically connected to the first electrode and the second electrode respectively;

[0440] a driving unit having a pixel driving circuit, the driving unit comprising: a third electrode, a fourth electrode, and a driving circuit, the third electrode and the fourth electrode being located on a side of the driving unit facing the light-emitting unit, the third electrode and the fourth electrode being electrically connected to the driving circuit, respectively, the third electrode being electrically connected to the first electrode, and the fourth electrode being electrically connected to the second electrode;

[0441] The first substrate is located on a side of the light emitting unit away from the driving unit.

[0442] Optionally, the light-emitting assembly includes a plurality of light-emitting units;

[0443] The plurality of light emitting units include a first color light emitting unit, a second color light emitting unit and a third color light emitting unit;

[0444] The first color, the second color and the third color are different from each other.

[0445] In at least one embodiment of the present disclosure, the light-emitting unit includes a color filter layer, a color conversion layer, and a light-emitting layer stacked in sequence in a direction away from the first substrate; the light-emitting layer emits blue light;

[0446] The light-emitting layer includes a first semiconductor layer, a multi-quantum well layer and a second semiconductor layer that are stacked, wherein the first semiconductor layer is electrically connected to the first electrode, the second semiconductor layer is electrically connected to the second electrode, and the light-emitting layer includes a first light-emitting portion, a second light-emitting portion and a third light-emitting portion.

[0447] Optionally, the driving circuit includes a plurality of thin film transistors, each of which includes a gate, a source and a drain.

[0448] In at least one embodiment of the present disclosure, the driving unit further includes a substrate; the driving circuit includes a buffer layer, an active layer, a first gate insulating layer, a first gate layer, an interlayer dielectric layer, a source and drain layer, and a planar layer, which are located on one side of the substrate and stacked in sequence; the third electrode and the fourth electrode are located on a side of the planar layer away from the substrate;

[0449] The active layer includes a plurality of active patterns corresponding to the plurality of thin film transistors, and each of the active patterns includes a source region, a drain region, and a channel region;

[0450] The source electrode and the drain electrode of the thin film transistor are located in the source-drain electrode layer, the source electrode of the thin film transistor is connected to the source region, and the drain electrode of the thin film transistor is connected to the drain region;

[0451] The first gate layer includes a plurality of gate patterns corresponding to the plurality of thin film transistors, and the channel region is an overlapping region of an orthographic projection of the gate pattern on the substrate and an orthographic projection of the active pattern on the substrate.

[0452] Optionally, the substrate may be located on a side of the driving unit away from the light-emitting unit.

[0453] In at least one embodiment of the present disclosure, at least one of the driving transistor and the data writing circuit includes the thin film transistor.

[0454] Optionally, the pixel driving circuit further includes a first light emitting control circuit, a second light emitting control circuit and a first control circuit;

[0455] At least one of the first light emission control circuit, the second light emission control circuit, and the first control circuit includes the thin film transistor.

[0456] In at least one embodiment of the present disclosure, at least one transistor in the pixel driving circuit may be the thin film transistor.

[0457] Optionally, the light-emitting component further includes a plurality of pins;

[0458] The plurality of pins are located on a side of the driving circuit away from the light-emitting unit and are electrically connected to the driving circuit. The plurality of pins are connected to the plurality of conductive pads in one conductive pad group in a one-to-one correspondence.

[0459] In at least one embodiment of the present disclosure, the driving unit further includes a substrate and a connection structure, the substrate having a connection via, the connection structure is located in the connection via, and the driving circuit is located on one side of the substrate;

[0460] The pin is located on a side of the substrate away from the driving circuit, and the pin is in contact with the connection structure. The pin and the driving circuit are connected via the connection structure.

[0461] In at least one embodiment of the present disclosure, the driving circuit includes a plurality of thin film transistors, each of which includes a gate, a source, and a drain;

[0462] One of the plurality of pins is connected to a source electrode of a thin film transistor among the plurality of thin film transistors, and is used for providing the driving circuit with a data driving signal transmitted from a display backplane in a display panel.

[0463] FIG11A is a schematic diagram of the structure of a light emitting assembly provided by an embodiment of the present disclosure. Referring to FIG11A , the light emitting assembly 10 includes: a light emitting unit 101 , a driving unit 102 , a plurality of pins 103 , and a first substrate 104 .

[0464] The light-emitting unit 101 includes a first electrode 1011 , a second electrode 1012 , and a light-emitting portion 1013 electrically connected to the first electrode 1011 and the second electrode 1012 .

[0465] The driving unit 102 includes a third electrode 1021, a fourth electrode 1022, and a driving circuit 1023. The third electrode 1021 and the fourth electrode 1022 are both located on the side of the driving unit 102 facing the light-emitting unit 101, i.e., the third electrode 1021 and the fourth electrode 1022 are closer to the light-emitting unit 101 than the driving circuit 1023. The third electrode 1021 and the fourth electrode 1022 are respectively electrically connected to the driving circuit 1023. The third electrode 1021 is electrically connected to the first electrode 1011, and the fourth electrode 1022 is electrically connected to the second electrode 1012.

[0466] The plurality of pins 103 are located on a side of the driving unit 102 away from the light emitting unit 101 and are electrically connected to the driving circuit 1023 .

[0467] In at least one embodiment of the present disclosure, the light-emitting component may be a light-emitting chip.

[0468] In some embodiments, the first substrate 104 is located on a side of the light-emitting unit 101 away from the driving unit 102. The orthographic projection of the light-emitting unit 101 on the first substrate 104 is located within the first substrate 104, and the orthographic projection of the light-emitting unit 101 on the driving unit 102 is located within the driving unit 102. In other words, both the first substrate 104 and the driving unit 102 have areas that extend beyond the light-emitting unit 101.

[0469] In some embodiments, the material of pins 103 may include a conductive material, such as metal. Optionally, at least one of pins 103 includes a first metal layer and a second metal layer stacked together. The first metal layer is located between the second metal layer and the driver unit 102, i.e., the first metal layer is closer to the driver unit 102 than the second metal layer.

[0470] The material of the first metal layer includes nickel (Ni), and the material of the second metal layer includes gold (Au). For example, the material of the first metal layer is nickel, and the material of the second metal layer is gold.

[0471] Through the design of the pin 103 in the embodiment of the present disclosure, when the light-emitting component 10 and the display backplane included in the display panel are fixed, the pin 103 can be fixedly connected to the pad of the display backplane through a gold deposition process using a welding process, thereby realizing the connection between the light-emitting component 10 and the display backplane.

[0472] Optionally, the plurality of light-emitting units 101 include a first color light-emitting unit, a second color light-emitting unit, and a third color light-emitting unit. The first color, the second color, and the third color are different from each other. For example, the first color is red, the second color is green, and the third color is blue.

[0473] FIG11B is a schematic diagram of the connection relationship between the light-emitting component and the driving backplane provided in an embodiment of the present disclosure.

[0474] 11B , three light-emitting components included in at least one embodiment of a display substrate are shown;

[0475] The light emitting component includes a first pin 131, a second pin 132 and a third pin 133;

[0476] At least one embodiment of the display substrate further includes a driving backplane P0;

[0477] The driving backplane P0 includes a first conductive pad Y01, a second conductive pad Y02, a third conductive pad Y03, a fourth conductive pad Y04, a fifth conductive pad Y05, a sixth conductive pad Y06, a seventh conductive pad Y07, an eighth conductive pad Y08 and a ninth conductive pad Y09;

[0478] In FIG11B , the first light-emitting component is labeled Z1, the third light-emitting component is labeled Z2, and the second light-emitting component is labeled Z3;

[0479] Y01 is electrically connected to the first pin 131 of the first light-emitting component Z1, Y02 is electrically connected to the second pin 132 of the first light-emitting component Z1, and Y03 is electrically connected to the third pin 133 of the first light-emitting component Z1; Y04 is electrically connected to the first pin 131 of the second light-emitting component Z2, Y05 is electrically connected to the second pin 132 of the second light-emitting component Z2, and Y06 is electrically connected to the third pin 133 of the second light-emitting component Z2;

[0480] Y07 is electrically connected to the first pin 131 of the third light-emitting component Z3 , Y08 is electrically connected to the second pin 132 of the third light-emitting component Z3 , and Y09 is electrically connected to the third pin 133 of the third light-emitting component Z3 .

[0481] In at least one embodiment of the present invention, Y01-Y09 may be Y1-Y9, and the corresponding order may be set according to design requirements.

[0482] For example, Y01 may be Y7, Y02 may be Y8, and Y03 may be Y9.

[0483] For example: Y01 can be Y7, Y02 can be Y6, and Y03 can be Y4.

[0484] 12 is a schematic diagram of a light-emitting unit according to an embodiment of the present invention. The light-emitting unit 101 includes a color filter layer 1014 , a color conversion layer 1015 , and a light-emitting layer 1016 , which are sequentially stacked in a direction away from the first substrate 104 .

[0485] The light emitting layer 1016 emits blue light. Referring to FIG13 , the light emitting layer 1016 includes a stacked first semiconductor layer 10161, a multi-quantum well layer 10162, and a second semiconductor layer 10163. The first semiconductor layer 10161 is electrically connected to the first electrode 1011, and the second semiconductor layer 10163 is electrically connected to the second electrode 1012.

[0486] Optionally, the first semiconductor layer 10161 may be an N-type doped layer, and the second semiconductor layer 10163 may be a P-type doped layer. Accordingly, the first electrode 1011 may be referred to as an N-type electrode, and the second electrode 1012 may be referred to as a P-type electrode. Optionally, the material of the first semiconductor layer 10161 may be N-type gallium nitride (GaN), and the first semiconductor layer 10161 is denoted as N-GaN. The material of the second semiconductor layer 10163 may be P-type gallium nitride (GaN), and the second semiconductor layer 10163 is denoted as P-GaN.

[0487] Furthermore, the light-emitting layer 1016 includes a first light-emitting portion, a second light-emitting portion, and a third light-emitting portion. That is, the first light-emitting portion, the second light-emitting portion, and the third light-emitting portion all emit blue light. FIG13 illustrates only one light-emitting portion.

[0488] The color conversion layer 1015 includes a first color conversion portion, a second color conversion portion, and a transparent portion. Figure 13 shows only one color conversion portion 10151. The orthographic projection of the first color conversion portion on the first substrate 104 overlaps with the orthographic projection of the first light-emitting portion on the first substrate 104. The first color conversion portion is used to convert the light emitted by the first light-emitting portion into a color corresponding to the first color conversion portion (for example, red). The orthographic projection of the second color conversion portion on the first substrate 104 overlaps with the orthographic projection of the second light-emitting portion on the first substrate 104. The second color conversion portion is used to convert the light emitted by the second light-emitting portion into a color corresponding to the second color conversion portion (for example, green). The orthographic projection of the third color conversion portion on the first substrate 104 overlaps with the orthographic projection of the transparent portion on the first substrate 104. The transparent portion is used to transmit light emitted by the third light-emitting portion.

[0489] Optionally, the color conversion layer 1015 further includes a spacer 10152 between any two adjacent structures among the first color conversion portion, the second color conversion portion and the transparent portion. The spacer 10152 is used to distinguish and separate different color conversion portions and transparent portions.

[0490] The color filter layer 1014 includes a first color block, a second color block, a third color block, and a black matrix 10142. FIG13 shows only one color block 10141. The black matrix 10142 is located between adjacent color blocks. The orthographic projection of the first color block on the first substrate 104 overlaps with the orthographic projection of the first color conversion portion on the first substrate 104. The first color block is used to transmit the light of the corresponding color after conversion by the first color conversion portion and block light of other colors. The orthographic projection of the second color block on the first substrate 104 overlaps with the orthographic projection of the second color conversion portion on the first substrate 104. The second color block is used to transmit the light of the corresponding color after conversion by the second color conversion portion and block light of other colors. The orthographic projection of the third color block on the first substrate 104 overlaps with the orthographic projection of the transparent portion on the first substrate 104. The third color block is used to transmit the light of the corresponding color transmitted by the transparent portion and block light of other colors.

[0491] For example, the first color block is a red color block, the second color block is a green color block, and the thirteenth color block is a blue color block.

[0492] 13 , the second semiconductor layer 10163 and the multi-quantum well layer 10162 are used to expose a target portion of the first semiconductor layer 10161. The light emitting layer 1016 further includes a raised electrode 10164, a conductive layer 10165, and an insulating layer 10166.

[0493] The raised electrode 10164 is connected to the target portion of the first semiconductor layer 10161, the conductive layer 10165 is located on the side of the second semiconductor layer 10163 away from the first substrate 104, and the insulating layer 10166 is located on the side of the raised electrode 10164 and the conductive layer 10165 away from the first substrate 104. The insulating layer 10166 has a first via (N-type via) and a second via (P-type via). The first via is used to expose the raised electrode 10164, and the raised electrode 10164 is connected to the first electrode 1011 through the first via. The second via is used to expose the conductive layer 10165, and the conductive layer 10165 is connected to the second electrode 1012 through the second via. Optionally, the conductive layer 10165 can be made of indium tin oxide (ITO), and the insulating layer 10166 can be a passivation layer (PVX).

[0494] As can be seen from FIG13 , the light-emitting unit 101 further includes an adhesive layer 1017 and a buffer layer 1018. Both the adhesive layer 1017 and the buffer layer 1018 are located between the color conversion layer 1015 and the light-emitting layer 1016. The adhesive layer 1017 is used to bond the color conversion layer 1015 and the buffer layer 1018. The buffer layer 1018 can be made of GaN.

[0495] Figures 12 and 13 are structural diagrams of at least one embodiment of a light-emitting unit. In actual operation, the light-emitting unit can be a red LED (light-emitting diode), a green LED, or a blue LED (which can directly emit red, green, or blue light from the multi-quantum well layer without a color conversion layer).

[0496] Figure 14 is a schematic diagram of the structure of a drive unit provided by an embodiment of the present disclosure. Referring to Figure 14 , it can be seen that the drive unit 102 further includes a substrate 1024 and a connection structure 1025. Substrate 1024 can be made of polyimide (PI), and can be referred to as a PI substrate. Substrate 1024 has connection vias, and connection structure 1025 is located within the connection vias.

[0497] 14 , the driving circuit 1023 is located on one side of the substrate 1024, and the pins 103 are located on a side of the substrate 1024 away from the driving circuit 1023. The pins 103 are in contact with the connection structure 1025. The pins 103 and the driving circuit 1023 are connected via the connection structure 1025, so that the pins 103 transmit driving signals to the driving circuit 1023 via the connection structure 1025.

[0498] Optionally, the cross-sectional area of ​​the connection structure 1025 in the direction perpendicular to the thickness of the substrate 1024 gradually changes with increasing distance from the driving circuit 1023. Referring to FIG14 , the cross-sectional area of ​​the connection structure 1025 in the direction perpendicular to the thickness of the substrate 1024 gradually increases with increasing distance from the driving circuit 1023.

[0499] That is, the area of ​​the side of the connection structure 1025 close to the driving circuit 1023 is smaller than the area of ​​the side of the connection structure 1025 close to the pin 103, and the projection of the side of the connection structure 1025 close to the driving circuit 1023 is located within the projection of the side of the connection structure 1025 close to the pin 103.

[0500] In the embodiment of the present disclosure, the driving circuit 1023 may include multiple thin film transistors and at least one storage capacitor. Optionally, the driving circuit 1023 may include seven thin film transistors and one storage capacitor, that is, the driving circuit 1023 is a 7T1C driving circuit 1023. Alternatively, the driving circuit 1023 may include other numbers of thin film transistors and other numbers of storage capacitors. The embodiment of the present application does not limit the number of thin film transistors included in the driving circuit 1023, nor the number of storage capacitors included.

[0501] Each thin film transistor includes a gate, a source, and a drain. The driving circuit 1023 includes multiple thin film transistors that are interconnected to achieve the function of driving the light emitting unit 101 to emit light.

[0502] Optionally, the plurality of thin film transistors include at least a data writing transistor, the source of which is connected to a data line of a display backplane in the display panel. The data line can transmit a data driving signal to the driving circuit 1023 through the data writing transistor.

[0503] In the embodiment of the present disclosure, one pin 103 among the multiple pins 103 included in the light-emitting component 10 is connected to the source of the data writing transistor in the driving circuit 1023, and the data writing transistor is connected to the third electrode 1021 of the driving unit 102 through other thin film transistors, so that the data line included in the display backplane in the display panel transmits the data driving signal to the first electrode 1011 of the light-emitting unit 101 through the pin 103, the driving circuit 1023, and the third electrode 1021 in sequence.

[0504] It should be noted that in order for the driving unit 102 to drive the light-emitting unit 101 to emit light, in addition to providing the data driving signal to the first electrode 1011 of the light-emitting unit 101, it is also necessary to provide a power signal (e.g., a VSS signal) to the second electrode 1012 of the light-emitting unit 101. Optionally, the display backplane can provide the same power signal to the multiple light-emitting components 10 included in the display panel. Therefore, the power signal can be provided to the second electrodes 1012 of the light-emitting units 101 in the multiple light-emitting components via pins located in the peripheral area of ​​the display panel (the pins are not shown in the drawings).

[0505] 14 , the driver circuit 1023 includes a buffer layer (buffer+barrier) m1, an active layer (poly) m2, a first gate insulator (GI) m3, a first gate layer (gate) m4, a second gate insulator m5, a second gate layer (not shown), an interlayer dielectric (ILD) m6, a source / drain layer m7, and a planarization layer (PLN) m8, which are stacked in sequence on one side of a substrate 1024. The third electrode 1021 and the fourth electrode 1022 included in the driver unit 102 are located on the side of the planarization layer m8 away from the substrate 1024.

[0506] The active layer m2 includes multiple active patterns corresponding to multiple thin film transistors, each of which includes a source region, a drain region, and a channel region. The source and drain of the thin film transistor are located in the source-drain layer, and the source of the thin film transistor is connected to the source region, and the drain is connected to the drain region.

[0507] The first gate layer m4 includes a plurality of gate patterns corresponding to a plurality of thin film transistors. The channel region is an overlapping region of an orthographic projection of the gate pattern on the substrate 1024 and an orthographic projection of the active pattern on the substrate 1024.

[0508] Referring to Figure 14 , the first gate layer m4 also includes a gate connector m41 connected to the connection structure 1025. This gate connector m41 is used to connect to the connection structure 1025 and the source of the data write transistor. To connect the connection structure 1025 and the gate connector m41, connection vias can also be provided in the buffer layer m1 and the first gate insulating layer m3. Furthermore, the connection structure 1025 is located not only within the connection via in the substrate 1024, but also within the connection vias in the buffer layer m1 and the first gate insulating layer m3.

[0509] In the embodiment of the present disclosure, referring to FIG. 14 , the area of ​​the orthographic projection of the pin 103 on the substrate 1024 is larger than the area of ​​the orthographic projection of the connection structure 1025 on the substrate 1024, and the orthographic projection of the pin 103 on the substrate 1024 overlaps the orthographic projection of the connection structure 1025 on the substrate 1024. Thus, the connection area between the pin 103 and the connection structure 1025 can be made as large as possible, thereby ensuring the reliability of the connection between the pin 103 and the connection structure 1025. For example, the connection area can be equal to the area of ​​the side of the connection structure 1025 closest to the pin 103.

[0510] FIG. 15 is a schematic diagram illustrating a combination of at least one embodiment of the driving unit shown in FIG. 14 and at least one embodiment of the light-emitting unit shown in FIG. 12 .

[0511] In a specific implementation, the pin 103 may be electrically connected to each conductive pad included in the driving backplane to transmit each voltage signal.

[0512] As shown in FIG16 , when preparing at least one embodiment shown in FIG15 , the following preparation process steps may be used:

[0513] Step S701: obtaining a first substrate and a light-emitting unit located on one side of the first substrate;

[0514] Step S702: obtaining a second substrate and a driving unit located on one side of the second substrate;

[0515] Step S703: bonding the light emitting unit and the driving unit together through a bonding process;

[0516] Step S704: peeling the second substrate from one side of the driving unit;

[0517] Step S705: forming a plurality of pins on a side of the driving unit away from the light-emitting unit;

[0518] Step S706: cutting the edge of the initial substrate using a cutting process.

[0519] In a specific implementation, a micro light emitting diode (Micro LED) display panel generally includes a display backplane, a driving unit integrated on the display backplane, and a light emitting chip bonded to the driving unit. When preparing the Micro LED display panel, in order to achieve color display, it is necessary to transfer and bond light emitting chips of different colors to a display backplane integrated with a driving unit, and light emitting chips of the same color are transferred at the same time, and light emitting chips of different colors are transferred in batches. That is, the number of transfers is the number of colors of the light emitting chip. Optionally, the light emitting chip includes light emitting chips of three colors, such as a red light emitting chip, a green light emitting chip, and a blue light emitting chip, and thus three transfers are required. This solution requires more transfers when preparing the Micro LED display panel, and the process is more complicated.

[0520] Furthermore, to reduce the manufacturing cost of Micro LED display panels, the display backplane is designed to be small (because if it is too large, if some of the light-emitting chips fail to emit light after transfer, the entire product will be scrapped, increasing the cost). Therefore, if this solution needs to achieve a large-scale display, it can only be achieved through splicing, which results in poor display quality.

[0521] The red, green and blue micro-display chips are bonded to the driving unit to form a new active-matrix light-emitting diode (AM-LED) chip with its own driving circuit. The AM-LED chip includes light-emitting chips of red, green and blue colors and a driving unit for driving the light-emitting chips. Furthermore, depending on the size of the display panel to be prepared, a corresponding number of AM-LED chips are used to perform one-time transfer bonding with the display backplane to realize the preparation of a color light-emitting diode (LED) display panel. At the same time, this solution only requires one transfer process, and the process is relatively simple. In addition, large-size display can be achieved without splicing, which can improve the utilization rate of the display backplane and thus reduce costs.

[0522] Furthermore, the AM-LED chip utilizes dual electrical and optical testing technology to select chips that meet both optical and driving performance requirements. This improves chip yield on the display panel and facilitates repair and replacement of defective chips, compared to solutions that integrate the driver circuitry onto the display backplane to form the display panel.

[0523] As shown in FIG17 , the display substrate according to at least one embodiment of the present disclosure includes a driving backplane P0 and a plurality of rows and columns of light-emitting components disposed on the driving backplane P0 ;

[0524] In FIG17 , the light emitting assembly labeled F11 is the first row and first column, the light emitting assembly labeled F12 is the first row and second column, and the light emitting assembly labeled F1b is the first row and b column; b is an integer greater than 2;

[0525] The light emitting component labeled F21 is the first row and first column, the light emitting component labeled F22 is the second row and second column, and the light emitting component labeled F2b is the second row and b column.

[0526] The light emitting component labeled Fa1 is the light emitting component in the first column of the a-th row, the light emitting component labeled Fa2 is the light emitting component in the second column of the a-th row, and the light emitting component labeled Fab is the light emitting component in the b-th column of the a-th row; a is an integer greater than 1;

[0527] Each light-emitting component is electrically connected to a corresponding conductive pad included in the driving backplane P0, and receives a data voltage, a gate driving signal, a power voltage signal, a reset voltage signal, a light-emitting control signal and a reset control signal from the driving backplane P0.

[0528] The display device described in the embodiment of the present disclosure includes the above-mentioned display substrate.

[0529] The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

Claims

1. A driving backplane, comprising a base substrate having a plurality of connection regions; the driving backplane further comprising a plurality of data lines, a plurality of gate lines, a plurality of voltage lines, and a plurality of conductive pad groups, the conductive pad groups being disposed in corresponding connection regions; the conductive pad groups comprising a plurality of conductive pads; The plurality of conductive pads include a first type of conductive pad for transmitting a data voltage, a second type of conductive pad for transmitting a gate driving signal, and a third type of conductive pad for transmitting a voltage signal; One of the data line and the gate line extends along a first direction, and the other of the data line and the gate line extends along a second direction; the voltage line includes a first voltage line portion extending in the first direction; the first direction intersects the second direction; The first type of conductive pads are electrically connected to the data lines, the second type of conductive pads are electrically connected to the gate lines, and the third type of conductive pads are electrically connected to the voltage lines.

2. The driving backplane according to claim 1, wherein: The voltage line further includes a second voltage line portion extending along a second direction; the second voltage line portion is electrically connected to the first voltage line portion; The first voltage line portion and the second voltage line portion are disposed in different conductive layers.

3. The driving backplane according to claim 1, wherein: The line width of the first voltage line portion is greater than the line width of the data line.

4. The driving backplane according to claim 2, wherein: Also included are a driving module and a power supply voltage lead disposed on the substrate; the voltage line includes a power supply voltage line; the power supply voltage line includes a first power supply voltage line portion extending along a first direction and a second power supply voltage line portion extending along a second direction; The driving module includes a power supply voltage output terminal, and the power supply voltage output terminal is electrically connected to the power supply voltage lead; The driving module is used to provide a power supply voltage signal through the power supply voltage output terminal; The power supply voltage lead is electrically connected to the first power supply voltage line portion.

5. The driving backplane according to claim 2, wherein: Also included is a driving module and a reset voltage lead disposed on the substrate; the voltage line includes a reset voltage line; the reset voltage line includes a first reset voltage line portion extending along a first direction and a second reset voltage line portion extending along a second direction; The driving module includes a reset voltage output terminal, and the reset voltage output terminal is electrically connected to the reset voltage lead; The driving module is used to provide a reset voltage signal through the reset voltage output terminal; The reset voltage lead is electrically connected to the first reset voltage line portion.

6. The driving backplane according to claim 1, wherein: Also included are a plurality of control voltage lines; the control voltage lines include a first control voltage line portion extending along a first direction; the plurality of conductive pads include a fourth type of conductive pad for transmitting a control voltage; The fourth type conductive pad is electrically connected to the control voltage line.

7. The driving backplane according to claim 6, wherein: The control voltage line further includes a second control voltage line portion extending along a second direction; the first control voltage line portion is electrically connected to the second control voltage line portion; The first control voltage line portion and the second control voltage line portion are disposed in different conductive layers.

8. The driving backplane according to claim 6, wherein: The line width of the first control voltage line portion is greater than the line width of the data line.

9. The driving backplane according to claim 7, wherein: It also includes a driving module disposed on the substrate; the driving module includes a first control voltage output terminal, and the driving module is used to provide a control voltage through the first control voltage output terminal; The first control voltage output terminal is electrically connected to at least one first control voltage line portion.

10. The driving backplane according to claim 9, wherein: The driving module further includes a second control voltage output terminal, and the driving module is configured to provide a control voltage through the second control voltage output terminal; The second control voltage output terminal is electrically connected to a first end portion of a second control voltage line portion closest to the driving module, and the first control voltage output terminal is electrically connected to a second end portion of the second control voltage line portion closest to the driving module.

11. The driving backplane according to any one of claims 1 to 10, wherein: Also included are a plurality of drive control lines; the plurality of conductive pads include a fifth type of conductive pad for transmitting a drive control signal; The driving control line extends along the second direction; The fifth type of conductive pad is electrically connected to the driving control line.

12. The driving backplane according to claim 2, wherein: The data line and the gate line are arranged in different conductive layers; The first voltage line portion and the gate line are provided in different conductive layers; The second voltage line portion and the data line are arranged in different conductive layers; The data line is provided in the same layer as the first voltage line portion, and the gate line is provided in the same layer as the second voltage line portion.

13. The driving backplane according to claim 7, wherein: The first control voltage line portion and the gate line are provided in different conductive layers; the second control voltage line portion and the data line are provided in different conductive layers; The data line is provided in the same layer as the first control voltage line portion, and the gate line is provided in the same layer as the second control voltage line portion.

14. The driving backplane according to claim 1, wherein: The orthographic projection of the data line on the base substrate is arranged between the orthographic projections of the two first voltage line portions on the base substrate.

15. The driving backplane according to claim 6, wherein: The orthographic projection of the data line on the base substrate is disposed between the orthographic projection of the first control voltage line portion on the base substrate and the orthographic projection of at least one first voltage line portion on the base substrate.

16. The driving backplane according to claim 6, wherein: The orthographic projection of the first voltage line portion on the base substrate does not overlap with the orthographic projection of the data line on the base substrate; An orthographic projection of the first control voltage line portion on the base substrate does not overlap with an orthographic projection of the data line on the base substrate.

17. The driver backplane according to any one of claims 1 to 10, wherein: It also includes a gate driving unit disposed on the base substrate; The gate driving unit is used to generate a multi-level gate driving signal.

18. The driver backplane according to any one of claims 1 to 10, wherein: Also included is a gate drive module, the gate drive module including a plurality of gate drive circuits connected in cascade to each other; the gate drive circuit is used to generate and output corresponding level gate drive signals through its output terminal; The output end of the gate driving circuit is electrically connected to the input end of the adjacent next-stage gate driving circuit, and is used to provide an input signal to the adjacent next-stage gate driving circuit.

19. A display substrate comprising the driving backplane according to any one of claims 1 to 18.

20. The display substrate according to claim 19, wherein The device comprises a plurality of light-emitting components disposed on the backplane; the light-emitting components include a substrate, and at least one pixel circuit disposed on the substrate, the pixel circuit including a light-emitting unit and a pixel driving circuit for driving the light-emitting unit; the at least one pixel circuit includes a first pixel circuit; The first pixel circuit receives a data voltage through a first first-type conductive pad; In the second direction, the first first-type conducting pad is disposed between the second-type conducting pad and at least one third-type conducting pad.

21. The display substrate according to claim 20, wherein: The at least one pixel circuit further includes a second pixel circuit; the second pixel circuit receives a data voltage through a second first-type conductive pad; In the second direction, the second first-type conducting pad is disposed between the second-type conducting pad and at least one third-type conducting pad.

22. The display substrate according to claim 21, wherein The at least one pixel circuit further includes a third pixel circuit; the second pixel circuit receives a data voltage through a third first-type conductive pad; The third first-type conducting pad and at least one third-type conducting pad are arranged along the first direction, or the third first-type conducting pad and the second-type conducting pad are arranged along the first direction.

23. The display substrate according to claim 20, wherein: Along the second direction, a first third-category conducting pad and a second third-category conducting pad are disposed on two opposite sides of the first first-category conducting pad.

24. The display substrate according to claim 19, wherein The device comprises a plurality of light-emitting components disposed on the back panel; the light-emitting components comprise a substrate, and at least one pixel circuit disposed on the substrate, the pixel circuit comprising a light-emitting unit and a pixel driving circuit for driving the light-emitting unit; The pixel driving circuit includes a driving transistor and a data writing circuit; The gate of the driving transistor is electrically connected to the control node, the first electrode of the driving transistor is electrically connected to the first node, and the second electrode of the driving transistor is electrically connected to the second node. The driving transistor is used to generate a driving current under the control of the potential of the control node; The control end of the data writing circuit is electrically connected to the gate line, the first end of the data writing circuit is electrically connected to the data line, and the second end of the data writing circuit is electrically connected to the first node. The data writing circuit is used to control the display data voltage provided by the data line to be written into the first node under the control of the gate drive signal provided by the gate line. point.

25. The display substrate according to claim 24, wherein: The pixel driving circuit further includes a first light emitting control circuit; A control terminal of the first light-emitting control circuit is electrically connected to a light-emitting control line, a first terminal of the first light-emitting control circuit is electrically connected to a power supply voltage line, and a second terminal of the first light-emitting control circuit is electrically connected to the first node, wherein the first light-emitting control circuit is configured to control communication between the power supply voltage line and the first node under control of a light-emitting control signal provided by the light-emitting control line; The power voltage line is electrically connected to the first third-type conductive pad.

26. The display substrate according to claim 25, wherein: The pixel driving circuit further includes a second light emitting control circuit and a first control circuit; The second light-emitting control circuit is electrically connected to the first control terminal, the second node, and the first electrode of the light-emitting unit, respectively, and is configured to control the second node to be connected to the first electrode of the light-emitting unit under the control of the potential of the first control terminal; the second electrode of the light-emitting unit is electrically connected to the first voltage line; and the first voltage line is electrically connected to the second third-category conductive pad; The first control circuit is electrically connected to the first control terminal, the second control terminal, and the data line, respectively. The first input terminal of the first control circuit is electrically connected to the light-emitting control line, the second input terminal of the first control circuit is electrically connected to the control voltage line, and the control terminal of the first control circuit is electrically connected to the reset control line. The first control circuit is configured to write a control data voltage provided by the data line into the second control terminal under the control of a reset control signal provided by the reset control line, maintain the potential of the second control terminal, and control the connection between the first control terminal and the light-emitting control line or the control voltage line under the control of the potential of the second control terminal. The light emitting control line is electrically connected to the first fifth type conductive pad, the reset control line is electrically connected to the second fifth type conductive pad, and the control voltage line is electrically connected to the fourth type conductive pad.

27. The display substrate according to claim 26, wherein: The light-emitting component includes a first pixel circuit, a second pixel circuit, and a third pixel circuit; the plurality of conductive pads include a first first-category conductive pad, a second first-category conductive pad, a third first-category conductive pad, a second second-category conductive pad, a first third-category conductive pad, a second third-category conductive pad, a fourth-category conductive pad, a first fifth-category conductive pad, and a second fifth-category conductive pad; A first end of the data writing circuit in the first pixel circuit is electrically connected to a first first-type conductive pad, a first end of the data writing circuit in the second pixel circuit is electrically connected to a second first-type conductive pad, and a first end of the data writing circuit in the third pixel circuit is electrically connected to a third first-type conductive pad; The control end of the data writing circuit in the first pixel circuit, the control end of the data writing circuit in the second pixel circuit, and the control end of the data writing circuit in the third pixel circuit are all electrically connected to the second type of conductive pad; The first end of the first light emitting control circuit in the first pixel circuit, the first end of the first light emitting control circuit in the second pixel circuit, and the first end of the first light emitting control circuit in the third pixel circuit are all electrically connected to a first third-type conductive pad; The second electrode of the light-emitting element in the first pixel circuit and the second electrode of the light-emitting element in the second pixel circuit and the second electrode of the light-emitting element in the third pixel circuit are electrically connected to the second third-type conductive pad; The second input terminal of the first control circuit in the first pixel circuit, the second input terminal of the first control circuit in the second pixel circuit, and the second input terminal of the first control circuit in the third pixel circuit are all electrically connected to the fourth type of conductive pad; The control end of the first light emitting control circuit in the first pixel circuit, the control end of the first light emitting control circuit in the second pixel circuit, and the control end of the first light emitting control circuit in the third pixel circuit are all electrically connected to the first fifth-category conductive pad; The control end of the first light emitting control circuit in the first pixel circuit, the control end of the first light emitting control circuit in the second pixel circuit, and the control end of the first light emitting control circuit in the third pixel circuit are all electrically connected to the first fifth-category conductive pad; The control end of the first control circuit in the first pixel circuit, the control end of the first control circuit in the second pixel circuit, and the control end of the first control circuit in the third pixel circuit are all electrically connected to the second fifth-category conducting pad.

28. The display substrate according to any one of claims 20 to 27, wherein: comprising a light emitting component disposed on the driving backplane and electrically connected to the conductive pad; The light emitting component comprises: a light-emitting unit, the light-emitting unit comprising: a first electrode, a second electrode, and a light-emitting portion electrically connected to the first electrode and the second electrode respectively; A driving unit having the pixel driving circuit, the driving unit comprising: a third electrode, a fourth electrode, and a driving circuit, the third electrode and the fourth electrode being located on a side of the driving unit facing the light-emitting unit, the third electrode and the fourth electrode being electrically connected to the driving circuit respectively, the third electrode being electrically connected to the first electrode, and the fourth electrode being electrically connected to the second electrode; The first substrate is located on a side of the light emitting unit away from the driving unit.

29. The display substrate according to claim 28, wherein: The light emitting assembly includes a plurality of light emitting units; The plurality of light emitting units include a first color light emitting unit, a second color light emitting unit and a third color light emitting unit; The first color, the second color and the third color are different from each other.

30. The display substrate according to claim 29, wherein The light-emitting unit includes a color filter layer, a color conversion layer, and a light-emitting layer stacked in sequence in a direction away from the first substrate; the light-emitting layer emits blue light; The light-emitting layer includes a first semiconductor layer, a multi-quantum well layer and a second semiconductor layer that are stacked, wherein the first semiconductor layer is electrically connected to the first electrode, the second semiconductor layer is electrically connected to the second electrode, and the light-emitting layer includes a first light-emitting portion, a second light-emitting portion and a third light-emitting portion.

31. The display substrate according to claim 28, wherein The driving circuit includes a plurality of thin film transistors, and each of the thin film transistors includes a gate, a source, and a drain.

32. The display substrate according to claim 31, wherein The driving unit further includes a substrate; the driving circuit includes a buffer layer, an active layer, a first gate insulating layer, a first gate layer, an interlayer dielectric layer, a source and drain layer, and a planar layer, which are stacked in sequence and located on one side of the substrate; the third electrode and the fourth electrode are located on a side of the planar layer away from the substrate; The active layer includes a plurality of active patterns corresponding to the plurality of thin film transistors, and each of the active patterns includes a source region, a drain region, and a channel region; The source electrode and the drain electrode of the thin film transistor are located in the source-drain electrode layer, the source electrode of the thin film transistor is connected to the source region, and the drain electrode of the thin film transistor is connected to the drain region; The first gate layer includes a plurality of gate patterns corresponding to the plurality of thin film transistors, and the channel region is an overlapping region of an orthographic projection of the gate pattern on the substrate and an orthographic projection of the active pattern on the substrate.

33. The display substrate according to claim 31 or 32, wherein: The pixel driving circuit includes a driving transistor and a data writing circuit; at least one of the driving transistor and the data writing circuit includes the thin film transistor.

34. The display substrate according to claim 33, wherein: The pixel driving circuit further includes a first light emitting control circuit, a second light emitting control circuit and a first control circuit; At least one of the first light emission control circuit, the second light emission control circuit, and the first control circuit includes the thin film transistor.

35. The display substrate according to claim 28, wherein The light emitting component further includes a plurality of pins; The plurality of pins are located on a side of the driving circuit away from the light-emitting unit and are electrically connected to the driving circuit. The plurality of pins are connected to the plurality of conductive pads in one conductive pad group in a one-to-one correspondence.

36. The display substrate according to claim 35, wherein: The driving unit further includes a substrate and a connection structure, wherein the substrate has a connection via hole, the connection structure is located in the connection via hole, and the driving circuit is located on one side of the substrate; The pin is located on a side of the substrate away from the driving circuit, and the pin is in contact with the connection structure. The pin and the driving circuit are connected via the connection structure.

37. The display substrate according to claim 35, wherein: The driving circuit includes a plurality of thin film transistors, each of which includes a gate, a source and a drain; One of the plurality of pins is connected to a source electrode of a thin film transistor among the plurality of thin film transistors, and is used for providing the driving circuit with a data driving signal transmitted from a display backplane in a display panel.

38. A display device comprising the display substrate according to any one of claims 19 to 37.

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