Array substrate, display panel, and display device

Abstract

An array substrate, a display panel, and a display device. The array substrate comprises: a plurality of first active patterns; a plurality of first metal wires; and a plurality of conductive portions. Each conductive portion comprises: a first conductive portion and a second conductive portion that are distributed in a first direction; adjacent first metal wires on two sides of each conductive portion comprise a first sub-metal wire and a second sub-metal wire, wherein the first sub-metal wire is electrically connected to a second portion, and a first portion is electrically connected to a first electrode by means of the corresponding conductive portion; and at least the distance between the orthographic projection of the second conductive portion on a substrate and the orthographic projection of the first sub-metal wire on the substrate is greater than the distance between the orthographic projection of the second conductive portion on the substrate and the orthographic projection of the second sub-metal wire on the substrate.

Description

Array substrate, display panel and display device Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to an array substrate, a display panel, and a display device. Background Technology

[0002] Virtual reality (VR) technology is a new technology that seamlessly integrates real-world and virtual-world information. The most significant characteristic of VR display products compared to conventional displays is their ultra-high resolution. Currently, the optimal solution for ultra-high PPI is Liquid Crystal Display (LCD) technology because the pixel area circuit in an LCD display structure has only one switching transistor (Thin Film Transistor, TFT), which is highly conducive to achieving high PPI.

[0003] Summary of the Invention

[0004] This disclosure provides an array substrate, a display panel, and a display device. The array substrate includes:

[0005] Substrate;

[0006] A first active layer, located on one side of the substrate, includes: a plurality of first active patterns; the first active patterns include: a first portion and a second portion distributed along a first direction;

[0007] The first metal layer includes: a plurality of first metal lines; the second part, in the portion projected onto the substrate, overlaps with the portion of the first metal lines projected onto the substrate.

[0008] The second metal layer includes: a plurality of second metal lines extending along a second direction;

[0009] A first conductive layer includes: a plurality of conductive portions located in the display area; at least one of the plurality of conductive portions has its orthographic projection on the substrate located between the orthographic projections of adjacent first metal lines on the substrate; the conductive portions include: a first conductive portion and a second conductive portion distributed along the first direction; the orthographic projections of the first conductive portion on the substrate overlap with the orthographic projections of the first portion on the substrate, and the orthographic projections of the second conductive portion on the substrate overlap with the orthographic projections of the second portion; the first conductive portion and the second conductive portion have different extending directions;

[0010] The second conductive layer includes: a plurality of first electrodes located in the display area;

[0011] The first metal lines adjacent to each other on both sides of the conductive portion include: a first sub-metal line and a second sub-metal line; wherein the first sub-metal line is electrically connected to the second portion; the first portion is electrically connected to the first electrode through the conductive portion; at least the distance between the orthographic projection of the second conductive portion on the substrate and the orthographic projection of the first sub-metal line on the substrate is greater than the distance between the orthographic projection of the second sub-metal line on the substrate.

[0012] In one possible implementation, the second conductive portion has a first outer edge toward the first sub-metal line and a second outer edge toward the second sub-metal line;

[0013] The distance between the projection of the first outer edge onto the substrate and the projection of the first sub-metal trace onto the substrate is greater than the distance between the projection of the second outer edge onto the substrate and the projection of the second sub-metal trace onto the substrate.

[0014] In one possible implementation, the first metal wire includes: a first sub-metal portion and a second sub-metal portion arranged alternately along the first direction; the first sub-metal portion and the second sub-metal portion extend in different directions.

[0015] The first conductive portion extends along the extending direction of the second sub-metal portion, and the second conductive portion extends along the extending direction of the first sub-metal portion.

[0016] In one possible implementation, the second conductive portion has a first outer edge toward the first sub-metal line and a second outer edge toward the second sub-metal line; the extension of the first outer edge intersects the extension of the second outer edge.

[0017] The distance between the orthographic projection of the first outer edge on the substrate and the orthographic projection of the first sub-metal trace on the substrate is greater than the distance between the orthographic projection of the second outer edge on the substrate and the orthographic projection of the second sub-metal trace on the substrate.

[0018] In one possible implementation, the first metal wire includes: a first sub-metal portion and a second sub-metal portion arranged alternately along the first direction; the first sub-metal portion and the second sub-metal portion extend in different directions.

[0019] The first outer edge extends along the first direction; the second outer edge extends in the same direction as the first sub-metal portion.

[0020] In one possible implementation, the second conductive portion has a first outer edge toward the first sub-metal line and a second outer edge toward the second sub-metal line;

[0021] The first outer edge includes: a first sub-edge portion and a second sub-edge portion; the second sub-edge portion is located on the side of the first sub-edge portion away from the first conductive portion, and the second sub-edge portion is located on the side of the extension line of the first sub-edge portion toward the first sub-metal trace;

[0022] The distance between the orthographic projection of the second sub-edge onto the substrate and the orthographic projection of the first sub-metal trace onto the substrate is greater than the distance between the orthographic projection of the second outer edge onto the substrate and the orthographic projection of the second sub-metal trace onto the substrate.

[0023] In one possible implementation, the first metal wire includes: a first sub-metal portion and a second sub-metal portion arranged alternately along the first direction; the first sub-metal portion and the second sub-metal portion extend in different directions.

[0024] The second sub-edge extends along the extension direction of the first sub-metal portion.

[0025] In one possible implementation, the first sub-edge extends along the extending direction of the second sub-metal portion; the second outer edge extends along the extending direction of the first sub-metal portion.

[0026] In one possible implementation, a first bend is provided between the first sub-metal portion and the second sub-metal portion; the first outer edge has a second bend.

[0027] The second bending portion is projected onto the substrate in the region between the projection of the first metal edge onto the substrate and the projection of the first connecting line onto the substrate, wherein the first metal edge is the outer edge of the second metal wire toward the first conductive portion, and the first connecting line is the connecting line of the first bending portions of two adjacent first metal wires.

[0028] In one possible implementation, the array substrate further includes: a third metal layer located on the side of the first active layer facing the substrate; the third metal layer includes: a plurality of third metal lines extending along the second direction; the orthographic projection of the third metal lines on the substrate covers the orthographic projection of the second metal lines on the substrate;

[0029] The first bent portion is projected onto the substrate in the region between the projection of the first metal edge onto the substrate and the projection of the second metal edge onto the substrate, wherein the second metal edge is the outer edge of the third metal line toward the first conductive portion.

[0030] In one possible implementation, the first outer edge has a second bend;

[0031] The orthographic projection of the second bent portion onto the substrate overlaps with the orthographic projection of the first metal edge onto the substrate, wherein the first metal edge is the outer edge of the second metal wire facing the first conductive portion.

[0032] In one possible implementation, the first conductive portion is located between two adjacent first sub-metal portions in the second direction; the second conductive portion is located between two adjacent second sub-metal portions in the second direction; and the extension direction of the first conductive portion is the same as the extension direction of the first sub-metal portion.

[0033] In one possible implementation, the first electrode includes: a first electrode portion and a second electrode portion distributed along the first direction; the extending direction of the first electrode portion is the same as the extending direction of the first sub-metal portion, and the extending direction of the second electrode portion is the same as the extending direction of the second sub-metal portion.

[0034] In one possible implementation, the orthographic projection of the first electrode portion onto the substrate overlaps with the orthographic projection of the second conductive portion onto the substrate, and they are electrically connected at the overlapping location.

[0035] In one possible implementation, the first conductive portion has a third outer edge toward the first sub-metal line and a fourth outer edge toward the second sub-metal line; the third edge is parallel to the fourth outer edge.

[0036] In one possible implementation, the distance between the projection of the third outer edge onto the substrate and the projection of the first sub-metal trace onto the substrate is greater than the distance between the projection of the fourth outer edge onto the substrate and the projection of the second sub-metal trace onto the substrate.

[0037] In one possible implementation, the distance between the projection of the third outer edge onto the substrate and the projection of the first sub-metal trace onto the substrate is equal to the distance between the projection of the fourth outer edge onto the substrate and the projection of the second sub-metal trace onto the substrate.

[0038] In one possible implementation, the second conductive portion has a fifth outer edge extending along the second direction, the fifth outer edge being located on the side of the second metal wire away from the first conductive portion.

[0039] In one possible implementation, the second conductive portion has a fifth outer edge extending along a second direction, and the orthographic projection of the second metal line onto the substrate covers the orthographic projection of the fifth outer edge onto the substrate.

[0040] In one possible implementation, the second metal wire has a sixth outer edge extending along the second direction;

[0041] The orthographic projection of the sixth outer edge onto the substrate coincides with the orthographic projection of the fifth outer edge onto the substrate.

[0042] In one possible implementation, the second part includes: a first sub-part and a second sub-part; the first sub-part extends along the second direction, and the orthographic projection of the first sub-part on the substrate overlaps with the orthographic projection of the first metal line on the substrate; the second sub-part connects the first sub-part and the first part.

[0043] The plurality of first active patterns include: a first active pattern row and a second active pattern row; the first active pattern row and the second active pattern row extend along a second direction and overlap along the first direction;

[0044] Both the first active pattern row and the second active pattern row include multiple first active patterns; and in the first active pattern row, the second sub-part extends along a third direction; in the second active pattern row, the second sub-part extends along a fourth direction, and the third direction intersects with the fourth direction.

[0045] In one possible implementation, in the first active pattern row, the first sub-part and the first part are located on different sides of the second sub-part; in the second active pattern row, the first sub-part and the first part are located on the same side of the second sub-part.

[0046] This disclosure also provides a display panel, which includes the array substrate as described in this disclosure.

[0047] This disclosure also provides a display device, which includes the display panel as described in this disclosure. Attached Figure Description

[0048] Figure 1A is one of the schematic diagrams of crosstalk failure in the display panel;

[0049] Figure 1B is the second schematic diagram of crosstalk failure in the display panel;

[0050] Figure 1C is the third schematic diagram of crosstalk failure in the display panel;

[0051] Figure 1D is the fourth schematic diagram of crosstalk failure in the display panel;

[0052] Figure 2A is one of the top views of the array substrate provided in the embodiments of this disclosure;

[0053] Figure 2B is a schematic diagram of the single film layer of the third metal layer in Figure 2A;

[0054] Figure 2C is a schematic diagram of the first active layer in Figure 2A;

[0055] Figure 2D is a schematic diagram of a single film layer of the second metal layer in Figure 2A;

[0056] Figure 2E is a schematic diagram of the single film layer of the first metal layer in Figure 2A;

[0057] Figure 2F is a schematic diagram of a single film layer of the first conductive layer in Figure 2A;

[0058] Figure 2G is a schematic diagram of a single film layer of the second conductive layer in Figure 2A;

[0059] Figure 3 is a cross-sectional view of the dashed line A1A2 in Figure 2A;

[0060] Figure 4A is a schematic diagram of the self-pixel electrode and associated structure provided in an embodiment of this disclosure;

[0061] Figure 4B is a schematic diagram of the first metal wire M11 and its associated structure provided in an embodiment of this disclosure;

[0062] Figure 4C is a schematic diagram of adjacent pixel electrodes and associated structures provided in an embodiment of this disclosure;

[0063] Figure 4D shows the first coupling capacitor C corresponding to Figure 4A. dp1 A schematic diagram of its structure;

[0064] Figure 4E shows the second coupling capacitor C corresponding to Figure 4A. dp2 A schematic diagram of its structure;

[0065] Figure 5 is a second schematic diagram of the array substrate provided in an embodiment of this disclosure;

[0066] Figure 6A is a third schematic diagram of the array substrate provided in the embodiments of this disclosure;

[0067] Figure 6B is a schematic diagram of a single film layer of the first conductive layer in Figure 6A;

[0068] Figure 6C is a fourth schematic diagram of the array substrate provided in the embodiments of this disclosure;

[0069] Figure 7 is a fifth schematic diagram of the array substrate provided in the embodiments of this disclosure;

[0070] Figure 8 is a schematic diagram of the array substrate provided in the embodiments of this disclosure. Detailed Implementation

[0071] Those skilled in the art will readily understand that the methods and content can be transformed into one or more forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited solely to the content described in the following embodiments. Unless otherwise specified, the embodiments and features described in this disclosure can be arbitrarily combined with each other.

[0072] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0073] The ordinal numbers such as "first," "second," and "third" used in this specification are used to avoid confusion among the constituent elements, not to limit the quantity. The term "multiple" in this disclosure can include two or more quantities.

[0074] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which the constituent elements are described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0075] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0076] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on the "elements that have a certain electrical function," as long as they enable the transmission of electrical signals between the connected components. Examples of "elements that have a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with one or more functions.

[0077] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain terminal, drain region, or drain) and the source electrode (source terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0078] Furthermore, the gate of a transistor can be referred to as the control electrode. In cases where transistors with opposite polarities are used, or where the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0079] In this specification, "parallel" refers to a state in which two straight lines form an angle of -10° or more and less than 10°, and therefore can include a state in which the angle is -5° or more and less than 5°. Similarly, "perpendicular" refers to a state in which two straight lines form an angle of 80° or more and less than 100°, and therefore can include a state in which the angle is 85° or more and less than 95°.

[0080] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0081] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0082] In this specification, "approximately" and "roughly" refer to situations where there are no strict limits and the process and measurement errors are allowed. In this specification, "roughly the same" can mean that the values ​​differ by no more than 10%.

[0083] In virtual reality (VR) head-mounted display products, the coupling capacitance Cdp1 between the data line and the electrically connected pixel is 1.322 Ff; the coupling capacitance Cdp2 between the data line and the adjacent pixel is 1.173 Ff; the difference in coupling capacitance between Cdp1 and Cdp2 (i.e., The difference between the two is 11.27%. In the column inversion structure, the coupling capacitance of the pixel electrode to the two adjacent data lines (with opposite polarities of the loaded data signals) is significantly different. The voltage of the pixel electrode is prone to deviate from the level, which can easily lead to crosstalk problems in the vertical direction.

[0084] Specifically, as shown in Figure 1A, there is a first coupling capacitance C between the data line and its own pixel electrode (the pixel electrode can be understood as the pixel electrode electrically connected to the data line) inside the pixel. dp1 And the second coupling capacitor C of the adjacent pixel electrode (the pixel electrode not electrically connected to the data line). dp2 When C dp1 >C dp2 Furthermore, when the differences are significant, the common crosstalk problem occurs. For example, when displaying a screen with a white center and black edges as shown in Figure 1B, the screen will exhibit a phenomenon where the top is brighter and the bottom is darker, with the center as the boundary, as shown in Figure 1C. Specifically, combining Figures 1B, 1C, and 1D, pixels A1 and A2 are two pixels at different positions on the same data line, pixels B1 and B2 are two pixels at different positions on the same data line, pixels B1 and A1 are two pixels in the same row on adjacent data lines, and pixels B2 and A2 are two pixels in the same row on adjacent data lines; when the pixel itself is coupled (the first coupling capacitance C...), the crosstalk effect occurs. dp1 ) and mutual coupling effect (second coupling capacitance C) dp2 When the voltages are inconsistent, the charging voltage of pixel A1 is the positive voltage of L127, which will be pulled up by the voltage of L255 in the middle of the screen, thus increasing the voltage difference between pixel A1 and the common electrode voltage (Vcom), resulting in a bright display. The charging voltage of pixel A2 is still the negative voltage of the previous frame, which will be pulled up by the voltage of L255 in the middle of the screen, thus decreasing the voltage difference between pixel A2 and the common electrode voltage (Vcom), resulting in a dark display. This is the defective phenomenon of the top being bright and the bottom being dark in the Crosstalk screen.

[0085] In view of this, referring to Figures 2A-2G and 3, wherein Figure 2B is a schematic diagram of a single film layer of the third metal layer in Figure 2A, Figure 2C is a schematic diagram of a single film layer of the first active layer in Figure 2A, Figure 2D is a schematic diagram of a single film layer of the second metal layer in Figure 2A, Figure 2E is a schematic diagram of a single film layer of the first metal layer in Figure 2A, Figure 2F is a schematic diagram of a single film layer of the first conductive layer in Figure 2A, Figure 2G is a schematic diagram of a single film layer of the second conductive layer in Figure 2A, Figure 3 is a cross-sectional schematic diagram at the dashed line A1A2 in Figure 2A, and Figure 4A is a schematic diagram of only a portion of the film layers in Figure 2A, this disclosure provides an array substrate, comprising:

[0086] Substrate 11;

[0087] The first active layer C1 is located on one side of the substrate 11 and includes: a plurality of first active patterns C11; the first active pattern C11 includes: a first part CA and a second part CB distributed along the first direction X, wherein the second part CB extends in a different direction than the first part CA.

[0088] The first metal layer M1 includes: multiple first metal lines M11; a first part CA projected onto the substrate 11, located between the projected projections of adjacent first metal lines M11 onto the substrate 11; and a second part CB projected onto the substrate 11, overlapping with the projected projections of the first metal lines M11 onto the substrate 11. Specifically, the first metal lines M11 can be data lines; specifically, the display area AA can have multiple first transistors; the second part CB, at the position overlapping with the first metal lines M11, can serve as the first electrode of the first transistor; the second part CB, at the position overlapping with the first metal lines M11, can be conductive, realizing the electrical connection between the first transistor and the data lines.

[0089] The second metal layer M2 includes: a plurality of second metal lines M21 extending along the second direction Y;

[0090] The first conductive layer D1 includes: a plurality of conductive portions D11 located in the display area AA; at least one of the conductive portions D11 has its orthographic projection on the substrate 11 located between the orthographic projections of adjacent first metal lines M11 on the substrate 11; the conductive portion D11 includes: a first conductive portion DA and a second conductive portion DB distributed along the first direction X; the orthographic projection of the first conductive portion DA on the substrate 11 overlaps with the orthographic projection of the first portion CA on the substrate 11, and the orthographic projections of the second conductive portion DB and the second portion CB on the substrate 11 overlap; the first conductive portion DA and the second conductive portion DB have different extension directions; specifically, the first conductive layer D1 can be a transparent conductive layer, and the conductive portion D11 can serve as the second electrode of a first transistor, connecting the first active pattern C11 with the first electrode D21; specifically, the orthographic projection shape of the conductive portion D11 on the substrate 11 can be bent, and the maximum length of the conductive portion D11 in the first direction X can be greater than its length in the second direction Y.

[0091] The second conductive layer D2 includes: a plurality of first electrodes D21 located in the display area AA; specifically, the second conductive layer D2 can be a transparent conductive layer, and the material of the second conductive layer D2 can be the same as the material of the first conductive layer D1; specifically, the first electrodes D21 can be pixel electrodes; specifically, the orthographic projection of the first electrode D21 onto the substrate 11 can be located between the orthographic projections of adjacent first metal lines M11 onto the substrate 11; specifically, the orthographic projection shape of the first electrode D21 onto the substrate 11 can be bent; the length of the first electrode D21 in the first direction X can be greater than its length in the second direction Y.

[0092] The first metal lines M11 adjacent to both sides of the conductive part D11 include: a first sub-metal line MA and a second sub-metal line MB; wherein the first sub-metal line MA is electrically connected to the second part CB, that is, the first metal line M11 electrically connected to the second part CB is used as the first sub-metal line MA, and the other first metal line M11 is used as the second metal line MB; the first part CA is electrically connected to the first electrode D21 through the conductive part D11; at least the distance a between the orthographic projection of the second conductive part DB on the substrate 11 and the orthographic projection of the first sub-metal line MA on the substrate 11 is greater than the distance b between the orthographic projection of the second sub-metal line MB on the substrate 11.

[0093] In this embodiment of the present disclosure, at least the distance a between the orthogonal projection of the second conductive part DB on the substrate 11 and the orthogonal projection of the first sub-metal line MA on the substrate 11 is greater than the distance b between the orthogonal projection of the second sub-metal line MB on the substrate 11. This can increase the distance between the second conductive part DB and the first sub-metal line MA, thereby reducing the capacitance between the second conductive part DB and the first sub-metal line MA, and increasing the capacitance between the second sub-metal line MB, thereby reducing the difference between the two and improving the vertical crosstalk problem.

[0094] The first metal line M11 and its associated structure can form a first coupling capacitor Cdp1 with its own pixel electrode and associated structure; the first metal line M11 and its associated structure can form a second coupling capacitor Cdp2 with the adjacent pixel electrode and associated structure; wherein, the own pixel electrode and associated structure can be the area shown in the dashed box in Figure 4A, specifically including: a first electrode D21 (shown in the dashed box S1 in Figure 4A), and a conductive part D11 connected to the first electrode D21 through the second via K2 (shown in the dashed box S2 in Figure 4A), and the conductive part D11 connected to the first via K2 through the first via K2. The first active pattern C11 connected to the second metal line M21 is located on the side of the second metal line M21 away from the second metal line M21 in the first direction X (as shown in the dashed box S3 in Figure 4A, that is, the part of the first active pattern C11 located below the second metal line M21. Since the time each row of pixels is on is very short during the display frame, it can be considered that the gate of the first transistor in the pixel is off most of the time, and the part of the first active pattern C11 covered by the second metal line M21 can be considered as an insulator); the first metal line M11 and the associated structure can be shown in the dashed box in Figure 4B. The region can specifically include: the first metal line M11 (as shown in the dashed box S4 in Figure 4B), and the portion of the first active pattern C11 electrically connected to the first metal line M11 through the third via K3 located on the side of the second metal line M21 in the first direction X, closer to the second metal line M21 (as shown in the dashed box S5 in Figure 4B, that is, the portion of the first active pattern C11 located on the upper side of the second metal line M21); the adjacent pixel electrode and associated structure can be the region shown in the dashed box in Figure 4C, specifically including: the adjacent first electrode D21 (as shown in the dashed box S6 in Figure 4C). And the adjacent conductive part D11 connected to the adjacent first electrode D21 through the second via K2 (as shown in the dashed box S7 in FIG4C), and the adjacent first active pattern C11 connected to the adjacent conductive part D11 through the first via K1 located on the side of the second metal line M21 away from the second metal line M21 in the first direction X (as shown in the dashed box S8 in FIG4C, that is, the part of the first active pattern C11 located on the lower side of the second metal line M21); the configuration of the first coupling capacitor Cdp1 can be as shown in FIG4D, and the configuration of the second coupling capacitor Cdp2 can be as shown in FIG4E.

[0095] According to the inventors' research, the main reason for the difference between the first coupling capacitor Cdp1 and the second coupling capacitor Cdp2 is the asymmetry in the design of the first active pattern C11. Furthermore, because the film between the first active layer C1 and the first conductive layer D1 is thinner, and the first active pattern C11 and the conductive portion D11 in the first coupling capacitor Cdp1 overlap vertically (as shown in the thick solid frame S in Figure 4D), the capacitance directly opposite is larger. However, the second coupling capacitor Cdp2 lacks this overlap, thus creating a difference in capacitance between the first coupling capacitor Cdp1 and the second coupling capacitor Cdp2. The main difference lies in the fact that, although the overlap area between the first active pattern C11 and the first electrode D21 in the first coupling capacitor Cdp1 is larger than the overlap area between the first active pattern C11 and the conductive part D11, the overlap capacitance is very small due to the thicker film layer between the first active pattern C11 and the first electrode D21, and the difference can be ignored. Furthermore, since there is only one film layer between the first metal line M11 and the conductive part D11, the lateral capacitance formed by the first metal line M11 and the conductive part D11 dominates in the second coupling capacitor Cdp2.

[0096] In this embodiment, by making the distance a between the orthographic projection of the second conductive part DB on the substrate 11 and the orthographic projection of the first sub-metal line MA on the substrate 11 greater than the distance b between the orthographic projection of the second sub-metal line MB on the substrate 11, the lateral capacitance between the first metal line M11 and the second conductive part DB can be increased, thereby increasing the second coupling capacitance Cdp2. Since the overlapping capacitance of the first active pattern C11 and the conductive part D11 (the area shown by the thick solid frame S in Figure 4D) occupies the main part in the first coupling capacitance Cdp1, the distance between the conductive part D11 and the second sub-metal line MB is reduced, which will not have a significant impact on the first coupling capacitance Cdp1, thereby reducing the difference between the second coupling capacitance Cdp2 and the first coupling capacitance Cdp1, thus improving the vertical crosstalk problem.

[0097] It should be noted that the distance 'a' between the orthographic projection of the second conductive part DB onto the substrate 11 and the orthographic projection of the first sub-metal line MA onto the substrate 11 can be the minimum distance 'a' between the orthographic projections of the second conductive part DB onto the substrate 11 and the first sub-metal line MA onto the substrate 11. Due to the manufacturing process, the outer edge of the orthographic projection of the second conductive part DB onto the substrate 11 may have some unevenness. Therefore, the distance 'a' between the orthographic projection of the second conductive part DB onto the substrate 11 and the orthographic projection of the first sub-metal line MA onto the substrate 11 can be the average distance between the orthographic projections of the second conductive part DB onto the substrate 11 and the first sub-metal line MA onto the substrate 11. Similarly, in the second conductive part DB... When the outer edge of the orthographic projection of the substrate 11 is straight, the distance b between the orthographic projection of the second conductive part DB on the substrate 11 and the orthographic projection of the second sub-metal line MB on the substrate 11 can be the minimum distance b between the orthographic projection of the second conductive part DB on the substrate 11 and the orthographic projection of the second sub-metal line MB on the substrate 11. When the outer edge of the orthographic projection of the second conductive part DB on the substrate 11 is uneven due to the manufacturing process, the distance b between the orthographic projection of the second conductive part DB on the substrate 11 and the orthographic projection of the second sub-metal line MB on the substrate 11 can be the average distance between the orthographic projection of the second conductive part DB on the substrate 11 and the orthographic projection of the second sub-metal line MB on the substrate 11.

[0098] It should be noted that the first sub-metal line MA is electrically connected to the second part CB, which can be understood as the first sub-metal line MA being electrically connected to the second part CB through the first transistor.

[0099] In one possible implementation, referring to FIG2A, the second conductive portion DB has a first outer edge w1 facing the first sub-metal line MA and a second outer edge w2 facing the second sub-metal line MB; the distance a between the orthographic projection of the first outer edge w1 onto the substrate 11 and the orthographic projection of the first sub-metal line MA onto the substrate 11 is greater than the distance b between the orthographic projection of the second outer edge w2 onto the substrate 11 and the orthographic projection of the second sub-metal line MB onto the substrate 11.

[0100] In one possible implementation, referring to FIG2A, the first metal line M11 includes: a first sub-metal portion M1a and a second sub-metal portion M1b arranged alternately along a first direction X; the first sub-metal portion M1a and the second sub-metal portion M1b have different extension directions; the first conductive portion DA extends along the extension direction of the second sub-metal portion M1b, and the second conductive portion DB extends along the extension direction of the first sub-metal portion M1a; specifically, the extension direction of the first conductive portion DA is the same as the extension direction of the second sub-metal portion M1b, and the extension direction of the second conductive portion DB is the same as the extension direction of the first sub-metal portion M1a.

[0101] In one possible implementation, referring to FIG2A, the first outer edge w1 is parallel to the second outer edge w2. In this embodiment of the present disclosure, the conductive portion D11 can be shifted to the right as a whole, thereby making the distance a between the orthographic projection of the second conductive portion DB on the substrate 11 and the orthographic projection of the first sub-metal line MA on the substrate 11 greater than the distance b between the orthographic projection of the second sub-metal line MB on the substrate 11.

[0102] In one possible implementation, the second conductive portion DB, together with the first sub-metal line MA and the second sub-metal line MB, can satisfy the following relationship: 0.05μm≤(ab) / 2≤0.15μm; specifically, the second conductive portion DB, together with the first sub-metal line MA and the second sub-metal line MB, can satisfy the following relationship: 0.06μm≤(ab) / 2≤0.14μm; specifically, the second conductive portion DB, together with the first sub-metal line MA and the second sub-metal line MB, can satisfy the following relationship: 0.07μm≤(ab) / 2≤0.13μm; specifically, the second conductive portion DB, together with the first sub-metal line MA and the second sub-metal line MB, can satisfy the following relationship: 0.08μm≤(ab) / 2≤0.12μm; specifically, the second conductive portion DB, together with the first sub-metal line MA and the second sub-metal line MB, can satisfy the following relationship: 0.05μm≤(ab) / 2≤0.15 ...6μm≤(ab) / 2≤0.14μm; specifically, the second conductive portion DB, together with the first sub-metal line MA and the second sub-metal line MB, can satisfy the following relationship: 0.07μm≤(ab) / 2≤0.13μm; specifically, the second conductive portion DB, together with the first sub-metal line MA and the second sub-metal line MB, can satisfy the following relationship: 0.08μm≤(ab) / 2≤0.12μm; specifically, the second conductive portion DB, together with the first sub-metal line MA and the second sub-metal line MB, can satisfy the following relationship The first sub-metal line MA and the second sub-metal line MB can satisfy the relationship: 0.09μm≤(ab) / 2≤0.11μm; specifically, the second conductive part DB, together with the first sub-metal line MA and the second sub-metal line MB, can satisfy the relationship: (ab) / 2=0.1μm; in this embodiment, after the second conductive part DB is shifted to the right by 0.1μm, the first coupling capacitance Cdp1 between the first metal line M11 and the connected pixel is 1.253Ff; the second coupling capacitance Cdp2 between the first metal line M11 and the adjacent pixel is 1.264Ff; the difference in coupling capacitance between the first coupling capacitance Cdp1 and the second coupling capacitance Cdp2 is 0.87%, which can significantly reduce the coupling effect of the coupling capacitance on the first metal line M11, thereby avoiding the occurrence of vertical crosstalk.

[0103] In one possible implementation, referring to FIG5, the second conductive portion DB has a first outer edge w1 facing the first sub-metal line MA and a second outer edge w2 facing the second sub-metal line MB; the extension line of the first outer edge w1 intersects the extension line of the second outer edge w2; the distance a between the orthographic projection of the first outer edge w1 on the substrate 11 and the orthographic projection of the first sub-metal line MA on the substrate 11 is greater than the distance b between the orthographic projection of the second outer edge w2 on the substrate 11 and the orthographic projection of the second sub-metal line MB on the substrate 11. In this embodiment, the upper end of the conductive part D11 can be straightened, thereby making the distance a between the orthographic projection of the second conductive part DB on the substrate 11 and the orthographic projection of the first sub-metal line MA on the substrate 11 greater than the distance b between the orthographic projection of the second sub-metal line MB on the substrate 11. Specifically, after the upper end of the conductive part D11 is straightened, the first coupling capacitance Cdp1 between the first metal line M11 and the connected pixel is 1.187 Ff; the second coupling capacitance Cdp2 between the first metal line M11 and the adjacent pixel is 1.176 Ff; the difference in coupling capacitance between the first coupling capacitance Cdp1 and the second coupling capacitance Cdp2 is 0.93%, which can significantly reduce the coupling effect of the coupling capacitance on the first metal line M11, thereby avoiding the occurrence of vertical crosstalk.

[0104] In one possible implementation, referring to FIG5, the first metal line M11 includes: a first sub-metal portion M1a and a second sub-metal portion M1b arranged alternately along a first direction; the first sub-metal portion M1a and the second sub-metal portion M1b have different extension directions; a first outer edge w1 extends along the first direction X; and a second outer edge w2 extends along the extension direction of the first sub-metal portion M1a. Specifically, the extension direction of the second outer edge w2 is the same as the extension direction of the first sub-metal portion M1a.

[0105] In one possible implementation, as shown in Figures 6A and 6B, the second conductive portion DB has a first outer edge w1 facing the first sub-metal line MA and a second outer edge w2 facing the second sub-metal line MB; the first outer edge w1 includes a first sub-edge portion w11 and a second sub-edge portion w12; the second sub-edge portion w12 is located on the side of the first sub-edge portion w11 away from the first conductive portion DA, and the second sub-edge portion w12 is located on the side of the extension line of the first sub-edge portion w11 facing the first sub-metal line MA; the distance a between the orthographic projection of the second sub-edge w12 on the substrate 11 and the orthographic projection a of the first sub-metal line MA on the substrate 11 is greater than the distance b between the orthographic projection b of the second outer edge w2 on the substrate 11 and the orthographic projection b of the second sub-metal line MB on the substrate. In this embodiment of the present disclosure, the upper end of the conductive part D11 can be recessed, thereby making the distance a between the orthogonal projection of the second sub-edge w12 on the substrate 11 and the orthogonal projection of the first sub-metal trace MA on the substrate 11 greater than the distance b between the orthogonal projection of the second outer edge w2 on the substrate 11 and the orthogonal projection of the second sub-metal trace MB on the substrate.

[0106] In one possible implementation, referring to Figures 6A and 6B, the second conductive portion DB, the first sub-metal line MA, and the second sub-metal line MB can satisfy the relationship: 0.3μm≤ab≤0.9μm; specifically, the second conductive portion DB, the first sub-metal line MA, and the second sub-metal line MB can satisfy the relationship: 0.4μm≤ab≤0.8μm; specifically, the second conductive portion DB, the first sub-metal line MA, and the second sub-metal line MB can satisfy the relationship: 0.5μm≤ab≤0.7 ... MA and the second sub-metal line MB can satisfy the relationship: ab = 0.6 μm; in this embodiment, after the upper end of the conductive part D11 is reduced by 0.6 μm, the first coupling capacitance Cdp1 between the first metal line M11 and the connected pixel is 1.185 Ff; the second coupling capacitance Cdp2 between the first metal line M11 and the adjacent pixel is 1.175 Ff; the difference in coupling capacitance between the first coupling capacitance Cdp1 and the second coupling capacitance Cdp2 is 0.84%, which can significantly reduce the coupling effect of the coupling capacitance on the first metal line M11, thereby avoiding the occurrence of vertical crosstalk.

[0107] In one possible implementation, as shown in Figures 6A and 6B, the first metal line M11 includes: a first sub-metal portion M1a and a second sub-metal portion M1b arranged alternately along a first direction X; the first sub-metal portion M1a and the second sub-metal portion M1b extend in different directions; the second sub-edge w12 extends along the extension direction of the first sub-metal portion M1a, specifically, the extension direction of the second sub-edge w12 is the same as the extension direction of the first sub-metal portion M1a.

[0108] In one possible implementation, as shown in Figures 6A and 6B, the first sub-edge w11 extends along the extension direction of the second sub-metal portion M1b; the second outer edge w21 extends along the extension direction of the first sub-metal portion M1a; specifically, the extension direction of the first sub-edge w11 is the same as the extension direction of the outer edge of the first conductive portion DA toward the side of the first sub-metal line MA, that is, the extension line of the outer edge of the first conductive portion DA toward the side of the first sub-metal line MA can be used as the first sub-edge w11; the extension direction of the second sub-edge w12 is parallel to the extension direction of the second outer edge w2.

[0109] In one possible implementation, as shown in FIG6C, a first bend O is provided between the first sub-metal part M1a and the second sub-metal part M1a; the first outer edge w1 has a second bend Q; the orthographic projection of the second bend Q onto the substrate 11 is located in the region between the orthographic projection of the first metal edge f1 onto the substrate 11 and the orthographic projection of the first connecting line OO onto the substrate 11, wherein the first metal edge f1 is the outer edge of the second metal line M21 facing the first conductive part DA, and the first connecting line OO is the connecting line of the first bend O of two adjacent first metal lines M11.

[0110] In one possible implementation, as shown in FIG6C, the array substrate further includes: a third metal layer M3 located on the side of the first active layer C1 facing the substrate 11; the third metal layer M3 includes: a plurality of third metal lines M31 extending along the second direction Y; the orthographic projection of the third metal lines M31 on the substrate 11 covers the orthographic projection of the second metal lines M21 on the substrate; the orthographic projection of the second bend Q on the substrate 11 is located in the region between the orthographic projection of the first metal edge f1 on the substrate 11 and the orthographic projection of the second metal edge f2 on the substrate 11, the second metal edge f2 being the outer edge of the third metal line M31 facing the side of the first conductive part DA.

[0111] In one possible implementation, as shown in Figures 6A and 6B, the first outer edge w1 has a second bend Q; the orthographic projection of the second bend Q onto the substrate 11 overlaps with the orthographic projection of the first metal edge f1 onto the layer substrate 11, wherein the first metal edge f1 is the outer edge of the second metal line M21 facing the first conductive part DA. In this embodiment of the present disclosure, the overlap of the orthographic projection of the second bend Q onto the substrate 11 and the orthographic projection of the first metal edge f1 onto the layer substrate 11 can achieve a large distance between the second conductive part DB and the first sub-metal line MA, while ensuring the conductivity of the second via K2 (connecting the conductive part D11 and the first electrode D21), avoiding the possibility that improper positioning of the second bend Q might affect the conductivity of the second via K2 connecting the conductive part D11 and the first electrode D21.

[0112] In one possible implementation, as shown in Figures 6A and 6B, the second outer edge w2 includes a third bend P, the orthographic projection of the third bend P onto the substrate 11 may overlap with the orthographic projection of the first connecting line OO onto the substrate 11.

[0113] In one possible implementation, referring to Figures 2A, 5, or 6A, the first conductive portion DA is located between two adjacent first sub-metal portions M1a in the second direction Y; the second conductive portion DB is located between two adjacent second sub-metal portions M1b in the second direction Y; the extension direction of the first conductive portion DA is the same as the extension direction of the first sub-metal portion M1a. That is, in the conductive portion D11, the bending trend of the first conductive portion DA and the second conductive portion DB is consistent with the bending trend of the first metal wire M11, and the conductive portion D11 is bent at the bending position of the first metal wire M11.

[0114] In one possible implementation, referring to FIG2A, the first electrode D21 includes a first electrode portion DC and a second electrode portion DD distributed along a first direction X; the extending direction of the first electrode portion DC is the same as the extending direction of the first sub-metal portion M1a, and the extending direction of the second electrode portion DD is the same as the extending direction of the second sub-metal portion M1b.

[0115] It should be noted that in Figure 2A, only a portion of the second electrode part DD is shown. The second electrode part DD may have more parts, but the extension direction of the remaining parts of the second electrode part DD is not shown. It can be consistent with the extension direction of the second electrode part DD shown in the figure, only an extension in the extension direction. For details, please refer to Figure 8. The embodiments disclosed herein are not limited thereto.

[0116] In one possible implementation, as shown in FIG2A, the orthographic projection of the first electrode portion DC onto the substrate 11 overlaps with the orthographic projection of the second conductive portion DB onto the substrate 11, and they are electrically connected at the overlapping position.

[0117] In one possible implementation, as shown in FIG2A, the first conductive portion DA has a third outer edge w3 toward the first sub-metal line MA and a fourth outer edge w4 toward the second sub-metal line MB; the third edge w3 and the fourth outer edge w4 are parallel.

[0118] In one possible implementation, referring to FIG2A, the distance c between the orthographic projection of the third outer edge w3 onto the substrate 11 and the orthographic projection of the first sub-metal trace MA onto the substrate 11 is greater than the distance d between the orthographic projection of the fourth outer edge w4 onto the substrate 11 and the orthographic projection of the second sub-metal trace MB onto the substrate 11. That is, by shifting the conductive portion D11 to the right as a whole, the distance a between the second conductive portion DB and the first sub-metal trace MA is made greater than the distance b between the second conductive portion DB and the second sub-metal trace MB.

[0119] In one possible implementation, as shown in FIG6A, the distance c between the orthographic projection of the third outer edge w3 onto the substrate 11 and the orthographic projection of the first sub-metal trace MA onto the substrate 11 is equal to the distance d between the orthographic projection of the fourth outer edge w4 onto the substrate 11 and the orthographic projection of the second sub-metal trace MB onto the substrate 11.

[0120] In one possible implementation, as shown in FIG2A, the second conductive portion DB has a fifth outer edge w5 extending along the second direction Y, the fifth outer edge w5 being located on the side of the second metal line M21 away from the first conductive portion DA.

[0121] In one possible implementation, referring to FIG7, the second conductive portion DB has a fifth outer edge w5 extending along the second direction Y. The orthographic projection of the second metal line M21 onto the substrate covers the orthographic projection of the fifth outer edge w5 onto the substrate. In this embodiment of the present disclosure, by making the upper end of the second conductive portion DB recessed within the second metal line M21, the opposing capacitance generated by the vertical overlap of the first active pattern C11 and the conductive portion D11 in the first coupling capacitor Cdp1 (as shown in the area indicated by the thick solid line frame S in FIG4D) can be reduced or eliminated. This reduces the first coupling capacitor Cdp1, reduces the coupling capacitance difference between the first coupling capacitor Cdp1 and the second coupling capacitor Cdp2, and reduces the coupling effect of the coupling capacitor on the first metal line M11, thereby avoiding the occurrence of vertical crosstalk.

[0122] In this embodiment, after the upper end of the second conductive part DB is recessed within the second metal line M21, the first coupling capacitance Cdp1 between the first metal line M11 and the connected pixel is 1.259 Ff; the second coupling capacitance Cdp2 between the first metal line M11 and the adjacent pixel is 1.136 Ff; the difference in coupling capacitance between the first coupling capacitance Cdp1 and the second coupling capacitance Cdp2 is 9.77%, which can significantly reduce the coupling effect of the coupling capacitance on the first metal line M11, thereby avoiding the occurrence of vertical crosstalk.

[0123] In one possible implementation, as shown in FIG7, the second metal line M21 has a sixth outer edge w6 extending along the second direction Y; a portion of the sixth outer edge w6 in the orthographic projection on the substrate 11 coincides with the orthographic projection of the fifth outer edge w5 in the substrate 11.

[0124] In one possible implementation, referring to FIG8, the second part CB includes: a first sub-part CB1 and a second sub-part CB2; the first sub-part CB1 extends along the second direction Y, and the orthographic projection of the first sub-part CB1 on the substrate 11 overlaps with the orthographic projection of the first metal line M11 on the substrate 11; the second sub-part CB2 connects the first sub-part CB1 and the first part CA; the plurality of first active patterns C11 include: a first active pattern row C100 and a second active pattern row C200; the first active pattern row C100 and the second active pattern row C200 extend along the second direction Y and overlap along the first direction X.

[0125] Both the first active pattern row C100 and the second active pattern row C200 include multiple first active patterns C11; and in the first active pattern row C100, the second sub-part CB2 extends along a third direction Z1; in the second active pattern row C200, the second sub-part CB2 extends along a fourth direction Z2, and the third direction Z1 intersects with the fourth direction Z2. Specifically, in the two adjacent first sub-metal lines MA and the second sub-metal line MB on both sides of the conductive part D11, the second sub-part CB2 of the first active pattern row C100 can be located in the first direction X and biased towards one side of the first sub-metal line MA, and the second sub-part CB2 of the second active pattern row C200 can be located in the first direction X and biased towards one side of the second sub-metal line MB.

[0126] In the embodiment shown in Figure 8, by designing the first active pattern C11 of adjacent rows as a mirror image of the vertical row, the darker pixel rows and the brighter pixel rows can be alternately distributed. If the pixels in odd-numbered rows are brighter, the pixels in even-numbered rows are darker. The brightness difference between the upper and lower rows of pixels is neutralized, reducing the coupling effect of the coupling capacitor on the first metal line M11, thereby avoiding vertical crosstalk. Specifically, in odd-numbered pixel rows, the first coupling capacitor Cdp1 between the first metal line M11 and the connected pixel is 1.192 Ff. The second coupling capacitance Cdp2 between M11 and its adjacent pixel is 1.301 Ff; in even-numbered pixel rows, the first coupling capacitance Cdp1 between the first metal line M11 and its connected pixel is 1.312 Ff, and in even-numbered pixel rows, the second coupling capacitance Cdp2 between the first metal line M11 and its adjacent pixel is 1.177 Ff; in odd-numbered rows, the second coupling capacitance Cdp2 of the pixel is greater than the first coupling capacitance Cdp1, and in even-numbered pixel rows, the first coupling capacitance Cdp1 is greater than the second coupling capacitance Cdp2, thus neutralizing the brightness difference between the upper and lower rows of pixels.

[0127] In one possible implementation, the third direction Z1 and the fourth direction Z2 are located on different sides of the first direction X.

[0128] In one possible implementation, the angle between the third direction Z1 and the first direction X ranges from 10° to 80°; in one possible implementation, the angle between the third direction Z1 and the first direction X ranges from 20° to 70°; in one possible implementation, the angle between the third direction Z1 and the first direction X ranges from 30° to 60°; in one possible implementation, the angle between the third direction Z1 and the first direction X ranges from 40° to 50°.

[0129] In one possible implementation, the angle formed between the fourth direction Z2 and the first direction X ranges from 10° to 80°; in one possible implementation, the angle formed between the fourth direction Z2 and the first direction X ranges from 20° to 70°; in one possible implementation, the angle formed between the fourth direction Z2 and the first direction X ranges from 30° to 60°; in one possible implementation, the angle formed between the fourth direction Z2 and the first direction X ranges from 40° to 50°.

[0130] In one possible implementation, referring to FIG8, in the first active pattern row C100, the first sub-part CB1 and the first part CA are located on different sides of the second sub-part CB2; in the second active pattern row C200, the first sub-part CB1 and the first part CA are located on the same side of the second sub-part CB2.

[0131] In one possible implementation, as shown in Figures 2A and 3, the first conductive layer D1 is located on the side of the first active layer C1 away from the substrate 11; the array substrate further includes: a first insulating layer F1 located between the first active layer C1 and the first conductive layer D1, and a first via K1 penetrating the first insulating layer F1, wherein the conductive part D11 is electrically connected to the first part CA through the first via K1.

[0132] In one possible implementation, as shown in Figures 2A and 3, the first electrode D21 is located on the side of the first conductive layer D1 away from the substrate 11; the array substrate further includes: a second insulating layer F2 located between the first conductive layer D1 and the first electrode D21, and a second via K2 penetrating the second insulating layer F2; the first electrode D21 is electrically connected to the conductive portion D11 of K2 through the second via.

[0133] In one possible implementation, the first insulating layer F1 comprises one or a combination of the following:

[0134] First gate insulating layer 15;

[0135] First interlayer dielectric layer 16;

[0136] Second interlayer dielectric layer 17.

[0137] Specifically, as shown in Figure 3, the first interlayer dielectric layer 16 can be located on the side of the first gate insulating layer 15 away from the substrate 11; the second interlayer dielectric layer 17 can be located on the side of the first interlayer dielectric layer 16 away from the substrate 11.

[0138] In one possible implementation, as shown in FIG3, the first insulating layer F1 includes: a first gate insulating layer 15, a first interlayer dielectric layer 16, and a second interlayer dielectric layer 17.

[0139] In one possible implementation, in conjunction with Figures 2A and 3, the array substrate further includes a third via K3 penetrating the first interlayer dielectric layer 16 and the second interlayer dielectric layer 17, wherein the first metal line M11 is electrically connected to the second part CB of the first active pattern C11 through the third via K3.

[0140] In one possible implementation, referring to FIG. 2A, the orthographic projection of the third metal line M31 onto the substrate 11 covers the orthographic projection of the second via K2 onto the substrate 11; specifically, the orthographic projection of the second metal line M21 onto the substrate 11 covers the orthographic projection of the second via K2 onto the substrate 11. In one possible implementation, the orthographic projection of the second via K2 onto the substrate 11 is located at the overlapping area of ​​the first electrode D21 and the conductive portion D11 on the substrate 11, thereby achieving electrical connection between the first electrode D21 and the conductive portion D11 at the overlapping area through the second via K2.

[0141] The orthographic projection of the first metal line M11 onto the substrate 11 covers the orthographic projection of the third via K3 onto the substrate 11. In one possible implementation, the orthographic projection of the first via K1 onto the substrate 11 is located at the overlapping region of the orthographic projections of the first part CA of the first active pattern C11 and the conductive part D11 onto the substrate 11, thereby achieving electrical connection between the first part CA and the conductive part D11 at the overlapping region through the first via K1.

[0142] In one possible implementation, the orthographic projection of the first metal line M11 onto the substrate 11 covers the orthographic projection of the third via K3 onto the substrate 11. Specifically, the orthographic projection of the third via K3 onto the substrate 11 is located at the overlapping area of ​​the orthographic projections of the first metal line M11 and the second portion CB of the first active pattern C11 onto the substrate 11, thereby achieving electrical connection between the first metal line M11 and the second portion CB of the first active pattern C11 through the third via K3.

[0143] In one possible implementation, the orthographic projections of the first via K1 and the second via K2 onto the substrate 11 are both located between the orthographic projections of the first sub-metal line MA and the second sub-metal line MB onto the substrate 11. In another possible implementation, the orthographic projections of the first via K1 and the second via K2 onto the substrate 11 have a gap in the first direction X.

[0144] In practical implementation, the thickness of the first insulating layer F1 between the first active layer C1 and the first conductive layer D1 can be adjusted by adjusting at least one or a combination of the first gate insulating layer 15, the first interlayer dielectric layer 16, and the second interlayer dielectric layer 17. Combined with rightward shifting of the conductive portion D11 and / or upward shifting of the second metal trace M21, precise capacitance difference control can be achieved, reducing the second coupling capacitance C. dp2 With the first coupling capacitor C dp1 The differences.

[0145] In one possible implementation, as shown in FIG3, the thickness of at least one of the first gate insulating layer 15, the first interlayer dielectric layer 16, and the second interlayer dielectric layer 17 is greater than [missing information].

[0146] In one possible implementation, the thickness of the first gate insulating layer 15 can be controlled to be The thickness of the first interlayer dielectric layer 16 is The thickness of the second interlayer dielectric layer 17 is To reduce the second coupling capacitance C dp2 With the first coupling capacitor C dp1 The difference. In one possible implementation, the thickness of the first gate insulating layer 15 can be controlled to be The thickness of the first interlayer dielectric layer 16 is The thickness of the second interlayer dielectric layer 17 is To reduce the second coupling capacitance C dp2 With the first coupling capacitor C dp1 The differences.

[0147] In one possible implementation, the thickness of the first gate insulating layer 15 can be controlled to be The thickness of the first interlayer dielectric layer 16 is The thickness of the second interlayer dielectric layer 17 is To reduce the second coupling capacitance C dp2 With the first coupling capacitor C dp1 The difference. In one possible implementation, the thickness of the first gate insulating layer 15 can be controlled to be The thickness of the first interlayer dielectric layer 16 is The thickness of the second interlayer dielectric layer 17 is To reduce the second coupling capacitance C dp2 With the first coupling capacitor C dp1 The differences.

[0148] In one possible implementation, the thickness of the first gate insulating layer 15 can be controlled to be The thickness of the first interlayer dielectric layer 16 is The thickness of the second interlayer dielectric layer 17 is To reduce the second coupling capacitance C dp2 With the first coupling capacitor C dp1 The difference. In one possible implementation, the thickness of the first gate insulating layer 15 can be controlled to be The thickness of the first interlayer dielectric layer 16 is The thickness of the second interlayer dielectric layer 17 is To reduce the second coupling capacitance C dp2 With the first coupling capacitor C dp1 The differences.

[0149] In one possible implementation, the third metal line M31 can be used to block at least a portion of the first active pattern C11 of the first transistor to avoid the illumination effect of ambient light on the first active pattern C11, thereby affecting the characteristics of the first transistor.

[0150] In one possible implementation, as shown in FIG. 2A, the orthogonal projection of the third metal line M31 onto the substrate 11 covers the orthogonal projection of the second via K2 onto the substrate 11. In this embodiment of the present disclosure, the orthogonal projection of the third metal line M31 onto the substrate 11 covers the orthogonal projection of the second via K2 onto the substrate 11. That is, by using the third metal line M31 of the array substrate to cover the second via K2, the risk of light leakage from the second via K2 on the array substrate can be reduced.

[0151] Based on the same inventive concept, embodiments of this disclosure also provide a display panel, which includes an array substrate as provided in embodiments of this disclosure.

[0152] Based on the same inventive concept, embodiments of this disclosure also provide a display device, which includes a display panel as provided in embodiments of this disclosure.

[0153] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the invention.

[0154] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if these modifications and variations to the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention also intends to include these modifications and variations.

Claims

1. An array substrate, wherein, The application relates to a display panel, comprising: a substrate; a first active layer located on one side of the substrate, comprising a plurality of first active patterns; the first active pattern comprises a first part and a second part distributed along a first direction; a first metal layer comprising a plurality of first metal lines; the second part overlaps with the first metal line in the substrate orthographic projection; a second metal layer comprising a plurality of second metal lines extending along a second direction; a first conductive layer comprising a plurality of conductive parts located in the display area; at least one conductive part in the plurality of conductive parts is located between the orthographic projections of adjacent first metal lines on the substrate; the conductive part comprises a first conductive part and a second conductive part distributed along the first direction; the first conductive part has an overlapping area with the first part in the orthographic projection of the substrate, and the second conductive part has an overlapping area with the second part in the orthographic projection of the substrate; the extension directions of the first conductive part and the second conductive part are different; a second conductive layer comprising a plurality of first electrodes located in the display area; wherein the first metal lines adjacent to the conductive part on both sides comprise a first sub-metal line and a second sub-metal line; the first sub-metal line is electrically connected with the second part; the first part is electrically connected with the first electrode through the conductive part; at least the second conductive part in the orthographic projection of the substrate has a spacing with the first sub-metal line in the orthographic projection of the substrate, which is greater than the spacing with the second sub-metal line in the orthographic projection of the substrate.

2. The array substrate of claim 1, wherein, The second conductive part has a first outer edge facing the first sub-metal line and a second outer edge facing the second sub-metal line; The spacing between the first outer edge in the orthographic projection of the substrate and the first sub-metal line in the orthographic projection of the substrate is greater than the spacing between the second outer edge in the orthographic projection of the substrate and the second sub-metal line in the orthographic projection of the substrate.

3. The array substrate of claim 2, wherein, The first metal line comprises a first sub-metal part and a second sub-metal part alternately arranged along the first direction; the extension directions of the first sub-metal part and the second sub-metal part are different; The first conductive part extends along the extension direction of the second sub-metal part, and the second conductive part extends along the extension direction of the first sub-metal part.

4. The array substrate of claim 1, wherein, The second conductive part has a first outer edge facing the first sub-metal line and a second outer edge facing the second sub-metal line; the extension line of the first outer edge intersects with the extension line of the second outer edge; The spacing between the first outer edge in the orthographic projection of the substrate and the first sub-metal line in the orthographic projection of the substrate is greater than the spacing between the second outer edge in the orthographic projection of the substrate and the second sub-metal line in the orthographic projection of the substrate.

5. The array substrate of claim 4, wherein, The first metal line comprises a first sub-metal part and a second sub-metal part alternately arranged along the first direction; the extension directions of the first sub-metal part and the second sub-metal part are different; The first outer edge extends along the first direction; and the extension direction of the second outer edge is the same as the extension direction of the first sub-metal part.

6. The array substrate of claim 1, wherein, The second conductive portion has a first outer edge facing the first sub-metal line and a second outer edge facing the second sub-metal line; The first outer edge includes: a first sub-edge portion and a second sub-edge portion; the second sub-edge portion is located on a side of the first sub-edge portion away from the first conductive portion, and the second sub-edge portion is located on a side of an extension line of the first sub-edge portion facing the first sub-metal trace; A distance between a positive projection of the second sub-edge on the substrate and a positive projection of the first sub-metal trace on the substrate is greater than a distance between a positive projection of the second outer edge on the substrate and a positive projection of the second sub-metal trace on the substrate.

7. The array substrate of claim 6, wherein, The first metal line includes: first sub-metal portions and second sub-metal portions alternately arranged along the first direction; extension directions of the first sub-metal portions and the second sub-metal portions are different; The second sub-edge extends along an extension direction of the first sub-metal portion.

8. The array substrate of claim 7, wherein, The first sub-edge extends along an extension direction of the second sub-metal portion; the second outer edge extends along an extension direction of the first sub-metal portion.

9. The array substrate of claim 6, wherein, A first bending portion is provided between the first sub-metal portion and the second sub-metal portion; a second bending portion is provided on the first outer edge; A positive projection of the second bending portion on the substrate is located in a region between a positive projection of a first metal edge on the substrate and a positive projection of a first connection line on the substrate, where the first metal edge is an outer edge of the second metal line facing the first conductive portion, and the first connection line is a connection line of the first bending portions of two adjacent first metal lines.

10. The array substrate of claim 9, wherein, The array substrate further includes: a third metal layer on a side of the first active layer facing the substrate; the third metal layer includes: multiple third metal lines extending along the second direction; a positive projection of the third metal line on the substrate covers a positive projection of the second metal line on the substrate; A positive projection of the second bending portion on the substrate is located in a region between a positive projection of the first metal edge on the substrate and a positive projection of a second metal edge on the substrate, and the second metal edge is an outer edge of the third metal line on a side facing the first conductive portion.

11. The array substrate of claim 6, wherein, The first outer edge has a second bending portion; A positive projection of the second bending portion on the substrate overlaps with a positive projection of a first metal edge on the substrate, and the first metal edge is an outer edge of the second metal line facing the first conductive portion.

12. The array substrate of any of claims 3, 5, 8-11, wherein, The first conductive portion is located between two adjacent first sub-metal portions in the second direction; the second conductive portion is located between two adjacent second sub-metal portions in the second direction; an extension direction of the first conductive portion is the same as an extension direction of the first sub-metal portion.

13. The array substrate of any of claims 3, 5, 8-12, wherein, The first electrode includes: a first electrode portion and a second electrode portion distributed along the first direction; an extension direction of the first electrode portion is the same as an extension direction of the first sub-metal portion, and an extension direction of the second electrode portion is the same as an extension direction of the second sub-metal portion.

14. The array substrate of claim 13, wherein, The first electrode portion has an overlapping area with the second conductive portion in the orthographic projection of the substrate, and is electrically connected at the overlapping position.

15. The array substrate of any of claims 1-14, wherein, The first conductive portion has a third outer edge facing the first sub-metal line, and a fourth outer edge facing the second sub-metal line; the third outer edge is parallel to the fourth outer edge.

16. The array substrate of claim 15, wherein, The distance between the third outer edge in the orthographic projection of the substrate and the first sub-metal line in the orthographic projection of the substrate is greater than the distance between the fourth outer edge in the orthographic projection of the substrate and the second sub-metal line in the orthographic projection of the substrate.

17. The array substrate of claim 16, wherein, The distance between the third outer edge in the orthographic projection of the substrate and the first sub-metal line in the orthographic projection of the substrate is equal to the distance between the fourth outer edge in the orthographic projection of the substrate and the second sub-metal line in the orthographic projection of the substrate.

18. The array substrate of any of claims 1-17, wherein, The second conductive portion has a fifth outer edge extending along the second direction, and the fifth outer edge is located on the side of the second metal line away from the first conductive portion.

19. The array substrate of any one of claims 1-17, wherein, The second conductive portion has a fifth outer edge extending along the second direction, and the second metal line in the orthographic projection of the substrate covers the fifth outer edge in the orthographic projection of the substrate.

20. The array substrate of claim 19, wherein, The second metal line has a sixth outer edge extending along the second direction; Part of the sixth outer edge in the orthographic projection of the substrate coincides with the fifth outer edge in the orthographic projection of the substrate.

21. The array substrate of any of claims 1-20, wherein, The second portion includes a first sub-portion and a second sub-portion; the first sub-portion extends along the second direction, and the first sub-portion in the orthographic projection of the substrate overlaps with the first metal line in the orthographic projection of the substrate; the second sub-portion connects the first sub-portion and the first portion; The plurality of first active patterns includes a first active pattern row and a second active pattern row; the first active pattern row and the second active pattern row are arranged in the second direction and overlap in the first direction; The first active pattern row and the second active pattern row each include a plurality of first active patterns; and in the first active pattern row, the second sub-portion extends in a third direction; in the second active pattern row, the second sub-portion extends in a fourth direction, and the third direction intersects the fourth direction.

22. The array substrate of claim 21, wherein, In the first active pattern row, the first sub-portion and the first portion are located on different sides of the second sub-portion; in the second active pattern row, the first sub-portion and the first portion are located on the same side of the second sub-portion.

23. A display panel, wherein, An array substrate as claimed in any one of claims 1-22.

24. A display device comprising: A display panel as claimed in claim 23.

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