Solar cell and manufacturing method therefor

Abstract

A solar cell and a manufacturing method therefor. The solar cell comprises a silicon substrate (10); the silicon substrate (10) comprises a first surface (S1) and a second surface (S2) arranged opposite to each other; the first surface (S1) comprises first regions (S11) and second regions (S12) which are alternately distributed; a tunneling passivation structure is provided on each first region (S11); a passivation structure is provided on each second region (S12); a first electrode (41) electrically connected to the tunneling passivation structure is further provided on the first region (S11); and the width W of the first regions (S11) is greater than the width L of the first electrodes (41).

Description

Solar cell and method for manufacturing the same

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on March 20, 2024 with application number 202410323940.8, the Chinese patent application filed with the China Patent Office on January 15, 2025 with application number 202510059555.1, and the Chinese patent application filed with the China Patent Office on January 15, 2025 with application number 202510059553.2, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application belongs to the technical field of solar cells, and for example relates to a solar cell and a method for preparing the same. Background Art

[0003] With the rapid development of the photovoltaic industry, the performance and efficiency requirements of solar cells in both domestic and international markets are constantly increasing. Consequently, industry manufacturers are focusing on the research and development of high-efficiency cells. Tunnel Oxide Passivated Contact (TOPCon) cells utilize an ultra-thin tunnel oxide layer and a doped polysilicon layer sequentially deposited on the back of the cell. This improves the cell's surface passivation, reduces the metal contact recombination current, and effectively increases the cell's open-circuit voltage and short-circuit current.

[0004] TOPCon cells of related technologies are usually single-sided TOPCon structures, with selective emitter technology used on the front side to achieve deep junctions with high boron doping concentrations in the metal area and shallow junctions with low boron doping concentrations in the non-metal area. However, the recombination in the metal area is still relatively high, which has become the main factor limiting the improvement of cell efficiency. In addition, the front boron diffusion requires a high temperature of over 1000°C, which consumes a lot of energy. The high temperature and the resulting borosilicate glass will shorten the life of the quartz tube, resulting in an increase in the cost of the entire process and equipment.

[0005] Therefore, it is necessary to provide a solar cell and a method for preparing the same. Summary of the Invention

[0006] The present application provides a solar cell and a method for manufacturing the same, so as to improve process tolerance and ensure contact passivation performance in the metal region.

[0007] The technical solution provided by an embodiment of the present application is as follows:

[0008] A solar cell includes a silicon substrate, the silicon substrate including a first surface and a second surface arranged opposite to each other, the first surface including a first region and a second region distributed at intervals, a tunneling passivation structure provided on the first region, a passivation structure provided on the second region, and a first electrode electrically connected to the tunneling passivation structure provided on the first region, wherein a width W of the first region is greater than a width L of the first electrode.

[0009] In one embodiment, a difference between a width W of the first region and a width L of the first electrode is greater than or equal to 40 μm.

[0010] In one embodiment, the difference between the width W of the first region and the width L of the first electrode is less than or equal to 600 μm; or the difference between the width W of the first region and the width L of the first electrode is less than or equal to 110 μm.

[0011] In one embodiment, the width of the first electrode is in the range of 5 μm to 40 μm; and / or the width of the first region is in the range of 45 μm to 640 μm or 45 μm to 150 μm.

[0012] In one embodiment, the tunneling passivation structure includes a first tunneling layer and a first doping layer sequentially stacked on the first region, and the passivation structure includes a blocking layer and a second doping layer sequentially stacked on the second region, and the first doping layer and the second doping layer have the same doping type.

[0013] In one embodiment, the first electrode is in contact with the first doped layer.

[0014] In one embodiment, the barrier layer and the second doping layer on the second region extend laterally into the first region and cover the first tunneling layer and the first doping layer.

[0015] In one embodiment, the first electrode is in contact with the second doped layer, or the first electrode penetrates the second doped layer and the barrier layer and is in contact with the first doped layer.

[0016] In one embodiment, the average doping concentration of the first doping layer is less than or equal to the average doping concentration of the second doping layer; and / or,

[0017] The average doping concentration of the first doping layer is 5E19cm -3 ~5E20cm -3 within the scope; and / or,

[0018] The average doping concentration of the second doping layer is 1E20cm -3 ~5E20cm -3 within the range.

[0019] In one embodiment, the thickness of the first doping layer is greater than the thickness of the second doping layer; and / or,

[0020] The thickness of the first doping layer is in the range of 30 nm to 300 nm or 100 nm to 200 nm; and / or,

[0021] The thickness of the second doping layer is in the range of 5 nm to 100 nm or 10 nm to 50 nm.

[0022] In one embodiment, the first doped layer is a doped polysilicon layer or multiple doped polysilicon layers with a doping concentration increasing from the inside to the outside; and / or,

[0023] The second doped layer is a doped polysilicon layer or multiple doped polysilicon layers with a doping concentration increasing from the inside to the outside.

[0024] In one embodiment, the first tunneling layer is any one or more combinations of a silicon oxide layer and a silicon oxynitride layer; and / or,

[0025] The thickness of the first tunneling layer is in the range of 0.5 nm to 3 nm or 1.5 nm to 2.5 nm; and / or,

[0026] The barrier layer is any one or more combinations of a silicon oxide layer and a silicon carbide layer; and / or,

[0027] The thickness of the barrier layer is in the range of 0.5 nm to 3 nm or 1.5 nm to 2.5 nm.

[0028] In one embodiment, a second tunneling layer and a third doping layer are stacked in sequence on the second surface of the silicon substrate, and a second electrode is also provided on the second surface. The doping type of the third doping layer is opposite to that of the first doping layer, and the second electrode is in contact with the third doping layer.

[0029] In one embodiment, the average doping concentration of the third doping layer is 3E20cm -3 ~3E21cm -3 or 5E20cm -3 ~3E21cm -3 within the scope; and / or,

[0030] The third doped layer is a doped polysilicon layer or multiple doped polysilicon layers with a doping concentration increasing from the inside to the outside; and / or,

[0031] The thickness of the third doping layer is in the range of 20 nm to 300 nm or 60 nm to 150 nm; and / or,

[0032] The second tunneling layer is any one or more combinations of a silicon oxide layer and a silicon oxynitride layer; and / or,

[0033] The thickness of the second tunneling layer is in the range of 0.5 nm to 3 nm or 1.5 nm to 2.5 nm.

[0034] In one embodiment, the silicon substrate is an N-type silicon substrate, the first doping layer and the second doping layer are P-type doped, and the third doping layer is N-type doped; and / or,

[0035] A light trapping structure is formed on the first surface and / or the second surface of the silicon substrate; and / or,

[0036] A first anti-reflection layer is stacked on the second doped layer; and / or,

[0037] A second anti-reflection layer is stacked on the third doping layer.

[0038] Another embodiment of the present application provides a technical solution as follows:

[0039] A method for preparing a solar cell, comprising the following steps:

[0040] Providing a silicon substrate, the silicon substrate comprising a first surface and a second surface opposite to each other, the first surface comprising a first region and a second region spaced apart;

[0041] preparing a tunneling passivation structure on the first region and preparing a passivation structure on the second region;

[0042] A first electrode electrically connected to the tunnel passivation structure is prepared on the first region, wherein a width L of the first electrode is smaller than a width W of the first region.

[0043] In one embodiment, the tunneling passivation structure includes: a first tunneling layer and a first doping layer, and the passivation structure includes a barrier layer and a second doping layer;

[0044] The preparation of the tunneling passivation structure, the passivation structure and the first electrode includes:

[0045] Depositing a first tunneling layer and a first doping layer on the entire surface of the first surface;

[0046] forming a patterned first mask on the first doped layer in the first region;

[0047] removing the first tunneling layer and the first doping layer on the second region by using an etching process and / or a texturing process;

[0048] cleaning and removing the first mask on the first doping layer;

[0049] preparing a barrier layer and a second doping layer stacked in sequence on the silicon substrate of the second region and the first doping layer of the first region, wherein the doping type of the second doping layer is the same as the doping type of the first doping layer;

[0050] preparing a first electrode on a first region of the first surface, the first electrode being in contact with the second doped layer or the first doped layer;

[0051] The difference between the width W of the first region and the width L of the first electrode satisfies: WL≥2X+2Y, where X is the process accuracy for forming the patterned first mask, and Y is the process accuracy for preparing the first electrode.

[0052] In one embodiment, forming a patterned first mask on the first doped layer in the first region includes:

[0053] An inorganic mask layer is prepared on the first doped layer, and patterned by a laser windowing process to remove the inorganic mask layer on the second region, wherein the process accuracy X of the laser windowing process is greater than or equal to 15 μm; or

[0054] An inorganic mask layer is prepared on the first doping layer, and a patterned organic mask layer is prepared on the first region by a screen printing process, wherein a process precision X of the screen printing process is greater than or equal to 15 μm.

[0055] In one embodiment, the preparation of the first electrode includes:

[0056] Printing a metal layer on the first area of ​​the first surface using a screen printing process, wherein a process accuracy Y of the screen printing process is greater than or equal to 5 μm;

[0057] The metal layer is sintered by adopting a sintering process to form a first electrode in ohmic contact with the silicon substrate.

[0058] In one embodiment, a difference between a width W of the first region and a width L of the first electrode is greater than or equal to 40 μm.

[0059] In one embodiment, the difference between the width W of the first region and the width L of the first electrode is less than or equal to 600 μm; or the difference between the width W of the first region and the width L of the first electrode is less than or equal to 110 μm.

[0060] In one embodiment, the width of the first electrode is in the range of 5 μm to 40 μm; and / or,

[0061] The width of the first region is in the range of 45 μm to 640 μm or 45 μm to 150 μm.

[0062] In one embodiment, the average doping concentration of the first doping layer is less than or equal to the average doping concentration of the second doping layer; and / or,

[0063] The average doping concentration of the first doping layer is 5E19cm -3 ~5E20cm -3 within the scope; and / or,

[0064] The average doping concentration of the second doping layer is 1E20cm -3 ~5E20cm -3 within the range.

[0065] In one embodiment, the thickness of the first doping layer is greater than the thickness of the second doping layer; and / or,

[0066] The thickness of the first doping layer is in the range of 30 nm to 300 nm or 100 nm to 200 nm; and / or,

[0067] The thickness of the second doping layer is in the range of 5 nm to 100 nm or 10 nm to 50 nm.

[0068] In one embodiment, the preparation method further comprises:

[0069] Prepare a second tunneling layer and a third doped layer stacked in sequence on the second surface, wherein the doping type of the third doped layer is opposite to that of the first doped layer;

[0070] A second electrode is prepared on the second surface and is in contact with the third doping layer.

[0071] In one embodiment, the preparation of the second electrode includes:

[0072] Printing a metal layer on the second surface using a screen printing process;

[0073] The metal layer is sintered by adopting a sintering process to form a second electrode in ohmic contact with the silicon substrate.

[0074] In one embodiment, the first doped layer, the second doped layer, and the third doped layer all include doped amorphous silicon layers, and the preparation method further includes:

[0075] The first doped layer, the second doped layer and the third doped layer are annealed at a temperature within a range of 900° C. to 980° C. to convert the doped amorphous silicon layer into a doped polysilicon layer.

[0076] In one embodiment, the preparation method further comprises:

[0077] preparing a second mask on the second doped layer to remove silicon oxide and amorphous silicon deposited on the surface and around the edges;

[0078] preparing a third mask on the third doped layer to remove silicon oxide and polysilicon deposited on the surface and around the edges;

[0079] The second mask and the third mask are removed and then cleaned.

[0080] In one embodiment, the preparation method further comprises:

[0081] A light trapping structure is prepared on the first surface and / or the second surface of the silicon substrate by a texturing process; and / or,

[0082] Prepare a first anti-reflection layer on the first surface of the silicon substrate; and / or,

[0083] A second anti-reflection layer is prepared on the second surface of the silicon substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0084] FIG1a is a schematic structural diagram of a solar cell in Example 1 of the present application;

[0085] FIG1b is a schematic diagram of a partially enlarged structure of point A in FIG1a;

[0086] FIG1c is a schematic diagram of the top view of the structure at point A in FIG1a;

[0087] Figures 2a to 2j are flow charts of the preparation process of the solar cell in Example 1 of the present application;

[0088] 3a to 3d are process flow charts of the patterning steps in Example 2 of the present application. DETAILED DESCRIPTION

[0089] In order to enable those skilled in the art to better understand the technical solutions of this application, the technical solutions in the embodiments of this application will be described below in conjunction with the accompanying drawings in the embodiments of this application. The described embodiments are only part of the embodiments of this application, not all of the embodiments.

[0090] In this application, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it can mean that the first feature is in direct contact with the second feature, or the first feature and the second feature are in indirect contact through an intermediate medium. Furthermore, when a first feature is "above," "above," or "above" a second feature, it can mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is higher in level than the second feature. When a first feature is "below," "below," or "below" a second feature, it can mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is lower in level than the second feature.

[0091] The theoretical efficiency of a single-sided TOPCon structure cell is 27.1%, and that of a double-sided TOPCon structure cell is 28.7%. To further improve efficiency, a double-sided tunneling passivation contact structure is required. However, when making a tunneling passivation contact structure on the front side of a TOPCon cell, if a thick poly-Si layer is first deposited on the front side, a mask is applied, and then the poly-Si layer is partially thinned using wet etching, it is difficult to accurately control the thickness of the poly-Si layer in the non-metallic area. This method has a narrow process window. If the tunneling passivation contact structure in the non-metallic area is not retained, the cell efficiency improvement will be relatively small. If direct laser windowing and secondary diffusion are used, the process flow is also complex, the process window is small and difficult to control, and high temperature boron diffusion is required.

[0092] The present application discloses a solar cell, including a silicon substrate, wherein the silicon substrate includes a first surface and a second surface arranged opposite to each other, the first surface includes a first region and a second region distributed at intervals, a tunneling passivation structure is provided on the first region, a passivation structure is provided on the second region, and a first electrode electrically connected to the tunneling passivation structure is also provided on the first region, wherein the width W of the first region is greater than the width L of the first electrode.

[0093] The present application also discloses a method for preparing a solar cell, comprising the following steps:

[0094] Providing a silicon substrate, the silicon substrate comprising a first surface and a second surface opposite to each other, the first surface comprising a first region and a second region spaced apart;

[0095] preparing a tunnel passivation structure on the first region and preparing a passivation structure on the second region;

[0096] A first electrode electrically connected to the tunnel passivation structure is prepared on the first region, and a width L of the first electrode is smaller than a width W of the first region.

[0097] This application can improve the process tolerance by setting the width of the metal area and the electrode, ensure that the electrode is located in the metal area, and ensure the contact passivation performance in the metal area.

[0098] The solar cell of the present application is a double-sided TOPCon cell, which has a tunneling passivation contact structure on both the front and back sides, ensuring the passivation contact of the front metal area or the back metal area, while reducing the parasitic absorption of the front metal area or the back non-metal area. Compared with the single-sided TOPCon cell in the related art, it can greatly improve the cell efficiency, and the preparation process is simple, which is suitable for mass production.

[0099] The present application is described below with reference to specific embodiments.

[0100] Example 1:

[0101] Figures 1a and 1b are schematic structural diagrams of a solar cell according to this embodiment. This solar cell is a bifacial TOPCon cell and includes a silicon substrate 10. The silicon substrate includes a first surface S1 and a second surface S2 disposed opposite each other. The first surface S1 includes a first region S11 and a second region S12. The first surface S1 is the front surface (i.e., the primary light-receiving surface) of the silicon substrate 10, and the second surface S2 is the back surface (i.e., the secondary light-receiving surface) of the silicon substrate 10. The first region S11 is a front metal region, and the second region S12 is a front non-metal region. In other embodiments, the first surface S1 may be the back surface (i.e., the secondary light-receiving surface) of the silicon substrate 10, the second surface S2 is the front surface (i.e., the primary light-receiving surface) of the silicon substrate 10, the first region S11 is a back metal region, and the second region S12 is a back non-metal region.

[0102] In this embodiment, a first tunneling layer 11 and a first doping layer 21 are sequentially stacked on the first region S11, and a barrier layer 12 and a second doping layer 22 are sequentially stacked on the second region S12. The barrier layer 12 and the second doping layer 22 extend laterally into the first region S11 and cover the surfaces of the first tunneling layer 11 and the first doping layer 12. A second tunneling layer 13 and a third doping layer 23 are sequentially stacked on the second surface S2.

[0103] In addition, a first electrode 41 is distributed on the first surface S1 and is located above the first region S11. The first electrode 41 contacts the second doped layer 22. A second electrode 42 is distributed on the second surface S2 and is in contact with the third doped layer 23. The first doped layer 21 and the second doped layer 22 have the same doping type, and the first doped layer 21 and the third doped layer 23 have opposite doping types.

[0104] Optionally, in this embodiment, the thickness of the first doping layer 21 is greater than the thickness of the second doping layer 22 .

[0105] Optionally, in this embodiment, a first anti-reflection layer 31 is stacked on the second doping layer 22 , and a second anti-reflection layer 32 is stacked on the third doping layer 23 .

[0106] The materials, thicknesses, doping concentrations, etc. of the multiple layers in the solar cell of this embodiment are described below.

[0107] The silicon substrate 10 in this embodiment is an N-type silicon substrate, and the resistivity is in the range of 0.3 Ω·cm to 7 Ω·cm, and optionally, in the range of 0.5 Ω·cm to 3.5 Ω·cm.

[0108] Optionally, light trapping structures are formed on both the first surface S1 and the second surface S2 of the silicon substrate 10 . For example, a pyramid textured surface structure can be formed on the first surface S1 and the second surface S2 of the silicon substrate 10 by alkali texturing.

[0109] In this embodiment, the first tunneling layer 11 and the second tunneling layer 13 are any one or more combinations of silicon oxide layers and silicon oxynitride layers, with a thickness in the range of 0.5 nm to 3 nm, and optionally in the range of 1.5 nm to 2.5 nm; the barrier layer 12 is any one or more combinations of silicon oxide layers and silicon carbide layers, with a thickness in the range of 0.5 nm to 3 nm, and optionally in the range of 1.5 nm to 2.5 nm.

[0110] In this embodiment, the first doped layer 21, the second doped layer 22, and the third doped layer 23 can all be a single doped polysilicon layer or multiple doped polysilicon layers with a doping concentration gradient increasing from the inside out (i.e., in a direction away from the substrate). The thickness of the first doped layer 21 is in the range of 30 nm to 300 nm, and can optionally be in the range of 100 nm to 200 nm; the thickness of the second doped layer 22 is in the range of 5 nm to 100 nm, and can optionally be in the range of 10 nm to 50 nm; and the thickness of the third doped layer 23 is in the range of 20 nm to 300 nm, and can optionally be in the range of 60 nm to 150 nm.

[0111] In addition, the first doping layer 21 and the second doping layer 22 are both P-type doped polysilicon layers, such as boron doped; and the third doping layer 23 is an N-type doped polysilicon layer, such as phosphorus doped.

[0112] If the second doping layer 22 is too thick, it will cause serious light absorption in the non-metallic area and large current loss. Therefore, the thickness of the second doping layer 22 is less than the thickness of the first doping layer 21. This can ensure the passivation effect of the metal area while reducing the light parasitic absorption of the non-metallic area, effectively improving the photoelectric conversion efficiency of the solar cell. In addition, both the first doping layer 21 and the second doping layer 22 use an annealing process to activate boron. The intermediate barrier layer 12 is relatively thin and will be penetrated by the doping elements during the annealing process. Therefore, the average doping concentration of the first doping layer 21 and the second doping layer 22 are not much different. In the actual process, the average doping concentration of the first doping layer 21 will be slightly less than the average doping concentration of the second doping layer 22 or be the same as the average doping concentration of the second doping layer 22, that is, the average doping concentration of the first doping layer 21 is less than or equal to the average doping concentration of the second doping layer 22.

[0113] Optionally, the average doping concentration of the first doping layer 21 is 5E19cm -3 ~5E20cm -3 When the first doping layer 21 is a P-type doped polysilicon layer, the doping concentration of the first doping layer 21 is within 5E19cm -3 ~5E20cm -3 when the first doped layer 21 is a multi-layer P-type doped polysilicon layer, taking the inner layer, the middle layer and the outer layer as an example, the doping concentration of the first doped layer 21 increases gradually from the inside to the outside.

[0114] The average doping concentration of the second doping layer 22 is 1E20 cm -3 ~5E20cm -3 When the second doping layer 22 is a P-type doped polysilicon layer, the doping concentration of the second doping layer 22 is within the range of 5E18cm -3 ~5E20cm -3 when the second doped layer 22 is a multi-layer P-type doped polysilicon layer, taking the inner layer, the middle layer and the outer layer as an example, the doping concentration of the second doped layer 22 increases gradually from the inside to the outside.

[0115] The average doping concentration of the third doping layer 23 is 3E20cm -3 ~3E21cm -3 Range, optional within 5E20cm -3 ~3E21cm -3 When the third doping layer 23 is a single N-type doped polysilicon layer, the doping concentration of the third doping layer 23 is in the range of 3E20cm-3 to 3E21cm-3; when the third doping layer 23 is a multi-layer N-type doped polysilicon layer, taking the inner layer, the middle layer and the outer layer as an example, the doping concentration of the third doping layer 23 increases from the inner to the outer layer. For example, the doping concentration of the inner layer is 3E20cm-3. -3 ~5E20cm -3 In the range, the doping concentration of the middle layer is 5E20cm -3 ~1E21cm -3 In the range, the doping concentration of the outer layer is 1E21cm -3 ~3E21cm -3 within the range.

[0116] In this embodiment, the first anti-reflection layer 31 on the first surface and the second anti-reflection layer 32 on the back surface can be a combination of one or more of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer, with a thickness ranging from 60 nm to 130 nm.

[0117] In this embodiment, the first electrode 41 on the first surface can contact the second doped layer 22, or can penetrate the barrier layer 12 and contact the first doped layer 21, but cannot damage the bottom first tunneling layer 11, ensuring the tunneling effect of the first tunneling layer 11. The second electrode 42 on the second surface is in electrical contact with the third doped layer 23, but cannot damage the bottom second tunneling layer 13, ensuring the tunneling effect of the second tunneling layer 13.

[0118] As shown in Figures 1b and 1c, the first electrode 41 in this embodiment is distributed directly above the first region S11, and the projection of the first electrode 41 on the first surface S1 is within the first region S11. Taking the gate line electrode as an example, the gate line electrode may include multiple vertically distributed main gate lines and multiple auxiliary gate lines (or fine gate lines). The main gate lines are usually prepared using a non-burn-through paste. The first electrode 41 in this application is described using the auxiliary gate lines as an example. The width L of the auxiliary gate lines is in the range of 5μm to 40μm. The first region S11 includes multiple linear regions distributed at intervals. The width W of the first region S11 is in the range of 45μm to 640μm, and can optionally be in the range of 45μm to 150μm.

[0119] The method for preparing a solar cell in this embodiment includes the following steps:

[0120] 1. Double-sided velveting

[0121] 2a , a silicon substrate 10 is provided. The silicon substrate includes a first surface S1 and a second surface S2 disposed opposite each other. The first surface S1 includes a first region S11 and a second region S12. The first surface S1 is the front surface (i.e., the primary light-receiving surface) of the silicon substrate 10, and the second surface S2 is the back surface (i.e., the secondary light-receiving surface) of the silicon substrate 10. The first region S11 is a front metal region, and the second region S12 is a front non-metal region. In other embodiments, the first surface S1 may also be the back surface (i.e., the secondary light-receiving surface) of the silicon substrate 10, the second surface S2 may be the front surface (i.e., the primary light-receiving surface) of the silicon substrate 10, the first region S11 is a back metal region, and the second region S12 is a back non-metal region.

[0122] The silicon substrate 10 in this embodiment is an N-type silicon substrate with a resistivity in the range of 0.3Ω·cm to 7Ω·cm, and optionally in the range of 0.5Ω·cm to 3.5Ω·cm. The first surface S1 and the second surface S2 of the silicon substrate are formed with a pyramid texture structure (not shown) by an alkali texturing process.

[0123] 2. Preparation of the first tunneling layer 11 and the first doping layer 21

[0124] A first tunneling layer 11 and a first doping layer 21 are sequentially stacked on the first region S11. For example, the following steps are included:

[0125] First, referring to FIG. 2 b , a first tunneling layer 11 , a first doping layer 21 and a first mask 51 are deposited on the entire surface of the first surface S1 .

[0126] Illustratively, in this embodiment, a plasma enhanced chemical vapor deposition (PECVD) process is used for deposition; the thickness of the first tunneling layer 11 is in the range of 0.5 nm to 3 nm, and can be optionally in the range of 1.5 nm to 2.5 nm; the first doping layer 21 is a boron-doped amorphous silicon layer, with an average doping concentration in the range of 5E19 cm-3 to 5E20 cm-3 and a thickness in the range of 30 nm to 300 nm, and can be optionally in the range of 100 nm to 200 nm; the first mask 51 is an inorganic mask, such as a silicon oxide mask, with a thickness in the range of 5 nm to 50 nm.

[0127] Then, referring to FIG. 2 c , a patterned first mask 51 is formed on the first doping layer 21 in the first region S11 through a patterning process.

[0128] Illustratively, in this embodiment, patterning is performed by a laser windowing process, and a large-area laser windowing is performed on the second region S12 by means of laser windowing, and the first mask 51 on the second region S12 is removed.

[0129] Then, referring to FIG. 2 d , the first tunneling layer 11 and the first doping layer 21 on the second region S12 are removed by an etching process and a texturing process.

[0130] In this embodiment, the second region S12 is subjected to a secondary texturing process using the patterned first mask 51 to etch away the first tunneling layer 11 and the first doping layer 21 deposited on the second region S12 .

[0131] Finally, referring to FIG. 2 e , the first mask 51 on the first doped layer is cleaned and removed.

[0132] As shown in Figure 1c, considering the process accuracy X of the laser window opening process during the patterning process of the laser window opening process, a certain width needs to be reserved on both the left and right sides of the first area S11. For example, if the process accuracy X of the laser window opening process in this embodiment is 15μm, then the difference between the width W of the first area S11 and the width L of the first electrode 41 needs to reserve a width of at least 30μm.

[0133] 3. Preparation of barrier layer 12 and second doping layer 22

[0134] As shown in FIG. 2 f , a barrier layer 12 , a second doping layer 22 and a second mask 52 stacked in sequence are prepared on the second region S12 and the first doping layer 21 .

[0135] Exemplarily, in this embodiment, a PECVD process is used for deposition; the thickness of the barrier layer 12 is in the range of 0.5 nm to 3 nm, and can be optionally in the range of 1.5 nm to 2.5 nm; the second doping layer 22 is a boron-doped amorphous silicon layer, with an average doping concentration in the range of 1E20 cm-3 to 5E20 cm-3 and a thickness in the range of 5 nm to 100 nm, and can be optionally in the range of 10 nm to 50 nm; the second mask 52 is an inorganic mask, such as a silicon oxide mask, with a thickness in the range of 5 nm to 100 nm.

[0136] In this embodiment, the barrier layer 12 and the second doping layer 22 are deposited on the entire surface of the first surface S1. In the actual process, the barrier layer 12 and the second doping layer 22 are not only deposited directly above the second region S12 and the first doping layer 21, but also deposited outside the sidewalls of the first tunneling layer 11 and the first doping layer 21.

[0137] In other embodiments, the barrier layer 12 and the second doping layer 22 may also be deposited on the second region S12 and the first doping layer 21 in different regions, which will not be further described here.

[0138] 4. Backside de-plating and polishing

[0139] Use single-sided chain equipment to remove the silicon oxide on the back and edge with hydrofluoric acid, then use alkaline solution to remove the amorphous silicon on the edge, and polish or micro-texture the back, and finally perform RCA (Radio Corporation of America) cleaning.

[0140] 5. Preparation of the second tunneling layer 13 and the third doping layer 23

[0141] 2g, a second tunneling layer 13, a third doping layer 23 and a third mask 53 stacked in sequence are prepared on the second surface S2.

[0142] For example, in this embodiment, the PECVD process is used for deposition; the thickness of the second tunneling layer 13 is in the range of 0.5nm to 3nm, and can be optionally in the range of 1.5nm to 2.5nm; the third doping layer 23 is a phosphorus-doped amorphous silicon layer with an average doping concentration of 3E20cm -3 ~3E21cm -3 Range, optional within 5E20cm -3 ~3E21cm -3 The thickness is within the range of 20nm to 300nm, and can be optionally within the range of 60nm to 150nm; the third mask 53 is an inorganic mask, such as a silicon oxide mask, and has a thickness within the range of 5nm to 50nm.

[0143] 6. Co-annealing treatment

[0144] The first doping layer 21 , the second doping layer 22 and the third doping layer 23 are subjected to high-temperature annealing treatment in a high-temperature annealing furnace. The annealing temperature is in the range of 900° C. to 980° C.

[0145] The co-annealing process can activate the doping atoms (phosphorus atoms and boron atoms) in the doping layer, convert the doped amorphous silicon layer into a doped polysilicon layer, and simultaneously form tunneling passivation contact structures on the front and back sides.

[0146] For example, after the co-annealing treatment, the first doping layer 21 and the second doping layer 22 are transformed from boron-doped amorphous silicon layers to boron-doped polysilicon layers, and the third doping layer 23 is transformed from phosphorus-doped amorphous silicon layers to phosphorus-doped polysilicon layers.

[0147] 7. De-plating and cleaning

[0148] The silicon oxide deposited on the first surface and the edge is removed by hydrofluoric acid using a single-sided chain device, and then the polysilicon deposited on the edge is removed by an alkaline solution. Finally, as shown in FIG2h , the second mask 52 on the first surface and the third mask 53 on the back are removed, and RCA cleaning is performed.

[0149] 8. Preparation of anti-reflection layer

[0150] 2 i , a PECVD process is used for deposition to prepare a first anti-reflection layer 31 on the second doping layer 22 , and a second anti-reflection layer 32 on the third doping layer 23 .

[0151] Illustratively, the first anti-reflection layer 31 and the second anti-reflection layer 32 in this embodiment can be a silicon nitride layer, or a silicon nitride layer and a silicon oxynitride layer, or a three-layer silicon nitride layer, a silicon oxynitride layer and a silicon oxide layer, and the thickness of the anti-reflection layer is in the range of 60nm to 130nm.

[0152] 9. Preparation of metal electrodes

[0153] 2 j , a first electrode 41 in ohmic contact with the silicon substrate 10 is formed on the first region S11 of the first surface S1 , and a second electrode 42 in ohmic contact with the silicon substrate 10 is formed on the second surface S2 .

[0154] For example, in this embodiment, a screen printing process is used to print metal layers on the first area S11 in the first surface S1 and on the second surface S2, respectively. The metal layers are sintered using a sintering process to form a first electrode 41 and a second electrode 42 that are in ohmic contact with the silicon substrate 10. Finally, light injection is used to post-process the cell.

[0155] As shown in Figure 1c, considering the process accuracy Y of the screen printing process in the process of preparing the electrode by the screen printing process, a certain width needs to be reserved on both the left and right sides of the first area S11. For example, if the process accuracy Y of the screen printing process in this embodiment is 5μm, then the difference between the width W of the first area S11 and the width L of the first electrode 41 needs to reserve a width of at least 10μm.

[0156] The above steps can be used to prepare double-sided TOPCon batteries, and finally the battery cells are tested, sorted, and stored.

[0157] Taking into account the process precision of the laser windowing process and the screen printing process, in this embodiment, the difference between the width W of the first region S11 and the width L of the first electrode 41 must satisfy the following requirement: WL ≥ 2X + 2Y, i.e., WL ≥ 40 μm. Furthermore, the density of the gate lines affects battery efficiency: the larger the gate line spacing, the lower the current transmission efficiency. Therefore, the difference between the width W of the first region S11 and the width L of the first electrode 41 must be within a certain range. For example, in this embodiment, WL ≤ 600 μm, preferably WL ≤ 110 μm.

[0158] Based on the above analysis, when the width L of the first electrode 41 in this embodiment is within the range of 5 μm to 40 μm, the width W of the first region S11 is within the range of 45 μm to 640 μm, and may optionally be within the range of 45 μm to 150 μm. In other embodiments, the width W of the first region S11 is affected by the width L of the first electrode 41, the process accuracy X of forming the patterned first mask, and the process accuracy Y of fabricating the first electrode. The range of W can be adaptively adjusted based on the values ​​of L, X, and Y.

[0159] Example 2:

[0160] The structure and preparation method of the solar cell in this embodiment are substantially the same as those in Example 1, except for the patterning step in step 2 of the preparation method.

[0161] For example, in Example 1, the first mask 51 is patterned by a laser windowing process. The patterning steps in this embodiment are, for example:

[0162] First, referring to FIG3a , a first tunneling layer 11 , a first doping layer 21 and a first mask 51 are deposited on the entire surface of the first surface S1 . The first mask 51 is an inorganic mask, such as a silicon oxide mask.

[0163] Then, referring to FIG. 3 b , a patterned fourth mask 54 is prepared on the first region S11 by screen printing. The fourth mask 54 is an organic mask, such as a resin mask.

[0164] Then, referring to FIG3 c , the second region is etched and subjected to a secondary texturing process using a wet etching process to remove the first tunneling layer 11 and the first doping layer 21 on the second region;

[0165] Finally, referring to FIG. 3 d , the first mask 51 and the fourth mask 54 on the first doping layer are cleaned and removed.

[0166] Similarly, considering the process accuracy X of the screen printing process during the patterning process of the screen printing process, a certain width needs to be reserved on both the left and right sides of the first area S11. For example, if the process accuracy X of the screen printing process in this embodiment is 15 μm, then the difference between the width W of the first area S11 and the width L of the first electrode 41 needs to reserve a width of at least 30 μm.

[0167] Referring to Example 1, in this embodiment, the difference between the width W of the first region S11 and the width L of the first electrode 41 must satisfy WL≥2X+2Y, that is, WL≥40 μm, and satisfy WL≤600 μm. Optionally, WL≤110 μm.

[0168] Example 3:

[0169] The method for preparing a solar cell in this embodiment includes the following steps:

[0170] 1. Double-sided velveting

[0171] The silicon substrate in this embodiment is an N-type silicon substrate with a resistivity in the range of 1Ω·cm to 2Ω·cm. A pyramid textured surface structure is formed on the first surface and the second surface of the silicon substrate by an alkali texturing process.

[0172] 2. Preparation of the first tunneling layer and the first doping layer

[0173] A tunneling silicon oxide layer with a thickness of 1.5nm to 2nm is grown on the first surface using the PECVD process, and then a 10nm thick intrinsic amorphous silicon layer, a 50nm thick lightly doped P-type amorphous silicon layer, a 120nm thick heavily doped P-type amorphous silicon layer are deposited in sequence, and finally a 20nm thick silicon oxide mask layer is deposited.

[0174] Among them, the average doping concentration of the lightly doped P-type amorphous silicon layer is 5E19cm -3 ~6E19cm -3 In the range of 1E20cm -3 ~3E20cm -3 within the range.

[0175] A large-area laser windowing is performed in the second area through a laser windowing process to remove the silicon oxide mask layer deposited in the second area. Then, a secondary alkali texturing process is performed on the second area to etch away the first tunneling layer and the first doping layer. Finally, the remaining silicon oxide mask layer is cleaned and removed.

[0176] 3. Preparation of barrier layer and second doping layer

[0177] A PECVD process is used to continue growing a tunneling silicon oxide layer with a thickness in the range of 1.5nm to 2nm on the first surface, and then a 5nm thick intrinsic amorphous silicon layer, a 10nm thick lightly doped P-type amorphous silicon layer, a 30nm thick heavily doped P-type amorphous silicon layer are deposited in sequence, and finally a 60nm thick silicon oxide mask layer is deposited.

[0178] Among them, the average doping concentration of the lightly doped P-type amorphous silicon layer is 1E20cm -3 ~2E20cm -3 In the range of 3E20cm -3 ~5E20cm -3 within the range.

[0179] 4. Backside de-plating and polishing

[0180] Use single-sided chain equipment to remove the silicon oxide coated on the back and edge with hydrofluoric acid, then use alkaline solution to remove the amorphous silicon coated on the edge, and polish or micro-texture the back, and finally perform RCA cleaning.

[0181] 5. Preparation of the second tunneling layer and the third doping layer

[0182] A tunneling silicon oxide layer with a thickness of 2nm to 2.5nm is grown on the second surface using the PECVD process, and then a 15nm thick intrinsic amorphous silicon layer, a 30nm thick lightly doped N-type amorphous silicon layer, a 70nm thick heavily doped N-type amorphous silicon layer are deposited in sequence, and finally a 20nm thick silicon oxide mask layer is deposited.

[0183] 6. Co-annealing treatment

[0184] The first doped layer, the second doped layer and the third doped layer are subjected to high-temperature annealing treatment in a high-temperature annealing furnace. The annealing temperature is in the range of 900°C to 980°C. The co-annealing treatment can activate the doping atoms (phosphorus atoms and boron atoms) in the doped layers, and convert the doped amorphous silicon layer into a doped polysilicon layer. At the same time, the doping atoms will diffuse into the intrinsic amorphous silicon layer, and finally convert the intrinsic amorphous silicon layer into a doped polysilicon layer, while forming a tunnel passivation contact structure on the front and back sides.

[0185] In other embodiments, the intrinsic amorphous silicon layer can be set in the middle layer, the lightly doped amorphous silicon layer can be set in the inner layer, and the heavily doped amorphous silicon layer can be set in the outer layer. In this way, after co-annealing treatment, an inner layer, a middle layer and an outer layer doped polysilicon layer structure can be formed. At this time, the average doping concentration of the middle layer doped polysilicon layer is the smallest, and the average doping concentration of the outer layer doped polysilicon layer is the largest.

[0186] 7. De-plating and cleaning

[0187] Use single-sided chain equipment to remove the silicon oxide on the first surface and the edge with hydrofluoric acid, then use alkaline solution to remove the polysilicon on the edge, and finally remove the silicon oxide mask layer on the front and back and perform RCA cleaning.

[0188] 8. Preparation of anti-reflection layer

[0189] The PECVD process is used to deposit anti-reflection layers of silicon nitride, silicon oxynitride, and silicon oxide structures on the front and back sides respectively, and the thickness of the anti-reflection layer is 100nm.

[0190] 9. Preparation of metal electrodes

[0191] A screen printing process is used to print metal layers on the first area of ​​the first surface and on the second surface respectively. A sintering process is used to sinter the metal layers to form a first electrode and a second electrode in ohmic contact with the silicon substrate. Finally, light injection is used to post-process the cell.

[0192] The above steps can be used to prepare double-sided TOPCon batteries, and finally the battery cells are tested, sorted, and stored.

[0193] Illustratively, in this embodiment, the widths of the first electrode and the second electrode are in the range of 5 μm to 40 μm, for example, 15 μm, and the width of the first region S11 is in the range of 45 μm to 150 μm, for example, 100 μm.

[0194] The double-sided TOPCon cell in the above embodiment adopts a Poly-finger structure with locally passivated contacts, which ensures contact passivation in the first area while reducing parasitic absorption in the second area. Compared with the single-sided TOPCon cell in the related art, it can greatly improve the cell efficiency, and the preparation process is simple, making it suitable for mass production.

[0195] The PECVD process is used to deposit the tunneling layer and the doped amorphous silicon layer twice, which can accurately control the thickness of the polysilicon layer. The process for preparing the Poly-finger structure of local passivation contact is more controllable and the process is simpler.

[0196] The middle barrier layer can easily penetrate through the first doped layer below to form hole transmission; in addition, the thickness of the second doped layer is relatively thin, and the electrode slurry can easily penetrate the barrier layer during the sintering process without affecting carrier transmission; the first tunneling layer uses an intrinsic amorphous silicon layer as a buffer layer, which can provide a certain window for the lower tunneling layer, ensuring that the lower layer can maintain a good passivation effect after the upper tunneling layer is penetrated.

[0197] In addition, the present application does not require a high-temperature (above 1000°C) boron diffusion process, and annealing can be performed in the temperature range of 900°C to 980°C. There is also no problem of borosilicate glass (boron trioxide) corroding the furnace tube in the boron diffusion process, which greatly improves the service life of the furnace tube and reduces equipment maintenance costs.

[0198] The embodiments are to be considered as illustrative and not restrictive, and the scope of the application is indicated by the appended claims rather than the foregoing description, and all changes that come within the meaning and range of equivalency of the claims are intended to be embraced therein.

[0199] It should be understood that although this specification is described according to implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity, and those skilled in the art should regard the specification as a whole.

Claims

1. A solar cell, comprising a silicon substrate, the silicon substrate comprising a first surface and a second surface arranged opposite to each other, the first surface comprising a first region and a second region spaced apart from each other, a tunneling passivation structure being provided on the first region, a passivation structure being provided on the second region, and a first electrode being electrically connected to the tunneling passivation structure being further provided on the first region, wherein a width W of the first region is greater than a width L of the first electrode.

2. The solar cell according to claim 1, wherein A difference between a width W of the first region and a width L of the first electrode is greater than or equal to 40 μm.

3. The solar cell according to claim 1, wherein The difference between the width W of the first region and the width L of the first electrode is less than or equal to 600 μm; or, A difference between a width W of the first region and a width L of the first electrode is less than or equal to 110 μm.

4. The solar cell according to claim 1, wherein Meet at least one of the following: The width of the first electrode is in the range of 5 μm to 40 μm; and The width of the first region is in the range of 45 μm to 640 μm or 45 μm to 150 μm.

5. The solar cell according to claim 1, wherein The tunneling passivation structure includes a first tunneling layer and a first doping layer sequentially stacked on the first region, and the passivation structure includes a barrier layer and a second doping layer sequentially stacked on the second region. The first doping layer and the second doping layer have the same doping type.

6. The solar cell according to claim 5, wherein The first electrode contacts the first doping layer.

7. The solar cell according to claim 5, wherein The barrier layer and the second doping layer on the second region extend laterally into the first region and cover the first tunneling layer and the first doping layer.

8. The solar cell according to claim 7, wherein The first electrode contacts the second doping layer, or the first electrode penetrates the second doping layer and the barrier layer and contacts the first doping layer.

9. The solar cell according to claim 5 or 7, wherein: Meet at least one of the following: The average doping concentration of the first doping layer is less than or equal to the average doping concentration of the second doping layer; The average doping concentration of the first doping layer is 5E19cm -3 ~5E20cm -3 within the scope; and, The average doping concentration of the second doping layer is 1E20cm -3 ~5E20cm -3 within the range.

10. The solar cell according to claim 5 or 7, wherein: Meet at least one of the following: The thickness of the first doping layer is greater than the thickness of the second doping layer; The thickness of the first doping layer is in the range of 30 nm to 300 nm or 100 nm to 200 nm; and, The thickness of the second doping layer is in the range of 5 nm to 100 nm or 10 nm to 50 nm.

11. The solar cell according to claim 5 or 7, wherein Meet at least one of the following: The first doped layer is a doped polysilicon layer or multiple doped polysilicon layers with a doping concentration increasing from the inside to the outside; and, The second doped layer is a doped polysilicon layer or multiple doped polysilicon layers with a doping concentration increasing from the inside to the outside.

12. The solar cell according to claim 5 or 7, wherein: Meet at least one of the following: The first tunneling layer is any one or more combinations of a silicon oxide layer and a silicon oxynitride layer; The thickness of the first tunneling layer is in the range of 0.5 nm to 3 nm or 1.5 nm to 2.5 nm; The barrier layer is any one or more combinations of a silicon oxide layer and a silicon carbide layer; and, The thickness of the barrier layer is in the range of 0.5 nm to 3 nm or 1.5 nm to 2.5 nm.

13. The solar cell according to claim 1, wherein A second tunneling layer and a third doping layer are sequentially stacked on the second surface of the silicon substrate. A second electrode is also provided on the second surface. The doping type of the third doping layer is opposite to that of the first doping layer. The second electrode is in contact with the third doping layer.

14. The solar cell according to claim 13, wherein Meet at least one of the following: The average doping concentration of the third doping layer is 3E20cm -3 ~3E21cm -3 or 5E20cm -3 ~3E21cm -3 within the scope; The third doped layer is a doped polysilicon layer or multiple doped polysilicon layers with a doping concentration increasing from the inside to the outside; The thickness of the third doping layer is in the range of 20nm to 300nm or 60nm to 150nm; The second tunneling layer is any one or more combinations of a silicon oxide layer and a silicon oxynitride layer; and, The thickness of the second tunneling layer is in the range of 0.5 nm to 3 nm or 1.5 nm to 2.5 nm.

15. The solar cell according to claim 13, wherein Meet at least one of the following: The silicon substrate is an N-type silicon substrate, the first doping layer and the second doping layer are P-type doped, and the third doping layer is N-type doped; A light trapping structure is formed on at least one of the first surface and the second surface of the silicon substrate; A first anti-reflection layer is stacked on the second doped layer; and A second anti-reflection layer is stacked on the third doping layer.

16. A method for preparing a solar cell, comprising the following steps: Providing a silicon substrate, the silicon substrate comprising a first surface and a second surface opposite to each other, the first surface comprising a first region and a second region spaced apart; preparing a tunneling passivation structure on the first region and preparing a passivation structure on the second region; A first electrode electrically connected to the tunnel passivation structure is prepared on the first region, wherein a width L of the first electrode is smaller than a width W of the first region.

17. The preparation method according to claim 16, wherein The tunneling passivation structure comprises: a first tunneling layer and a first doping layer, and the passivation structure comprises a barrier layer and a second doping layer; The preparation of the tunneling passivation structure, the passivation structure and the first electrode includes: Depositing a first tunneling layer and a first doping layer on the entire surface of the first surface; forming a patterned first mask on the first doped layer in the first region; removing the first tunneling layer and the first doping layer on the second region by using at least one of an etching process and a texturing process; cleaning and removing the first mask on the first doping layer; preparing a barrier layer and a second doping layer stacked in sequence on the silicon substrate of the second region and the first doping layer of the first region, wherein the doping type of the second doping layer is the same as the doping type of the first doping layer; preparing a first electrode on a first region of the first surface, the first electrode being in contact with the second doped layer or the first doped layer; The difference between the width W of the first region and the width L of the first electrode satisfies: WL≥2X+2Y, where X is the process accuracy for forming the patterned first mask, and Y is the process accuracy for preparing the first electrode.

18. The preparation method according to claim 17, wherein Forming a patterned first mask on the first doped layer in the first region includes: An inorganic mask layer is prepared on the first doped layer, and patterned by a laser windowing process to remove the inorganic mask layer on the second region, wherein the process accuracy X of the laser windowing process is greater than or equal to 15 μm; or An inorganic mask layer is prepared on the first doping layer, and a patterned organic mask layer is prepared on the first region by a screen printing process, wherein a process precision X of the screen printing process is greater than or equal to 15 μm.

19. The preparation method according to claim 17, wherein The preparation of the first electrode comprises: Printing a metal layer on the first area of ​​the first surface using a screen printing process, wherein a process accuracy Y of the screen printing process is greater than or equal to 5 μm; The metal layer is sintered by adopting a sintering process to form a first electrode in ohmic contact with the silicon substrate.

20. The preparation method according to claim 16, wherein A difference between a width W of the first region and a width L of the first electrode is greater than or equal to 40 μm.

21. The preparation method according to claim 16, wherein The difference between the width W of the first region and the width L of the first electrode is less than or equal to 600 μm; or, A difference between a width W of the first region and a width L of the first electrode is less than or equal to 110 μm.

22. The preparation method according to claim 16, wherein Meet at least one of the following: The width of the first electrode is in the range of 5 μm to 40 μm; and The width of the first region is in the range of 45 μm to 640 μm or 45 μm to 150 μm.

23. The preparation method according to claim 17, wherein Meet at least one of the following: The average doping concentration of the first doping layer is less than or equal to the average doping concentration of the second doping layer; The average doping concentration of the first doping layer is 5E19cm -3 ~5E20cm -3 within the scope; and, The average doping concentration of the second doping layer is 1E20cm -3 ~5E20cm -3 within the range.

24. The preparation method according to claim 17, wherein Meet at least one of the following: The thickness of the first doping layer is greater than the thickness of the second doping layer; The thickness of the first doping layer is in the range of 30 nm to 300 nm or 100 nm to 200 nm; and, The thickness of the second doping layer is in the range of 5 nm to 100 nm or 10 nm to 50 nm.

25. The preparation method according to claim 17, further comprising: Prepare a second tunneling layer and a third doped layer stacked in sequence on the second surface, wherein the doping type of the third doped layer is opposite to that of the first doped layer; A second electrode is prepared on the second surface and is in contact with the third doping layer.

26. The preparation method according to claim 25, wherein The preparation of the second electrode comprises: Printing a metal layer on the second surface using a screen printing process; The metal layer is sintered by adopting a sintering process to form a second electrode in ohmic contact with the silicon substrate.

27. The preparation method according to claim 25, wherein The first doping layer, the second doping layer, and the third doping layer all include doped amorphous silicon layers, and the preparation method further includes: The first doped layer, the second doped layer and the third doped layer are annealed at a temperature within a range of 900° C. to 980° C. to convert the doped amorphous silicon layer into a doped polysilicon layer.

28. The preparation method according to claim 27, further comprising: preparing a second mask on the second doped layer to remove silicon oxide and amorphous silicon deposited on the surface and around the edges; preparing a third mask on the third doped layer to remove silicon oxide and polysilicon deposited on the surface and around the edges; The second mask and the third mask are removed and then cleaned.

29. The preparation method according to claim 16, further comprising at least one of the following: preparing a light trapping structure on at least one of the first surface and the second surface of the silicon substrate by a texturing process; Preparing a first anti-reflection layer on the first surface of the silicon substrate; and, A second anti-reflection layer is prepared on the second surface of the silicon substrate.

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