Inter-process communication method and apparatus, and electronic device, storage medium and computer program product

Abstract

Provided in the present disclosure are an inter-process communication method and apparatus, and an electronic device, a storage medium and a computer program product. The method comprises: setting different priorities for different IPC channels in a configuration table; and in response to an interrupt signal sent by a transmitting-end core, reading messages from message queues of the corresponding IPC channels in descending order of the priorities. In the solution of the present disclosure, a receiving-end core sets different priorities for different IPC channels in a configuration table, and a transmitting-end core acquires the priority of each message required to be sent to the receiving-end core; the transmitting-end core writes the messages into message queues of the IPC channels of the corresponding priorities, and sends an interrupt signal to the receiving-end core; and in response to the interrupt signal sent by the transmitting-end core, the receiving-end core may read a message, which has the highest priority, from the message queues of the corresponding IPC channels in descending order of the priorities, such that messages with high priorities can be preferentially processed by the receiving-end core.

Description

Inter-core communication method and device, electronic device, storage medium and computer program product

[0001] Cross-reference to Related Applications

[0002] The present application claims priority to the Chinese patent application No. 202410317413.6, filed on March 19, 2024, entitled "Inter-core communication method, device, electronic device and storage medium", the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of inter-core communication, and relates to but is not limited to an inter-core communication method, device, electronic device, storage medium and computer program product. BACKGROUND

[0004] In the related inter-core communication technology, for example, a sending core sends a message to a receiving core:

[0005] Both the sending core and the receiving core are built-in with a configuration table, wherein the configuration table mainly configures parameters for different Inter-Process Communication (IPC) channels. In the application process, the sending core and the receiving core establish an IPC channel by modifying the channel priority parameter in the configuration table statically, then the sending core writes the message to be transmitted into the message queue of the IPC channel, modifies the write index of the control block, and triggers an interrupt sending signal to the receiving core to notify the receiving core; after receiving the interrupt signal, the receiving core reads a message from the message queue of the IPC channel, modifies the read index of the control block, and then continues to process the next message in the IPC channel.

[0006] The messages in the above inter-core communication scheme are processed one by one according to the principle of first-in first-out of the message queue. If the sending core sends a message with a higher priority which needs to be transmitted to the receiving core for processing, according to the principle of first-in first-out of the message queue, the message with a higher priority can only be queued and cannot be processed by the receiving core in priority. SUMMARY

[0007] The present disclosure provides an inter-core communication method, device, electronic device, storage medium and computer program product.

[0008] According to a first aspect of the present disclosure, an inter-core communication method is provided, comprising:

[0009] Different priorities are set for different IPC channels in the configuration table, and the configuration table is a configuration table of different IPC channels preset;

[0010] In response to the interrupt signal sent by the sending kernel, messages are read from the message queue of the corresponding IPC channel in order of priority from high to low; the interrupt signal is used to indicate that the sending kernel has completed message writing to the message queue of the corresponding IPC channel.

[0011] In some embodiments of the present disclosure, in response to the interrupt signal sent by the sending kernel, messages are read from the message queue of the corresponding IPC channel in order of priority from high to low, including:

[0012] In response to the interrupt signal associated with the highest-priority IPC channel sent by the sending kernel, queue information in the message queue of the highest-priority IPC channel is obtained in order of priority, the queue information at least including a queue head address, a read index, and a write index;

[0013] The message in the queue address indicated by the read index and the queue head address is read;

[0014] The read index is updated using the read index incremented by 1 to obtain an updated read index;

[0015] The message in the queue address indicated by the updated read index and the queue head address is read;

[0016] It is determined whether the read index and the write index are the same;

[0017] If the determination result is yes, messages are read from the message queue of the highest-priority IPC channel in order of priority from high to low.

[0018] In some embodiments of the present disclosure, in response to the interrupt signal sent by the sending kernel, messages are read from the message queue of the corresponding IPC channel in order of priority from high to low, including:

[0019] In response to the interrupt signal associated with the highest-priority IPC channel sent by the sending kernel, messages are read from the message queue of the corresponding IPC channel in order of priority;

[0020] During the reading of the messages, if a new interrupt signal sent by the sending kernel is obtained, it is determined whether the IPC channel associated with the new interrupt signal is marked to ignore priority.

[0021] If the determination result is no, messages are read from the message queue of the corresponding IPC channel in order of priority from high to low.

[0022] According to a second aspect of the present disclosure, an inter-core communication method is provided, including:

[0023] The priority of each message in at least one message that needs to be sent to a receiving kernel is obtained;

[0024] write the message into the message queue of the IPC channel corresponding to the priority, and send an interrupt signal to the receiving end kernel; the interrupt signal is used to make the receiving end kernel read the message from the message queue of the corresponding IPC channel in order of priority from high to low.

[0025] In some embodiments of the present disclosure, writing the message into the message queue of the IPC channel corresponding to the priority comprises:

[0026] obtaining queue information of the message queue of the IPC channel corresponding to the priority of the message, the queue information at least including a queue head address and a write index;

[0027] writing the message into the queue address indicated by the write index and the queue head address;

[0028] updating the write index by incrementing the write index by 1.

[0029] In some embodiments of the present disclosure, after writing each message into the message queue of the IPC channel corresponding to the priority, the inter-core communication method provided by the present disclosure further comprises:

[0030] in response to the existence of a new message that needs to be sent to the receiving end kernel, obtaining the priority corresponding to the new message;

[0031] writing the new message into the message queue of the IPC channel corresponding to the priority, and sending an interrupt signal to the receiving end kernel.

[0032] In some embodiments of the present disclosure, sending the interrupt signal to the receiving end kernel comprises:

[0033] determining whether the receiving end kernel and the sending end kernel belong to the same processor;

[0034] if the determination result is yes, sending a software-triggered interrupt type interrupt signal to the receiving end kernel;

[0035] if the determination result is no, sending a shared peripheral interrupt type interrupt signal to the receiving end kernel.

[0036] According to a third aspect of the present disclosure, an inter-core communication device is provided, applied to a receiving end kernel, comprising:

[0037] a setting part configured to set different priorities for different IPC channels in a configuration table, the configuration table being a preset configuration table of different IPC channels;

[0038] a reading part configured to read a message from a message queue of a corresponding IPC channel in order of priority from high to low in response to an interrupt signal sent by a sending end kernel; the interrupt signal is used to indicate that the sending end kernel has completed writing of the message into the message queue of the corresponding IPC channel.

[0039] According to a fourth aspect of the present disclosure, an inter-core communication apparatus is provided, applied to a sending end core, comprising:

[0040] an obtaining part, configured to obtain a priority of each message in at least one message to be sent to a receiving end core;

[0041] a writing part, configured to write the message into a message queue of an IPC channel corresponding to the priority, and send an interrupt signal to the receiving end core; the interrupt signal is used to make the receiving end core read the message from the message queue of the corresponding IPC channel in order of priority from high to low.

[0042] According to a fifth aspect of the present disclosure, an electronic device is provided, comprising:

[0043] at least one processor; and

[0044] a memory in communication with the at least one processor;

[0045] The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform any possible method of the first aspect or the second aspect.

[0046] According to a sixth aspect of the present disclosure, a non-transitory computer readable storage medium storing computer instructions is provided, the computer instructions being used to make a computer execute any possible method of the first aspect or the second aspect.

[0047] According to a seventh aspect of the present disclosure, a computer program product is provided, comprising computer executable instructions or computer programs, which, when executed by a processor, implement any possible method of the first aspect or the second aspect.

[0048] The present disclosure provides an inter-core communication method, apparatus, electronic device, storage medium and computer program product. The inter-core communication method comprises: the receiving end core sets different priorities for different IPC channels in a configuration table, the configuration table being a preset configuration table of different IPC channels; the sending end core obtains a priority of each message in at least one message to be sent to the receiving end core; the message is written into a message queue of an IPC channel corresponding to the priority, and an interrupt signal is sent to the receiving end core; the interrupt signal is used to make the receiving end core read the message from the message queue of the corresponding IPC channel in order of priority from high to low. The receiving end core reads the message from the message queue of the corresponding IPC channel in order of priority from high to low in response to the interrupt signal sent by the sending end core; the interrupt signal is used to indicate that the sending end core has completed writing the message into the message queue of the corresponding IPC channel.

[0049] According to the scheme of the present disclosure, by setting different priorities for different IPC channels in the configuration table by the receiving end kernel, the sending end kernel obtains the priority of each message in at least one message that needs to be sent to the receiving end kernel; the message is written into the message queue of the IPC channel corresponding to the priority, and an interrupt signal is sent to the receiving end kernel; the receiving end kernel responds to the interrupt signal sent by the sending end kernel, and in the order of high to low priority, the message with the highest priority can be read from the message queue of the corresponding IPC channel, so that the message with high priority can be processed by the receiving end kernel in priority.

[0050] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present application, nor is it intended to limit the scope of the present application. Other features of the present application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0051] The accompanying drawings are used to better understand the present scheme and do not constitute a limitation on the present disclosure. Among them:

[0052] FIG. 1 is a flowchart of a first inter-core communication method according to an embodiment of the present disclosure;

[0053] FIG. 2 is a flowchart of a second inter-core communication method according to an embodiment of the present disclosure;

[0054] FIG. 3 is a schematic diagram of a first inter-core communication device according to an embodiment of the present disclosure;

[0055] FIG. 4 is a schematic diagram of a second inter-core communication device according to an embodiment of the present disclosure;

[0056] FIG. 5 is a flowchart of an inter-core communication method according to an application example of the present disclosure;

[0057] FIG. 6 is a schematic diagram of a multi-priority message processing process of a receiving end kernel according to an application example of the present disclosure;

[0058] FIG. 7 is a schematic block diagram of an example electronic device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0059] In order to more clearly understand the above-mentioned purposes, features and advantages of the present application, the scheme of the present application will be further described below. It should be noted that the embodiments of the present application and the features in the embodiments can be combined with each other without conflict.

[0060] In the following description, many specific details are set forth in order to provide a thorough understanding of the present application, but the present application can also be implemented in other ways different from those described herein; obviously, the embodiments in the description are only a part of the embodiments of the present application, not all the embodiments.

[0061] It should be noted that, in this document, relational terms such as "first" and "second", and the like can be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", "has", "having", "includes", "including", or any other variation thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a", "has... a", "includes... a", or "has... a" does not, without more constraints, preclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0062] In order for those skilled in the art to better understand the technical solutions described in the embodiments of the present disclosure, before introducing the embodiments of the present disclosure, first, the related terms in the present application are simply introduced:

[0063] Inter-core communication / inter-process communication: in the present application, it refers to the mechanism of mutual transmission of messages and sharing of resources between different processor cores / processes.

[0064] Mailbox interrupt: in the present application, it refers to an IPC implementation form based on hardware-specific memory access, which is commonly used for lightweight data communication (such as control information) between on-chip processors, has the advantages of good real-time performance, high communication efficiency, wide application range, etc., and is often used as an effective solution for heterogeneous core communication of vehicle-mounted real-time systems.

[0065] System on Chip (SoC): in the present application, it refers to a dedicated integrated circuit product containing a complete operating system and embedded software.

[0066] First In First Out (FIFO): in the present application, it refers to a first-in first-out data storage buffer.

[0067] The inter-core communication method provided by the embodiments of the present disclosure can be applied to a file system for managing a flash memory device, and the execution subject of the method can be a file system or a file management module in an operating system kernel.

[0068] As shown in FIG. 1, the first inter-core communication method provided by the embodiments of the present disclosure has a receiving end of inter-core communication as the execution subject, and the method includes the following steps:

[0069] Step 101, setting different priorities for different IPC channels in the configuration table, the configuration table being a preset configuration table of different IPC channels;

[0070] In an embodiment, the IPC channel refers to a channel for data communication between the sending kernel and the receiving kernel.

[0071] In an embodiment, both the sending kernel and the receiving kernel have a configuration table, which is used to configure the priorities and interrupt types of the IPC channels.

[0072] In an embodiment, the receiving kernel sets different priorities for different IPC channels in the configuration table.

[0073] In an embodiment, the configuration table includes information such as channel ID, reverse channel ID, channel type, channel priority, buffer queue size, and first address.

[0074] In an embodiment, different IPC channels correspond to different channel IDs.

[0075] In an embodiment, different priorities for different IPC channels in the configuration table can be achieved by changing the channel priority parameters corresponding to different IPC channels in the configuration table.

[0076] In an embodiment, a static configuration method is used to set different priorities for different IPC channels in the configuration table.

[0077] In an embodiment, the channel type is used to indicate the interrupt type of the trigger message notification.

[0078] In an embodiment, the channel type includes a software trigger interrupt type (such as a software generated interrupt (SGI)) and a shared peripheral interrupt type (such as a Mailbox interrupt).

[0079] In an embodiment, multiple priority levels can be set according to the requirements of the messages to be sent. For example, if the priority level of the message to be sent is low, fewer priority levels can be roughly divided; if the priority level of the message to be sent is high, more priority levels can be further divided.

[0080] In an embodiment, the priority of the IPC channel is used to indicate the order of message sending in different IPC channels, and messages in IPC channels with high priorities are processed first.

[0081] In an embodiment, only one IPC channel is configured in the configuration table, or no channel priority is set for a certain IPC channel, i.e., when reading different priority information, the specific configuration in the corresponding configuration table can be the reading priority order of the messages.

[0082] In step 102, in response to the interrupt signal sent by the sending end kernel, messages are read from the message queue of the corresponding IPC channel in order of priority from high to low.

[0083] In an embodiment, the messages can be control information, state information, image information, voice information, and the like.

[0084] In an embodiment, the interrupt signal is used to indicate that the sending end kernel has completed message writing to the message queue of the corresponding IPC channel. The type of the interrupt signal can be a software trigger interrupt type interrupt signal, or a shared peripheral interrupt type interrupt signal, and the type of the interrupt signal is determined by the judgment result of the sending end kernel judging the attributes of the sending end kernel and the receiving end kernel.

[0085] In an embodiment, the interrupt signal can be sent by the interrupt controller of the sending end kernel.

[0086] In an embodiment, when the configuration table includes a plurality of IPC channels with different priorities, each interrupt signal can correspond to an IPC channel.

[0087] In an embodiment, the interrupt signal sent by the sending end kernel is obtained, and the message queue of the current IPC channel and the message queue of all IPC channels with a higher priority than the current IPC channel are traversed to read the message with the highest priority.

[0088] The inter-core communication method provided by the embodiments of the present disclosure includes: setting different priorities for different IPC channels in a configuration table, the configuration table being a configuration table of different IPC channels preset; in response to an interrupt signal sent by a sending end kernel, reading messages from a message queue of a corresponding IPC channel in order of priority from high to low; and the interrupt signal being used to indicate that the sending end kernel has completed message writing to the message queue of the corresponding IPC channel.

[0089] According to the scheme of the present disclosure, the receiving end kernel sets different priorities for different IPC channels in a configuration table, and the sending end kernel obtains the priority of each message in at least one message to be sent to the receiving end kernel; the message is written to the message queue of the IPC channel corresponding to the priority, and an interrupt signal is sent to the receiving end kernel; and in response to the interrupt signal sent by the sending end kernel, the receiving end kernel can read the message with the highest priority from the message queue of the corresponding IPC channel in order of priority from high to low, so that the message with a high priority can be processed by the receiving end kernel in priority.

[0090] In Embodiment 1, in the scenario of configuring multiple different priority levels of IPC channels for a configuration table, in response to an interrupt signal sent by a sending kernel, messages are read from a message queue of a corresponding IPC channel in order of priority from high to low, including:

[0091] In response to an interrupt signal associated with an IPC channel of the highest priority sent by the sending kernel, queue information in the message queue of the IPC channel of the highest priority is obtained in order of priority.

[0092] In an embodiment, the queue information at least includes a queue head address, a read index, and a write index.

[0093] In an embodiment, the queue information of the message queue of the IPC channel is generally stored in a control block of the IPC channel.

[0094] In an embodiment, the queue head address is used to indicate an address of a first message in the current message queue.

[0095] In an embodiment, the read index is used to indicate index information of a message to be read, i.e., an offset based on the queue head address.

[0096] In an embodiment, the write index is used to indicate index information of a message to be written.

[0097] Reading a message in a queue address indicated by the read index and the queue head address;

[0098] In an embodiment, after reading the message in the queue address indicated by the read index and the queue head address, the read message is passed into an IPC callback function registered in the control block for processing.

[0099] Updating the read index by using the read index incremented by 1 to obtain an updated read index;

[0100] In an embodiment, the updated read index is used to indicate index information of a message to be read next in the message queue of the current priority level.

[0101] In an embodiment, by updating the read index by using the read index incremented by 1, messages in the message queue of the current priority level can be read in turn.

[0102] Reading a message in a queue address indicated by the updated read index and the queue head address;

[0103] In an embodiment, the message in the queue address indicated by the updated read index and the queue head address is adjacent to the message in the queue address indicated by the read index and the queue head address before updating.

[0104] Determining whether the read index and the write index are the same;

[0105] In an embodiment, if the read index and the write index are the same, it indicates that the message queue is empty, i.e. there is no message in the message queue.

[0106] If the result of the judgment is yes, messages are read from the message queues of the IPC channels except the one with the highest priority in order of priority from high to low.

[0107] In an embodiment, if the read index and the write index are the same, it indicates that the messages in the message queue of the IPC channel with the highest priority have been read, and messages need to be read from the message queues of the IPC channels except the one with the highest priority.

[0108] In an embodiment, if the read index and the write index are different, messages continue to be read from the message queue of the IPC channel with the highest priority.

[0109] It should be noted that Embodiment 1 and steps 101-102 can be combined.

[0110] In Embodiment 2, in the case of a configuration table in which only one IPC channel is configured, or in the case of an IPC channel for which no channel priority is set, i.e. it is configured to read messages of different priorities, the specific configuration in the corresponding configuration table can be the order of reading priority of the read messages. In step 102, it includes:

[0111] In response to the interrupt signal associated with the highest priority IPC channel sent by the sending kernel, messages are read from the message queue of the corresponding IPC channel in order of priority.

[0112] In an embodiment, the interrupt signal is used to indicate that there is a newly written message in the message queue.

[0113] In an embodiment, after reading each message, all addresses in the message queue of each IPC channel need to be traversed in order of priority from high to low, and the message in the address with the highest priority is read.

[0114] During the reading of the messages, if a new interrupt signal sent by the sending kernel is obtained, it is judged whether the IPC channel associated with the new interrupt signal is marked to ignore the priority.

[0115] In an embodiment, the new interrupt signal sent by the sending kernel can be obtained by the interrupt controller of the receiving kernel.

[0116] In an embodiment, the receiving kernel can be the same as or different from the processor used by the sending kernel.

[0117] In an embodiment, the IPC channel associated with the new interrupt signal refers to the IPC channel that receives the new interrupt signal.

[0118] In an embodiment, the mark-ignoring priority refers to that the IPC channel is not marked with a priority.

[0119] In an embodiment, if the IPC channel associated with the interrupt signal is marked with the mark-ignoring priority, the application scenario of the inter-core communication method proposed in the present disclosure is not met.

[0120] If the result is no, the messages are read from the message queue of the corresponding IPC channel in the order of high to low priority.

[0121] In an embodiment, if the IPC channel associated with the interrupt signal is not marked with the mark-ignoring priority, i.e., the priority of the IPC channel is marked, the application scenario of the inter-core communication method proposed in the present disclosure is met, and the message in the first address of the message queue of the IPC channel with the highest priority needs to be obtained in the order of high to low priority of the IPC channel.

[0122] It should be noted that the embodiment 2 can be combined with steps 101-102, and in some special application scenarios, for example, when the configuration table includes not only the IPC channels with different priorities but also the IPC channel marked with the mark-ignoring priority, the embodiment 1, the embodiment 2, and steps 102-102 can also be combined, and the specific implementation can be determined by the actual situation, which is not limited here.

[0123] As shown in FIG. 2, the second inter-core communication method provided by the embodiment of the present disclosure has the sending end core of the inter-core communication as the execution subject, and the method includes the following steps:

[0124] Step 201: obtaining the priority of each message in at least one message to be sent to the receiving end core;

[0125] In an embodiment, the priorities of the multiple messages in the at least one message can be the same or different.

[0126] In an embodiment, the priority of each message in the at least one message to be sent to the receiving end core can be obtained by setting the priority parameter in RabbitMQ.

[0127] Step 202: writing the message into the message queue of the IPC channel corresponding to the priority, and sending an interrupt signal to the receiving end core; the interrupt signal is used to make the receiving end core read the message from the message queue of the corresponding IPC channel in the order of high to low priority.

[0128] In an embodiment, when the IPC channel is marked with the mark-ignoring priority, the messages in the message queue of the IPC channel can be read according to the first-in first-out principle.

[0129] In an embodiment, when the IPC channel is not marked to ignore priority, messages in the message queue of the IPC channel can be read in the order of priority.

[0130] In embodiment 3, writing a message into the message queue of the IPC channel corresponding to the priority includes:

[0131] Obtaining queue information of the message queue of the IPC channel corresponding to the priority of the message;

[0132] In an embodiment, the queue information at least includes a queue head address and a write index.

[0133] In an embodiment, the IPC channel corresponding to the priority of the message is obtained, for example, if there are three priority levels of IPC channels, high, medium and low, message 1 is a very urgent message, which belongs to the high priority IPC channel, message 4 is a general urgent message, which belongs to the medium priority IPC channel, and message 7 is a non-urgent message, which belongs to the low priority IPC channel.

[0134] In an embodiment, the queue information of the message queue of the IPC channel corresponding to the priority of the message at least includes a queue head address and a write index, that is, the queue information of the message queue of the IPC channel corresponding to the priority of the message in the foregoing embodiment is obtained, for example, the queue information of the message queue of the high priority IPC channel corresponding to the priority of message 1 at least includes a queue head address and a write index.

[0135] Writing the message into the queue address indicated by the write index and the queue head address;

[0136] In an embodiment, the queue address of the message queue is limited, which can be 100 or 1000, which is not limited in the present disclosure.

[0137] In an embodiment, the message is written into the queue address indicated by the write index and the queue head address in the message queue of the IPC channel corresponding to the priority of the message.

[0138] The write index is updated by using the write index after incrementing 1.

[0139] In an embodiment, the updated write index is used to indicate the index information of the next message written into the message queue of the current priority IPC channel.

[0140] It should be noted that embodiment 3 can be combined with steps 201-202 to implement.

[0141] In embodiment 4, after writing the message into the message queue of the IPC channel corresponding to the priority, the inter-core communication method further includes:

[0142] In response to the existence of a new message that needs to be sent to the receiving end core, obtaining the priority corresponding to the new message;

[0143] In an embodiment, the new message is a message newly written into the message queue by the sending kernel.

[0144] In an embodiment, the new message can have one or more.

[0145] The new message is written into the message queue of the IPC channel corresponding to the priority, and an interrupt signal is sent to the receiving kernel.

[0146] In an embodiment, after receiving the interrupt signal, the receiving kernel reiterates the message queues of all the IPC channels to obtain the message in the message queue with the highest current priority.

[0147] It should be noted that embodiment 4 can be combined with steps 201-202; embodiment 4 can also be combined with embodiment 3 and then combined with steps 201-202, and the specific combination process can be realized by actual application scenarios, which is not limited here.

[0148] In embodiment 5, sending an interrupt signal to the receiving kernel includes:

[0149] Judging whether the receiving kernel and the sending kernel belong to the same processor;

[0150] In an embodiment, the processor information of the receiving kernel and the sending kernel can be obtained from the configuration information related to the receiving kernel and the sending kernel.

[0151] If the judgment result is yes, a software-triggered interrupt type interrupt signal is sent to the receiving kernel;

[0152] In an embodiment, the software-triggered interrupt type interrupt signal refers to an interrupt signal generated by software by writing a special register.

[0153] If the judgment result is no, a shared peripheral interrupt type interrupt signal is sent to the receiving kernel.

[0154] In an embodiment, the shared peripheral interrupt type interrupt signal refers to an interrupt signal sent by an external device accessible by the system.

[0155] In an embodiment, the external device can be a keyboard, a network adapter, a hard drive, etc.

[0156] In an embodiment, the shared peripheral interrupt type interrupt signal can be triggered by level or edge.

[0157] In an embodiment, the shared peripheral interrupt type interrupt signal can be generated by Mailbox.

[0158] It should be noted that the embodiment 5 can be combined with steps 201-202; the embodiment 5 can also be combined with the embodiment 4, and then combined with steps 201-202; the embodiment 5 can also be combined with the embodiment 3 and the embodiment 4, and then combined with steps 201-202, and the specific implementation process can be determined by the actual application scenario, which is not limited here.

[0159] According to the scheme of the present disclosure:

[0160] Firstly, the sending end kernel obtains the priority of each message in at least one message to be sent to the receiving end kernel by setting different priorities for different IPC channels in the configuration table through the receiving end kernel; the message is written into the message queue of the IPC channel corresponding to the priority, and an interrupt signal is sent to the receiving end kernel; the receiving end kernel responds to the interrupt signal sent by the sending end kernel, and can read the message with the highest priority from the message queue of the corresponding IPC channel in the order of priority from high to low, so that the message with high priority can be processed by the receiving end kernel in priority.

[0161] Secondly, the message with the highest priority is written into the first address of the message queue of the IPC channel corresponding to the priority according to the order of the priority of the message, and considering that the message queue reads and writes messages according to the principle of first in first out, the message with high priority can be written in front of the message queue, so that the message with high priority can be read first.

[0162] The inter-core communication method of the present disclosure is further described below with a specific application example. Correspondingly, the scenario of this embodiment can be that there is a need to deliver messages with different emergency levels between two cores, and multiple IPC channels can be statically configured between the two cores, and the channels are marked with different priority levels. Among them, multiple IPC channels can be obtained by flexibly dividing priority levels according to business needs, that is, if N levels are subdivided, at least N IPC channels need to be established; if there is no such need, only one IPC channel can be configured, or multiple IPC channels can be marked with the same priority level or ignore the priority level, but different priority messages can be transmitted in the same IPC channel, and the messages can be processed according to the priority of the messages during transmission.

[0163] FIG. 5 is a flowchart of an inter-core communication method provided by an application example of the present disclosure, as shown in FIG. 5, the inter-core communication method provided by the application example of the present disclosure includes the following steps:

[0164] Step 501, the receiving end kernel sets different priorities for different IPC channels in the configuration table, and the configuration table is a preset configuration table of different IPC channels;

[0165] Step 502, the sending end kernel obtains the priority of each message in at least one message to be sent to the receiving end kernel;

[0166] Step 503, the sending end kernel obtains the queue information of the message queue of the IPC channel corresponding to the priority of the message, the queue information at least including the queue head address and the write index;

[0167] Step 504, the sending end kernel writes the message into the queue address indicated by the write index and the queue head address;

[0168] In an embodiment, the sending end kernel updates the write index by using the write index increased by 1;

[0169] Step 505, the sending end kernel obtains the priority of a new message in response to the existence of the new message to be sent to the receiving end kernel;

[0170] Step 506, the sending end kernel writes the new message into the message queue of the IPC channel corresponding to the priority;

[0171] Step 507, it is judged whether the receiving end kernel and the sending end kernel belong to the same processor;

[0172] If the judgment result is yes, step 508 is entered;

[0173] If the judgment result is no, step 509 is entered;

[0174] Step 508, the sending end kernel sends a software-triggered interrupt type interrupt signal to the receiving end kernel;

[0175] Step 509, the sending end kernel sends a shared peripheral interrupt type interrupt signal to the receiving end kernel;

[0176] Step 510, the receiving end kernel obtains the interrupt signal sent by the sending end kernel in response to the interrupt signal sent by the sending end kernel; the interrupt signal is used to indicate that the sending end kernel has completed the message writing into the message queue of the corresponding IPC channel;

[0177] Step 511, in response to the interrupt signal associated with the IPC channel of the highest priority sent by the sending end kernel, the receiving end kernel obtains the queue information of the message queue of the IPC channel of the highest priority in the order of priority, the queue information at least including the queue head address, the read index and the write index;

[0178] Step 512, the receiving end kernel reads the message in the queue address indicated by the read index and the queue head address;

[0179] Step 513, the receiving end kernel updates the read index by using the read index increased by 1 to obtain the updated read index;

[0180] Step 514, the receiving end kernel reads the updated read index and the message in the queue address indicated by the queue head address;

[0181] Step 515, it is judged whether the read index and the write index are the same;

[0182] If the judgment result is yes, step 516 is entered;

[0183] If the judgment result is no, step 513 is returned;

[0184] Step 516, according to the order from high to low of the priority, the messages are read from the message queue of the IPC channel except the message queue of the highest priority IPC channel.

[0185] In an embodiment, the receiving end kernel updates the read index by incrementing 1 until the read index and the write index are the same.

[0186] In an embodiment, as shown in Figure 6, the receiving end kernel multi-priority message processing process diagram.

[0187] Four IPC channels are established between the sending end kernel and the receiving end kernel, and the priorities of the four IPC channels are sequentially increased from bottom to top. The numbers in the blocks in the figure represent the order of message processing. The messages corresponding to 1, 2, 3, 5, 6, 8, and 9 are the messages to be processed in each channel at the initial moment (i.e., when the interrupt service is entered after receiving the L1 channel interrupt notification). The message corresponding to 4 is the message sent during the processing of message 3. The message corresponding to 7 is the message sent during the processing of message 6. The specific processing process is as follows:

[0188] Prepare to process the message of the L1 channel. First, detect and process the message 1 of the L3 channel, and then process the message 2 of the L3 channel. At this time, there is no unprocessed message in the L3 channel, and the L2 channel is entered.

[0189] After processing the message 3 of the L2 channel, it is detected that there is a message 4 in the L3 channel with a higher priority, and then the message 4 of the L3 channel is processed. At this time, there is no unprocessed message in the L3 channel, and the L2 channel is entered.

[0190] After processing the message 5 of the L2 channel, it is detected that there is no unprocessed message in the L3 channel and the L2 channel in turn, and the L1 channel is entered.

[0191] After processing the message 6 of the L1 channel, it is detected that there is no unprocessed message in the L3 channel, but there is a new message 7 in the L2 channel, and then the message 7 of the L2 channel is processed first, and then the message 8 and the message 9 of the L1 channel are processed.

[0192] In an embodiment, a plurality of message queues with different priorities can be placed in different buffer areas of an IPC channel to save interrupt resources.

[0193] Corresponding to the above-mentioned inter-core communication method, the present application also provides an inter-core communication device. Since the device embodiment of the present application corresponds to the above-mentioned method embodiment, for the details not disclosed in the device embodiment, reference can be made to the above-mentioned method embodiment, which will not be described in detail herein.

[0194] Fig. 3 is a structural schematic diagram of a first inter-core communication device provided by the embodiment of the present disclosure. As shown in Fig. 3, the inter-core communication device 300 comprises:

[0195] The setting part 301 is configured to set different priorities for different IPC channels in the configuration table, and the configuration table is a preset configuration table of different IPC channels;

[0196] The reading part 302 is configured to read messages from the message queue of the corresponding IPC channel in the order from high to low priority in response to the interrupt signal sent by the sending core; and the interrupt signal is used to indicate that the sending core has completed the message writing of the message queue of the corresponding IPC channel.

[0197] In an embodiment, the reading part 302 is specifically configured to:

[0198] In response to the interrupt signal associated with the IPC channel of the highest priority sent by the sending core, the queue information in the message queue of the IPC channel of the highest priority is obtained in the order of priority, and the queue information at least includes the queue head address, the read index and the write index;

[0199] The message in the queue address indicated by the read index and the queue head address is read;

[0200] The read index is updated by using the read index incremented by 1 to obtain an updated read index;

[0201] The message in the queue address indicated by the updated read index and the queue head address is read;

[0202] It is judged whether the read index and the write index are the same;

[0203] If the result of the judgment is yes, the messages are read from the message queues of the IPC channels other than the message queue of the IPC channel of the highest priority in the order from high to low priority.

[0204] In an embodiment, the reading part 302 is specifically configured to:

[0205] In response to the interrupt signal associated with the IPC channel of the highest priority sent by the sending core, the messages are read from the message queue of the corresponding IPC channel in the order of priority;

[0206] In the process of reading the messages, if a new interrupt signal sent by the sending core is obtained, it is judged whether the IPC channel associated with the new interrupt signal is marked to ignore the priority.

[0207] If the result is no, messages are read from the message queue of the corresponding IPC channel in order of priority from high to low.

[0208] FIG. 4 is a structural schematic diagram of a second inter-core communication device according to an embodiment of the present disclosure. As shown in FIG. 4, the inter-core communication device 400 includes:

[0209] The obtaining part 401 is configured to obtain a priority of each of at least one message to be sent to a receiving end core;

[0210] The writing part 402 is configured to write the message into a message queue of an IPC channel corresponding to the priority, and send an interrupt signal to the receiving end core; the interrupt signal is used to make the receiving end core read the message from the message queue of the corresponding IPC channel in order of priority from high to low.

[0211] In an embodiment, the writing part 402 is specifically configured to:

[0212] Obtain queue information of the message queue of the IPC channel corresponding to the priority of the message, the queue information at least including a queue head address and a write index;

[0213] Write the message into a queue address indicated by the write index and the queue head address;

[0214] Update the write index by using the write index incremented by 1.

[0215] In an embodiment, the inter-core communication device 400 further includes an interrupt sending part, and the interrupt sending part is configured to:

[0216] In response to the existence of a new message to be sent to the receiving end core, obtain a priority corresponding to the new message;

[0217] Write the new message into a message queue of an IPC channel corresponding to the priority, and send an interrupt signal to the receiving end core.

[0218] In an embodiment, the interrupt sending part is further configured to:

[0219] Determine whether the receiving end core and the sending end core belong to the same processor;

[0220] If the result is yes, send a software-triggered interrupt type interrupt signal to the receiving end core;

[0221] If the result is no, send a shared peripheral interrupt type interrupt signal to the receiving end core.

[0222] It should be noted that the foregoing explanation and description of the method embodiments are also applicable to the device of the present embodiment, and the principles are the same, which are not limited in the present embodiment.

[0223] According to an embodiment of the present disclosure, the present disclosure further provides an electronic device.

[0224] Specifically, the embodiment of the present disclosure provides an electronic device, comprising:

[0225] at least one processor; and

[0226] a memory connected with the at least one processor in communication; wherein

[0227] The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the steps of the aforementioned inter-core communication method.

[0228] The embodiment of the present disclosure provides a non-transitory computer readable storage medium storing computer instructions, wherein the computer instructions are used to make a computer execute the steps of the aforementioned inter-core communication method.

[0229] The embodiment of the present disclosure provides a computer program product comprising computer executable instructions or computer programs, wherein the computer executable instructions or computer programs are executed by a processor to implement the steps of the aforementioned inter-core communication method.

[0230] FIG. 7 shows a schematic block diagram of an example electronic device 700 that can be used to implement embodiments of the present disclosure. The electronic device is intended to represent various forms of digital computers, such as laptops, desktops, tablets, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular telephones, smart phones, wearable devices, in-vehicle devices, and other similar computing devices. The components shown here, their connections and relationships, and their functions, are meant to be examples only, and are not meant to limit implementations of the present disclosure described and / or claimed in this document.

[0231] As shown in FIG. 7, the electronic device 700 includes a computing unit 701 that can perform various appropriate actions and processes according to a computer program stored in a ROM (Read-Only Memory) 702 or a computer program loaded into a RAM (Random Access Memory) 703 from a storage unit 708. In the RAM 703, various programs and data required for the operation of the device 700 can also be stored. The computing unit 701, the ROM 702, and the RAM 703 are connected to each other through a bus 704. An I / O (Input / Output) interface 705 is also connected to the bus 704.

[0232] A plurality of components in the device 700 are connected to the I / O interface 705, including: an input unit 706, such as a keyboard, a mouse, etc.; an output unit 707, such as various types of displays, speakers, etc.; a storage unit 708, such as a magnetic disk, an optical disk, etc.; and a communication unit 709, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 709 allows the device 700 to exchange information / data with other devices through computer networks, such as the Internet, and / or various telecommunication networks.

[0233] The computing unit 701 can be various general and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 701 include, but are not limited to, a CPU (Central Processing Unit), a GPU (Graphic Processing Unit), various special-purpose AI (Artificial Intelligence) computing chips, various computing units running machine learning model algorithms, a DSP (Digital Signal Processor), and any appropriate processor, controller, microcontroller, etc. The computing unit 701 performs various methods and processes described above, such as the inter-core communication method. For example, in some embodiments, the inter-core communication method can be implemented as a computer software program, which is tangibly embodied in a machine-readable medium, such as the storage unit 708. In some embodiments, part or all of the computer program can be loaded and / or installed on the device 700 via the ROM 702 and / or the communication unit 709. When the computer program is loaded into the RAM 703 and executed by the computing unit 701, one or more steps of the methods described above can be performed. Alternatively, in other embodiments, the computing unit 701 can be configured to perform the aforementioned inter-core communication method by other any appropriate means, such as by means of firmware.

[0234] Various implementations of the systems and techniques described above can be realized in digital electronic circuitry, integrated circuitry, a Field Programmable Gate Array (FPGA), an Application-Specific Integrated Circuit (ASIC), an Application Specific Standard Product (ASSP), a System on a Chip (SOC), a Complex Programmable Logic Device (CPLD), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include implementation in one or more computer programs that are executable and / or interpretable on a programmable system including at least one programmable processor, which can be special or general purpose, coupled to receive data and instructions from, and to transmit data and instructions to, a storage system, at least one input device, and at least one output device.

[0235] Program code for carrying out methods of the present disclosure can be written in any combination of one or more programming languages. This program code can be provided to a processor or controller of a general or special purpose computer, such that the program code, when executed by the processor or controller, causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code can be implemented in a wholly in machine language, in partially in machine language, in partially in a high level language, and other combinations thereof. The program code can execute entirely on the machine, partly on the machine as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.

[0236] In the context of this disclosure, a machine-readable medium can be a tangible medium that contains or stores a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include but is not limited to an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of the machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer disk, a hard disk, RAM, ROM, EPROM (Electrically Programmable Read-Only-Memory), or flash memory, an optical fiber, a CD-ROM (Compact Disc Read-Only Memory), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0237] It should be understood that the various forms of flow shown above can be reordered, additional or deleted steps can be used. For example, the steps described in the present disclosure can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in the present disclosure can be achieved, which are not limited herein.

[0238] The above is merely a specific implementation of the present application, and those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described system, module and unit can refer to the corresponding processes in the foregoing method embodiments, which will not be described here. It should be understood that the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be covered within the protection scope of the present application. Industrial applicability

[0239] The present application discloses a kind of inter-core communication method, device, electronic equipment, storage medium and computer program product.The described method includes: different priority is set for different IPC channel in configuration table;In response to the interrupt signal sent by sending end kernel, according to the order of priority from high to low, message is read from the message queue of corresponding IPC channel.According to the scheme of the present disclosure, the message with the highest priority can be read from the message queue of corresponding IPC channel according to the order of priority from high to low, so that the message with high priority can be preferentially processed by receiving end kernel.

Claims

1. A method for inter-core communication, applied to a receiving core, comprising: setting different priorities for different IPC channels in a configuration table, the configuration table being a configuration table of different IPC channels preset; reading messages from message queues of the corresponding IPC channels in order of the priorities from high to low in response to an interrupt signal sent by a sending core, the interrupt signal being used to indicate that the sending core has completed message writing to the message queues of the corresponding IPC channels.

2. The method of claim 1, wherein, The reading messages from the message queues of the corresponding IPC channels in response to the interrupt signal sent by the sending core, comprises: in response to the interrupt signal associated with the IPC channel of the highest priority sent by the sending core, obtaining queue information in the message queue of the IPC channel of the highest priority in order of the priorities, the queue information at least including a queue head address, a read index and a write index; reading messages in the queue address indicated by the read index and the queue head address; updating the read index by using the read index incremented by 1 to obtain an updated read index; reading messages in the queue address indicated by the updated read index and the queue head address; judging whether the read index and the write index are the same; if the result of the judgment is yes, reading messages from the message queues of the IPC channels other than the message queue of the IPC channel of the highest priority in order of the priorities from high to low.

3. The method of claim 1, wherein, The reading messages from the message queues of the corresponding IPC channels in response to the interrupt signal sent by the sending core, comprises: in response to the interrupt signal associated with the IPC channel of the highest priority sent by the sending core, reading messages from the message queues of the corresponding IPC channels in order of the priorities; in the process of reading messages, if a new interrupt signal sent by the sending core is obtained, judging whether the IPC channel associated with the new interrupt signal is marked to ignore the priority; if the result of the judgment is no, reading messages from the message queues of the corresponding IPC channels in order of the priorities from high to low. 4.A method for inter-core communication, applied to a sending core, comprising: obtaining a priority of each message of at least one message needed to be sent to a receiving core; writing the message to a message queue of an IPC channel corresponding to the priority and sending an interrupt signal to the receiving core, the interrupt signal being used to make the receiving core read messages from the message queues of the corresponding IPC channels in order of the priorities from high to low.

5. The method of claim 4, wherein, The writing the message to the message queue of the IPC channel corresponding to the priority, comprises: obtaining queue information of the message queue of the IPC channel corresponding to the priority of the message, the queue information at least including a queue head address and a write index; writing the message to a queue address indicated by the write index and the queue head address; updating the write index by using the write index incremented by 1.

6. The method of claim 4 or 5, wherein, After the writing of each of the messages into the message queue of the IPC channel corresponding to the priority, the method further comprises: in response to the existence of a new message needing to be sent to the receiving end kernel, acquiring a priority corresponding to the new message; writing the new message into the message queue of the IPC channel corresponding to the priority, and sending an interrupt signal to the receiving end kernel.

7. The method according to any one of claims 4 to 6, wherein, The sending of the interrupt signal to the receiving end kernel comprises: judging whether the receiving end kernel and the sending end kernel belong to the same processor; if the result of the judgment is yes, sending a software-triggered interrupt type interrupt signal to the receiving end kernel; if the result of the judgment is no, sending a shared peripheral interrupt type interrupt signal to the receiving end kernel.

8. An inter-core communication device applied to a receiving end kernel, comprising: a setting part configured to set different priorities for different IPC channels in a configuration table, the configuration table being a preset configuration table of different IPC channels; a reading part configured to, in response to an interrupt signal sent by a sending end kernel, read messages from the message queue of the corresponding IPC channel in the order from high to low according to the priorities; the interrupt signal being used to indicate that the sending end kernel has completed the writing of messages into the message queue of the corresponding IPC channel.

9. An inter-core communication device applied to a sending end kernel, comprising: an acquiring part configured to acquire a priority of each of at least one message needing to be sent to a receiving end kernel; a writing part configured to write the messages into the message queue of the IPC channel corresponding to the priority, and send an interrupt signal to the receiving end kernel; the interrupt signal being used to make the receiving end kernel read messages from the message queue of the corresponding IPC channel in the order from high to low according to the priorities.

10. An electronic device, comprising: at least one processor; and a memory connected to the at least one processor in communication; the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the method of any one of claims 1 to 3, or claims 4 to 7.

11. A non-transitory computer-readable storage medium storing computer instructions, the computer instructions being used to make the computer execute the method according to any one of claims 1 to 3, or claims 4 to 7.

12. A computer program product comprising computer executable instructions or a computer program, the computer executable instructions or the computer program being executed by a processor to implement the method of any one of claims 1 to 3, or claims 4 to 7. ​

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