Semiconductor device

Abstract

The present invention provides a transistor having favorable electrical characteristics. This semiconductor device includes such a transistor. The transistor has an oxide semiconductor layer as a semiconductor layer. The oxide semiconductor layer has a source region and a drain region of the transistor, and a channel formation region located between the source region and the drain region. The oxide semiconductor layer may contain indium oxide. The concentration of at least one of yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, and a light rare earth element in the source region and the drain region is higher than the concentration of that in the channel formation region.

Description

Semiconductor Devices

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a memory device, a display device, and an electronic device. Another embodiment of the present invention relates to a manufacturing method of a semiconductor device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), driving methods thereof, and manufacturing methods thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be semiconductor devices and each may have a semiconductor device.

[0004] In recent years, the development of semiconductor devices has progressed, and semiconductor devices mainly use LSIs (Large Scale Integration), CPUs (Central Processing Units), memories (storage devices), etc. A CPU is an aggregate of semiconductor elements that have integrated circuits (including transistors and memories) formed into chips by processing a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0005] 2. Description of the Related Art Integrated circuits (ICs) such as LSIs, CPUs, or memories are mounted on circuit boards, such as printed wiring boards, and are used as components of various electronic devices.

[0006] Furthermore, a technology for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. Such transistors are widely applied to electronic devices such as integrated circuits (ICs) and display devices. While silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, oxide semiconductors have also attracted attention as other materials.

[0007] Furthermore, it is known that a transistor using an oxide semiconductor has an extremely small leakage current in an off state. For example, Patent Document 1 discloses a CPU with low power consumption that utilizes the property of a transistor using an oxide semiconductor that has a small leakage current. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time by utilizing the property of a transistor using an oxide semiconductor that has a small leakage current.

[0008] In addition, with the recent trend toward smaller and lighter electronic devices, there is an increasing demand for higher density integrated circuits. There is also a demand for improved productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technique for increasing the density of integrated circuits by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film to provide multiple memory cells in an overlapping manner. Patent Document 4 discloses a technique for increasing the density of integrated circuits by vertically arranging the channel of a transistor using an oxide semiconductor film.

[0009] JP 2012-257187 A JP 2011-151383 A WO 2021 / 053473 JP 2013-211537 A

[0010] M. Oota et al. , “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig. , 2019, pp. 50-53

[0011] An object of one embodiment of the present invention is to provide a transistor with favorable electrical characteristics.An object of one embodiment of the present invention is to provide a transistor with large on-state current.An object of one embodiment of the present invention is to provide a transistor with small parasitic capacitance.An object of one embodiment of the present invention is to provide a highly reliable transistor, semiconductor device, memory device, or display device.An object of one embodiment of the present invention is to provide a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated.An object of one embodiment of the present invention is to provide a semiconductor device, memory device, or display device with low power consumption.An object of one embodiment of the present invention is to provide a memory device with high operating speed.An object of one embodiment of the present invention is to provide a display device with high definition or a high aperture ratio.An object of one embodiment of the present invention is to provide a manufacturing method of the transistor, semiconductor device, memory device, or display device.

[0012] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0013] One embodiment of the present invention is a semiconductor device including a transistor. The transistor includes an oxide semiconductor layer. The oxide semiconductor layer includes a source region, a drain region, and a channel formation region located between the source region and the drain region. The oxide semiconductor layer includes indium oxide. The concentrations of a first element in the source region and the drain region are higher than the concentration of the first element in the channel formation region. The first element is at least one of yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, and a light rare earth element.

[0014] Alternatively, in the above aspect, the semiconductor device may include a first layer and a second layer, the first layer being in contact with an upper surface of the oxide semiconductor layer in a region between a source region and a channel formation region, the second layer being in contact with an upper surface of the oxide semiconductor layer in a region between a drain region and a channel formation region, the source electrode of the transistor having a region in contact with the source region and a region located on the first layer, and the drain electrode of the transistor having a region in contact with the drain region and a region located on the second layer.

[0015] Alternatively, one embodiment of the present invention includes a transistor, a first layer, and a second layer. The transistor includes an oxide semiconductor layer. The oxide semiconductor layer has a source region, a drain region, and a channel formation region located between the source region and the drain region. The oxide semiconductor layer includes indium oxide. The first layer is in contact with a top surface of a region between the source region and the channel formation region of the oxide semiconductor layer. The second layer is in contact with a top surface of a region between the drain region and the channel formation region of the oxide semiconductor layer. A source electrode of the transistor has a region in contact with the source region and a region located over the first layer. the source electrode has a region in contact with the drain region and a region located on the second layer; the gate insulating layer of the transistor has a region located between the first layer and the second layer and a region located between the source electrode and the drain electrode; the gate electrode of the transistor is provided on the gate insulating layer so as to overlap with the channel formation region; the concentrations of the first element in the source region and the drain region are higher than the concentration of the first element in the channel formation region, and the first element is at least one of yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, and a light rare earth element.

[0016] Alternatively, in the above aspect, the first element may be at least one of yttrium, zirconium, silver, cadmium, tin, and antimony.

[0017] Alternatively, in the above aspect, the first layer and the second layer may each be an oxide layer containing indium, zinc, and a second element, and the second element may be one or more of gallium, aluminum, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony.

[0018] Alternatively, in the above embodiment, an oxide layer may be provided, the oxide semiconductor layer may be provided in contact with a top surface of the oxide layer, and the oxide layer may have cubic crystal grains.

[0019] Alternatively, in the above embodiment, the degree of lattice mismatch between the crystal grains of the oxide semiconductor layer and the crystal grains of the oxide layer may be greater than or equal to 0% and less than or equal to 10%.

[0020] Alternatively, in the above aspect, the oxide layer may include yttrium, zirconium, and oxygen.

[0021] According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be provided. According to one embodiment of the present invention, a transistor with large on-state current can be provided. According to one embodiment of the present invention, a transistor with small parasitic capacitance can be provided. According to one embodiment of the present invention, a highly reliable transistor, semiconductor device, memory device, or display device can be provided. According to one embodiment of the present invention, a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device, memory device, or display device with low power consumption can be provided. According to one embodiment of the present invention, a memory device with high operating speed can be provided. According to one embodiment of the present invention, a display device with high definition or a high aperture ratio can be provided. According to one embodiment of the present invention, a manufacturing method of the above transistor, semiconductor device, memory device, or display device can be provided.

[0022] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0023] FIGS. 1A and 1B are plan views showing an example of a semiconductor device. FIGS. 2A to 2C are cross-sectional views showing an example of a semiconductor device. FIGS. 3A to 3C are perspective views showing an example of a semiconductor device. FIGS. 4A and 4B are cross-sectional views showing an example of a semiconductor device. FIGS. 5A to 5C are cross-sectional views showing an example of a semiconductor device. FIGS. 6A and 6B are cross-sectional views showing an example of a semiconductor device. FIGS. 7A to 7C are cross-sectional views showing an example of a semiconductor device. FIG. 8A is a plan view showing an example of a semiconductor device. FIG. 8B is a cross-sectional view showing an example of a semiconductor device. FIG. 9 is a cross-sectional view showing an example of a semiconductor device. FIG. 10A is a plan view showing an example of a semiconductor device. FIGS. 10B to 10D are cross-sectional views showing an example of a semiconductor device. FIGS. 11A and 11B are cross-sectional views showing an example of a semiconductor device. FIG. 12 is a cross-sectional view showing an example of a semiconductor device. FIGS. 13A and 13B are cross-sectional views showing an example of a semiconductor device. FIG. 14A is a plan view showing an example of a semiconductor device. FIGS. 14B to 14D are cross-sectional views showing an example of a semiconductor device. FIG. 15A is a plan view showing an example of a semiconductor device. 15B and 15C are cross-sectional views showing an example of a semiconductor device. FIG. 16A is a plan view showing an example of a semiconductor device. FIGS. 16B to 16D are cross-sectional views showing an example of a semiconductor device. FIG. 17A is a plan view showing an example of a semiconductor device. FIGS. 17B and 17C are cross-sectional views showing an example of a semiconductor device. FIG. 18A is a plan view showing an example of a semiconductor device. FIGS. 18B and 18C are cross-sectional views showing an example of a semiconductor device. FIG. 19A is a plan view showing an example of a method for manufacturing a semiconductor device. FIGS. 19B to 19D are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIG. 20A is a plan view showing an example of a method for manufacturing a semiconductor device. FIGS. 20B to 20D are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIG. 21A is a plan view showing an example of a method for manufacturing a semiconductor device. FIGS. 21B to 21D are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIG. 22A is a plan view showing an example of a method for manufacturing a semiconductor device. FIGS. 22B to 22D are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIG. 23A is a plan view illustrating an example of a method for manufacturing a semiconductor device.23B to 23D are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 24A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 24B to 24D are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 25A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 25B to 25D are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 26 is a block diagram illustrating a structural example of a semiconductor device. FIGS. 27A to 27H are diagrams illustrating a circuit structural example of a memory cell. FIG. 28 is a cross-sectional view illustrating an example of a semiconductor device. FIGS. 29A and 29B are perspective views illustrating a structural example of a semiconductor device. FIG. 30 is a cross-sectional view illustrating an example of a semiconductor device. FIG. 31 is a cross-sectional view illustrating an example of a semiconductor device. FIG. 32 is a block diagram illustrating a CPU. FIGS. 33A and 33B are perspective views illustrating an example of a semiconductor device. FIGS. 34A and 34B are perspective views illustrating an example of a semiconductor device. FIG. 35 is a conceptual diagram illustrating layers of a memory device. FIGS. 36A and 36B are diagrams illustrating an example of an electronic device.

[0093] Figs. 36C to 36E are diagrams showing an example of a mainframe computer. Fig. 37 is a diagram showing an example of space equipment. Fig. 38 is a diagram showing an example of a storage system applicable to a data center. Figs. 39A and 39B are perspective views showing an example of a display device. Fig. 40 is a cross-sectional view showing an example of the configuration of a display device. Fig. 41 is a cross-sectional view showing an example of the configuration of a display device. Fig. 42 is a cross-sectional view showing an example of the configuration of a display device. Fig. 43A is a plan view showing an example of the configuration of a display device. Figs. 43B to 43D are cross-sectional views showing an example of the configuration of a display device. Figs. 44A and 44B are cross-sectional views showing an example of the configuration of a display device. Figs. 45A and 45B are circuit diagrams showing an example of the configuration of a display device. Figs. 46A to 46D are circuit diagrams showing an example of the configuration of a display device. Figs. 47A to 47D are circuit diagrams showing an example of the configuration of a display device. Fig. 48 is a circuit diagram showing an example of the configuration of a display device. Figs. 49A to 49F are diagrams showing an example of electronic equipment. Figs. 50A to 50F are diagrams showing an example of electronic equipment. 51A to 51G are diagrams showing an example of an electronic device.

[0024] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0025] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0026] Furthermore, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0027] In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or stacking order). Furthermore, the ordinal numbers assigned to components in one part of this specification may not match the ordinal numbers assigned to the same components in other parts of this specification or in the claims.

[0028] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing a switching operation to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0029] In this specification and the like, a transistor using an oxide semiconductor or a metal oxide for a semiconductor layer and a transistor having an oxide semiconductor or a metal oxide for a channel formation region may be referred to as an OS (oxide semiconductor) transistor. A transistor having silicon for a channel formation region may be referred to as a Si transistor.

[0030] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A transistor has a region (also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, the channel formation region refers to a region through which current mainly flows.

[0031] Furthermore, the functions of "source" and "drain" may be interchanged when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. Therefore, in this specification, the terms "source" and "drain" may be used interchangeably.

[0032] Note that impurities in a semiconductor refer to, for example, elements other than the main components constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity. The presence of impurities may increase the density of defect states in the semiconductor or reduce the crystallinity, for example. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor. Specific examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water may also function as an impurity. For example, the inclusion of impurities may cause oxygen deficiency (V) in the oxide semiconductor. Ｏ (also called) may be formed.

[0033] In this specification and the like, an oxynitride refers to a material whose composition contains more oxygen than nitrogen. A nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0034] To analyze the content of elements such as hydrogen, oxygen, carbon, or nitrogen contained in a film, for example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS) or electron spectroscopy for chemical analysis (ESCA) can be used. XPS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more, or 1 atomic% or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., 0.5 atomic% or less, or 1 atomic% or less). When comparing the content of elements, it is more preferable to perform a combined analysis using both SIMS and XPS analytical methods.

[0035] In this specification and the like, the term "content" refers to the ratio of a component contained in a film. For example, when an oxide semiconductor layer contains a metal element X, a metal element Y, and a metal element Z, the number of atoms of each of the metal elements X, Y, and Z contained in the oxide semiconductor layer is expressed as A. Ｘ , A Ｙ , A Ｚ When the content of the metal element X is Ｘ / (A Ｘ +A Ｙ +A Ｚ In addition, the ratio of the number of atoms of the metal element X, the metal element Y, and the metal element Z in the oxide semiconductor layer (atomic ratio) can be expressed as follows: Ｘ : B Ｙ : B Ｚ When the content of the metal element X is expressed as B Ｘ / (B Ｘ +B Ｙ +B Ｚ ) can be shown as

[0036] It should be noted that the terms "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0037] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases where the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -20 degrees or more and 20 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases where the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 70 degrees or more and 110 degrees or less.

[0038] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as an object. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; wiring is not a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements. Note that A, B, and C, which will be described later, represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0039] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no electrical signal is exchanged or an interaction of electrical potential occurs between A and B, it can still be defined that "A and B are indirectly connected" as long as there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B.

[0040] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, and cases where a gate insulating film of a transistor is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0041] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another transistor from a power supply, GND, etc.

[0042] In this specification and the like, unless otherwise specified, the off-state current refers to the leakage current between the source and drain when the transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state current refers to the leakage current between the source and the gate when the voltage V ｇｓ is the threshold voltage V ｔｈ (For p-channel transistors, V ｔｈ This refers to a state of being (higher than)

[0043] In this specification, "normally on" refers to a state in which a channel exists and a current flows through a transistor even when no voltage is applied to the gate, and "normally off" refers to a state in which no current flows through a transistor when no potential is applied to the gate or when the gate-source voltage is 0 V.

[0044] In this specification and the like, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle (also called the taper angle) between the inclined side surface and the substrate surface or the surface to be formed is greater than 0 degrees and less than 90 degrees. Note that the side surface of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0045] In this specification, when it is stated that A is located on B, at least a portion of A is located on B. Therefore, for example, it can be rephrased as "A has a region located on B." Similarly, when it is stated that A contacts B or A overlaps B, at least a portion of A contacts B or overlaps B. Therefore, it can be rephrased as "A has a region contacting B" or "A has a region overlapping B," respectively. Similarly, in this specification, when it is stated that A covers B, at least a portion of A covers B. Therefore, for example, it can be rephrased as "A has a region covering B."

[0046] In this specification, etc., a device fabricated using a metal mask or an FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. Also, in this specification, etc., a device fabricated without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure.

[0047] In this specification and the like, a structure in which different light-emitting layers are formed for light-emitting elements (also referred to as light-emitting devices) with different emission wavelengths is sometimes referred to as an SBS (Side By Side) structure. The SBS structure allows the materials and configuration to be optimized for each light-emitting element, increasing the degree of freedom in selecting materials and configurations and making it easier to improve brightness and reliability.

[0048] In this specification and the like, holes or electrons may be referred to as "carriers." Specifically, a hole injection layer or an electron injection layer may be referred to as a "carrier injection layer," a hole transport layer or an electron transport layer may be referred to as a "carrier transport layer," and a hole block layer or an electron block layer may be referred to as a "carrier block layer." Note that the above-mentioned carrier injection layer, carrier transport layer, and carrier block layer may not be clearly distinguishable. Furthermore, one layer may have two or three functions among the carrier injection layer, carrier transport layer, and carrier block layer.

[0049] In this specification and the like, a light-emitting element has an EL layer between a pair of electrodes. The EL layer has at least a light-emitting layer. Here, examples of layers (also referred to as functional layers) included in the EL layer include a light-emitting layer, a carrier injection layer (a hole injection layer and an electron injection layer), a carrier transport layer (a hole transport layer and an electron transport layer), and a carrier block layer (a hole block layer and an electron block layer). In this specification and the like, one of the pair of electrodes may be referred to as a pixel electrode, and the other may be referred to as a common electrode.

[0050] In the display devices disclosed in this specification, etc., the sacrificial layer (which may also be referred to as a mask layer) refers to a layer that is located above at least the light-emitting layer (more specifically, the layer that is processed into an island shape among the layers that make up the EL layer) and has the function of protecting the light-emitting layer during the manufacturing process.

[0051] In this specification and the like, a step disconnection refers to a phenomenon in which a layer, a film, or an electrode is separated due to the shape of the surface on which it is formed (for example, a step or the like).

[0052] In this specification, the term "island-like" refers to a state in which two or more layers formed using the same material in the same process are physically separated. For example, an island-like light-emitting layer refers to a state in which the light-emitting layer is physically separated from an adjacent light-emitting layer.

[0053] In the drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification and the like, the "X direction" refers to the direction along the X axis, and there may be no distinction between the forward direction and the reverse direction unless explicitly stated. The same applies to the "Y direction" and the "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other.

[0054] Embodiment 1 In this embodiment, a semiconductor device of one embodiment of the present invention will be described.

[0055] One embodiment of the present invention relates to a transistor including an indium oxide film as a semiconductor layer and a semiconductor device including the transistor. The indium oxide film is a metal oxide film that is likely to have crystallinity. For example, the indium oxide film can be a single-crystal film or a polycrystalline film. This allows, for example, a structure in which no grain boundaries are observed in the channel formation region of the transistor. Therefore, carrier scattering at the grain boundaries can be suppressed, and a transistor with high field-effect mobility can be realized. Furthermore, a highly reliable transistor can be realized.

[0056] Furthermore, indium oxide films tend to allow one or both of hydrogen and oxygen to move more easily than, for example, indium gallium zinc oxide (In—Ga—Zn oxide, also referred to as IGZO) films. Therefore, it can be said that indium oxide films are films into which one or both of hydrogen and oxygen are more easily supplied and from which one or both of hydrogen and oxygen are more easily discharged than, for example, an IGZO film.

[0057] In the channel formation region of the metal oxide film, oxygen vacancies (Vo) and impurities are preferably reduced as much as possible. On the other hand, if an excessive amount of oxygen is supplied to the metal oxide film, the reliability of the transistor decreases. From the above, in the semiconductor device of one embodiment of the present invention, the hydrogen concentration in the metal oxide film is preferably low. Furthermore, it is preferable that an appropriate amount of oxygen is supplied to the metal oxide film to reduce the excess amount of oxygen.

[0058] By using an indium oxide film, through which one or both of hydrogen and oxygen can easily move, as the metal oxide film, the hydrogen concentration in the metal oxide film can be reduced. Also, the amount of excess oxygen in the metal oxide film can be reduced. As described above, by using an indium oxide film as the semiconductor layer, a highly reliable semiconductor device can be provided.

[0059] The semiconductor layer is provided with a source region and a drain region in addition to a channel formation region of the transistor. The source region and the drain region are regions with reduced resistance, e.g., regions with lower electrical resistivity than the channel formation region. The source region and the drain region can be formed by adding an impurity element to the semiconductor layer.

[0060] Here, the impurity element is preferably a metal element with a large period number in the periodic table, as long as the semiconductor layer maintains crystallinity even when added. The greater the overlap of the orbitals of the metal elements, the greater the carrier conduction tends to be. Therefore, by including a metal element with a large period number in the periodic table in the source and drain regions, the field-effect mobility of the transistor can be increased. Furthermore, elements with a large period number in the periodic table are less likely to diffuse than elements with a small period number in the periodic table. Therefore, by including a metal element with a large period number in the periodic table in the source and drain regions, the impurity element can be prevented from entering the channel formation region compared to when elements with a small period number in the periodic table are included in the source and drain regions. Therefore, a highly reliable semiconductor device can be provided.

[0061] Examples of metal elements with a larger periodic number in the periodic table include metal elements belonging to Period 5, which is the same period as indium contained in the semiconductor layer, and metal elements belonging to Period 6, which is a periodic table with a larger periodic number than indium. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, and light rare earth elements (lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium). The source region and the drain region of the transistor according to one embodiment of the present invention each contain at least one of these metal elements.

[0062] Here, it is particularly preferable that the source region and the drain region contain, as an impurity element, a metal element belonging to the fifth period. That is, it is particularly preferable that the source region and the drain region contain, as an impurity element, a metal element belonging to the same period as indium contained in the semiconductor layer. This makes it easier to form an intra-gap level. Therefore, carriers are more likely to conduct hopping through the intra-gap level. Furthermore, when a donor level is formed, the electron concentration can be increased. As described above, the contact resistance between the source electrode and the semiconductor layer and the contact resistance between the drain electrode and the semiconductor layer can be reduced. Therefore, a transistor with high on-state current can be provided. From the above, it is preferable that the source region and the drain region of the transistor of one embodiment of the present invention contain at least one of yttrium, zirconium, silver, cadmium, tin, and antimony, each of which belongs to the fifth period, which is the same period as indium. In particular, it is particularly preferable that antimony is contained.

[0063] <Structural Example 1 of Semiconductor Device> A structural example of a semiconductor device of one embodiment of the present invention will be described below.

[0064] FIG. 1A is a plan view of a semiconductor device having a transistor 200. Note that some elements are omitted from the plan view of FIG. 1A for clarity. Some elements may also be omitted from the subsequent plan views. FIG. 1B is a plan view in which some elements are omitted from FIG. 1A.

[0065] 2A is a cross-sectional view taken along dashed dotted line A1-A2 in FIGS. 1A and 1B, and is also a cross-sectional view in the channel length direction of the transistor 200. FIG. 2B is a cross-sectional view taken along dashed dotted line A3-A4 in FIGS. 1A and 1B, and is also a cross-sectional view in the channel width direction of the transistor 200. FIG. 2C is a cross-sectional view taken along dashed dotted line A5-A6 in FIGS. 1A and 1B.

[0066] 3A to 3C are perspective views illustrating an example of a semiconductor device according to one embodiment of the present invention. Parts of the configuration illustrated in FIG. 3A are illustrated in FIGS. 3B and 3C. FIG. 3B includes an example cross-sectional configuration taken along dashed lines A1-A2 in FIGS. 1A and 1B. FIG. 3C includes an example cross-sectional configuration taken along dashed lines A3-A4 in FIGS. 1A and 1B.

[0067] Fig. 4A is an example of an enlarged view of Fig. 2A, showing an example of a stacked structure of some layers.

[0068] 1A to 4A, the X direction, the Y direction, and the Z direction are indicated by arrows. Note that although the same X, Y, and Z symbols are used in FIGS. 1A to 4A, the directions do not necessarily have to match.

[0069] 1A to 4A includes an insulating layer 212 over a substrate (not shown), an insulating layer 214 over the insulating layer 212, a transistor 200, an insulating layer 216, a layer 233a, and a layer 233b over the insulating layer 214, insulating layers 271a and 271b over the transistor 200, an insulating layer 275 over the insulating layer 271a, the insulating layer 271b, and the insulating layer 216, an insulating layer 280 over the insulating layer 275, an insulating layer 282 over the transistor 200 and the insulating layer 280, an insulating layer 283 over the insulating layer 282, and an insulating layer 285 over the insulating layer 283. The insulating layer 212, the insulating layer 214, the insulating layer 280, the insulating layer 282, the insulating layer 283, and the insulating layer 285 function as interlayer films.

[0070] [Transistor 200] The transistor 200 includes a conductive layer 205, an insulating layer 221 over the conductive layer 205, an insulating layer 222 over the insulating layer 221, an insulating layer 224 over the insulating layer 222, an oxide layer 227 over the insulating layer 224, an oxide semiconductor layer 230 over the oxide layer 227, a conductive layer 242a over the oxide semiconductor layer 230 and over the layer 233a, a conductive layer 242b over the oxide semiconductor layer 230 and over the layer 233b, an insulating layer 271a over the conductive layer 242a, an insulating layer 271b over the conductive layer 242b, an insulating layer 250 over the oxide semiconductor layer 230, and a conductive layer 260 over the insulating layer 250.

[0071] The oxide semiconductor layer 230 includes a low-resistance region 230na, a low-resistance region 230nb, and a channel formation region 230i. The channel formation region 230i is located between the low-resistance region 230na and the low-resistance region 230nb.

[0072] The low-resistance region 230na and the low-resistance region 230nb are regions having a higher carrier concentration than the channel formation region 230i. One of the low-resistance region 230na and the low-resistance region 230nb functions as a source region. The other of the low-resistance region 230na and the low-resistance region 230nb functions as a drain region. Note that in FIG. 1B, the conductive layers 242a and 242b are omitted, and only the low-resistance region 230na and the low-resistance region 230nb are shown.

[0073] The conductive layer 260 functions as a first gate electrode (also referred to as an upper gate electrode or a top gate electrode) of the transistor 200. The insulating layer 250 functions as a first gate insulating layer of the transistor 200. The conductive layer 205 functions as a second gate electrode (also referred to as a lower gate electrode or a bottom gate electrode) of the transistor 200. The insulating layers 224, 222, and 221 each function as a second gate insulating layer of the transistor 200. The conductive layer 242a functions as one of a source electrode and a drain electrode of the transistor 200. The conductive layer 242b functions as the other of the source electrode and drain electrode of the transistor 200.

[0074] The conductive layer 242a and the conductive layer 242b each have a region in contact with the top surface of the oxide semiconductor layer 230. A region in contact with the conductive layer 242a in the oxide semiconductor layer 230 and a region in its vicinity function as a low-resistance region 230na. Similarly, a region in contact with the conductive layer 242b in the oxide semiconductor layer 230 and a region in its vicinity function as a low-resistance region 230nb.

[0075] The insulating layer 250 is provided to have a region located between the conductive layer 242 a and the conductive layer 242 b. The insulating layer 250 can have a region in contact with the side surface of the conductive layer 242 a on the channel formation region 230 i side, a region in contact with the side surface of the conductive layer 242 b on the channel formation region 230 i side, and a region in contact with the top surface of the oxide semiconductor layer 230 in a region between the low-resistance region 230 na and the low-resistance region 230 nb.

[0076] The conductive layer 260 is provided over the insulating layer 250. At least a part of a region of the oxide semiconductor layer 230 that overlaps with the conductive layer 260 becomes a channel formation region 230i.

[0077] The oxide semiconductor layer 230 includes a metal oxide (also referred to as an oxide semiconductor) that functions as a semiconductor. That is, the transistor 200 is an OS transistor.

[0078] Indium oxide is preferably used as the metal oxide used for the oxide semiconductor layer 230. For example, the oxide semiconductor layer 230 preferably includes an indium oxide film. The higher the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements included in the metal oxide, the higher the field-effect mobility of the transistor 200. Therefore, by using indium oxide for the oxide semiconductor layer 230, the transistor 200 can have high on-state current and high frequency characteristics.

[0079] Furthermore, the indium oxide film preferably has crystallinity. For example, the indium oxide film preferably has crystal grains in the channel formation region 230i. Specifically, the indium oxide film is preferably a single-crystal film or a polycrystalline film. Note that the indium oxide film may be an amorphous film containing crystal grains.

[0080] The crystallinity of the film can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED), or a combination of these techniques.

[0081] In a crystalline film, for example, crystal grains can be confirmed in a high-resolution transmission electron microscope (TEM) image. Furthermore, in a crystalline film, for example, crystal grain boundaries can sometimes be confirmed in a high-resolution TEM image. That is, crystal grains and crystal grain boundaries can sometimes be observed in a high-resolution TEM image of a crystalline film. The total magnification when acquiring a TEM image is preferably 2,000,000 times or more, and more preferably 4,000,000 times or more.

[0082] When the indium oxide film is a single-crystal film, the indium oxide film has one crystal grain, and no crystal grain boundary is observed throughout the oxide semiconductor layer 230. That is, no crystal grain boundary is observed in the channel formation region 230i. With such a structure, carrier scattering at the crystal grain boundary can be suppressed, and a transistor with high field-effect mobility can be realized. In addition, a highly reliable transistor can be realized.

[0083] When the indium oxide film is a polycrystalline film, it is preferable that no grain boundaries are observed in the channel formation region 230i, so that even if the indium oxide film is a polycrystalline film, the same effect as that of a configuration in which the indium oxide film is a single-crystalline film can be achieved.

[0084] The thickness of the oxide semiconductor layer 230 is preferably 2 nm to 50 nm, more preferably 2.5 nm to 30 nm, still more preferably 2.5 nm to 20 nm, still more preferably 5 nm to 20 nm, and still more preferably 5 nm to 10 nm. Note that the oxide semiconductor layer 230 preferably has a region with the above-described thickness in at least a part thereof. For example, the channel formation region of the oxide semiconductor layer 230 preferably has a region with the above-described thickness.

[0085] Setting the thickness of the oxide semiconductor layer 230 within the above range can improve the crystallinity of the oxide semiconductor layer 230. By improving the crystallinity of the oxide semiconductor layer 230, the oxide semiconductor layer 230 can have crystal grains.

[0086] In an oxide semiconductor layer with high crystallinity, an indium oxide film is a film through which one or both of hydrogen and oxygen move more easily than, for example, an IGZO film. Therefore, it can be said that an indium oxide film is a film through which one or both of hydrogen and oxygen are more easily supplied and from which one or both of hydrogen and oxygen are more easily discharged than, for example, an IGZO film. Note that it can be said that an indium oxide film is a film with high permeability to one or both of hydrogen and oxygen compared to, for example, an IGZO film. In other words, it can be said that an indium oxide film is a film with low barrier properties against one or both of hydrogen and oxygen compared to, for example, an IGZO film.

[0087] An OS transistor has an oxygen vacancy (V Ｏ ) and impurities, the electrical characteristics are likely to fluctuate and reliability may be reduced. ＯH) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the OS transistor is likely to be normally on. Therefore, it is preferable that oxygen vacancies and impurities are reduced as much as possible in the channel formation region of the oxide semiconductor. In other words, it is preferable that the carrier concentration of the channel formation region of the oxide semiconductor is reduced and the channel formation region of the oxide semiconductor is made i-type (intrinsic) or substantially i-type.

[0088] Furthermore, when an excessive amount of oxygen is supplied to the oxide semiconductor layer 230, electron traps due to the excess oxygen are formed, for example, in the insulating layer 250. This makes the OS transistor more susceptible to positive drift degradation in a +GBT (gate bias-temperature) stress test. In other words, the amount of positive drift degradation in the +GBT stress test increases.

[0089] Therefore, in the semiconductor device of one embodiment of the present invention, the hydrogen concentration in the oxide semiconductor layer 230 is preferably low. Furthermore, an appropriate amount of oxygen is preferably supplied to the oxide semiconductor layer 230. Furthermore, it is preferable to reduce the amount of excess oxygen in the oxide semiconductor layer 230.

[0090] By using an indium oxide film, through which one or both of hydrogen and oxygen easily move, as the oxide semiconductor layer 230, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced. In addition, the amount of excess oxygen in the oxide semiconductor layer 230 can be reduced. As described above, by using an indium oxide film as the oxide semiconductor layer 230, a highly reliable semiconductor device can be provided.

[0091] For example, the insulating layer 250 preferably has a function of capturing or fixing oxygen (also referred to as gettering). As described above, an indium oxide film is a film through which oxygen easily moves. Therefore, for example, when the insulating layer 250 has a function of capturing or fixing oxygen, excess oxygen in the oxide semiconductor layer 230 can diffuse to the insulating layer 250 and be captured or fixed. Therefore, the OS transistor can suppress positive drift degradation in a +GBT stress test caused by oxygen released by heating (hereinafter also referred to as excess oxygen). Examples of insulating materials having a function of capturing or fixing oxygen include aluminum oxide, hafnium oxide, hafnium zirconium oxide, and oxides containing hafnium and silicon (hafnium silicate). Examples of insulating layers having a function of capturing or fixing oxygen include an aluminum oxide film, a hafnium oxide film, a hafnium zirconium oxide film, and a hafnium silicate film.

[0092] Note that an aluminum oxide film, a hafnium oxide film, a hafnium zirconium oxide film, and a hafnium silicate film have the function of capturing or fixing hydrogen. As described above, an indium oxide film is a film through which hydrogen easily moves. Therefore, for example, when the insulating layer 250 has the function of capturing or fixing hydrogen, hydrogen in the oxide semiconductor layer 230 can be diffused into the insulating layer 250 and the hydrogen can be captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 (particularly, the hydrogen concentration in the channel formation region 230i) can be reduced. Therefore, the V in the channel formation region 230i can be reduced. Ｏ By reducing H, the channel forming region 230i can be made i-type or substantially i-type.

[0093] When the oxide semiconductor layer 230 contains gallium atoms, the gallium atoms bond with excess oxygen atoms to form a Ga—O structure. The Ga—O structure functions as an acceptor that traps electrons. Therefore, a transistor including the oxide semiconductor layer 230 containing gallium atoms and excess oxygen atoms exhibits a large variation in threshold voltage in a positive bias temperature stress (PBTS) test. Therefore, by reducing the gallium concentration in the oxide semiconductor layer 230, the variation in threshold voltage in the PBTS test can be reduced. This allows the transistor to have high reliability against positive bias application.

[0094] The band gap of indium oxide is greater than or equal to 2.5 eV and less than or equal to 3.7 eV. By using indium oxide with a wide band gap for the oxide semiconductor layer 230, the off-state current of the transistor can be reduced, and the power consumption of the semiconductor device can be sufficiently reduced.

[0095] An OS transistor is an accumulation-type transistor in which electrons serve as majority carriers. That is, the carriers in an OS transistor are electrons. Assuming that the relaxation time of carriers is constant, the smaller the effective mass of electrons (carriers), the higher the electron mobility (carrier mobility). That is, by using a metal oxide film with a small effective mass of electrons for the oxide semiconductor layer 230, the on-state current or field-effect mobility of the transistor 200 can be increased.

[0096] Indium oxide has a small effective mass of electrons. Therefore, by using indium oxide having a small effective mass of electrons for the oxide semiconductor layer 230, a transistor with a large on-state current, a transistor with high field-effect mobility, and a transistor with high frequency characteristics (also referred to as f characteristics) can be realized. Furthermore, the effective mass of electrons in indium oxide is smaller than the effective mass of electrons in, for example, silicon. Therefore, in terms of the effective mass of electrons, the f characteristics of a transistor using indium oxide for a channel formation region are higher than the f characteristics of a Si transistor.

[0097] Indium oxide has a large effective mass of holes. Therefore, by using indium oxide, which has a large effective mass of holes, for the oxide semiconductor layer 230, a transistor with extremely small off-state current can be realized. Furthermore, the effective mass of holes in indium oxide is larger than the effective mass of holes in, for example, silicon. Therefore, in terms of the effective mass of holes, the off-state current of a transistor using indium oxide for a channel formation region is sufficiently smaller than the off-state current of a Si transistor.

[0098] In a transistor using indium oxide for the oxide semiconductor layer 230, the off-state current per μm of the channel width at room temperature is 1×10 −１７ A / μm or less, preferably 1×10 −１８ A / μm or less, more preferably 1×10 −１９ The off-state current value at 85° C. per 1 μm of channel width can be reduced to 1×10 −１６ A / μm or less, preferably 1×10 −１７ A / μm or less, more preferably 1×10 −１８ It is possible to make it less than A / μm.

[0099] Furthermore, miniaturization of an OS transistor can improve the high-frequency characteristics of the transistor. For example, the cutoff frequency of the transistor can be increased. Specifically, the cutoff frequency of the transistor can be set to 50 GHz or higher, preferably 100 GHz or higher, and more preferably 150 GHz or higher at room temperature.

[0100] The channel tends to flow in a region up to a depth of 1 nm from the surface of the oxide semiconductor layer 230 on the insulating layer 250 side. Therefore, the channel formation region 230i can be, for example, a region that overlaps with the conductive layer 260 of the oxide semiconductor layer 230 and has a depth of 1 nm or less from the surface on the insulating layer 250 side. Furthermore, the channel formation region 230i can be, for example, a region that overlaps with the conductive layer 260 of the oxide semiconductor layer 230 and has a depth of 1 nm or less from the interface with the insulating layer 250.

[0101] Note that the interface between the oxide semiconductor layer 230 and the insulating layer 250 can be confirmed by, for example, a cross-sectional TEM image, a cross-sectional scanning transmission electron microscope (STEM) image, etc. In addition, the interface between the oxide semiconductor layer 230 and the insulating layer 250 can sometimes be confirmed by using SIMS or by performing line analysis of the composition by EDX on the interface between the oxide semiconductor layer 230 and the insulating layer 250 and its surroundings.

[0102] For example, EDX line analysis is performed on the interface and its periphery, with the direction perpendicular to the surface on which the oxide semiconductor layer 230 is formed as the depth direction. Next, in the profile of the quantitative values ​​of each element in the depth direction obtained by the analysis, the depth at which the quantitative value of a metal (e.g., aluminum) that is the main component of the insulating layer 250 but is not the main component of the oxide semiconductor layer 230 becomes half-value can be defined as the interface. Alternatively, in the profile of the quantitative values ​​of each element in the depth direction obtained by the analysis, the depth at which the quantitative value of a metal (e.g., indium) that is the main component of the oxide semiconductor layer 230 but is not the main component of the insulating layer 250 becomes half-value can be defined as the interface.

[0103] The low-resistance region 230na and the low-resistance region 230nb are regions with reduced resistance, and are regions with lower electrical resistivity than the channel formation region 230i, for example. When an impurity element is added to the oxide semiconductor layer 230, carriers are generated. The regions where carriers are generated become the low-resistance region 230na and the low-resistance region 230nb. By adding an impurity element to the oxide semiconductor layer 230, valence electron control can be performed.

[0104] Here, the impurity element is preferably a metal element having a large period number in the periodic table, as long as the oxide semiconductor layer 230 maintains crystallinity even when added. The greater the overlap between the orbitals of the metal elements, the greater the carrier conduction. Therefore, by including a metal element having a large period number in the periodic table in the low-resistance region 230na and the low-resistance region 230nb, the field-effect mobility of the transistor 200 can be increased. Furthermore, elements having a large period number in the periodic table are less likely to diffuse than elements having a small period number in the periodic table. Therefore, by including a metal element having a large period number in the periodic table in the low-resistance region 230na and the low-resistance region 230nb, the impurity element can be prevented from entering the channel formation region 230i more effectively than by including an element having a small period number in the periodic table in the low-resistance region 230na and the low-resistance region 230nb. Therefore, a highly reliable semiconductor device can be provided.

[0105] Examples of metal elements with larger periodic numbers in the periodic table include metal elements belonging to Period 5, which is the same period as indium contained in the oxide semiconductor layer 230, and metal elements belonging to Period 6, which has a larger periodic number in the periodic table than indium. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, and light rare earth elements (lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium). The low-resistance region 230na and the low-resistance region 230nb each contain at least one of these metal elements. Specifically, the concentrations of these metal elements in the low-resistance region 230na and the low-resistance region 230nb are higher than the concentrations in the channel formation region 230i.

[0106] Here, it is particularly preferable that the low-resistance region 230na and the low-resistance region 230nb contain, as an impurity element, a metal element belonging to the fifth period. That is, it is particularly preferable that the low-resistance region 230na and the low-resistance region 230nb contain, as an impurity element, a metal element belonging to the same period as indium contained in the oxide semiconductor layer 230. This makes it easier to form an intra-gap level. Therefore, carriers are more likely to conduct hopping through the intra-gap level. Furthermore, when a donor level is formed, the electron concentration can be increased. As a result, the contact resistance between the conductive layer 242a and the oxide semiconductor layer 230 and the contact resistance between the conductive layer 242b and the oxide semiconductor layer 230 can be reduced. Therefore, a transistor with a large on-current can be provided. For these reasons, it is particularly preferable that the low-resistance region 230na and the low-resistance region 230nb each contain at least one of yttrium, zirconium, silver, cadmium, tin, and antimony, which belong to the fifth period, the same period as indium.

[0107] It is particularly preferable that the low resistance region 230na and the low resistance region 230nb contain antimony. In this case, the antimony concentration in the low resistance region 230na and the low resistance region 230nb is 1×10 １７ atoms / cm ３ 8 x 10 or more ２１ atoms / cm ３ Preferably, 1×10 １７ atoms / cm ３ 5x10 or more ２０ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ 5x10 or more ２０ atoms / cm ３ Alternatively, the antimony concentration in each of the low resistance regions 230na and 230nb is preferably 0.5 atomic % or more and 30 atomic % or less, and more preferably 1 atomic % or more and 10 atomic % or less. The antimony concentration in the channel formation region 230i is 1×10 １７ atoms / cm ３Preferably less than 1 x 10 １５ atoms / cm ３ Less than 5 x 10 is more preferable. １４ atoms / cm ３ or less is more preferable. Alternatively, the antimony concentration in the channel formation region 230i is preferably less than 0.5 atomic%, more preferably 0.01 atomic% or less, and even more preferably 0.0002 atomic% or less. The above preferred ranges also apply when the low resistance region 230na and the low resistance region 230nb each contain any of the above metal elements other than antimony. Note that the low resistance region 230na and the low resistance region 230nb may contain a metal element belonging to the fourth period, such as zinc.

[0108] In this specification and the like, when the concentration of an impurity contained in an oxide semiconductor layer is expressed in atomic %, the impurity concentration is a value obtained by dividing the number of atoms of the impurity element by the number of atoms of the main element of the oxide semiconductor layer. For example, when the concentration of an impurity in an indium oxide film is expressed in atomic %, the impurity concentration is a value obtained by dividing the number of atoms of the impurity element by the sum of the number of indium atoms and the number of oxygen atoms. Note that the impurity concentration in the indium oxide film may also be a value obtained by dividing the number of atoms of the impurity element by the number of indium atoms.

[0109] When the oxide semiconductor layer 230 is an n-type semiconductor, an impurity element imparting p-type conductivity may be added to the channel formation region 230i. For example, one or both of cadmium and zinc may be added to the channel formation region 230i. This may make it easier to make the channel formation region 230i i-type or substantially i-type. In this case, the concentration of the added element in the channel formation region 230i is 5×10 １４ atoms / cm ３ 5x10 or more １８ atoms / cm ３ Preferably less than 5 x 10 １４ atoms / cm ３ 1x10 or more １８ atoms / cm ３ More preferably, 1×10 １５ atoms / cm ３ 5x10 or more １７atoms / cm ３ Alternatively, the concentration of the additional element in the channel formation region 230i is preferably 0.0002 atomic % or more and 0.5 atomic % or less, and more preferably 0.001 atomic % or more and 0.1 atomic % or less.

[0110] The concentration of the metal element contained in at least one of the low resistance region 230na, the low resistance region 230nb, and the channel formation region 230i can be measured by, for example, inductively coupled plasma mass spectrometry (ICP-MS), XPS, SIMS, time-of-flight secondary ion mass spectrometry (ToF-SIMS), Auger electron spectroscopy (AES), energy dispersive X-ray spectroscopy (EDX), or the like. The evaluation can be performed using, for example, plasma atomic emission spectroscopy (ICP-AES), inductively coupled plasma atomic emission spectroscopy (ICP-AES), or the like.

[0111] In the semiconductor device of one embodiment of the present invention, the layer 233a can be provided so as to overlap with a region between the low-resistance region 230na and the channel formation region 230i. Furthermore, the layer 233b can be provided so as to overlap with a region between the low-resistance region 230nb and the channel formation region 230i. The layer 233a can be in contact with an upper surface of the oxide semiconductor layer 230 in a region between the low-resistance region 230na and the channel formation region 230i. Similarly, the layer 233b can be in contact with an upper surface of the oxide semiconductor layer 230 in a region between the low-resistance region 230nb and the channel formation region 230i. The conductive layer 242a can be provided so as to cover at least part of the upper surface of the oxide semiconductor layer 230 in the low-resistance region 230na, the side surface of the layer 233a on the low-resistance region 230na side, and the upper surface of the layer 233a. Similarly, the conductive layer 242b can be provided to cover at least a part of the upper surface of the oxide semiconductor layer 230 in the low-resistance region 230nb, the side surface of the layer 233b on the low-resistance region 230nb side, and the upper surface of the layer 233b.

[0112] The insulating layer 250 is provided to have a region located between the conductive layer 242a and the conductive layer 242b and a region located between the layer 233a and the layer 233b. The insulating layer 250 can have a region in contact with the side surface of the layer 233a on the channel formation region 230i side and a region in contact with the side surface of the layer 233b on the channel formation region 230i side.

[0113] In the semiconductor device of one embodiment of the present invention, an impurity element can be added to the oxide semiconductor layer 230 by using the layers 233a and 233b as masks. Specifically, the impurity element can be added to the oxide semiconductor layer 230 by using the layers that will become the layers 233a and 233b as masks. As a result, low-resistance regions 230na and 230nb can be formed in the oxide semiconductor layer 230. The layers that will become the layers 233a and 233b can overlap with the entire oxide semiconductor layer 230 except for the low-resistance regions 230na and 230nb. The layers 233a and 233b are also referred to as mask layers. Note that the semiconductor device of one embodiment of the present invention does not necessarily have to include the layers 233a and 233b. In this case, the impurity element can be added to the oxide semiconductor layer 230 by using, for example, a resist mask.

[0114] The layers 233a and 233b are preferably oxide layers each containing two or three elements selected from indium, zinc, and the element M. That is, the layers 233a and 233b are preferably metal oxide layers. Note that the layers 233a and 233b do not necessarily contain zinc. Here, it is preferable to use a material having a high etching selectivity with respect to the oxide semiconductor layer 230 for the layers 233a and 233b, because this can prevent at least part of the oxide semiconductor layer 230 from being removed when the layers to be the layers 233a and 233b are processed by etching.

[0115] The element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specifically, the element M is preferably one or more of gallium, aluminum, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M is more preferably one or more selected from gallium, aluminum, tin, and yttrium, and more preferably gallium. In this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification and the like may include metalloid elements.

[0116] The layer 233 a and the layer 233 b may be formed of, for example, indium zinc oxide (In—Zn oxide, also referred to as IZO (registered trademark)), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide, also referred to as IGTO), indium aluminum zinc oxide (In—Al—Zn oxide, I Examples of usable oxides include indium tin zinc oxide (In-Sn-Zn oxide, also referred to as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO, IGZAO, or IAGZO).

[0117] By using metal oxide layers for the layers 233a and 233b, like the oxide semiconductor layer 230, in a manufacturing process of a semiconductor device according to one embodiment of the present invention, a region to be the channel formation region 230i can be prevented from being in contact with a layer other than a metal oxide layer before the insulating layer 250 is formed. As described above, a foreign layer can be prevented from being formed on the top surface of the channel formation region 230i of the oxide semiconductor layer 230. This can improve the reliability of the transistor 200. For example, an increase in the electrical resistance of the channel formation region 230i due to the foreign layer can be prevented, which can prevent a decrease in the on-state current of the transistor 200. Note that when the layer 233a is a metal oxide layer, the boundary between the layer 233a and the oxide semiconductor layer 230 may not be clearly visible. Similarly, when the layer 233b is a metal oxide layer, the boundary between the layer 233b and the oxide semiconductor layer 230 may not be clearly visible.

[0118] When an impurity element is added to the oxide semiconductor layer 230 using the layers that will become the layers 233a and 233b as masks, the impurity element is also added to the layers 233a and 233b. For example, when antimony is added to the oxide semiconductor layer 230 using the layers that will become the layers 233a and 233b as masks, antimony is also added to the layers 233a and 233b. The addition of an impurity element to the layers 233a and 233b may reduce the resistance of the layers 233a and 233b. As a result, at least a part of the layer 233a may function as one of a source region and a drain region, and at least a part of the layer 233b may function as the other of the source region and the drain region. In this case, the impurity concentrations in at least a part of the layer 233a and at least a part of the layer 233b can be approximately the same as the impurity concentrations in the low-resistance region 230na and the low-resistance region 230nb, respectively.

[0119] Note that the layers 233a and 233b do not have to be metal oxide layers as long as they function as masks when an impurity element is added to the oxide semiconductor layer 230. The layers 233a and 233b can be, for example, insulating layers or conductive layers. The layers 233a and 233b can also be, for example, layers containing a semiconductor material other than a metal oxide.

[0120] When the layers 233a and 233b are insulating layers, the layers 233a and 233b can be made of, for example, a material that can be used for the insulating layer 224. When the layers 233a and 233b are conductive layers, the layer 233a can be made of, for example, a material that can be used for the conductive layer 242a, and the layer 233b can be made of, for example, a material that can be used for the conductive layer 242b. Note that when the layers 233a and 233b are conductive layers, for example, the boundary between the conductive layer 242a and the layer 233a and the boundary between the conductive layer 242b and the layer 233b may not be clearly visible.

[0121] The layers 233a and 233b may be included as components of the transistor 200. In particular, when the layers 233a and 233b are conductive layers, the layers 233a and 233b can be included as components of the transistor 200. In this case, the layer 233a functions as a source electrode of the transistor 200 together with the conductive layer 242a, and the layer 233b functions as a drain electrode of the transistor 200 together with the conductive layer 242b. Even when the layers 233a and 233b are semiconductor layers such as metal oxide layers, the layers 233a and 233b can be included as components of the transistor 200.

[0122] 2A to 4A show an example in which an oxide layer 227 is provided between the insulating layer 224 and the oxide semiconductor layer 230. The oxide semiconductor layer 230 is provided over the oxide layer 227 and has a region in contact with the oxide layer 227. The oxide layer 227 is a layer that allows crystal grains included in the oxide semiconductor layer 230 to grow from below or does not inhibit the crystal grains included in the oxide semiconductor layer 230 from growing from above.

[0123] Indium oxide crystals have a cubic crystal structure, and the lattice constant of the cubic crystal structure is 1.0117 nm (see ICSD (Inorganic Crystal Structure Database) coll.code.14387).

[0124] When indium oxide is used for the oxide semiconductor layer 230, it is preferable to use an oxide having a cubic crystal structure for the oxide layer 227. When the crystal of the oxide layer 227 has the same crystal structure as the crystal of the oxide semiconductor layer 230, the oxide semiconductor layer 230 can grow epitaxially using the oxide layer 227 as a nucleus, thereby improving the crystallinity of the oxide semiconductor layer 230. For example, zirconium oxide or yttria-stabilized zirconia (YSZ) can be used for the oxide layer 227. The crystals of zirconium oxide and YSZ each have a cubic crystal structure. Note that when the crystal of the oxide semiconductor layer 230 and the crystal of the oxide layer 227 have the same crystal structure, the crystal orientation of the surface of the oxide layer 227 is not particularly limited. For example, it may be

[100] ,

[110] , or

[111] .

[0125] It is preferable that the difference (also referred to as lattice mismatch) between the crystal lattice constant of the oxide layer 227 and the crystal lattice constant of the oxide semiconductor layer 230 be small. By using an oxide that reduces the lattice mismatch for the oxide layer 227, the crystallinity of the oxide semiconductor layer 230 can be improved.

[0126] One method for evaluating the degree of lattice mismatch is to use the lattice mismatch value shown below. The lattice mismatch Δa [%] of the crystals of the forming film with respect to the crystals of the forming film is calculated using the following formula (1). Hereinafter, the lattice mismatch Δa of the crystals of the forming film with respect to the crystals of the forming film may be simply referred to as the lattice mismatch Δa of the forming film with respect to the forming film.

[0127]

[0128] In formula (1), L １ is the lattice constant of the crystal of the formed film, and L ２ is the lattice constant of the crystal of the film to be formed.

[0129] The lattice mismatch Δa of the crystal grains of the oxide semiconductor layer 230 with respect to the crystal grains of the oxide layer 227 is preferably 0% to 10%, more preferably 0% to 5%, and even more preferably 0% to 3%. By using a material that reduces the lattice mismatch with the oxide semiconductor layer 230 for the oxide layer 227, the crystallinity of the oxide semiconductor layer 230 can be improved.

[0130] For example, Zr ０．９ Y ０．１ O １．９５The crystal lattice constant is 0.51481 nm (see ICSD coll.code.248790). Therefore, the lattice mismatch between the crystal grains of the indium oxide film and the crystal grains of YSZ is 1.74%. Therefore, when indium oxide is used for the oxide semiconductor layer 230, YSZ can be suitably used for the oxide layer 227. Note that YSZ contains yttrium, zirconium, and oxygen. The content of yttrium in YSZ is 2 atomic % to 15 atomic %, preferably 5 atomic % to 10 atomic %.

[0131] When YSZ is used as the oxide layer 227 and indium oxide is used as the oxide semiconductor layer 230, a buffer layer containing indium and zirconium may be formed at the interface between the oxide layer 227 and the oxide semiconductor layer 230. Because the ionic radii of indium and zirconium are different, it is presumed that the lattice constant of the buffer layer will be a value between the lattice constants of the YSZ crystal and the indium oxide crystal. Therefore, by forming the buffer layer, it is possible to reduce the lattice mismatch between the oxide layer 227 and the oxide semiconductor layer 230, and improve the crystallinity of the oxide semiconductor layer 230.

[0132] Note that the crystal orientation of the oxide layer 227 and the crystal orientation of the oxide semiconductor layer 230 may not be the same in some cases. For example, the oxide layer 227 having a layered crystal structure may be provided under indium oxide having a cubic crystal structure. Specifically, when a film having a hexagonal or trigonal crystal structure is used as the oxide layer 227, the crystal orientation of the surface of the oxide layer 227 is set to

[001] and the crystal orientation of the bottom surface of the oxide semiconductor layer 230 is set to

[111] , whereby the above-described certain crystal orientation relationship can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite-type and YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７The above structure can be considered as a structure in which an oxide semiconductor layer having cubic crystals is formed on an oxide layer having crystals of a layered structure. That is, it can also be considered as a stacked structure manufactured by using a heteroepitaxial growth technique or a technique similar to heteroepitaxial growth.

[0133] Specifically, zinc oxide, In—Ga oxide, In—Zn oxide, gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), indium aluminum zinc oxide (In—Al—Zn oxide), In—Ga—Zn oxide, indium tin zinc oxide (In—Sn—Zn oxide), or the like can be used for the oxide layer 227. For example, for the oxide layer 227, an In—Ga—Zn oxide having a composition of In:Ga:Zn=1:3:2 (atomic ratio) or thereabouts, or an In—Ga—Zn oxide having a composition of In:Ga:Zn=1:1:1 (atomic ratio) or thereabouts can be used.

[0134] Note that there is no particular limitation on a material that can be used for the oxide layer 227. The oxide layer 227 may be formed using either an insulating material or a semiconductor material. When an insulating material is used for the oxide layer 227, the oxide layer 227 may be considered as part of the insulating layer 224. When a semiconductor material is used for the oxide layer 227, the oxide layer 227 may be considered as part of the oxide semiconductor layer 230.

[0135] Note that the transistor 200 does not necessarily include the oxide layer 227. In this case, the oxide semiconductor layer 230 can be in contact with the top surface of the insulating layer 224.

[0136] An insulating layer 275 is provided over the insulating layer 271a and the insulating layer 271b, and an insulating layer 280 is provided over the insulating layer 275. An opening 289 is formed in the insulating layer 280 and the insulating layer 275, reaching the insulating layer 222 and the oxide semiconductor layer 230, and the opening 289 overlaps a region between the conductive layer 242a and the conductive layer 242b. In a plan view, the side surface of the insulating layer 280 in the opening 289 coincides or substantially coincides with the side surface of the conductive layer 242a and the side surface of the conductive layer 242b. The insulating layer 250 and the conductive layer 260 are disposed in the opening 289. An insulating layer 282 is provided in contact with the top surface of the insulating layer 280, the upper end of the insulating layer 250, and the top surface of the conductive layer 260. An insulating layer 283 is provided over the insulating layer 282.

[0137] An opening 244a reaching the conductive layer 242a is provided in the insulating layers 285, 283, 282, 280, 275, and 271a. Similarly, an opening 244b reaching the conductive layer 242b is provided in the insulating layers 285, 283, 282, 280, 275, and 271b. A conductive layer 243a and an insulating layer 241a are provided in the opening 244a, and a conductive layer 243b and an insulating layer 241b are provided in the opening 244b. The insulating layer 241a is provided in contact with the sidewall of the opening 244a. Similarly, the insulating layer 241b is provided in contact with the sidewall of the opening 244b. Furthermore, the conductive layer 243a is provided inside the insulating layer 241a, and the conductive layer 243b is provided inside the insulating layer 241b. The conductive layer 243a functions as a via that connects the conductive layer 242a to a wiring or the like provided over the transistor 200. Similarly, the conductive layer 243b functions as a via that connects the conductive layer 242b to a wiring or the like provided over the transistor 200. Note that the openings 244a, 244b, the conductive layers 243a, and the conductive layers 243b shown in FIG. 1A are omitted in FIG. 1B.

[0138] An insulating layer containing excess oxygen is provided near the oxide semiconductor layer 230, and heat treatment is performed to supply oxygen from the insulating layer to the oxide semiconductor layer 230, thereby eliminating oxygen vacancies and V ＯH can be reduced. However, if an excessive amount of oxygen is supplied to the low-resistance region 230na or the low-resistance region 230nb, the on-state current or the field-effect mobility of the transistor 200 may decrease. Furthermore, variations in the amount of oxygen supplied to the low-resistance region 230na or the low-resistance region 230nb within the substrate surface may cause variations in the characteristics of a semiconductor device including the transistor 200. Furthermore, if the amount of oxygen supplied from the insulating layer to the oxide semiconductor layer 230 becomes excessively large, the electrical characteristics and reliability of the transistor 200 may be adversely affected. Furthermore, oxygen may diffuse into the conductive layer 260, the conductive layer 242a, the conductive layer 242b, and the like, and these conductive layers may be oxidized, resulting in a loss of conductivity.

[0139] First, at least one of an insulating layer having a barrier property against hydrogen and an insulating layer having a function of capturing or fixing hydrogen is formed near the oxide semiconductor layer 230, and V in the channel formation region of the oxide semiconductor layer 230 and its vicinity is formed. Ｏ It is preferable to reduce H.

[0140] At least one of the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283 preferably functions as a barrier insulating layer against hydrogen. At least one of the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283 preferably functions as a barrier insulating layer against impurities. At least one of the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283 preferably functions as a barrier insulating layer against oxygen. Note that all of the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283 do not necessarily need to be provided. As long as the insulating layer has sufficient barrier properties against hydrogen, impurities, oxygen, and the like, the insulating layer can be formed by appropriately selecting from the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283. For example, a structure can be used in which the insulating layer 216 and the conductive layer 205 are formed in contact with the upper surface of the insulating layer 212 without providing the insulating layer 214.

[0141] In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. The barrier properties are defined as a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). Note that hydrogen when described as a corresponding substance includes, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. − Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, and NO ２ The term "oxygen" when used in reference to a corresponding substance refers to at least one of an oxygen atom, an oxygen molecule, and the like.

[0142] It is preferable that the insulating layer 212, the insulating layer 221, the insulating layer 275, and the insulating layer 283 have a function of suppressing diffusion of hydrogen. For example, it is preferable that the insulating layer 212, the insulating layer 221, the insulating layer 275, and the insulating layer 283 be made of silicon nitride, which has a higher hydrogen barrier property.

[0143] The insulating layer 214, the insulating layer 222, and the insulating layer 282 preferably have a function of capturing or fixing hydrogen. For example, aluminum oxide is preferably used for the insulating layer 214 and the insulating layer 282. Furthermore, for example, hafnium oxide, which is a high-k material, is preferably used for the insulating layer 222 that functions as the second gate insulating layer.

[0144] 2A , for example, by providing an insulating layer 212 having a function of suppressing hydrogen diffusion under the transistor 200, it is possible to suppress diffusion of hydrogen from a layer below the transistor 200. Furthermore, by providing an insulating layer 214 having a function of capturing or fixing hydrogen, hydrogen contained in the insulating layer 216 or the like can be captured or fixed in the insulating layer 214. This allows the hydrogen concentration in the oxide semiconductor layer 230 and its vicinity to be reduced.

[0145] Furthermore, by providing the insulating layer 221 having a function of suppressing diffusion of hydrogen under the oxide semiconductor layer 230, it is possible to suppress diffusion of hydrogen from below the oxide semiconductor layer 230. Furthermore, by providing the insulating layer 222 having a function of capturing or fixing hydrogen, hydrogen contained in the insulating layer 224 or the like can be captured or fixed in the insulating layer 222. As a result, the hydrogen concentration in the oxide semiconductor layer 230 and its vicinity can be reduced.

[0146] Furthermore, by providing the insulating layer 275 having the function of suppressing diffusion of hydrogen so as to cover the oxide semiconductor layer 230, the conductive layer 242a, the conductive layer 242b, and the like, it is possible to suppress diffusion of hydrogen from the insulating layer 280 to the oxide semiconductor layer 230, the conductive layer 242a, the conductive layer 242b, and the like.

[0147] Furthermore, by providing the insulating layer 283 having a function of suppressing diffusion of hydrogen over the transistor 200, diffusion of hydrogen from above the transistor 200 can be suppressed. Furthermore, by providing the insulating layer 282 having a function of capturing or fixing hydrogen, hydrogen contained in the insulating layer 280 or the like can be captured or fixed to the insulating layer 282. As a result, the hydrogen concentration in the oxide semiconductor layer 230 and its vicinity can be reduced.

[0148] In this manner, by using a structure in which the transistor 200 is surrounded by barrier insulating layers against hydrogen from above and below, diffusion of hydrogen into the oxide semiconductor layer 230 is reduced, and the V Ｏ H can be reduced. As a result, the electrical characteristics and reliability of the transistor 200 can be improved.

[0149] Excess oxygen is preferably contained in one or both of the insulating layer 224 and the insulating layer 280. By supplying the oxygen to the oxide semiconductor layer 230 through the insulating layer 250 by heat treatment, oxygen vacancies in the channel formation region can be reduced.

[0150] By performing heat treatment on the insulating layer 224 containing excess oxygen, a suitable amount of oxygen can be supplied to the oxide semiconductor layer 230 through the oxide layer 227. Furthermore, by performing heat treatment on the insulating layer 280 containing excess oxygen, a suitable amount of oxygen can be supplied to the oxide semiconductor layer 230 through the insulating layer 250. In the heat treatment described above, it is preferable that at least one of the insulating layers 222, 221, 214, and 212 under the insulating layer 224 has a barrier property against oxygen, because the oxygen contained in the insulating layer 224 can be prevented from excessively diffusing from the insulating layer 224. Furthermore, it is preferable that one or both of the insulating layers 282 and 283 over the insulating layer 280 have a barrier property against oxygen, because the oxygen contained in the insulating layer 280 can be prevented from excessively diffusing from the insulating layer 280. When the insulating layer 275 has a barrier property against oxygen, excessive diffusion of oxygen contained in the insulating layer 224 from the insulating layer 224 and excessive diffusion of oxygen contained in the insulating layer 280 from the insulating layer 280 can be prevented. Note that by performing the heat treatment with openings formed in parts of the insulating layer 280, the insulating layer 282, and the insulating layer 283, part of the oxygen contained in the insulating layer 280 can be diffused outward, and the amount of oxygen supplied from the insulating layer 280 to the oxide semiconductor layer 230 can be adjusted. Furthermore, when the transistor 200 does not include the oxide layer 227, oxygen can be easily supplied from the insulating layer 224 to the oxide semiconductor layer 230 in some cases.

[0151] The insulating layer 250 preferably has a structure that allows oxygen to diffuse from the insulating layer 280 to the oxide semiconductor layer 230 and prevents the conductive layers 242a, 242b, and 260 from being oxidized.

[0152] The insulating layer 250 is formed within the opening 289 in contact with the top surface of the insulating layer 222, the side surface of the insulating layer 224, the side surface and top surface of the oxide semiconductor layer 230, the side surface of the conductive layer 242a, the side surface of the conductive layer 242b, the side surface of the insulating layer 271a, the side surface of the insulating layer 271b, the side surface of the insulating layer 275, and the side surface of the insulating layer 280.

[0153] Here, as shown in FIG. 4A, the insulating layer 250 preferably has a stacked-layer structure of an insulating layer 250_1 in contact with the oxide semiconductor layer 230, an insulating layer 250_2 over the insulating layer 250_1, and an insulating layer 250_3 over the insulating layer 250_2.

[0154] 4B is a cross-sectional view illustrating a structural example of the insulating layer 224, the oxide layer 227, the oxide semiconductor layer 230, the layer 233a, the layer 233b, the conductive layer 242a, the conductive layer 242b, the insulating layer 271a, the insulating layer 271b, the insulating layer 275, the insulating layer 280, the insulating layer 250, the conductive layer 260, the insulating layer 282, and the insulating layer 283. In addition, FIG. 4B illustrates an example in which the insulating layer 250 has a stacked structure of an insulating layer 250_1, an insulating layer 250_2 over the insulating layer 250_1, an insulating layer 250_4 over the insulating layer 250_2, and an insulating layer 250_3 over the insulating layer 250_4. At this time, the insulating layer 250_1 is formed in the opening 289 in contact with the top surface of the insulating layer 222, the side surface of the insulating layer 224, the side surface and top surface of the oxide semiconductor layer 230, the side surface of the conductive layer 242a, the side surface of the conductive layer 242b, the side surface of the insulating layer 271a, the side surface of the insulating layer 271b, the side surface of the insulating layer 275, and the side surface of the insulating layer 280.

[0155] The insulating layer 250_1 can be formed using any of the materials that can be used for the insulating layer 250. For example, the insulating layer 250_1, which has a region in contact with the side surfaces of the conductive layer 242a and the conductive layer 242b, has a function of capturing or fixing oxygen, thereby preventing the side surfaces of the conductive layer 242a and the conductive layer 242b from being oxidized and forming an oxide film on the side surfaces. This can prevent a decrease in the on-state current or the field-effect mobility of the transistor 200. Furthermore, with such a structure, the amount of oxygen in the insulating layer 250_2 absorbed by the conductive layer 242a and the conductive layer 242b can be reduced. Therefore, an appropriate amount of oxygen can be supplied from the insulating layer 250_2 to the oxide semiconductor layer 230, and oxygen vacancies in the channel formation region of the oxide semiconductor layer 230 can be reduced.

[0156] Furthermore, by providing the insulating layer 250_1 between the insulating layer 280 and the insulating layer 250_2 and between the insulating layer 250_2 and the oxide semiconductor layer 230, excessive supply of oxygen from the insulating layer 280 to the oxide semiconductor layer 230 can be suppressed, and an appropriate amount of oxygen can be supplied to the oxide semiconductor layer 230. Therefore, the amount of oxygen in the channel formation region of the oxide semiconductor layer 230 and its vicinity can be controlled to an appropriate amount, thereby preventing the transistor 200 from becoming excessively normally off and improving reliability. Furthermore, excessive oxidation of the source and drain regions can be suppressed, which can cause a decrease in on-state current or a decrease in field-effect mobility of the transistor 200.

[0157] By adopting the above-described structure, the channel formation region can be made i-type or substantially i-type, and the source region and drain region can be made n-type, for example, thereby providing a semiconductor device with excellent electrical characteristics. Furthermore, by adopting the above-described structure, the semiconductor device can have excellent electrical characteristics even when miniaturized or highly integrated. Furthermore, miniaturizing the transistor 200 can improve high-frequency characteristics. Specifically, the cutoff frequency can be improved.

[0158] It is also preferable to use a high-k material with a high relative dielectric constant for the insulating layer 250_1. An example of a high-k material is an oxide containing one or both of aluminum and hafnium. Using a high-k material for the insulating layer 250_1 makes it possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulating layer. Furthermore, it is possible to reduce the equivalent oxide thickness (EOT) of the insulating layer that functions as the gate insulating layer.

[0159] From the above, it is preferable to use an oxide containing one or both of aluminum and hafnium as the insulating layer 250_1, and it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium. Aluminum oxide having an amorphous structure is more preferable because an amorphous film can be formed relatively easily using an ALD method. In this embodiment, aluminum oxide is used as the insulating layer 250_1. Aluminum oxide has a function of capturing or fixing oxygen and hydrogen, and therefore can be suitably used as the insulating layer 250_1.

[0160] For example, the insulating layer 250_2 preferably includes a material with a low dielectric constant, such as a silicon oxide film or a silicon oxynitride film.

[0161] Silicon oxide or silicon nitride is an insulating material with high dielectric strength. This can reduce leakage current of a transistor. Furthermore, a silicon oxide film or a silicon oxynitride film is also a film with high hydrogen permeability. Therefore, the insulating layer 250 may have a three-layer structure including an insulating layer 250_2, an insulating layer 250_1 over the insulating layer 250_2, and an insulating layer 250_3 over the insulating layer 250_1. With this structure, hydrogen in the oxide semiconductor layer 230 can diffuse to the insulating layer 250_1 through the insulating layer 250_2 and be captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced.

[0162] The insulating layer 250_3 preferably has a barrier property against hydrogen. With such a structure, diffusion of hydrogen into the oxide semiconductor layer 230 can be suppressed. Furthermore, the insulating layer 250_3 preferably has a barrier property against oxygen. The insulating layer 250_3 is provided between the channel formation region of the oxide semiconductor layer 230 and the conductive layer 260. With such a structure, oxygen contained in the channel formation region of the oxide semiconductor layer 230 can be prevented from diffusing into the conductive layer 260 and forming oxygen vacancies in the channel formation region of the oxide semiconductor layer 230. Furthermore, oxygen contained in the oxide semiconductor layer 230 can be prevented from diffusing into the conductive layer 260 and oxidizing the conductive layer 260. The insulating layer 250_3 is preferably at least less permeable to oxygen than the insulating layer 250_2. Furthermore, the insulating layer 250_3 preferably has a function of suppressing diffusion of hydrogen. This can prevent impurities such as hydrogen contained in the conductive layer 260 from diffusing into the oxide semiconductor layer 230. For example, silicon nitride is preferably used as the insulating layer 250_3.

[0163] The insulating layer 250_4 can be formed using an insulating material that can be used for the insulating layer 250_1. For example, the insulating layer 250_4 preferably has a function of capturing or fixing hydrogen. By providing the insulating layer 250_4 between the insulating layer 250_3 and the insulating layer 250_2, hydrogen contained in the insulating layer 250_2 and the like can be more effectively captured or fixed.

[0164] Specifically, the insulating layer 250 preferably has a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the oxide semiconductor layer 230 side. With such a structure, hydrogen in the oxide semiconductor layer 230 can diffuse to the insulating layer 250_1 or the insulating layer 250_4 and be captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced.

[0165] The insulating layer 250 is preferably a thin film. For example, the subthreshold swing value (also referred to as S value) can be reduced by setting the thickness of the insulating layer 250 to 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less. Note that the S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude with the drain voltage held constant in the subthreshold region.

[0166] Furthermore, in order to miniaturize the transistor 200, the insulating layers 250_1 to 250_4 preferably have thin film thicknesses. The insulating layers 250_1 to 250_4 each have a film thickness of preferably 0.1 nm to 20 nm, more preferably 0.1 nm to 10 nm, more preferably 0.5 nm to 5.0 nm, more preferably 1.0 nm to less than 5.0 nm, and still more preferably 1.0 nm to 3.0 nm. Note that each of the insulating layers 250_1 to 250_4 preferably has a region with the above film thickness in at least a portion thereof.

[0167] Note that the insulating layer 250 may have a four-layer structure without the insulating layer 250_3. For example, an insulating layer having a function of capturing or fixing oxygen can be used as the insulating layer 250_1, an insulating layer containing a material with a low dielectric constant can be used as the insulating layer 250_2, and an insulating layer having a function of capturing or fixing hydrogen can be used as the insulating layer 250_4. Specifically, the insulating layer 250 can have a three-layer structure in which an aluminum oxide film, a silicon oxide film, and a hafnium oxide film are stacked in this order from the oxide semiconductor layer 230 side.

[0168] In order to thin the insulating layers 250_1 to 250_4 as described above, the insulating layers 250_1 to 250_4 are preferably deposited by an ALD method. In addition, in order to form the insulating layers 250_1 to 250_4 in the opening 289 with good coverage, the insulating layers 250_1 to 250_4 are preferably deposited by an ALD method.

[0169] It is preferable to use the ALD process two or more times in forming the insulating layer 250 having a stacked structure of multiple insulating films. For example, it is preferable that two or more of the multiple insulating films included in the insulating layer 250 are formed using the ALD process. By forming at least two or more types of insulating films using the ALD process, it is possible to improve the coverage and film thickness uniformity of the insulating layer 250. Furthermore, for example, it is possible to increase productivity by successively forming two or more types of insulating films using the ALD process.

[0170] Although the above description has been given of a structure in which the insulating layer 250 has a three-layer structure of insulating layers 250_1 to 250_3 or a four-layer structure of insulating layers 250_1 to 250_4, the present invention is not limited to this. The insulating layer 250 can have a structure including at least one of the insulating layers 250_1 to 250_4. By forming the insulating layer 250 using one, two, or three of the insulating layers 250_1 to 250_4, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0171] The conductive layer 205 is arranged to have a region overlapping with the oxide semiconductor layer 230 and the conductive layer 260. The conductive layer 205 can be formed using a conductive material described in [Conductive Layer] below. Here, the conductive layer 205 is provided so as to be embedded in an opening formed in the insulating layer 216. The conductive layer 205 is preferably provided to extend in the channel width direction as shown in FIGS. 1A to 4A . With this structure, the conductive layer 205 functions as a wiring when a plurality of transistors 200 are provided.

[0172] 4A , the conductive layer 205 preferably includes a conductive layer 205_1 and a conductive layer 205_2. The conductive layer 205_1 is provided in contact with the bottom surface and sidewall of the opening. The conductive layer 205_2 is provided so as to fill a recess in the conductive layer 205_1 formed along the opening. Here, the height of the top surface of the conductive layer 205 is the same as or approximately the same as the height of the top surface of the insulating layer 216.

[0173] Here, the conductive layer 205_1 contains hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to have a conductive material that has a function of suppressing the diffusion of impurities such as copper atoms, etc., or a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0174] By using a conductive material having a function of reducing hydrogen diffusion for the conductive layer 205_1, impurities such as hydrogen contained in the conductive layer 205_2 can be prevented from diffusing into the oxide semiconductor layer 230 through the insulating layer 216 or the like. Furthermore, by using a conductive material having a function of suppressing oxygen diffusion for the conductive layer 205_1, it is possible to suppress a decrease in the conductivity of the conductive layer 205_2 due to oxidation. Examples of conductive materials having a function of suppressing oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The conductive layer 205_1 can have a single-layer structure or a stacked-layer structure of any of the above conductive materials. For example, the conductive layer 205_1 preferably contains titanium nitride.

[0175] The conductive layer 205_2 is preferably formed using a conductor with high conductivity. For example, the conductive layer 205_2 is preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component. For example, the conductive layer 205_2 preferably contains tungsten.

[0176] The conductive layer 205 can function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductive layer 205 independently of the potential applied to the conductive layer 260. In particular, applying a negative potential to the conductive layer 205 can increase the Vth of the transistor 200 and reduce the off-state current. Therefore, applying a negative potential to the conductive layer 205 can reduce the drain current when the potential applied to the conductive layer 260 is 0 V, compared to when no negative potential is applied.

[0177] 4A shows a stacked structure of the conductive layer 205_1 and the conductive layer 205_2, the present invention is not limited thereto, and the conductive layer 205 may have a single-layer structure or a stacked structure of three or more layers. For example, the conductive layer 205_1 may have a two-layer structure of a tantalum nitride film and a titanium nitride film on the tantalum nitride film, and the conductive layer 205_2 having a tungsten film may be provided on the conductive layer 205_1. With such a structure, impurities such as hydrogen and metal impurities such as copper contained in the lower layer of the transistor 200 can be prevented from diffusing into the conductive layer 205.

[0178] The insulating layer 224 functions as a second gate insulating layer together with the insulating layers 221 and 222 .

[0179] The insulating layer 224 preferably includes, for example, a silicon oxide film or a silicon oxynitride film. This allows oxygen to be supplied from the insulating layer 224 to the oxide semiconductor layer 230, thereby reducing oxygen vacancies. Note that the insulating layer 224 may have a stacked structure of two or more layers. In this case, the insulating layer 224 is not limited to a stacked structure made of the same material, and may have a stacked structure made of different materials.

[0180] Similarly to the oxide semiconductor layer 230, the insulating layer 224 is preferably processed into an island shape. Thus, when a plurality of transistors 200 are provided, each transistor 200 has an insulating layer 224 of approximately the same size. As a result, the amount of oxygen supplied from the insulating layer 224 to the oxide semiconductor layer 230 in each transistor 200 becomes approximately the same. Therefore, variation in the electrical characteristics of the transistors 200 within the substrate plane can be suppressed.

[0181] Furthermore, by providing the insulating layer 224 in an island shape, at least a part of the lower surface of the conductive layer 260 can be provided below the lower surface of the oxide semiconductor layer 230 (see FIG. 2B ). This allows the conductive layer 260 to be provided facing the upper surface and side surface of the oxide semiconductor layer 230, and therefore the electric field of the conductive layer 260 can be applied to the upper surface and side surface of the oxide semiconductor layer 230.

[0182] However, the insulating layer 224 does not necessarily have to be processed into an island shape. For example, as shown in Figures 5A to 5C, the insulating layer 224 may not be formed into an island shape, but may have an opening formed in a part of it. Here, Figures 5A, 5B, and 5C correspond to Figures 2A, 2B, and 2C, respectively. Note that Figures 1A and 1B can be referred to for plan views of the semiconductor device shown in Figures 5A to 5C.

[0183] 5A to 5C , the thickness of a region that does not overlap with the oxide layer 227 is thinner than the thickness of a region that overlaps with the oxide layer 227. The insulating layer 224 has an opening in a region that does not overlap with the oxide layer 227 and overlaps with the insulating layer 250. When a plurality of transistors are provided over the same substrate, providing the insulating layer 224 in this manner allows the oxide semiconductor layer 230 of each transistor to be provided over the same insulating layer 224. This can reduce variation in the amount of oxygen supplied from the insulating layer 224 to the oxide semiconductor layer 230 of each transistor. Therefore, variation in the electrical characteristics of each transistor can be reduced.

[0184] Note that, for example, in the insulating layer 224 shown in FIG. 5B, an opening is formed in the region that does not overlap with the oxide layer 227 and overlaps with the insulating layer 250, but the opening may not be provided.

[0185] The conductive layers 242a, 242b, and 260 can be formed using the conductive materials described in the section "Conductive Layer" below. In particular, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion for the conductive layers 242a, 242b, and 260. Examples of such conductive materials include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layers 242a, 242b, and 260.

[0186] For the conductive layers 242a and 242b, it is preferable to use a metal nitride, such as a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. For example, tantalum nitride can be used for the conductive layers 242a and 242b. Alternatively, for example, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferable because they are conductive materials that are resistant to oxidation or that maintain their conductivity even when they absorb oxygen.

[0187] Alternatively, the conductive layer 242a and the conductive layer 242b may each have a stacked structure. In this case, it is preferable to use the above-mentioned conductive material for the lower layer of the conductive layer 242a and the conductive layer 242b and to use a conductive material having higher conductivity than the upper layer of the conductive layer 242a and the conductive layer 242b. For example, tantalum nitride can be used for the lower layer and tungsten can be used for the upper layer.

[0188] The insulating layers 271a and 271b are inorganic insulating layers that function as etching stoppers and protect the conductive layers 242a and 242b when processing the conductive layers 242a and 242b. Furthermore, since the insulating layers 271a and 271b are in contact with the conductive layers 242a and 242b, they are preferably inorganic insulators that are less likely to oxidize the conductive layers 242a and 242b. Therefore, each of the insulating layers 271a and 271b preferably has a two-layer structure. Here, the lower layers of the insulating layers 271a and 271b are preferably made of a nitride insulator that can be used for the insulating layer 250_3, and preferably made of silicon nitride, in order to prevent the conductive layers 242a and 242b from being oxidized. The insulating layer 271a and the insulating layer 271b are each preferably formed using an oxide insulator, which can be used for the insulating layer 250_2, and preferably using silicon oxide, so as to function as an etching stopper.

[0189] The insulating layers that are the basis for the insulating layers 271a and 271b function as masks for the conductive layers that are the basis for the conductive layers 242a and 242b. Therefore, as shown in FIG. 2A , for example, the conductive layers 242a and 242b do not have curved upper ends. As a result, the conductive layers 242a and 242b have angular upper ends. The angular upper ends of the conductive layers 242a and 242b increase the cross-sectional areas of the conductive layers 242a and 242b compared to when the upper ends have curved surfaces. As a result, the resistance of the conductive layers 242a and 242b is reduced, thereby increasing the on-state current of the transistor 200.

[0190] The conductive layer 260 is provided in the opening 289 so as to cover, via the insulating layer 250, the upper surface of the insulating layer 222, the side surface of the insulating layer 224, the side surface of the oxide layer 227, and the side surface and upper surface of the oxide semiconductor layer 230. The height of the upper surface of the conductive layer 260 is equal to or approximately equal to the height of the upper end of the insulating layer 250 and the height of the upper surface of the insulating layer 280.

[0191] The sidewall of the opening 289 may be perpendicular or approximately perpendicular to the upper surface of the insulating layer 222, or may be tapered. By tapering the sidewall, the coverage of the insulating layer 250 provided in the opening 289 is improved, and defects such as voids can be reduced.

[0192] In this specification and the like, the sidewall of an opening refers to the side surface within the opening of the layer in which the opening is formed.

[0193] 1A to 4A, the conductive layer 260 is preferably provided to extend in the channel width direction. With this structure, when a plurality of transistors 200 are provided, the conductive layer 260 functions as a wiring.

[0194] The conductive layer 260 is preferably made of a highly conductive material such as tungsten. Furthermore, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion as the conductive layer 260. Examples of such conductive materials include conductive materials containing nitrogen (e.g., titanium nitride or tantalum nitride) and conductive materials containing oxygen (e.g., ruthenium oxide). This can suppress a decrease in the conductivity of the conductive layer 260.

[0195] The conductive layer 260 is preferably formed using a conductive material containing oxygen and a metal element contained in the oxide semiconductor layer 230. That is, the conductive layer 260 is preferably formed using a conductive material containing indium and oxygen. Alternatively, a conductive material containing nitrogen (for example, titanium nitride, tantalum nitride, or the like) may be used. Alternatively, one or more selected from indium tin oxide (In—Sn oxide, also referred to as ITO), indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, In—Zn oxide, and indium tin oxide containing silicon oxide (also referred to as ITSO) may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. By using such a material, hydrogen contained in the oxide semiconductor layer 230 can be captured in some cases. Alternatively, hydrogen entering from an outer insulating layer or the like can be captured in some cases.

[0196] 2B , in a cross-sectional view of the transistor 200 in the channel width direction, a curved surface may be formed between the side surface of the oxide semiconductor layer 230 and the top surface of the oxide semiconductor layer 230. In other words, the end of the side surface and the end of the top surface may be curved.

[0197] 4A, for example, the conductive layer 260 preferably has a two-layer structure. Here, the conductive layer 260 preferably includes a conductive layer 260_1 and a conductive layer 260_2 disposed over the conductive layer 260_1. For example, the conductive layer 260_1 is preferably disposed so as to surround the bottom and side surfaces of the conductive layer 260_2. In this case, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion as the conductive layer 260_1.

[0198] The conductive layer 260_1 can be formed using a conductive material that can be used for the conductive layer 205_1. For example, the conductive layer 260_1 has a function of suppressing oxygen diffusion, which can suppress a decrease in the conductivity of the conductive layer 260_2 due to oxidation of the conductive layer 260_2 by oxygen contained in the insulating layer 280 or the like.

[0199] The conductive layer 260_2 can be formed using a conductive material that can be used for the conductive layer 205_2. The conductive layer 260_2 may have a stacked-layer structure, for example, a stacked-layer structure of a titanium film or a titanium nitride film and a conductive material that can be used for the conductive layer 205_2.

[0200] The insulating layer 216, the insulating layer 280, and the insulating layer 285 preferably have a lower relative dielectric constant than the insulating layer 222. By using a material with a low relative dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.

[0201] For example, the insulating layer 216, the insulating layer 280, and the insulating layer 285 can each be made of a material with a low dielectric constant, as described in the "Insulating Layer" section below. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are also preferred because they allow for the easy formation of a region containing excess oxygen.

[0202] Furthermore, the upper surfaces of the insulating layer 216 and the insulating layer 280 may each be flattened.

[0203] It is preferable that the concentration of impurities such as water and hydrogen is reduced in the insulating layer 280. For example, it is preferable that the insulating layer 280 has an oxide containing silicon, such as silicon oxide or silicon oxynitride.

[0204] The conductive layers 243a and 243b can be formed using a conductive material described in the section "Conductive Layer" below. The conductive layers 243a and 243b are preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component, for example. The conductive layers 243a and 243b may have a stacked structure.

[0205] 4A, the conductive layer 243a and the conductive layer 243b may have a two-layer laminated structure. The conductive layer 243a includes a conductive layer 243a1 formed along the opening 244a and a conductive layer 243a2 formed inside the conductive layer 243a1. The conductive layer 243b includes a conductive layer 243b1 formed along the opening 244b and a conductive layer 243b2 formed inside the conductive layer 243b1.

[0206] The conductive layer 243a1 and the conductive layer 243b1 can be formed as a single layer or a stacked layer using a conductive material that can be used for the conductive layer 205_1. Providing the conductive layer 243a1 and the conductive layer 243b1 can prevent impurities such as water and hydrogen from entering the oxide semiconductor layer 230 through the conductive layer 243a2 and the conductive layer 243b2. Note that the conductive layer 243a2 and the conductive layer 243b2 are preferably formed using a conductive material that can be used for the conductive layer 243a and the conductive layer 243b.

[0207] 2A and 4A, the height of the upper surfaces of the conductive layers 243a and 243b is the same or approximately the same as the height of the upper surface of the insulating layer 285. Also, as shown in Fig. 4A, the lower part of the conductive layer 243a may be formed so as to be embedded in the conductive layer 242a. Similarly, the lower part of the conductive layer 243b may be formed so as to be embedded in the conductive layer 242b.

[0208] The insulating layers 241a and 241b are preferably barrier insulating layers applicable to the insulating layer 275 and the like. For example, silicon nitride is preferably used for the insulating layers 241a and 241b. The insulating layers 241a and 241b are provided in contact with the insulating layers 285, 283, 282, 275, 271a, and 271b. This can prevent impurities such as water and hydrogen contained in the insulating layer 280 and the like from being mixed into the oxide semiconductor layer 230 through the conductive layers 243a and 243b. Silicon nitride is particularly suitable because it has a high barrier property against hydrogen. Furthermore, oxygen contained in the insulating layer 280 can be prevented from being absorbed by the conductive layers 243a and 243b.

[0209] The insulating layer 241 a and the insulating layer 241 b may have a stacked structure. In this case, a first insulating layer in contact with a sidewall of an opening such as the insulating layer 280 and a second insulating layer on the inner side thereof preferably use a combination of a barrier insulating layer against oxygen and a barrier insulating layer against hydrogen.

[0210] <Configuration Example 2 of Semiconductor Device> The following describes a semiconductor device having a configuration different from that shown in Figures 1A to 5C. Note that the following mainly describes the parts that are different from the semiconductor device shown in Figures 1A to 5C, and descriptions of overlapping parts may be omitted.

[0211] In the example shown in Figures 2A and 2B, the insulating layer 250 contacts the side surfaces of the insulating layer 280, the insulating layer 275, the insulating layer 271a, and the insulating layer 271b in the opening 289, but the present invention is not limited to this configuration. For example, as shown in Figures 6A and 6B, an insulating layer may be provided between the insulating layer 250 and the insulating layer 280 in the opening 289. Here, Figures 6A and 6B correspond to Figures 2A and 2B, respectively. Note that Figures 1A and 1B can be referred to for plan views of the semiconductor device shown in Figures 6A and 6B. Also, Figure 2C can be referred to for a cross-sectional view between the dashed dotted line A5-A6 shown in Figures 1A and 1B.

[0212] 7A is a cross-sectional view illustrating an example of the structure of the insulating layer 224, the oxide layer 227, the oxide semiconductor layer 230, the layer 233a, the layer 233b, the conductive layer 242a, the conductive layer 242b, the insulating layer 271a, the insulating layer 271b, the insulating layer 275, the insulating layer 280, the insulating layer 250, the conductive layer 260, the insulating layer 282, and the insulating layer 283 shown in FIG. 7A illustrates an example in which the insulating layer 250 has a stacked structure of an insulating layer 250_1, an insulating layer 250_2 over the insulating layer 250_1, and an insulating layer 250_3 over the insulating layer 250_2. 7B and 7C show an example in which the insulating layer 250 has a stacked structure of an insulating layer 250_1, an insulating layer 250_2 on the insulating layer 250_1, an insulating layer 250_4 on the insulating layer 250_2, and an insulating layer 250_3 on the insulating layer 250_4.

[0213] 6A to 7C, the conductive layer 242a and the conductive layer 242b are each shown as a two-layer structure. The conductive layer 242a has a stacked structure of a conductive layer 242a1 and a conductive layer 242a2 on the conductive layer 242a1. The conductive layer 242b has a stacked structure of a conductive layer 242b1 and a conductive layer 242b2 on the conductive layer 242b1. The conductive layers 242a1 and 242b1 correspond to the lower layers of the conductive layers 242a and 242b, respectively, and the conductive layers 242a2 and 242b2 correspond to the upper layers of the conductive layers 242a and 242b, respectively.

[0214] 6A to 7C includes an insulating layer 254. As shown in FIGS. 6A to 7C , the insulating layer 254 is disposed in the opening 289 and is in contact with the side surfaces of the insulating layer 280, the side surfaces of the insulating layer 275, the side surfaces of the insulating layer 271a, the side surfaces of the insulating layer 271b, the side surfaces of the conductive layer 242a2, the side surfaces of the conductive layer 242b2, the top surfaces of the conductive layer 242a1, the top surfaces of the conductive layer 242b1, and the top surface of the insulating layer 222 in the opening 289. In other words, the insulating layer 254 can be said to be in contact with the side walls of the opening 289 and to be formed in a sidewall shape.

[0215] The insulating layer 254 preferably has a barrier property against oxygen. The insulating layer 254 having a barrier property against oxygen can prevent the side surfaces of the conductive layers 242a and 242b from being oxidized and oxide films from being formed on the side surfaces. This can prevent a decrease in on-state current or a decrease in field-effect mobility of the transistor 200. An oxygen barrier insulating layer can be used as the insulating layer 254. For example, silicon nitride is preferably used as the insulating layer 254.

[0216] The opening 289 overlaps the region between the conductive layer 242a2 and the conductive layer 242b2. In a plan view, the side surfaces of the insulating layer 280 and the insulating layer 275 in the opening 289 coincide or substantially coincide with the side surfaces of the conductive layer 242a2 and the conductive layer 242b2. Also, in a plan view, the side surfaces of the insulating layer 271a in the opening 289 coincide or substantially coincide with the side surfaces of the conductive layer 242a2, and the side surfaces of the insulating layer 271b coincide or substantially coincide with the side surfaces of the conductive layer 242b2. Furthermore, portions of the conductive layers 242a1 and 242b1 are formed to protrude into the opening 289. In other words, the region of the conductive layer 242a1 on whose upper surface the insulating layer 254 is formed (hereinafter, sometimes referred to as the protruding portion of the conductive layer 242a1) protrudes toward the conductive layer 260 more than the conductive layer 242a2. Similarly, in the conductive layer 242b1, the region on whose upper surface the insulating layer 254 is formed (hereinafter, sometimes referred to as the protruding portion of the conductive layer 242b1) is formed to protrude toward the conductive layer 260 side more than the conductive layer 242b2.

[0217] Here, part of the top surface of the conductive layer 242a1 is in contact with the conductive layer 242a2, and part of the top surface of the conductive layer 242b1 is in contact with the conductive layer 242b2. Therefore, the insulating layer 254 is in contact with another part of the top surface of the conductive layer 242a1, another part of the top surface of the conductive layer 242b1, a side surface of the conductive layer 242a2, and a side surface of the conductive layer 242b2 inside the opening 289. Furthermore, the insulating layer 250 is in contact with the top surface of the oxide semiconductor layer 230, the side surface of the conductive layer 242a1, the side surface of the conductive layer 242b1, and the side surface of the insulating layer 254.

[0218] The insulating layer 254 is formed by anisotropic etching to have a sidewall shape in contact with the side wall of the opening 289. The insulating layer 254 is formed in contact with the side surface of the conductive layer 242a2 and the side surface of the conductive layer 242b2 and has a function of protecting the conductive layer 242a2 and the conductive layer 242b2.

[0219] Furthermore, the insulating layer 254 functions as a mask when separating the conductive layer 242a1 from the conductive layer 242b1. Therefore, as shown in Fig. 7A, within the opening 289, the side edges of the insulating layer 254 coincide or substantially coincide with the side edges of the conductive layer 242a1 and the conductive layer 242b1.

[0220] Note that after separating the conductive layer 242a1 and the conductive layer 242b1, it is preferable to perform heat treatment in an atmosphere containing oxygen before forming the insulating layer 250. At this time, since the insulating layer 254 is formed in contact with the side surfaces of the conductive layer 242a2 and the conductive layer 242b2, excessive oxidation of the conductive layer 242a2 and the conductive layer 242b2 can be prevented. Furthermore, even when microwave plasma treatment is performed after separating the conductive layer 242a1 and the conductive layer 242b1, formation of an oxide film on the side surfaces of the conductive layer 242a and the conductive layer 242b can be suppressed.

[0221] The insulating layer 254, the insulating layer 250, and the conductive layer 260 are provided to reflect the shape of the opening 289. Therefore, the insulating layer 254 is provided so as to cover the sidewall of the opening 289, the insulating layer 250 is provided so as to cover the bottom of the opening 289 and the insulating layer 254, and the conductive layer 260 is provided so as to fill the recess of the insulating layer 250.

[0222] The thickness of the insulating layer 254 is preferably 0.5 nm to 20 nm, more preferably 0.5 nm to 10 nm, and even more preferably 0.5 nm to 3 nm. By setting the insulating layer 254 to the above thickness, excessive oxidation of the conductive layer 242a2 and the conductive layer 242b2 can be suppressed. Note that the insulating layer 254 preferably has a region with the above thickness at least in part. Furthermore, since the insulating layer 254 is provided in contact with the sidewall of the opening 289, it is preferable to deposit the insulating layer 254 by an ALD method or the like, which has good coverage. If the insulating layer 254 is too thick, the deposition time of the insulating layer 254 by the ALD method increases, resulting in reduced productivity. Therefore, the thickness of the insulating layer 254 is preferably within the above range. The insulating layer 254 preferably has a thickness large enough not to excessively hinder diffusion of excess oxygen from the insulating layer 280 to the insulating layer 250_2 and from the insulating layer 250_2 to the oxide semiconductor layer 230.

[0223] As shown in FIG. 7A , in a cross-sectional view of the transistor 200 in the channel length direction, the distance L1 between the conductive layers 242a1 and 242b1 is smaller than the distance L2 between the conductive layers 242a2 and 242b2. Here, distance L1 refers to the shortest distance between the conductive layers 242a1 and 242b1, and distance L2 refers to the shortest distance between the conductive layers 242a2 and 242b2. This configuration allows the distance between the source and drain to be shortened, thereby shortening the channel length accordingly. This improves the frequency characteristics of the transistor 200. By miniaturizing the semiconductor device in this way, a semiconductor device with improved operating speed can be provided.

[0224] 7A , the difference between the distance L2 and the distance L1 is equal to or approximately equal to twice the film thickness of the insulating layer 254. In other words, the distance L2 is equal to or approximately equal to the distance L1 obtained by adding twice the film thickness of the insulating layer 254. Here, the film thickness of the insulating layer 254 refers to the width of at least a portion of the insulating layer 254 in the Y direction.

[0225] The insulating layer 254 may also have a stacked structure of two or more layers. In this case, at least one layer can be the inorganic insulating layer that is resistant to oxidation. For example, it is preferable to use the inorganic insulating layer that is resistant to oxidation as the first insulating layer of the insulating layer 254, and to use an insulating material (e.g., silicon oxide, etc.) applicable to the insulating layer 250_2 as the second insulating layer on the first insulating layer of the insulating layer 254. It is preferable that the second insulating layer of the insulating layer 254 has a lower dielectric constant than the first insulating layer of the insulating layer 254. In this way, by forming the insulating layer 254 into a two-layer structure and increasing its thickness, the distance between the conductive layer 260 and the conductive layer 242a or 242b can be increased, and parasitic capacitance can be reduced.

[0226] Although the above describes an example in which the insulating layer 254 is formed into a sidewall shape by anisotropic etching, the present invention is not limited to this. As shown in Figure 7C, the insulating layer 254 may also have an opening 288 inside the opening 289. In this case, the opening 288 can be formed by removing a part of the insulating film that will become the insulating layer 254 by lithography. The opening 288 preferably overlaps with the region between the conductive layer 242a1 and the conductive layer 242b1.

[0227] 7C, in a cross-sectional view, a protrusion is formed at the lower part of the insulating layer 254. The protrusion of the insulating layer 254 overlaps with the protrusion of the conductive layer 242a1 and the protrusion of the conductive layer 242b1.

[0228] 6A to 7C have described a configuration in which the insulating layer 254 is provided in contact with the sidewall of the opening 289, but the present invention is not limited to this configuration. For example, as shown in FIGS. 8A to 9, a configuration in which the insulating layer 254 is not provided inside the opening 289 may be used. Here, FIGS. 8A, 8B, and 9 correspond to FIGS. 1A, 6A, and 7C, respectively. Note that for the cross-sectional views between the dashed dotted lines A3-A4 and A5-A6 shown in FIG. 8A, reference can be made to FIGS. 2B and 2C, respectively.

[0229] 8B and 9 , in a configuration in which the insulating layer 254 is not provided, a portion of the insulating layer 250 is disposed so as to overlap the protruding portions of the conductive layer 242a1 and the conductive layer 242b1. Also, a portion of the conductive layer 260 may be disposed so as to overlap the protruding portions of the conductive layer 242a1 and the conductive layer 242b1. Here, the protruding portions of the conductive layer 242a1 and the conductive layer 242b1 contact the insulating layer 250. Furthermore, the side surface of the insulating layer 250 contacts the side surfaces of the insulating layer 280, the insulating layer 275, the insulating layer 271a, the insulating layer 271b, the conductive layer 242a2, and the conductive layer 242b2.

[0230] The insulating layer 250 is formed to reflect the shape of the opening 289. Therefore, the insulating layer 250 is formed to reflect the shapes of the conductive layers 242a1 and 242b1 protruding into the opening 289.

[0231] 9, in a cross-sectional view of the transistor 200 in the channel length direction, the distance L1 between the conductive layer 242a1 and the conductive layer 242b1 is smaller than the distance L2 between the conductive layer 242a2 and the conductive layer 242b2. This configuration allows the distance between the source and the drain to be shortened, thereby shortening the channel length accordingly. This improves the frequency characteristics of the transistor 200. By miniaturizing the semiconductor device in this way, a semiconductor device with improved operating speed can be provided.

[0232] 9, the width of the upper portion of the conductive layer 260 can be made larger than the distance L1, thereby reducing the wiring resistance of the conductive layer 260. As a result, the power consumption of the semiconductor device can be reduced.

[0233] The following describes a configuration example of a semiconductor device having a transistor with a different configuration from the above-described transistor 200. Note that differences from the semiconductor device having the transistor 200 will be mainly described, and descriptions of overlapping parts may be omitted.

[0234] [Transistor 200A] Fig. 10A is a plan view of a semiconductor device including transistor 200A. Fig. 10B is a cross-sectional view taken along dashed dotted line B1-B2 in Fig. 10A. Fig. 10C is a cross-sectional view taken along dashed dotted line B3-B4 in Fig. 10A. Fig. 10D is a cross-sectional view taken along dashed dotted line B5-B6 in Fig. 10B. Fig. 10D is also referred to as a plan view. Figs. 11A and 11B are enlarged examples of Figs. 10B and 10D, respectively.

[0235] 10A to 11B includes an insulating layer 210 over a substrate (not shown), a transistor 200A over the insulating layer 210, and an insulating layer 280 over the insulating layer 210. The transistor 200A includes a conductive layer 220, a conductive layer 240 over the insulating layer 280, an oxide semiconductor layer 230, an insulating layer 250 over the oxide semiconductor layer 230, and a conductive layer 260 over the insulating layer 250. The insulating layer 280 is located over the conductive layer 220.

[0236] 10B to 11B show an example in which the conductive layer 220 has a two-layer structure of a conductive layer 220_1 and a conductive layer 220_2 over the conductive layer 220_1. Also, an example in which the conductive layer 240 has a two-layer structure of a conductive layer 240_1 and a conductive layer 240_2 over the conductive layer 240_1 is shown. Furthermore, an example in which the conductive layer 260 has a two-layer structure of a conductive layer 260_1 and a conductive layer 260_2 over the conductive layer 260_1 is shown.

[0237] The conductive layer 260 functions as a gate electrode of the transistor 200A. The insulating layer 250 functions as a gate insulating layer of the transistor 200A. The conductive layer 220 functions as one of a source electrode and a drain electrode of the transistor 200A. The conductive layer 240 functions as the other of the source electrode and the drain electrode of the transistor 200A. The conductive layer 260 has a region that functions as a gate wiring.

[0238] As shown in FIGS. 10B, 10C, and 11A, an opening 290 is provided in the insulating layer 280 and the conductive layer 240, reaching the conductive layer 220.

[0239] The openings 290 include an opening in the insulating layer 280 and an opening in the conductive layer 240. The shape and size of the openings 290 in a plan view may differ depending on the layer. When the top surface shape of the openings 290 is circular, the openings in each layer may or may not be concentric.

[0240] The oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are each arranged so that at least a portion thereof is located within the opening 290. Furthermore, the regions of the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 that are arranged within the opening 290 are provided so as to reflect the shape of the opening 290.

[0241] The oxide semiconductor layer 230 is provided so as to cover the bottom and sidewall of the opening 290. The oxide semiconductor layer 230 has a recess that reflects the shape of the opening 290. The oxide semiconductor layer 230 has a region along the sidewall of the opening 290, a region along the top surface of the conductive layer 220, and a region along the top surface of the conductive layer 240. The oxide semiconductor layer 230 has a region that is in contact with the top surface of the conductive layer 240 and a region that is in contact with the top surface of the conductive layer 220 within the opening 290.

[0242] The insulating layer 250 is provided to cover the oxide semiconductor layer 230. The insulating layer 250 is provided on the insulating layer 280 to cover the top surface and side surfaces of the oxide semiconductor layer 230 and the side surfaces of the conductive layer 240. The insulating layer 250 has a recess that reflects the shape of the recess that the oxide semiconductor layer 230 has.

[0243] The conductive layer 260 is provided so as to fill at least a part of the recessed portion of the insulating layer 250. In addition, the conductive layer 260 has a region in the opening 290 that overlaps with the oxide semiconductor layer 230 with the insulating layer 250 sandwiched therebetween.

[0244] The oxide semiconductor layer 230 has a region overlapping with the conductive layer 260 with the insulating layer 250 interposed therebetween. At least a part of the region functions as a channel formation region 230i of the transistor 200A. A region of the oxide semiconductor layer 230 near the conductive layer 220 functions as a low-resistance region 230na. A region of the oxide semiconductor layer 230 near the conductive layer 240 functions as a low-resistance region 230nb. Similar to the transistor 200, the low-resistance region 230na functions as one of the source region and drain region of the transistor 200A. The low-resistance region 230nb functions as the other of the source region and drain region of the transistor 200A.

[0245] Specifically, in the transistor 200A, a region along the sidewall of the opening 290 in the oxide semiconductor layer 230 functions as a channel formation region 230i. A region along the top surface of the conductive layer 220 in the oxide semiconductor layer 230 functions as a low-resistance region 230na. A region along the top surface of the conductive layer 240 in the oxide semiconductor layer 230 functions as a low-resistance region 230nb.

[0246] For example, after forming a film that will become the oxide semiconductor layer 230, an impurity element can be added to the film to form the low-resistance regions 230na and 230nb without using a mask. Here, for example, when the impurity element is added from a direction perpendicular or substantially perpendicular to the top surface of the insulating layer 210, the amount of the impurity element added is smaller in the region of the film that will become the oxide semiconductor layer 230 along the sidewall of the opening 290 than in the region of the film that will become the oxide semiconductor layer 230 along the top surface of the conductive layer 220 and the region of the film that will become the oxide semiconductor layer 230 along the top surface of the conductive layer 240. Therefore, the impurity concentration in the channel formation region 230i can be lower than the impurity concentrations in the low-resistance regions 230na and 230nb. As described above, the impurity element can be a metal element with a larger period number in the periodic table, such as antimony. Note that the impurity element may be added after the oxide semiconductor layer 230 is formed.

[0247] The oxide semiconductor layer 230 is provided inside the opening 290. The transistor 200A has a structure in which one of the source electrode and the drain electrode (the conductive layer 220 here) is located below and the other of the source electrode and the drain electrode (the conductive layer 240 here) is located above, and thus current flows vertically. That is, a channel is formed along the side surface of the opening 290. This allows the transistor 200A to occupy a smaller area than a planar transistor in which a channel formation region, a source region, and a drain region are separately provided on the XY plane. Therefore, the semiconductor device can be highly integrated. Furthermore, when the semiconductor device of one embodiment of the present invention is used in a memory device, the memory capacity per unit area can be increased. Note that the channel length direction of the transistor 200A can be said to have a component in the height direction (vertical direction); therefore, the transistor 200A can be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, a vertical channel transistor, or the like.

[0248] The transistor 200A includes a metal oxide functioning as a semiconductor in the oxide semiconductor layer 230 including a channel formation region. That is, the transistor 200A can be said to be an OS transistor.

[0249] As shown in FIG. 11A , the conductive layer 220 has a recess that overlaps with the opening 290. Specifically, the recess is provided in the conductive layer 220_2 at a position that overlaps with the opening 290. By having the recess at the position that overlaps with the opening 290, the height of the bottom surface of the insulating layer 250 and the height of the bottom surface of the conductive layer 260 in the opening 290 can be lower than the height of the top surface of the conductive layer 220_2 that is in contact with the insulating layer 280, relative to the top surface of the insulating layer 210, as compared to when the conductive layer 220_2 does not have the recess. Here, the height of each surface can be determined based on the surface on which the transistor is to be formed. Here, the top surface of the insulating layer 210 is used as the reference. The surface used as the reference is not limited to the surface on which the transistor is to be formed. For example, the top surface of a substrate on which a transistor or a semiconductor device is provided may be used as the reference.

[0250] The oxide semiconductor layer 230 is in contact with the bottom and side surfaces of the recessed portion of the conductive layer 220_2. The recessed portion in the conductive layer 220_2 can increase the area where the oxide semiconductor layer 230 and the conductive layer 220_2 are in contact with each other. Therefore, the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220_2 can be reduced.

[0251] 10C illustrates a structure in which the end of the conductive layer 240 and the end of the oxide semiconductor layer 230 are aligned or substantially aligned outside the opening 290. The conductive layer 240 and the oxide semiconductor layer 230 can be manufactured by processing using the same mask. This is preferable because the number of masks required for manufacturing a semiconductor device can be reduced. Note that the present invention is not limited to this. For example, a structure may be employed in which any one of the end of the oxide semiconductor layer 230, the end of the conductive layer 240_1, and the end of the conductive layer 240_2 is located inside or outside the other in the X direction or Y direction.

[0252] It is preferable that the side surface of the conductive layer 240 and the side surface of the insulating layer 280 coincide or substantially coincide within the opening 290. With such a configuration, the opening 290 can be formed simultaneously in the conductive layer 240 and the insulating layer 280. Furthermore, the film thickness distribution of the oxide semiconductor layer 230 and the like provided within the opening 290 can be made uniform. Furthermore, it is possible to prevent the oxide semiconductor layer 230 and the like from being divided by a step or the like between the conductive layer 240 and the insulating layer 280.

[0253] 10A , the transistor 200A is provided at the intersection of a conductive layer 260 extending in the X direction and a conductive layer 240 extending in the Y direction. As shown in FIG. 10A , the diameter of the opening 290 can be made smaller than both the width of the short side of the conductive layer 240 and the width of the short side of the conductive layer 260. In this way, the transistor 200A can be said to have a structure that allows for high integration and miniaturization.

[0254] As shown in FIGS. 10D and 11B , by forming the opening 290 to have a circular shape in a plan view, the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are arranged concentrically. Therefore, the side surface of the conductive layer 260 provided at the center of the opening 290 faces the side surface of the oxide semiconductor layer 230 with the insulating layer 250 interposed therebetween. That is, in a plan view, the entire periphery of the oxide semiconductor layer 230 becomes a channel formation region. In this case, for example, the channel width of the transistor 200A is determined by the periphery length of the oxide semiconductor layer 230. That is, the channel width of the transistor 200A can be determined by the width of the opening 290 (or the diameter when the opening 290 is circular in a plan view). In FIGS. 11A and 11B , the width D of the opening 290 is shown. Also, in FIG. 11B , the channel width W of the transistor 200A is shown.

[0255] Furthermore, by providing the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 concentrically, the distance between the conductive layer 260 and the oxide semiconductor layer 230 becomes approximately uniform, and therefore a gate electric field can be applied to the oxide semiconductor layer 230 approximately uniformly.

[0256] Increasing the width D of the opening 290 increases the channel width per unit area, thereby increasing the on-state current. Meanwhile, the area occupied by the transistor 200A, for example, the area of ​​the transistor 200A in a plan view, is roughly determined by the width of the opening 290. Reducing the width D of the opening 290 reduces the area occupied by the transistor 200A, thereby enabling a semiconductor device to be highly integrated.

[0257] The width D of the opening 290 may vary in the depth direction. Here, the shortest distance between the two side surfaces of the conductive layer 240 on the opening side in a cross-sectional view is used as the width D. In other words, the minimum width of the opening in the conductive layer 240 is used as the width D of the opening 290. Alternatively, the width of the opening at the highest position in the conductive layer 240, the width of the opening at the lowest position, the width of the opening at a midpoint between these, or the average value of these three widths may be used as the width D. Here, an example is shown in which the width D of the opening 290 is determined using the width of the opening in the conductive layer 240, but the method for determining the width D is not particularly limited. For example, the shortest distance between the two side surfaces of the insulating layer 280 on the opening side may be used as the width D. Alternatively, the width of the opening at the highest position in the insulating layer 280, the width of the opening at the lowest position, the width of the opening at a midpoint between these, or the average value of these three widths may be used as the width D of the opening 290.

[0258] The width D of the opening 290 is set depending on the film thickness of each of the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 provided in the opening 290. The width D of the opening 290 is, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and is preferably 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less. When the opening 290 has a circular shape in a plan view, the width D of the opening 290 corresponds to the diameter of the opening 290, and the channel width W can be calculated as "D × π".

[0259] In this embodiment, an example is shown in which the opening 290 is circular in plan view. By using a circular shape, the processing accuracy during the formation of the opening can be improved, and openings of minute sizes can be formed. However, the present invention is not limited to this. In plan view, the opening 290 can be, for example, a circle or a substantially circular shape such as an ellipse, a polygonal shape such as a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, or a star-shaped polygon, or a polygonal shape with rounded corners. The circle is not limited to a perfect circle. Furthermore, the polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles equal to or less than 180 degrees).

[0260] The channel length of the transistor 200A is the distance between the low-resistance region 230na and the low-resistance region 230nb. In other words, the channel length of the transistor 200A is determined by the thickness of the insulating layer 280 on the conductive layer 220. Therefore, the channel length of the transistor 200A does not affect the area occupied by the transistor 200A, for example, the area of ​​the transistor 200A in a planar view. In FIG. 11A , the channel length L of the transistor 200A is indicated by a dashed double-headed arrow. Note that the channel length L can be considered as the distance between the edge of the region where the oxide semiconductor layer 230 and the conductive layer 220 contact each other and the edge of the region where the oxide semiconductor layer 230 and the conductive layer 240 contact each other in a cross-sectional view. In this case, the channel length L corresponds to the length of the side surface of the insulating layer 280 on the opening 290 side in a cross-sectional view.

[0261] The channel length of the transistor 200A can be set by the film thickness of the insulating layer 280. Therefore, the channel length of the transistor 200A can be, for example, 500 nm or less, 300 nm or less, 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and can be 0.1 nm or more, 1 nm or more, or 5 nm or more. Typically, the channel length can be 1 nm or more and 300 nm or less, preferably 5 nm or more and 100 nm or less. This can improve productivity and yield in forming the insulating layer 280, forming the opening 290 in the insulating layer 280, and the like. Furthermore, the on-state current of the transistor 200A can be increased, thereby improving frequency characteristics.

[0262] The channel length L of the transistor 200A is preferably at least shorter than the channel width W of the transistor 200A. The channel length L of the transistor 200A is preferably 0.1 to 0.99 times, more preferably 0.5 to 0.8 times, the channel width W of the transistor 200A. With such a structure, a transistor with good electrical characteristics and high reliability can be realized.

[0263] Since the insulating layer 210 functions as an interlayer film, it is preferable to use a material with a low relative dielectric constant. By using a material with a low relative dielectric constant for the interlayer film, parasitic capacitance occurring between wirings can be reduced.

[0264] The insulating layer 210 preferably has a barrier property against hydrogen. When the insulating layer 210 provided below the oxide semiconductor layer 230 has a barrier property against hydrogen, diffusion of hydrogen from below the transistor 200A to the oxide semiconductor layer 230 can be suppressed.

[0265] The insulating layer 210 preferably has a function of capturing or fixing hydrogen. When the insulating layer 210 has a function of capturing or fixing hydrogen, hydrogen in the oxide semiconductor layer 230 can be diffused to the insulating layer 210 through the conductive layer 220 and the hydrogen can be captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced.

[0266] The concentration of impurities such as hydrogen or water in the insulating layer 210 is preferably reduced, which can prevent impurities such as hydrogen or water from entering a channel formation region of the oxide semiconductor layer 230.

[0267] For example, FIG. 11A shows an example in which the insulating layer 210 has a single-layer structure. The insulating layer 210 can have a stacked structure of two or more layers. For example, the insulating layer 210 can have a two-layer structure of a first insulating layer and a second insulating layer on the first insulating layer. In this case, for example, it is preferable that the first insulating layer has a barrier property against hydrogen, and the second insulating layer has a function of capturing or fixing hydrogen. Specifically, it is preferable to use silicon nitride as the first insulating layer and aluminum oxide, hafnium oxide, hafnium zirconium oxide, or hafnium silicate as the second insulating layer.

[0268] 12 is a diagram showing an example in which an oxide layer 227 is provided below the oxide semiconductor layer 230 shown in FIG. 11A . In a semiconductor device including a transistor 200A, the oxide layer 227 is preferably thin. For example, the oxide layer 227 is preferably thinner than the oxide semiconductor layer 230. When the oxide semiconductor layer 230 is in contact with the conductive layer 240 via the oxide layer 227, an increase in contact resistance between the oxide semiconductor layer 230 and the conductive layer 240 can be suppressed. Specifically, the oxide layer 227 preferably has a region with a thickness of 0.1 nm or more and less than 2 nm, and more preferably has a region with a thickness of 0.5 nm or more and less than 2 nm.

[0269] For example, FIG. 11A shows an example in which the insulating layer 250 has a single-layer structure. Note that the insulating layer 250 can have a stacked structure of two or more layers. In this case, the insulating layer 250 is preferably formed using two or more types of films. By using two or more types of films as the insulating layer 250, the insulating layer 250 can have multiple functions. Examples of the functions of the insulating layer 250 include a function of extracting excess oxygen from the oxide semiconductor layer 230, a function of extracting hydrogen from the oxide semiconductor layer 230, and a function of suppressing diffusion of hydrogen into the oxide semiconductor layer 230.

[0270] The conductive layer 220 and the conductive layer 240 are conductive layers in contact with the oxide semiconductor layer 230, and therefore, it is preferable to use a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, a metal oxide having conductivity (also referred to as an oxide conductor), or a conductive material that has a function of suppressing oxygen diffusion, for each of them. Examples of the conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layer 220 and the conductive layer 240.

[0271] By using a conductive material containing oxygen for the conductive layer 220, the conductive layer 220 can maintain its conductivity even if it absorbs oxygen. Similarly, by using a conductive material containing oxygen for the conductive layer 240, the conductive layer 240 can maintain its conductivity even if it absorbs oxygen. Furthermore, even when an insulator containing oxygen such as hafnium oxide is used for the insulating layer 210, the conductive layer 220 is preferable because it can maintain its conductivity. For each of the conductive layer 220 and the conductive layer 240, it is preferable to use, for example, ITO, ITSO, In—Zn oxide, or the like.

[0272] When the conductive layer 220 and the conductive layer 240 each have a stacked structure, by using a conductive material containing oxygen for the layer in the stacked structure that has the largest contact area with the oxide semiconductor layer 230, the contact resistance between the conductive layer 220 and the oxide semiconductor layer 230 and between the conductive layer 240 and the oxide semiconductor layer 230 can be reduced.

[0273] 10B, 10C, and 11A has a two-layer structure including a conductive layer 240_1 and a conductive layer 240_2 over the conductive layer 240_1. In this case, for example, it is preferable to use a conductive material containing oxygen for the conductive layer 240_2 and a material having higher conductivity than the conductive layer 240_2 for the conductive layer 240_1. Specifically, it is preferable to use an oxide conductor (e.g., ITO, ITSO, or In—Zn oxide) for the conductive layer 240_2 and tungsten for the conductive layer 240_1. Ruthenium, titanium nitride, tantalum nitride, or the like may also be used for the conductive layer 240_1. By using an oxide conductor for the conductive layer 240_2 that is mainly in contact with the oxide semiconductor layer 230, the contact resistance with the oxide semiconductor layer 230 can be reduced. Furthermore, by using a material having higher conductivity than an oxide conductor for the layers constituting the conductive layer 240, the conductivity of the conductive layer 240 can be increased.

[0274] Note that a conductive material containing oxygen can be used for the conductive layer 240_1, and a material having higher conductivity than that of the conductive layer 240_2 can be used for the conductive layer 240_2. In this case, an oxide conductor is used for the layer of the conductive layer 240 that is closest to the channel formation region of the oxide semiconductor layer 230. Therefore, the current path between the source and the drain can be shortened, and the on-state current of the transistor 200A can be increased.

[0275] 10B, 10C, and 11A has a two-layer structure of a conductive layer 260_1 and a conductive layer 260_2 over the conductive layer 260_1, similar to the conductive layer 260 shown in Fig. 4A. Alternatively, the conductive layer 260 may have a stacked structure of three or more layers, similar to the conductive layer 260 shown in Fig. 4A.

[0276] 10B, 10C, and 11A show a configuration in which the side surface of the conductive layer 240 and the side surface of the insulating layer 280 are aligned or substantially aligned within the opening 290, but the present invention is not limited to this. For example, the side surface of the conductive layer 240 and the side surface of the insulating layer 280 may be discontinuous within the opening 290. Furthermore, the inclination of the side surface of the conductive layer 240 and the inclination of the side surface of the insulating layer 280 within the opening 290 may differ from each other. In this case, part of the side wall of the opening 290 has a tapered shape.

[0277] 13A and 13B show examples in which at least a portion of the sidewall of the opening 290 shown in Fig. 11A is tapered. Fig. 13A shows an example in which the side surface of the conductive layer 240 in the opening 290 is tapered. Fig. 13B shows an example in which the side surface of the conductive layer 240 and the side surface of the insulating layer 280 in the opening 290 are each tapered.

[0278] By tapering the sidewall of the opening 290, the coverage of the oxide semiconductor layer 230, the insulating layer 250, and the like can be improved, and defects such as voids can be reduced. When the sidewall of the opening 290 is tapered, for example, the taper angle (angle θ240) of the side surface of the conductive layer 240 in the opening 290 and the taper angle (angle θ280) of the side surface of the insulating layer 280 in the opening 290 are preferably 45 degrees or more and less than 90 degrees. Specifically, a taper angle of 80 degrees or more and less than 90 degrees is preferable, as this allows for miniaturization or high integration of the semiconductor device. Furthermore, a taper angle of 45 degrees or more or 50 degrees or more and less than 80 degrees, 75 degrees or less, 70 degrees or less, 65 degrees or less, or 60 degrees or less is preferable, as this improves the coverage of the film formed in the opening 290.

[0279] Furthermore, for example, it is preferable that angle θ240 is smaller than angle θ280. With such a configuration, the coverage of the oxide semiconductor layer 230 and the like on the side surface of the conductive layer 240 in the opening 290 is improved, and defects such as voids can be reduced. Furthermore, when the insulating layer 280 has a stacked structure, the inclination of the side surface of each layer in the opening 290 may be different. Similarly, when the conductive layer 240 has a stacked structure, the inclination of the side surface of each layer in the opening 290 may be different.

[0280] [Transistor 200B] Fig. 14A is a plan view of a semiconductor device including transistor 200B. Fig. 14B is a cross-sectional view taken along dashed dotted line B1-B2 in Fig. 14A. Fig. 14C is a cross-sectional view taken along dashed dotted line B3-B4 in Fig. 14A. Fig. 14D is a cross-sectional view taken along dashed dotted line B5-B6 in Fig. 14B. Fig. 14D is also referred to as a plan view.

[0281] 14A to 14D includes an insulating layer 210 over a substrate (not shown), a transistor 200B over the insulating layer 210, and an insulating layer 280 over the insulating layer 210. The semiconductor device also includes a conductive layer 243a, a conductive layer 243b, and a conductive layer 246. The semiconductor device also includes an insulating layer 283 over the transistor 200B and an insulating layer 285 over the insulating layer 283.

[0282] The transistor 200B includes a conductive layer 220 , a conductive layer 240 a and a conductive layer 240 b over an insulating layer 280 , an oxide semiconductor layer 230 , an insulating layer 250 , and a conductive layer 260 .

[0283] The conductive layer 260 functions as a gate electrode of the transistor 200B. The insulating layer 250 functions as a gate insulating layer of the transistor 200B. The conductive layer 220 functions as one of a source electrode and a drain electrode of the transistor 200B. The conductive layer 240a and the conductive layer 240b each function as the other of the source electrode and the drain electrode of the transistor 200B.

[0284] 14A to 14D, the insulating layer 280 is provided with a groove 291 that reaches the conductive layer 220. The groove 291 extends in the X direction.

[0285] In this specification and the like, a groove can be rephrased as a slit or a trench. Also, a groove portion can be rephrased as a slit portion or a trench portion. Note that a groove portion may also be rephrased as a slit or a trench.

[0286] 14A to 14D differs from the transistor 200A shown in Figures 10A to 10D in that some components of the transistor are provided in a groove 291 instead of an opening 290. The transistor 200B also differs from the transistor 200A shown in Figures 10A to 10D in that the conductive layer 240 is separated into a conductive layer 240a and a conductive layer 240b by the groove 291.

[0287] The oxide semiconductor layer 230 , the insulating layer 250 , and the conductive layer 260 are each disposed so that at least a portion thereof is located within the groove 291 .

[0288] The oxide semiconductor layer 230 is provided in an island shape. The oxide semiconductor layer 230 is provided so as to extend along part of the bottom and part of the sidewall of the groove 291. The oxide semiconductor layer 230 has a region that extends along the sidewall of the groove 291, a region that extends along the upper surface of the conductive layer 220 (the bottom surface of the recess in the conductive layer 220), and a region that extends along the upper surface of the conductive layer 240. The oxide semiconductor layer 230 has a region that contacts the upper surface of the conductive layer 240, a region that contacts the side surface of the conductive layer 240 on the groove 291 side, and a region that contacts the bottom and side surfaces of the recess in the conductive layer 220 within the groove 291.

[0289] The insulating layer 250 is provided to cover the oxide semiconductor layer 230. The insulating layer 250 is provided on the insulating layer 280 to cover the top surface and side surfaces of the oxide semiconductor layer 230 and the side surfaces of the conductive layer 240.

[0290] The conductive layer 260 is provided so as to fill at least a part of the groove 291. Therefore, the conductive layer 260 is provided so as to extend in the direction in which the groove 291 extends.

[0291] In the transistor 200B, a channel is formed along the sidewall of the groove 291. Specifically, in the transistor 200B, a region along the sidewall of the groove 291 in the oxide semiconductor layer 230 functions as a channel formation region 230i. Similarly to the transistor 200A, a region along the upper surface of the conductive layer 220 (the bottom surface of the recess of the conductive layer 220) in the oxide semiconductor layer 230 functions as a low-resistance region 230na. Furthermore, a region along the upper surface of the conductive layer 240 in the oxide semiconductor layer 230 functions as a low-resistance region 230nb. In the transistor 200B, the low-resistance regions 230na and 230nb can be formed by the same method as the low-resistance regions 230na and 230nb in the transistor 200A, respectively.

[0292] An opening 244a reaching the conductive layer 240a and an opening 244b reaching the conductive layer 240b are provided in the insulating layer 285, the insulating layer 283, the insulating layer 250, and the oxide semiconductor layer 230. A conductive layer 243a is provided in the opening 244a, and a conductive layer 243b is provided in the opening 244b. The conductive layer 243a is in contact with the conductive layer 240a, and the conductive layer 243b is in contact with the conductive layer 240b.

[0293] The conductive layer 246 is provided on the insulating layer 285. The conductive layer 246 is connected to the conductive layer 240a via the conductive layer 243a and to the conductive layer 240b via the conductive layer 243b. The conductive layer 246 functions as the other of the source wiring and the drain wiring. The conductive layer 246 extends in the Y direction. In other words, the direction in which the conductive layer 246 extends intersects with the direction in which the groove portion 291 extends.

[0294] In the transistor 200A, the width of the conductive layer 240 in the X direction (short side) needs to be larger than the width D of the opening 290 in order to provide the conductive layer 240 in an extended state. On the other hand, in the transistor 200B, the conductive layer 240a and the conductive layer 240b, which function as the other of the source electrode and the drain electrode, are connected to each other through the conductive layer 246. Therefore, the width of the conductive layer 240a and the conductive layer 240b in the X direction can be reduced, and can be made smaller than the width D1 of the groove 291 (see FIG. 14D ), for example. This allows miniaturization of the semiconductor device.

[0295] In a plan view, the side surface of the conductive layer 260 provided in the groove 291 faces the side surface of the oxide semiconductor layer 230 with the insulating layer 250 interposed therebetween. Therefore, the channel width of the transistor 200B is determined by the width D2 of the oxide semiconductor layer 230 (see FIG. 14D ). The channel width of the transistor 200B can be calculated as "2×D2."

[0296] Note that in the transistor 200A, it is not necessary to process the oxide semiconductor layer 230 in the opening 290, which facilitates processing of the oxide semiconductor layer 230 and improves productivity of the semiconductor device.

[0297] In a plan view of the transistor 200B, a region of the oxide semiconductor layer 230 located in the groove 291 does not have a curved surface. Therefore, distortion is unlikely to occur in a region of the oxide semiconductor layer 230 near the insulating layer 250, and deterioration in the crystallinity of the region can be suppressed. Note that the region includes a channel formation region.

[0298] Note that in a plan view of the transistor 200A, a region of the oxide semiconductor layer 230 located at the opening 290 has a curved surface. However, the curvature of the curved surface can be reduced (the radius of curvature of the curved surface can be increased) by increasing the width of the opening 290 or by reducing the film thickness of the oxide semiconductor layer 230. Thus, distortion occurring in a region of the oxide semiconductor layer 230 near the insulating layer 250 can be reduced, and deterioration in the crystallinity of the region can be suppressed.

[0299] 14A to 14D , the height of the top surface of the conductive layer 260 is higher than the height of the top surface of the insulating layer 250. Note that the present invention is not limited to this. The height of the top surface of the conductive layer 260 may be the same as or approximately the same as the height of the top surface of the insulating layer 250, or may be lower than the height of the top surface of the insulating layer 250.

[0300] 15A to 15C will be used to describe modifications of the transistor 200B described with reference to FIGS. 14A to 14D. FIG. 15A is a plan view of a semiconductor device including the transistor 200B. FIG. 15B is a cross-sectional view taken along dashed dotted line B1-B2 in FIG. 15A. FIG. 15C is a cross-sectional view taken along dashed dotted line B3-B4 in FIG. 15A. Note that FIG. 14D can be referred to for a cross-sectional view taken along dashed dotted line B5-B6 in FIG. 15B.

[0301] The transistor 200B shown in FIGS. 15A to 15C differs from the transistor 200B shown in FIGS. 14A to 14C in that the height of the top surface of the conductive layer 260 is lower than the height of the top surface of the insulating layer 250.

[0302] By configuring the top surface of the conductive layer 260 to be lower than the top surface of the insulating layer 250, the area where the conductive layer 260 faces the conductive layer 240a or the conductive layer 240b can be reduced, and the parasitic capacitance generated between the conductive layer 260 and the conductive layer 240a or the conductive layer 240b can be reduced. Furthermore, by configuring the above, the physical distance between the conductive layer 260 and the conductive layer 246 can be increased, and the parasitic capacitance generated between the conductive layer 260 and the conductive layer 246 can be reduced. Therefore, the frequency characteristics of a circuit using the transistor can be improved.

[0303] 14A to 14C, the cross-sectional area of ​​the conductive layer 260 functioning as a gate wiring can be larger than that of the transistor 200B shown in Figures 15A to 15C. As a result, the transistor 200B shown in Figures 14A to 14C can have lower wiring resistance than the transistor 200B shown in Figures 15A to 15C. Therefore, the power consumption of the semiconductor device can be reduced.

[0304] 14A to 15C illustrate a configuration in which the extension direction of the groove 291 coincides with the extension direction of the conductive layer 260 functioning as the gate wiring, but the present invention is not limited to this. For example, the extension direction of the groove 291 may intersect with the extension direction of the gate wiring.

[0305] [Transistor 200C] Fig. 16A is a plan view of a semiconductor device including transistor 200C. Fig. 16B is a cross-sectional view taken along dashed dotted line B1-B2 in Fig. 16A. Fig. 16C is a cross-sectional view taken along dashed dotted line B3-B4 in Fig. 16A. Fig. 16D is a cross-sectional view taken along dashed dotted line B5-B6 in Fig. 16B.

[0306] 16A to 16D includes an insulating layer 210 over a substrate (not shown), a transistor 200C over the insulating layer 210, and an insulating layer 280 over the insulating layer 210. The semiconductor device also includes an insulating layer 285 and a conductive layer 265 over the insulating layer 285. The insulating layer 285 is provided over the insulating layer 250.

[0307] Similar to the transistor 200B, the transistor 200C includes a conductive layer 220, a conductive layer 240a, a conductive layer 240b, an oxide semiconductor layer 230, an insulating layer 250, and a conductive layer 260. The oxide semiconductor layer 230 includes a channel formation region 230i, a low-resistance region 230na, and a low-resistance region 230nb.

[0308] 16A to 16D differ from the semiconductor device shown in Figures 14A to 14D mainly in that it has a conductive layer 265 and does not have an insulating layer 283, a conductive layer 243a, a conductive layer 243b, or a conductive layer 246. It also differs from the semiconductor device shown in Figures 14A to 14D mainly in that the conductive layer 260 is provided in an island shape and that the conductive layers 240a and 240b are provided in an extended manner.

[0309] The conductive layer 265 is provided to extend in the Y direction, and the conductive layers 240a and 240b are provided to extend in the X direction.

[0310] The conductive layer 260 is provided in an island shape. In a plan view, the outer periphery of the conductive layer 260 is located inside the outer periphery of the oxide semiconductor layer 230. Note that in a plan view, the outer periphery of the conductive layer 260 may overlap with a part of the outer periphery of the oxide semiconductor layer 230 or may be located outside the part of the outer periphery of the oxide semiconductor layer 230.

[0311] The conductive layer 265 contacts the conductive layer 260 .

[0312] In the YZ plane including the oxide semiconductor layer 230, the end of the oxide semiconductor layer 230 outside the groove 291 is located more inward than the end of the conductive layer 240 outside the groove 291 (see FIG. 16B ). Note that in the YZ plane including the oxide semiconductor layer 230, the end of the oxide semiconductor layer 230 outside the groove 291 may coincide or approximately coincide with the end of the conductive layer 240 outside the groove 291, or may be located more outward than the end of the conductive layer 240 outside the groove 291.

[0313] As described above, the insulating layer 285 is provided on the insulating layer 250. Furthermore, as shown in Figures 16C and 16D, the insulating layer 285 is provided so as to fill in the region of the groove 291 where the conductive layer 260 is not located.

[0314] 16A to 16D , the physical distance between the conductive layer 260 and the conductive layer 240a or 240b can be increased, and the parasitic capacitance generated between the conductive layer 260 and the conductive layer 240a or 240b can be reduced. Furthermore, the physical distance between the conductive layer 265 and the conductive layer 240a or 240b can be increased, and the parasitic capacitance generated between the conductive layer 265 and the conductive layer 240a or 240b can be reduced. Therefore, the frequency characteristics of a circuit using the transistor can be improved.

[0315] 16A to 16D illustrate a configuration in which the conductive layer 260 has a region facing the side surface of the conductive layer 240a with the oxide semiconductor layer 230 interposed therebetween and a region facing the side surface of the conductive layer 240b with the oxide semiconductor layer 230 interposed therebetween, but the present invention is not limited to this. For example, a first conductive layer facing the side surface of the conductive layer 240a with the oxide semiconductor layer 230 interposed therebetween and a second conductive layer facing the side surface of the conductive layer 240b with the oxide semiconductor layer 230 interposed therebetween may be provided.

[0316] [Transistor 200D] Fig. 17A is a plan view of a semiconductor device having two transistors. Fig. 17B is a cross-sectional view taken along dashed dotted lines B1-B2 and B5-B6 shown in Fig. 17A.

[0317] 17A to 17C includes an insulating layer 210 on a substrate (not shown), transistors 200Da and 200Db on the insulating layer 210, and an insulating layer 280 on the insulating layer 210. Hereinafter, the transistors 200Da and 200Db may be collectively referred to as the transistor 200D.

[0318] The transistor 200Da includes a conductive layer 220a, a conductive layer 240a on the insulating layer 280, an oxide semiconductor layer 230a, an insulating layer 250a on the oxide semiconductor layer 230a, and a conductive layer 260a on the insulating layer 250a. The transistor 200Db includes a conductive layer 220b, a conductive layer 240b on the insulating layer 280, an oxide semiconductor layer 230b, an insulating layer 250b on the oxide semiconductor layer 230b, and a conductive layer 260b on the insulating layer 250b.

[0319] The conductive layer 260a functions as a gate electrode of the transistor 200Da. The insulating layer 250a functions as a gate insulating layer of the transistor 200Da. The conductive layer 220a functions as one of a source electrode and a drain electrode of the transistor 200Da. The conductive layer 240a functions as the other of the source electrode and the drain electrode of the transistor 200Da.

[0320] Similarly, the conductive layer 260b functions as a gate electrode of the transistor 200Db. The insulating layer 250b functions as a gate insulating layer of the transistor 200Db. The conductive layer 220b functions as one of a source electrode and a drain electrode of the transistor 200Db. The conductive layer 240b functions as the other of the source electrode and the drain electrode of the transistor 200Db.

[0321] The semiconductor device shown in Figures 17A to 17C differs from the semiconductor device shown in Figures 16A to 16D in that the conductive layer 220, the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are each separated in and near the groove 291.

[0322] The oxide semiconductor layer 230a and the oxide semiconductor layer 230b are both provided so as to extend along part of the bottom and part of the sidewall of the groove 291. The oxide semiconductor layer 230a has a region that extends along the side surface of the groove 291, a region that extends along the upper surface of the conductive layer 220a (the bottom surface of the recess in the conductive layer 220a), and a region that extends along the upper surface of the conductive layer 240a. Similarly, the oxide semiconductor layer 230b has a region that extends along the side surface of the groove 291, a region that extends along the upper surface of the conductive layer 220b (the bottom surface of the recess in the conductive layer 220b), and a region that extends along the upper surface of the conductive layer 240b. The oxide semiconductor layer 230a has a portion that contacts the upper surface of the conductive layer 240a, a portion that contacts the side surface of the conductive layer 240a on the groove 291 side, and a portion that contacts the bottom and side surfaces of the recess in the conductive layer 220a within the groove 291. Similarly, the oxide semiconductor layer 230b has a portion in contact with the upper surface of the conductive layer 240b, a portion in contact with the side surface of the conductive layer 240b on the groove 291 side, and a portion in contact with the bottom surface and side surface of the recess of the conductive layer 220b within the groove 291.

[0323] The oxide semiconductor layer 230a includes a channel formation region 230ai, a low-resistance region 230ana, and a low-resistance region 230anb. The oxide semiconductor layer 230b includes a channel formation region 230bi, a low-resistance region 230bna, and a low-resistance region 230bnb.

[0324] The low-resistance region 230ana functions as one of the source region and drain region of the transistor 200Da. The low-resistance region 230anb functions as the other of the source region and drain region of the transistor 200Da. The low-resistance region 230bna functions as one of the source region and drain region of the transistor 200Db. The low-resistance region 230bnb functions as the other of the source region and drain region of the transistor 200Db.

[0325] In the transistor 200Da, a region of the oxide semiconductor layer 230a extending along the sidewall of the groove 291 functions as a channel formation region 230ai. A region of the oxide semiconductor layer 230a extending along the upper surface of the conductive layer 220a (the bottom surface of the recess of the conductive layer 220a) functions as a low-resistance region 230ana. A region of the oxide semiconductor layer 230a extending along the upper surface of the conductive layer 240a functions as a low-resistance region 230anb. The low-resistance region 230ana and the low-resistance region 230bna can be formed by a method similar to the method for forming the low-resistance region 230na in the transistor 200B. The low-resistance region 230anb and the low-resistance region 230bnb can be formed by a method similar to the method for forming the low-resistance region 230nb in the transistor 200B.

[0326] In the YZ plane including the oxide semiconductor layer 230a and the oxide semiconductor layer 230b, by providing two transistors (transistor 200Da and transistor 200Db) in the groove portion 291, miniaturization and high integration of the semiconductor device can be promoted.

[0327] Although FIGS. 17B and 17C illustrate a configuration in which the insulating layer 250 is separated into insulating layers 250a and 250b, the present invention is not limited to this.

[0328] 18A to 18C will be used to describe modifications of the two transistors described with reference to FIGS. 17A to 17C. FIG. 18A is a plan view of a semiconductor device having two transistors 200. FIG. 18B is a cross-sectional view taken along dashed dotted line B1-B2 in FIG. 18A. FIG. 18C is a cross-sectional view taken along dashed dotted line B5-B6 in FIG. 18A.

[0329] 18A to 18C differs from the semiconductor device shown in FIGS. 17A to 17C in that the insulating layer 250 covers the oxide semiconductor layer 230a and the oxide semiconductor layer 230b. Covering the oxide semiconductor layer 230a and the oxide semiconductor layer 230b with the insulating layer 250 can cover the side surface of the oxide semiconductor layer 230a on the groove 291 side and the side surface of the oxide semiconductor layer 230b on the groove 291 side. This can suppress diffusion of hydrogen into the oxide semiconductor layer 230a and the oxide semiconductor layer 230b. This allows a highly reliable transistor to be realized.

[0330] Note that a structure similar to that of the transistor 200 can also be applied to each of the transistor 200A, the transistor 200B, the transistor 200C, and the transistor 200D.

[0331] <Constituent Materials of Semiconductor Device> Materials that can be used in the semiconductor device of this embodiment will be described below. Note that each layer that constitutes the semiconductor device of this embodiment may have a single-layer structure or a multilayer structure.

[0332] [Oxide Semiconductor Layer] As described above, the oxide semiconductor layer 230 has a channel formation region. The oxide semiconductor layer 230 further has a source region and a drain region. The source region and the drain region are n-type regions (low-resistance regions) having a higher carrier concentration than the channel formation region. The oxide semiconductor layer 230 may have a stacked structure of two or more layers.

[0333] The carrier concentration in the channel formation region is 1×10 １８ cm −３ Below, 1 x 10 １７ cm −３ Less than 1 x 10 １６ cm −３Less than 1 x 10 １５ cm −３ Less than 1 x 10 １４ cm −３ Less than 1 x 10 １３ cm −３ Less than 1 x 10 １２ cm −３ Less than 1 x 10 １１ cm −３ Less than or 1 x 10 １０ cm −３ The lower limit of the carrier concentration in the channel formation region is not particularly limited, but is preferably less than 1×10 −９ cm −３ It can be said that:

[0334] As described in the above embodiment, in an OS transistor, oxygen vacancies (V Ｏ The presence of impurities may cause fluctuations in electrical characteristics and reduce reliability. Therefore, reducing the impurity concentration in the oxide semiconductor is effective for stabilizing the electrical characteristics of an OS transistor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in a nearby film. Examples of impurities include hydrogen, carbon, and nitrogen.

[0335] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the carbon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than or equal to 3×10, more preferably １９ atoms / cm ３ or less, more preferably 1 × 10 １９ atoms / cm ３ Less than or equal to 3×10, more preferably １８ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３The silicon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than or equal to 3×10, more preferably １９ atoms / cm ３ or less, more preferably 1 × 10 １９ atoms / cm ３ Less than or equal to 3×10, more preferably １８ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ The following applies.

[0336] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor is likely to be normally on. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ or less, more preferably 1 × 10 １９ atoms / cm ３ Less than or equal to 5×10, more preferably １８ atoms / cm ３ or less, more preferably 1 × 10 １８ atoms / cm ３ or less, more preferably 5 × 10 １７ atoms / cm ３ The following applies.

[0337] Furthermore, hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. Hydrogen entering the oxygen vacancy may generate electrons as carriers. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to be normally on. Therefore, it is preferable to reduce hydrogen as much as possible in the channel formation region of the oxide semiconductor. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Less than 5×10 １９ atoms / cm ３ less than 1×10 １９ atoms / cm ３ less than 5×10 １８ atoms / cm ３ less than 1×10 １８ atoms / cm ３ less than 1×10 １７ atoms / cm ３ Note that the lower limit of the hydrogen concentration in the channel formation region of the oxide semiconductor is not particularly limited, but is, for example, less than 1×10 １６ atoms / cm ３ It can be more than that.

[0338] Furthermore, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels are formed and carriers are generated in some cases. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to be normally on. Therefore, when the concentration of the alkali metal or the alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 １８ atoms / cm ３ Below 2 × 10, preferably １６ atoms / cm ３ Do the following:

[0339] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0340] [Insulating Layer] It is preferable to use an inorganic insulating film for each of the insulating layers (insulating layer 210, insulating layer 212, insulating layer 214, insulating layer 216, insulating layer 221, insulating layer 222, insulating layer 224, insulating layer 250, insulating layer 254, insulating layer 271a, insulating layer 271b, insulating layer 275, insulating layer 280, insulating layer 282, insulating layer 283, insulating layer 285, etc.) included in the semiconductor device. Examples of inorganic insulating films include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of the oxynitride insulating film include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film. Examples of the nitride oxide insulating film include a silicon nitride oxide film and an aluminum nitride oxide film. An insulating layer included in a semiconductor device may be an organic insulating film.

[0341] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulating layers. Using a high-dielectric-constant (high-k) material for the gate insulating layer allows for lower voltage operation of the transistor while maintaining the physical film thickness. It also allows for thinner equivalent oxide thickness (EOT) of the gate insulating layer. Meanwhile, using a material with a low dielectric constant for the insulating layer that functions as an interlayer film can reduce the parasitic capacitance that occurs between wiring. Therefore, it is preferable to select materials according to the function of the insulating layer. Note that materials with a low dielectric constant also have high dielectric strength.

[0342] Examples of materials with a high relative dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0343] Examples of materials with a low dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other inorganic insulating materials with a low dielectric constant include silicon oxide containing fluorine, silicon oxide containing carbon, and silicon oxide containing carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0344] Furthermore, a material capable of exhibiting ferroelectricity may be used for the insulating layer of a semiconductor device. Examples of materials capable of exhibiting ferroelectricity include metal oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide. Examples of materials capable of exhibiting ferroelectricity include a material obtained by adding element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to hafnium oxide. Here, the ratio of the number of hafnium atoms to the number of element J1 atoms can be appropriately set; for example, the ratio of the number of hafnium atoms to the number of element J1 atoms can be set to 1:1 or close to that. Examples of materials capable of exhibiting ferroelectricity include a material obtained by adding element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to zirconium oxide. The ratio of the number of zirconium atoms to the number of atoms of element J2 can be set appropriately, for example, the ratio of the number of zirconium atoms to the number of atoms of element J2 can be set to 1:1 or close to that. Furthermore, as a material that can have ferroelectricity, lead titanate (PbTiO Ｘ Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), or barium titanate, may also be used.

[0345] Furthermore, examples of materials that may exhibit ferroelectricity include metal nitrides containing element M1, element M2, and nitrogen. Here, element M1 is one or more elements selected from aluminum, gallium, indium, etc. Furthermore, element M2 is one or more elements selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. The ratio of the number of atoms of element M1 to the number of atoms of element M2 can be appropriately set. Furthermore, metal oxides containing element M1 and nitrogen may exhibit ferroelectricity even without containing element M2. Furthermore, examples of materials that may exhibit ferroelectricity include materials in which element M3 is added to the above metal nitrides. Furthermore, element M3 is one or more elements selected from magnesium, calcium, strontium, zinc, cadmium, etc. Here, the ratio of the number of atoms of the element M1, the number of atoms of the element M2, and the number of atoms of the element M3 can be set appropriately.

[0346] Furthermore, materials that can have ferroelectricity include SrTaO ２ N and BaTaO ２ Perovskite-type oxynitrides such as N, GaFeO with κ-alumina structure ３ etc.

[0347] Although metal oxides and metal nitrides have been exemplified in the above description, the present invention is not limited to these. For example, metal oxynitrides in which nitrogen is added to the aforementioned metal oxides, or metal oxynitrides in which oxygen is added to the aforementioned metal nitrides, may also be used.

[0348] Furthermore, as a material capable of exhibiting ferroelectricity, for example, a mixture or compound made of a plurality of materials selected from the materials listed above can be used. Alternatively, the insulating layer 454 described in Embodiment 2 can have a layered structure made of a plurality of materials selected from the materials listed above. Incidentally, the crystal structure (characteristics) of the materials listed above may change depending not only on the film formation conditions but also on various processes, etc., and therefore, in this specification and the like, a material that exhibits ferroelectricity is referred to not only as a ferroelectric but also as a material capable of exhibiting ferroelectricity.

[0349] In this specification, a layer of a material that can have ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Also, in this specification, a device having such a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device.

[0350] Ferroelectricity is believed to be exhibited by the displacement of oxygen or nitrogen in crystals contained in the ferroelectric layer due to an external electric field. Furthermore, it is believed that the exhibiting of ferroelectricity depends on the crystal structure of the crystals contained in the ferroelectric layer. Therefore, for an insulating layer to exhibit ferroelectricity, the insulating layer must contain crystals. In particular, an insulating layer containing crystals having an orthorhombic crystal structure is preferred because it exhibits ferroelectricity. The crystal structure of the crystals contained in the insulating layer may be one or more selected from the group consisting of tetragonal, orthorhombic, monoclinic, and hexagonal. The insulating layer may also have an amorphous structure. In this case, the insulating layer may have a composite structure having an amorphous structure and a crystalline structure.

[0351] A metal oxide containing either or both of hafnium and zirconium is also an insulating material capable of capturing or fixing hydrogen. Therefore, by using a metal oxide containing either or both of hafnium and zirconium for at least a part of a gate insulating layer, hydrogen contained in the oxide semiconductor layer can be captured or fixed, thereby reducing the hydrogen concentration in the oxide semiconductor layer. Furthermore, a transistor having the gate insulating layer can function as a ferroelectric field effect transistor (FeFET).

[0352] Furthermore, adding a Group 3 element in the periodic table to an oxide containing one or both of hafnium and zirconium increases the oxygen vacancy concentration in the oxide, making it easier to form crystals with an orthorhombic crystal structure. This is preferable because it increases the proportion of crystals with an orthorhombic crystal structure and increases the remanent polarization. On the other hand, if the amount of the Group 3 element added is too large, the crystallinity of the oxide may decrease, making it difficult to exhibit ferroelectricity. Therefore, the content of the Group 3 element in the oxide containing one or both of hafnium and zirconium is preferably 0.1 atomic% to 10 atomic%, more preferably 0.1 atomic% to 5 atomic%, and even more preferably 0.1 atomic% to 3 atomic%. Here, the content of the Group 3 element refers to the ratio of the number of atoms of the Group 3 element to the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

[0353] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulating layer that has a function of suppressing the permeation of impurities and oxygen. The insulating layer that has a function of suppressing the permeation of impurities and oxygen can be, for example, a single-layer or stacked insulating layer containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, the insulating layer that has a function of suppressing the permeation of impurities and oxygen can be made of a metal oxide such as aluminum oxide, magnesium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide; a nitride such as aluminum nitride or silicon nitride; or a nitride oxide such as silicon nitride oxide.

[0354] Specifically, examples of materials for the insulating layer that have the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen, include metal oxides such as aluminum oxide, magnesium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and oxides containing aluminum and hafnium (hafnium aluminate). Examples of nitrides include aluminum nitride, aluminum titanium nitride, and silicon nitride. Examples of nitride oxides include silicon nitride oxide. Examples of materials for the insulating layer that have the function of suppressing the permeation of oxygen include gallium oxide.

[0355] An insulating layer, such as a gate insulating layer, that is in contact with an oxide semiconductor layer or that is provided near the oxide semiconductor layer is preferably an insulating layer having a region containing excess oxygen. For example, when an insulating layer having a region containing excess oxygen is in contact with an oxide semiconductor layer or is located near the oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be reduced. Examples of insulating materials that easily form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide having vacancies. Examples of insulating layers that easily form a region containing excess oxygen include a silicon oxide film, a silicon oxynitride film, and a silicon oxide film having vacancies.

[0356] An insulating layer provided in contact with or near an oxide semiconductor layer is preferably a barrier insulating layer against hydrogen. When the insulating layer has a barrier property against hydrogen, diffusion of hydrogen into the oxide semiconductor layer can be suppressed. The barrier insulating layer against hydrogen can also be said to have a function of suppressing diffusion of hydrogen.

[0357] Examples of insulating materials having the function of capturing or fixing hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, oxides containing aluminum and hafnium (hafnium aluminate), hafnium silicate, etc. These metal oxides may further contain zirconium, and examples thereof include oxides containing hafnium and zirconium.

[0358] An insulating layer having the function of capturing or fixing hydrogen preferably has an amorphous structure. In a metal oxide having an amorphous structure, some oxygen atoms have dangling bonds, which enhances the ability to capture or fix hydrogen. Therefore, when the insulating layer has an amorphous structure, the function of capturing or fixing hydrogen can be enhanced.

[0359] By making the insulating layer an amorphous structure, it is possible to suppress the formation of crystal grain boundaries. By suppressing the formation of crystal grain boundaries, it is possible to improve the flatness of the insulating layer. This makes it possible to uniformize the film thickness distribution of the insulating layer and reduce areas with extremely thin film thickness, thereby improving the breakdown voltage of the insulating layer. It is also possible to uniformize the film thickness distribution of a film provided on the insulating layer. Furthermore, by suppressing the formation of crystal grain boundaries in the insulating layer, it is possible to reduce leakage current caused by defect levels at the crystal grain boundaries. Therefore, the insulating layer can function as an insulating film with low leakage current.

[0360] The insulating layer may have a crystalline region and / or a grain boundary in a part thereof.

[0361] The ability to capture or fix a corresponding substance can also be said to have the property of making it difficult for the corresponding substance to diffuse. Therefore, the ability to capture or fix a corresponding substance can be rephrased as barrier properties.

[0362] Examples of materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium (hafnium aluminate), oxides containing hafnium and zirconium (hafnium zirconium oxide), silicon nitride, and silicon nitride oxide.

[0363] The inorganic insulating layers cited as insulating layers having the function of capturing or fixing hydrogen and insulating layers having the function of suppressing hydrogen diffusion also have barrier properties against oxygen. Examples of materials for the oxygen barrier insulating layer include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and hafnium silicate.

[0364] [Conductive Layer] For the conductive layers (conductive layer 205, conductive layer 220, conductive layer 240, conductive layer 240a, conductive layer 240b, conductive layer 242a, conductive layer 242b, conductive layer 243a, conductive layer 243b, conductive layer 246, conductive layer 260, conductive layer 265, etc.) included in the semiconductor device, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing any of the above metal elements as a component, or an alloy combining any of the above metal elements, etc. As the alloy containing any of the above metal elements as a component, a nitride of the alloy or an oxide of the alloy may be used. For example, it is preferable to use tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. Furthermore, semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0365] Nitrogen-containing conductive materials, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; oxygen-containing conductive materials, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metal elements, such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are resistant to oxidation, have a function of suppressing oxygen diffusion, or maintain conductivity even after absorbing oxygen. Examples of oxygen-containing conductive materials include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, ITO, indium tin oxide containing titanium oxide, ITSO, In—Zn oxide, and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive film formed using a conductive material containing oxygen may be referred to as an oxide conductive film.

[0366] Conductive materials containing tungsten, copper, or aluminum as a main component are preferred because they have high conductivity.

[0367] A plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0368] When a metal oxide is used for the channel formation region of a transistor, the conductive layer that functions as a gate electrode preferably has a stacked structure that combines a material containing the metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0369] [Substrate] Substrates on which transistors are formed can include, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates having a metal nitride or a metal oxide. Examples of substrates include substrates having a conductor or semiconductor provided on an insulating substrate, substrates having a conductor or insulator provided on a semiconductor substrate, and substrates having a semiconductor or insulator provided on a conductive substrate. Alternatively, a substrate provided with elements may be used, such as a capacitor element, a resistor element, a switch element, a light-emitting element, or a memory element.

[0370] The above is the description of the materials that can be used for the semiconductor device of this embodiment mode.

[0371] <Example of Manufacturing Method of Semiconductor Device> An example of a manufacturing method of a semiconductor device of one embodiment of the present invention will be described below with reference to FIGS. 19A to 25D . In FIGS. 19A to 25D , A in each diagram is a plan view. B in each diagram is a cross-sectional view taken along dashed-dotted line A1-A2 in A in each diagram. C in each diagram is a cross-sectional view taken along dashed-dotted line A3-A4 in A in each diagram. D in each diagram is a cross-sectional view taken along dashed-dotted line A5-A6 in A in each diagram.

[0372] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum deposition method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like.

[0373] Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source, DC sputtering, which uses a direct current power supply, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used to form insulating films, while DC sputtering is mainly used to form metal conductive films. Pulsed DC sputtering is mainly used to form films of compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0374] CVD methods can be further classified into plasma-enhanced CVD (PECVD) methods that utilize plasma, thermal CVD (TCVD) methods that utilize heat, and photo-CVD (photo-CVD) methods that utilize light. CVD methods can also be further classified into metal CVD (MCVD) methods and metal organic CVD (MOCVD) methods depending on the source gas used.

[0375] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can minimize plasma damage to the workpiece because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, the thermal CVD method does not cause plasma damage during film formation, so films with fewer defects can be obtained.

[0376] As the ALD method, a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, a plasma ALD (PEALD: Plasma Enhanced ALD) method in which a plasma-excited reactant is used, or the like can be used.

[0377] Note that some precursors used in the ALD method contain elements such as carbon or chlorine. Therefore, films formed by the ALD method may contain more elements such as carbon or chlorine than films formed by other film formation methods. The amounts of these elements can be quantified using XPS or SIMS. Note that the metal oxide film formation method of one embodiment of the present invention uses the ALD method, but employs one or both of a high substrate temperature during film formation and an impurity removal treatment. Therefore, the amount of carbon and chlorine contained in the film may be smaller than when the ALD method is used without these.

[0378] Unlike film formation methods in which particles emitted from a target or the like are deposited, the ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece. Therefore, it is a film formation method that is less affected by the shape of the workpiece and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio.

[0379] The CVD and ALD methods differ from sputtering methods in which particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio. However, because the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as the CVD method, which have a faster film formation rate.

[0380] Furthermore, the CVD method allows deposition of a film of any composition by adjusting the flow rate ratio of the source gases. For example, the CVD method allows deposition of a film with a continuously changing composition by changing the flow rate ratio of the source gases during deposition. When deposition is performed while changing the flow rate ratio of the source gases, the time required for deposition can be shortened compared to deposition using multiple deposition chambers because no time is required for transport or pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0381] In addition, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0382] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by a wet film formation method such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.

[0383] Furthermore, when processing a thin film that constitutes a semiconductor device, a photolithography method or the like can be used. Alternatively, the thin film may be processed by a nanoimprint method, a sandblasting method, a lift-off method, or the like. Furthermore, an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0384] There are two typical photolithography methods: one is to form a resist mask on the thin film to be processed, and then remove part of the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then expose and develop it to process the thin film into the desired shape.

[0385] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, ArF laser light, etc. Exposure can also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure. An electron beam can also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0386] For etching the thin film, dry etching, wet etching, sandblasting, or the like can be used.

[0387] An example of a method for manufacturing the semiconductor device shown in FIG. 1A and FIGS. 2A to 2C will be described below.

[0388] 19A to 19D , a substrate (not shown) is prepared, and an insulating layer 212, an insulating layer 214, an insulating layer 216, a conductive layer 205, an insulating layer 221, an insulating layer 222, an insulating film 224f, an oxide film 227f, and an oxide semiconductor film 230f are formed in this order on the substrate. The insulating film 224f is a film that will become the insulating layer 224 in a later step. The oxide film 227f is a film that will become the oxide layer 227 in a later step. The oxide semiconductor film 230f is a film that will become the oxide semiconductor layer 230 in a later step.

[0389] The oxide film 227f can be formed by a sputtering method, a CVD method, a vacuum evaporation method, a PLD method, an ALD method, or the like.

[0390] The oxide film 227f is preferably formed by a sputtering method. Forming the oxide film 227f by a sputtering method can improve the crystallinity of the oxide semiconductor film 230f. Furthermore, forming the oxide film 227f by a sputtering method in an atmosphere containing oxygen can supply oxygen to the insulating film 224f.

[0391] The oxide semiconductor film 230f is preferably formed by ALD. A precursor and an oxidizing agent can be used to form the oxide semiconductor film 230f. The precursor preferably contains indium. In this case, an indium oxide film is formed as the oxide semiconductor film 230f. That is, an oxide film containing a single element other than oxygen is formed. Note that when the precursor contains indium, thermal ALD can be used as the ALD method.

[0392] In the method for forming the oxide semiconductor film 230f, it is preferable to use a precursor having a low impurity concentration, i.e., a high purity. For example, by using a precursor having a purity of 3N (99.9%) or more, preferably 4N (99.99%) or more, more preferably 5N (99.999%) or more, further preferably 6N (99.9999%) or more, the impurities in the oxide semiconductor film 230f can be reduced.

[0393] The gallium content of the precursor containing indium is preferably 1000 ppm or less, more preferably 500 ppm or less, still more preferably 100 ppm or less, still more preferably 50 ppm or less, still more preferably 10 ppm or less, and still more preferably 1 ppm or less. By using a precursor with a low gallium content, an oxide semiconductor film 230f with a low gallium concentration can be formed.

[0394] The aluminum content of the precursor containing indium is preferably 1000 ppm or less, more preferably 500 ppm or less, still more preferably 100 ppm or less, still more preferably 50 ppm or less, still more preferably 10 ppm or less, and still more preferably 1 ppm or less. By using a precursor with a low aluminum content, the aluminum concentration in the oxide semiconductor film 230f can be reduced, and the crystallinity of the oxide semiconductor film 230f can be improved.

[0395] Examples of precursors that can be used that contain indium include trimethylindium, triethylindium, ethyldimethylindium, tris(1-methylethyl)indium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) acetylacetonate, (3-(dimethylamino)propyl)dimethylindium, (diethylphosphino)dimethylindium, chlorodimethylindium, bromodimethylindium, and dimethyl(2-propanolato)indium.

[0396] Alternatively, an inorganic precursor containing no hydrocarbon may be used as the indium-containing precursor. Examples of the inorganic precursor containing indium include halogen-based indium compounds such as trifluoroindium (indium(III) fluoride), indium trichloride (indium(III) chloride), indium tribromide (indium(III) bromide), and indium triiodide (indium(III) iodide). Indium trichloride has a decomposition temperature of approximately 500°C to 700°C. Therefore, by using indium trichloride, film formation can be performed by the ALD method while heating the substrate at approximately 400°C to 600°C, for example, at 500°C.

[0397] The oxidant preferably contains ozone. By using ozone, oxygen, or the like that does not contain hydrogen as the oxidant, the amount of hydrogen entering the oxide semiconductor film 230f can be reduced.

[0398] Here, the temperature to which the substrate is heated when the precursor is introduced into the reaction chamber is defined as a first temperature, and the temperature to which the substrate is heated when the oxidizing agent is introduced into the reaction chamber is defined as a second temperature.

[0399] The first temperature is preferably set to a temperature corresponding to the decomposition temperature of the precursor. Here, in the case of a thermal ALD method using triethylindium as a precursor containing indium, the first temperature is, for example, 100° C. or higher and 350° C. or lower, preferably 150° C. or higher and 300° C. or lower. By providing the oxide film 227f, the oxide semiconductor film 230f having crystallinity can be formed even if the first temperature is lower than the above-mentioned temperature. When the oxide film 227f is provided, the first temperature can be set to a temperature from room temperature (25° C.) to 300° C. or lower, preferably from room temperature to 200° C. or lower, more preferably from room temperature to 150° C. or lower.

[0400] The second temperature is preferably higher than the first temperature. For example, when the oxidizing agent contains ozone, the second temperature is preferably higher than 200° C. and lower than 450° C., more preferably higher than or equal to 250° C. and lower than or equal to 400° C., and further preferably higher than or equal to 300° C. and lower than or equal to 350° C. With this configuration, the hydrogen concentration in the oxide semiconductor layer can be reduced. Furthermore, by setting the first temperature lower than the second temperature, particles generated by decomposition of the precursor can be suppressed. Note that the second temperature may be the same as the first temperature. With this configuration, the substrate heating temperature can be kept constant during the formation of the oxide semiconductor film 230f, thereby improving productivity.

[0401] It is preferable that the reaction chamber into which the precursor is introduced and the reaction chamber into which the oxidizing agent is introduced are the same. This configuration allows for film formation without the need to load and unload the substrate, thereby improving productivity. It is also possible to use different reaction chambers for the introduction of the precursor and the introduction of the oxidizing agent. By providing a first reaction chamber set to a first temperature and a second reaction chamber set to a second temperature, the first temperature and the second temperature can be maintained, respectively. This facilitates temperature control, improving work efficiency and safety.

[0402] When the indium oxide film included in the oxide semiconductor film 230f is formed by the ALD method, the edges of the indium oxide are presumably passivated because they are terminated with oxygen. The passivation of the edges is presumably associated with fewer defects. Therefore, it is presumed that a highly reliable transistor can be realized.

[0403] Note that the oxide semiconductor film 230f can be formed by a sputtering method in an atmosphere containing oxygen. Furthermore, by using a sputtering method that does not require the use of hydrogen-containing molecules as a deposition gas, the hydrogen concentration in the oxide semiconductor film 230f can be reduced. For example, oxygen or a mixed gas of oxygen and a noble gas may be used as a sputtering gas.

[0404] After the oxide semiconductor film 230f is formed, a process for supplying oxygen to the oxide semiconductor film 230f may be performed. This allows oxygen to be supplied to the oxide semiconductor film 230f by heat or the like applied after the process. Examples of the process for supplying oxygen include heat treatment in an oxygen-containing atmosphere and plasma treatment (including microwave plasma treatment) in an oxygen-containing atmosphere.

[0405] Next, heat treatment is preferably performed. By performing the heat treatment, impurities such as hydrogen or water contained in the oxide semiconductor film 230f can be reduced. The temperature of the heat treatment is preferably from 100° C. to 650° C., more preferably from 250° C. to 600° C., further preferably from 300° C. to 500° C. or from 350° C. to 550° C., and typically 400° C.

[0406] The heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas content is preferably about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, after the heat treatment in the nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen.

[0407] The gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, moisture and the like can be prevented from being introduced into the oxide semiconductor film 230f as much as possible.

[0408] The heat treatment can reduce impurities such as carbon, hydrogen, or water in the oxide semiconductor film 230f. Reducing the impurities in the film in this manner improves the crystallinity of the oxide semiconductor film 230f, resulting in a denser and more compact structure. This increases the crystalline regions in the oxide semiconductor film 230f, reducing in-plane variations in the crystalline regions in the oxide semiconductor film 230f. This reduces in-plane variations in the electrical characteristics of the transistor.

[0409] In the case where the insulating film 224f contains oxygen, oxygen is preferably supplied from the insulating film 224f to the oxide semiconductor film 230f through the oxide film 227f by the heat treatment. Ｏ H can be reduced.

[0410] Note that microwave plasma treatment may be performed after the oxide semiconductor film 230f is formed. By performing the microwave plasma treatment, the concentration of impurities such as hydrogen or water contained in the oxide semiconductor film 230f can be reduced. Furthermore, a crystalline region of the oxide semiconductor film 230f may grow.

[0411] In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz to 300 GHz. Microwave plasma treatment refers to treatment using a device with a power source that generates high-density plasma using microwaves. Microwave plasma treatment can also be called microwave-excited high-density plasma treatment.

[0412] By performing microwave plasma treatment in an atmosphere containing oxygen, the impurity concentration in the oxide semiconductor film 230f can be reduced. Examples of impurities include hydrogen and carbon. While the above example illustrates a configuration in which microwave plasma treatment is performed on the oxide semiconductor film 230f in an atmosphere containing oxygen, the present invention is not limited to this. For example, microwave plasma treatment may be performed on an insulating film, more specifically, a silicon oxide film, provided near the oxide semiconductor film 230f in an atmosphere containing oxygen. Furthermore, the heat generated by the microwave plasma treatment may increase the crystallinity of the oxide semiconductor film 230f.

[0413] The microwave plasma treatment is preferably carried out under reduced pressure, and the pressure is preferably from 10 to 1000 Pa, more preferably from 50 to 700 Pa, and even more preferably from 100 to 400 Pa. The treatment temperature is preferably from room temperature (25°C) to 750°C, more preferably from 300 to 500°C, and can be from 400 to 450°C.

[0414] When microwave plasma treatment is performed, the substrate may be heated. The substrate is preferably heated to a temperature above room temperature (e.g., 25°C), above 100°C, above 200°C, above 300°C, or above 400°C, and below 500°C, or below 450°C. For example, the substrate is preferably heated to a temperature above room temperature and below 500°C, more preferably above 100°C and below 450°C, more preferably above 200°C and below 450°C, even more preferably above 300°C and below 450°C, and even more preferably above 400°C and below 450°C.

[0415] The microwave plasma treatment can be performed using, for example, oxygen gas and argon gas. In the microwave plasma treatment using oxygen gas and argon gas, the main oxygen radical is triplet oxygen (O( ３ P ｊ )), singlet oxygen (O( １ D ２ )), and oxygen ions (O ２ ＋) can take three states. Note that oxygen ions act effectively in reducing the hydrogen concentration in the oxide film by microwave plasma processing. The amount of oxygen radicals in each state varies depending on the oxygen flow rate ratio or pressure in microwave plasma processing. For example, under conditions where the oxygen flow rate ratio is low and the pressure is low, the amount of oxygen ions tends to increase. On the other hand, if the oxygen flow rate ratio or pressure is excessively low, there is a concern that the control of the oxygen flow rate becomes unstable, making it difficult to stabilize the discharge, and that the oxide film may be etched. Therefore, for example, when the oxygen flow rate ratio (O ２ / (O ２ +Ar)) is preferably greater than 0% and not greater than 10%, more preferably 0.5% to 5%, more preferably 0.5% to 3%, and typically more preferably 1%.

[0416] The shorter the processing time of the microwave plasma treatment, the higher the productivity. Therefore, for example, the processing time of the microwave plasma treatment is preferably 1 minute or more and 60 minutes or less, more preferably 1 minute or more and 30 minutes or less, and even more preferably 1 minute or more and 10 minutes or less.

[0417] By performing microwave plasma treatment in an atmosphere containing oxygen, oxygen gas is converted into plasma using microwaves or high frequency waves such as RF, and oxygen radicals generated by converting the oxygen gas into plasma can act on the oxide semiconductor layer. Due to the action of plasma, microwaves, oxygen radicals, or the like, defects in which hydrogen has entered oxygen vacancies in the oxide semiconductor layer (hereinafter referred to as V Ｏ By splitting V (sometimes referred to as H) into oxygen vacancies and hydrogen, the hydrogen impurities can be removed from the oxide semiconductor layer. Ｏ H can be reduced. At this time, carbon bonded to oxygen, hydrogen, or the like can also be removed in some cases. In this way, impurities such as carbon or hydrogen can be reduced by performing microwave plasma treatment. Furthermore, by supplying the oxygen radicals to oxygen vacancies formed in the oxide semiconductor layer, the oxygen vacancies in the oxide semiconductor layer can be further reduced.

[0418] Furthermore, a reaction occurs between part of oxygen present in the oxide semiconductor before the microwave plasma treatment and hydrogen in the oxide semiconductor. In other words, the reaction proceeds as follows: 2H + O → H ２ O↑” reaction occurs, converting the hydrogen to H ２ O (also called dehydration or dehydrogenation). ２ Since O is one of the factors that hinder improvement of crystallinity, it is preferable to remove O from the oxide semiconductor. ２ The hydrogen concentration in the oxide semiconductor can be reduced by removing the hydrogen as O, which can also promote improvement in crystallinity. Note that the hydrogen concentration in the oxide semiconductor can be further reduced by increasing the temperature during the microwave plasma treatment.

[0419] After the microwave plasma treatment, a heat treatment may be performed without exposing the substrate to the outside air. The temperature of the heat treatment is, for example, preferably 100° C. or higher and 750° C. or lower, more preferably 300° C. or higher and 500° C. or lower, and even more preferably 400° C. or higher and 450° C. or lower.

[0420] It should be noted that the crystallinity can be improved by plasma treatment containing oxygen gas instead of microwave plasma treatment.

[0421] Oxygen supplied to the oxide semiconductor layer can be in various forms such as oxygen atoms, oxygen molecules, oxygen ions (charged oxygen atoms or oxygen molecules), and oxygen radicals (oxygen atoms, oxygen molecules, or oxygen ions having an unpaired electron). Note that the oxygen injected into the oxide semiconductor layer is preferably in one or more of the above forms, and is particularly preferably in the form of oxygen radicals.

[0422] In this manner, impurities in the oxide semiconductor film 230f can be reduced, and the crystallinity of the oxide semiconductor film 230f can be improved.

[0423] 19A to 19D, a layer 233 is formed on the oxide semiconductor film 230f. The layer 233 will become layers 233a and 233b in a later step. The layer 233 can be formed, for example, by forming a film that will become the layer 233 on the oxide semiconductor film 230f and processing the film. The film that will become the layer 233 can be processed by dry etching or wet etching. In particular, dry etching is preferable because it is suitable for fine processing.

[0424] For example, a metal oxide layer, specifically a metal oxide layer containing indium, can be formed as the layer 233. Here, it is preferable to process the film to be the layer 233 under conditions where the etching selectivity with respect to the oxide semiconductor film 230f is high, because this can prevent at least a part of the oxide semiconductor film 230f from being removed.

[0425] 20A to 20D , the impurity element 189 is added to the oxide semiconductor film 230f. Specifically, the impurity element 189 is added to the oxide semiconductor film 230f using the layer 233 as a mask. The impurity element 189 can be a metal element having a larger periodic number in the periodic table, such as antimony.

[0426] As a result, a low-resistance region 230n is formed in a region of the oxide semiconductor film 230f that does not overlap with the layer 233. The low-resistance region 230n includes a region that will later become the low-resistance region 230na and a region that will later become the low-resistance region 230nb. The layer 233 is also referred to as a mask layer. Note that the impurity element 189 is added not only to the oxide semiconductor film 230f but also to the layer 233. This may result in a low resistance of the layer 233. For example, when the layer 233 is a metal oxide layer, the resistance of the layer 233 may be low.

[0427] The impurity element 189 can be preferably added by plasma ion doping or ion implantation, which can control the concentration profile in the depth direction with high precision by adjusting the ion acceleration voltage, dose, etc.

[0428] By using an ion implantation method in which a source gas is ionized and the ions are mass-separated before being added, it is possible to increase the purity of the added impurity element 189. Furthermore, by using a plasma ion doping method in which a source gas is ionized and the ions are added without mass-separation, it is possible to increase productivity.

[0429] Note that the method for adding the impurity element 189 is not limited, and for example, plasma treatment, treatment using thermal diffusion by heating, or the like may be used. In the case of the plasma treatment, plasma is generated in a gas atmosphere containing the impurity element 189, and the impurity element 189 can be added by performing the plasma treatment. As an apparatus for generating the plasma, a dry etching apparatus, an ashing apparatus, a plasma CVD apparatus, a high-density plasma CVD apparatus, or the like may be used.

[0430] The impurity element 189 is preferably added while the substrate is heated. This allows damage to the oxide semiconductor film 230f caused when the impurity element 189 is added to be repaired. For example, even when at least a part of the oxide semiconductor film 230f is made amorphous by the addition of the impurity element 189, the amorphous portion can be recrystallized. Furthermore, by adding the impurity element 189 while heating the substrate, the added impurity element 189 can be activated. As described above, by adding the impurity element 189 while heating the substrate, the addition of the impurity element 189 to the oxide semiconductor film 230f, repair of damage caused by the addition, and activation of the added impurity element 189 can be performed simultaneously.

[0431] The substrate temperature in the step of adding the impurity element 189 is preferably 150°C or higher and lower than the strain point of the substrate, more preferably 200°C or higher and 500°C or lower, even more preferably 200°C or higher and 450°C or lower, even more preferably 250°C or higher and 400°C or lower, even more preferably 250°C or higher and 350°C or lower, or even more preferably 300°C or higher and 400°C or lower, even more preferably 300°C or higher and 350°C or lower.

[0432] Heat treatment may be performed after the impurity element 189 is added. By performing the heat treatment, damage to the oxide semiconductor film 230f caused in the step of adding the impurity element 189 can be repaired. In addition, the added impurity element 189 can be activated.

[0433] In the method for manufacturing a semiconductor device of one embodiment of the present invention, the layer 233 does not necessarily have to be formed. In this case, a resist mask is formed over the oxide semiconductor film 230f, and then the impurity element 189 is added to a region of the oxide semiconductor film 230f that does not overlap with the resist mask, so that the low-resistance region 230n can be formed. Then, the resist mask is removed.

[0434] 21A to 21D , a conductive film 242f is formed over the layer 233 and the oxide semiconductor film 230f, and an insulating film 271f is formed over the conductive film 242f. The conductive film 242f will become the conductive layer 242a and the conductive layer 242b in a later step. The insulating film 271f will become the insulating layer 271a and the insulating layer 271b in a later step.

[0435] The conductive film 242f can be formed to cover the layer 233. The conductive film 242f can be formed to have a region in contact with the top surface of the layer 233, a region in contact with the side surface of the layer 233, and a region in contact with the top surface of the low-resistance region 230n of the oxide semiconductor film 230f.

[0436] By forming the conductive film 242f after the formation of the layer 233, the conductive film 242f can be prevented from contacting a region of the oxide semiconductor film 230f that will later become a channel formation region. As described above, by using a metal oxide layer as the layer 233, it is possible to prevent a different layer from being formed on the top surface of the region that will later become the channel formation region. This makes it possible to provide a method for manufacturing a semiconductor device with high yield.

[0437] Note that the layer 233 does not have to be a metal oxide layer as long as it functions as a mask when the impurity element 189 is added to the oxide semiconductor film 230f. The layer 233 can be, for example, an insulating layer or a conductive layer. Alternatively, the layer 233 can be, for example, a layer containing a semiconductor material other than a metal oxide.

[0438] When the layer 233 is an insulating layer, the layer 233 can be formed using, for example, a material that can be used for the insulating film 224f. When the layer 233 is a conductive layer, the layer 233 can be formed using, for example, a material that can be used for the conductive film 242f.

[0439] The conductive film 242f and the insulating film 271f can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. Note that heat treatment may be performed before the formation of the insulating film 271f. The heat treatment may be performed under reduced pressure, and the insulating film 271f may be formed successively without exposure to the air. By performing such treatment, moisture and hydrogen adsorbed on the surface of the conductive film 242f can be removed, and the moisture and hydrogen concentrations in the conductive film 242f can be further reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower.

[0440] 22A to 22D , the insulating film 224f, the oxide film 227f, the oxide semiconductor film 230f, the conductive film 242f, and the insulating film 271f are processed into an island shape. This forms the insulating layer 224, the oxide layer 227, the oxide semiconductor layer 230, the conductive layer 242, and the insulating layer 271. By processing the oxide semiconductor film 230f, the low-resistance region 230n is divided, and low-resistance regions 230na and 230nb are formed.

[0441] For the above processing, a dry etching method or a wet etching method can be used. Processing by a dry etching method is suitable for microfabrication. The insulating film 224f, the oxide film 227f, the oxide semiconductor film 230f, the conductive film 242f, and the insulating film 271f may be processed under different conditions.

[0442] Here, the insulating film 224f, the oxide film 227f, the oxide semiconductor film 230f, the conductive film 242f, and the insulating film 271f are preferably collectively processed into an island shape. In this case, the upper end of the insulating layer 224 preferably coincides with or substantially coincides with the lower end of the oxide layer 227. Furthermore, the upper end of the oxide layer 227 preferably coincides with or substantially coincides with the lower end of the oxide semiconductor layer 230. Furthermore, the upper end of the oxide semiconductor layer 230 preferably coincides with or substantially coincides with the lower end of the conductive layer 242. Furthermore, the upper end of the conductive layer 242 preferably coincides with or substantially coincides with the lower end of the insulating layer 271. Such a structure can reduce the number of steps required for manufacturing a semiconductor device according to one embodiment of the present invention. Therefore, a method for manufacturing a semiconductor device with high productivity can be provided.

[0443] The insulating layer 224, the oxide layer 227, the oxide semiconductor layer 230, the layer 233, the conductive layer 242, and the insulating layer 271 are formed so as to at least partially overlap with the conductive layer 205. For example, the insulating layer 222 is exposed in a region that does not overlap with the insulating layer 224. However, this is not limiting, and for example, the insulating layer 224 may remain on the insulating layer 222 in a region that does not overlap with the oxide layer 227, as shown in FIGS.

[0444] 22B to 22D , the side surfaces of the insulating layer 224, the oxide layer 227, the oxide semiconductor layer 230, the conductive layer 242, and the insulating layer 271 can be tapered. The taper angle of the side surfaces of the insulating layer 224, the oxide layer 227, the oxide semiconductor layer 230, the conductive layer 242, and the insulating layer 271 may be, for example, greater than or equal to 60° and less than 90°. By tapering the side surfaces in this manner, coverage by the insulating layer 275 and the like can be improved in later steps, and defects such as voids can be reduced.

[0445] Furthermore, the side surfaces of the insulating layer 224, the oxide layer 227, the oxide semiconductor layer 230, the conductive layer 242, and the insulating layer 271 may be perpendicular or approximately perpendicular to the top surface of the insulating layer 222. With such a structure, a reduction in area and high density can be achieved when forming a plurality of transistors.

[0446] When the insulating film 224f, the oxide film 227f, the oxide semiconductor film 230f, the conductive film 242f, and the insulating film 271f are processed by etching, the insulating layer 271 can function as an etching stopper that protects the conductive layer 242. For example, if a metal hard mask is formed on the insulating layer 271 in the etching process, it may be difficult to obtain an etching selectivity with respect to the conductive layer 242 when the hard mask is removed. However, by forming the insulating layer 271 on the conductive layer 242, the insulating layer 271 can function as an etching stopper that protects the conductive layer 242 in the etching process for removing the hard mask. This prevents a curved surface from being formed between the side surface and the top surface of the conductive layer 242. Therefore, the conductive layer 242 has a square-shaped upper end. This increases the cross-sectional area of ​​the conductive layer 242 compared to when the upper end has a curved surface. Furthermore, using a nitride insulator, which does not easily oxidize metals, for the insulating layer 271 can prevent excessive oxidation of the conductive layer 242. This reduces the electrical resistance of the conductive layer 242. Therefore, a transistor with a large on-state current can be manufactured.

[0447] Furthermore, by processing the insulating layer 224 into an island shape, the insulating layer 275 can be provided in contact with the side surface of the insulating layer 224 and the top surface of the insulating layer 222 in a step described later. That is, the insulating layer 224 can be separated from the insulating layer 280 by the insulating layer 275. With such a structure, impurities such as excessive oxygen and hydrogen can be prevented from being mixed into the oxide semiconductor layer 230 from the insulating layer 280 through the insulating layer 224.

[0448] 23A to 23D , an insulating layer 275 is formed to cover the insulating layer 224, the oxide layer 227, the oxide semiconductor layer 230, the conductive layer 242, and the insulating layer 271, and an insulating layer 280 is formed over the insulating layer 275. The insulating layers 275 and 280 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. Here, after the insulating layer 275 is formed, an insulating film that will become the insulating layer 280 is preferably formed and then subjected to CMP treatment to form the insulating layer 280 having a flat upper surface.

[0449] As a result, the oxide semiconductor layer 230 and the conductive layer 242 can be covered with the insulating layer 275 having a function of suppressing oxygen diffusion. This can suppress direct diffusion of oxygen from the insulating layer 280 or the like to the oxide semiconductor layer 230 and the conductive layer 242 in a later step.

[0450] 23A to 23D , the insulating layer 280, the insulating layer 275, the insulating layer 271, the conductive layer 242, and the layer 233 are processed using lithography. As a result, an opening 289 is formed that reaches the oxide semiconductor layer 230 and the insulating layer 222. By forming the opening 289, the insulating layer 271 is divided to form the insulating layers 271a and 271b. The conductive layer 242 is divided to form the conductive layers 242a and 242b. Furthermore, the layer 233 is divided to form the layers 233a and 233b. The opening 289 is formed to include a region between the low-resistance regions 230na and 230nb of the oxide semiconductor layer 230 and a region overlapping with the conductive layer 205.

[0451] The layer 233 is preferably processed under conditions where the etching selectivity with respect to the oxide semiconductor layer 230 is high. This can prevent at least a part of the oxide semiconductor layer 230 from being removed when the layer 233 is processed.

[0452] After the layers 233a and 233b are formed, an impurity element may be added to a region of the oxide semiconductor layer 230 that overlaps with the opening 289. For example, when the oxide semiconductor layer 230 is an n-type semiconductor, an impurity element that imparts p-type conductivity can be added. For example, one or both of cadmium and zinc can be added. This may make it easier to make the channel formation region 230i i-type or substantially i-type. The impurity element can be added by a method similar to that for adding the impurity element 189 described above.

[0453] 24A to 24D , an insulating layer 250 and a conductive layer 260 are formed so as to have regions located within the opening 289. For example, within the opening 289, an insulating film to become the insulating layer 250 is formed along the top surface of the insulating layer 222, the side surface of the insulating layer 224, the side surface and top surface of the oxide semiconductor layer 230, the side surface of the layer 233a, the side surface of the layer 233b, the side surface of the conductive layer 242a, the side surface of the conductive layer 242b, the side surface of the insulating layer 271a, the side surface of the insulating layer 271b, the side surface of the insulating layer 275, and the side surface of the insulating layer 280. Next, a conductive film to become the conductive layer 260 is formed on the insulating film to fill the opening 289. Thereafter, regions of the insulating film to become the insulating layer 250 and the conductive film to become the conductive layer 260 exposed from the opening 289 are removed by CMP treatment. As a result, the insulating layer 250 and the conductive layer 260 on the insulating layer 250 are formed within the opening 289. As described above, at least a part of a region of the oxide semiconductor layer 230 that overlaps with the conductive layer 260 becomes the channel formation region 230i.

[0454] Through the above steps, the transistor 200 can be formed.

[0455] 24A to 24D , an insulating layer 282 is formed on the insulating layer 250, the conductive layer 260, and the insulating layer 280. After that, an insulating layer 283 is formed on the insulating layer 282, and an insulating layer 285 is formed on the insulating layer 283. The insulating layer 282, the insulating layer 283, and the insulating layer 285 can each be formed by using, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0456] The insulating layers 282, 283, and 285 are preferably formed by a sputtering method, which does not require the use of hydrogen-containing molecules in a deposition gas, so that the hydrogen concentrations in the insulating layers 282, 283, and 285 can be reduced.

[0457] Here, the insulating layers 282, 283, and 285 are preferably formed successively by, for example, a sputtering method without exposure to the air environment. By forming the insulating layers 282, 283, and 285 without exposure to the air, impurities or moisture from the air environment can be prevented from adhering to the insulating layers 282, 283, and 285. This allows the vicinity of the interface between the insulating layers 282 and 283 and the vicinity of the interface between the insulating layers 283 and 285 to be kept clean.

[0458] 25A to 25D , an opening 244a reaching the conductive layer 242a is formed in the insulating layers 285, 283, 282, 280, 275, and 271a. An opening 244b reaching the conductive layer 242b is formed in the insulating layers 285, 283, 282, 280, 275, and 271b. The openings 244a and 244b can be formed using, for example, lithography. The openings 244a and 244b are preferably formed by processing the workpiece using dry etching. Because dry etching allows anisotropic etching, it is suitable for forming openings 244a and 244b with a high aspect ratio.

[0459] Next, insulating films that will become insulating layers 241a and 241b in a later step are formed along the sidewalls of the openings 244a and 244b. The insulating films can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The insulating films that will become insulating layers 241a and 241b are preferably formed by ALD because they are formed in the openings 244a and 244b, which have a large aspect ratio. Furthermore, insulating films that have the function of suppressing oxygen permeation are preferably used as the insulating films that will become insulating layers 241a and 241b. For example, silicon nitride is preferably formed by PEALD. Silicon nitride is preferred because it has high blocking properties against hydrogen.

[0460] Next, as shown in FIGS. 25A to 25D , the insulating film is anisotropically etched to form insulating layers 241a and 241b. Here, the insulating layer 241a is formed so as to cover the sidewall of the opening 244a. Similarly, the insulating layer 241b is formed so as to cover the sidewall of the opening 244b. Dry etching or the like can be used as anisotropic etching of the insulating film that will become the insulating layers 241a and 241b. For example, reactive ion etching is preferably performed. By forming the insulating layer 241a so as to cover the sidewall of the opening 244a and the insulating layer 241b so as to cover the sidewall of the opening 244b, oxygen permeation from the outside can be suppressed, and oxidation of the conductive layers 243a and 243b, which will be formed in the next process, can be prevented. Furthermore, impurities such as water and hydrogen contained in the insulating layer 280 can be prevented from diffusing into the conductive layers 243a and 243b. Note that the anisotropic etching may form recesses in parts of the top surfaces of the conductive layers 242a and 242b.

[0461] Next, conductive films to be the conductive layers 243a and 243b are formed. The conductive films preferably have a stacked structure including a conductor that has a function of suppressing permeation of impurities such as water and hydrogen. For example, the conductive films can be stacked layers of tantalum nitride, titanium nitride, or the like, and tungsten, molybdenum, copper, or the like. The conductive films to be the conductive layers 243a and 243b can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0462] 25A to 25D, CMP treatment is performed to remove parts of the conductive film that will become the conductive layers 243a and 243b, thereby exposing the top surface of the insulating layer 285. As a result, the conductive film remains only in the openings 244a and 244b, and the conductive layers 243a and 243b have flat top surfaces. Note that the CMP treatment may remove part of the top surface of the insulating layer 285.

[0463] After the conductive layers 243a and 243b are formed, heat treatment may be further performed. The heat treatment may be performed under conditions similar to those of the above-described heat treatment. By performing the heat treatment, the amount of oxygen supplied to the oxide semiconductor layer 230 can be adjusted. This can improve the electrical characteristics and reliability of the transistor 200.

[0464] In this manner, the semiconductor device shown in FIG. 1A and FIGS. 2A to 2C can be manufactured.

[0465] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0466] Embodiment 2 In this embodiment, a semiconductor device 900 according to one embodiment of the present invention will be described. The semiconductor device 900 can function as a memory device.

[0467] Fig. 26 is a block diagram showing a configuration example of a semiconductor device 900. The semiconductor device 900 shown in Fig. 26 has a driver circuit 910 and a memory array 920. The memory array 920 has one or more memory cells 950. Fig. 26 shows an example in which the memory array 920 has a plurality of memory cells 950 arranged in a matrix.

[0468] The transistor described as an example in Embodiment 1 can be applied to the memory cell 950. By using the transistor, the operation speed of the memory device can be improved. Furthermore, miniaturization and high integration of the memory device can be achieved. Furthermore, the capacitance per area of ​​the memory device can be increased.

[0469] The driver circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generating circuit 928.

[0470] In the semiconductor device 900, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0471] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 912.

[0472] The control circuit 912 is a logic circuit having a function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.

[0473] The voltage generating circuit 928 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 928. For example, when an H-level signal is given as the signal WAKE, the signal CLK is input to the voltage generating circuit 928, and the voltage generating circuit 928 generates a negative voltage.

[0474] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cells 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0475] The row decoder 941 and the column decoder 942 have the function of decoding the signal ADDR. The row decoder 941 is a circuit for specifying a row to be accessed, and the column decoder 942 is a circuit for specifying a column to be accessed. The row driver 923 has the function of selecting the row specified by the row decoder 941. The column driver 924 has the function of writing data to the memory cells 950, reading data from the memory cells 950, and retaining the read data.

[0476] The input circuit 925 has a function of holding a signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is data (Din) to be written to the memory cell 950. The data (Dout) read from the memory cell 950 by the column driver 924 is output to the output circuit 926. The output circuit 926 has a function of holding Dout. In addition, the output circuit 926 has a function of outputting Dout to the outside of the semiconductor device 900. The data output from the output circuit 926 is a signal RDA.

[0477] The PSW 931 is a V ＤＤ The PSW 932 has the function of controlling the supply of V to the row driver 923. ＨＭ Here, the high power supply potential of the semiconductor device 900 is V ＤＤ and the low power supply potential is GND (ground potential). ＨＭ is the high power supply potential used to drive the word line high, and V ＤＤ 26, in the peripheral circuit 915, V ＤＤ Although the number of power domains to which power is supplied is set to one, it is also possible to provide a plurality of power domains. In this case, a tapered power switch can be provided for each power domain.

[0478] 27A to 27H, examples of other memory cell configurations that can be applied to the memory cell 950 will be described.

[0479] 27A shows an example of a circuit configuration of a DRAM memory cell. In this specification and the like, a DRAM using an OS transistor is referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). A memory cell 951 includes a transistor M1 and a capacitor CA.

[0480] The transistor M1 may have a front gate (sometimes simply referred to as a gate) and a back gate. In this case, the back gate may be connected to a wiring to which a constant potential or a signal is applied, or the front gate and the back gate may be connected to each other.

[0481] A first terminal of the transistor M1 is connected to a first terminal of the capacitance element CA, a second terminal of the transistor M1 is connected to the wiring BIL, and a gate of the transistor M1 is connected to the wiring WOL. The second terminal of the capacitance element CA is connected to the wiring CAL.

[0482] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0483] Data is written and read by applying a high-level potential to the wiring WOL to turn on the transistor M1 and connect the wiring BIL to the first terminal of the capacitor CA.

[0484] Furthermore, the memory cell that can be used as the memory cell 950 is not limited to the memory cell 951, and the circuit configuration can be changed. For example, the memory cell 952 shown in FIG. 27B may be used. The memory cell 952 is an example of a memory cell that does not include a capacitor CA and a wiring CAL. The first terminal of the transistor M1 is in an electrically floating state.

[0485] In the memory cell 952, the potential written through the transistor M1 is held in a capacitance (also referred to as a parasitic capacitance) between the first terminal and the gate, which is indicated by a dashed line. With this configuration, the configuration of the memory cell can be significantly simplified.

[0486] Note that the OS transistor described in Embodiment 1 is preferably used as the transistor M1. Use of the OS transistor described in Embodiment 1 can improve the operation speed of the memory device. Furthermore, the area occupied by the memory cell can be reduced. Furthermore, an OS transistor has a characteristic of extremely low off-state current. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be significantly reduced. That is, written data can be held by the transistor M1 for a long time, which reduces the frequency of refreshing the memory cell. Alternatively, the refresh operation of the memory cell can be eliminated. Furthermore, the extremely low leakage current allows multilevel data or analog data to be held in the memory cell 951 and the memory cell 952.

[0487] An example of the structure of a DOSRAM will now be described with reference to Fig. 28. In Fig. 28, the X direction is parallel to the channel width direction of the illustrated transistor, the Y direction is perpendicular to the X direction, and the Z direction is perpendicular to the X and Y directions.

[0488] 28, a memory cell 951 includes a transistor M1 and a capacitor CA. An insulating layer 284 is provided over the transistor M1. The insulating layer 284 can be formed using an insulator that can be used for the insulating layer 216.

[0489] 28 illustrates an example in which the transistor M1 has a structure similar to that of the transistor 200 described in Embodiment 1. In this embodiment, the same components as those in the semiconductor device described in Embodiment 1 are denoted by the same reference numerals. For details of the transistor 200, refer to Embodiment 1. Note that a transistor having a structure similar to that of any of the transistors 200A to 200D described in Embodiment 1 may be used as the transistor M1.

[0490] 28, the conductive layer 243b extends in the Z direction and functions as the wiring BIL. The conductive layer 260 of the transistor 200 extends in the X direction and functions as the wiring WOL.

[0491] In the semiconductor device shown in FIG. 28, the capacitor CA includes a conductive layer 453 over the conductive layer 242a, an insulating layer 454 over the conductive layer 453, and a conductive layer 460 (conductive layer 460a and conductive layer 460b) over the insulating layer 454.

[0492] At least a portion of the conductive layer 453, the insulating layer 454, and the conductive layer 460 is disposed in openings provided in the insulating layer 271a, the insulating layer 275, the insulating layer 280, the insulating layer 282, the insulating layer 283, and the insulating layer 285, respectively. Ends of the conductive layer 453, the insulating layer 454, and the conductive layer 460 are located at least on the insulating layer 283, and preferably on the insulating layer 285. The insulating layer 454 is provided so as to cover an end of the conductive layer 453. This allows the conductive layer 453 and the conductive layer 460 to be electrically insulated from each other.

[0493] The capacitance of the capacitor CA can be increased by increasing the depth of the openings provided in the insulating layer 271a, the insulating layer 275, the insulating layer 280, the insulating layer 282, the insulating layer 283, and the insulating layer 285 (that is, by increasing the thickness of one or more of the insulating layer 271a, the insulating layer 275, the insulating layer 280, the insulating layer 282, the insulating layer 283, and the insulating layer 285). Increasing the capacitance per unit area of ​​the capacitor CA allows for miniaturization or high integration of the memory device.

[0494] The conductive layer 453 has a region that functions as one electrode (lower electrode) of the capacitor element CA. The insulating layer 454 has a region that functions as a dielectric of the capacitor element CA. The conductive layer 460 has a region that functions as the other electrode (upper electrode) of the capacitor element CA. The upper portion of the conductive layer 460 can be extended to function as a wiring CAL. The capacitor element CA constitutes an MIM (Metal-Insulator-Metal) capacitor.

[0495] The conductive layer 242a provided over and overlapping with the oxide semiconductor layer 230 functions as an electrode connected to a lower electrode of the capacitor CA.

[0496] The conductive layers 453 and 460 included in the capacitor CA can be formed using any of various conductors that can be used for the conductive layer 205 or the conductive layer 260. The conductive layers 453 and 460 are preferably formed by a film formation method with good coverage, such as an ALD method or a CVD method. For example, the conductive layer 453 can be formed using titanium nitride or tantalum nitride formed by an ALD method or a CVD method.

[0497] The top surface of the conductive layer 242a is in contact with the bottom surface of the conductive layer 453. Here, by using a conductive material with good conductivity for the conductive layer 242a, contact resistance between the conductive layer 453 and the conductive layer 242a can be reduced.

[0498] Alternatively, the conductive layer 460a may be formed using titanium nitride by an ALD method or a CVD method, and the conductive layer 460b may be formed using tungsten by a CVD method. Note that if the adhesion of tungsten to the insulating layer 454 is sufficiently high, the conductive layer 460 may have a single-layer structure of tungsten formed by a CVD method.

[0499] The insulating layer 454 of the capacitor CA is preferably formed using a high-dielectric-constant (high-k) material as described in the previous embodiment. By using such a high-k material, the insulating layer 454 can be thick enough to suppress leakage current and ensure sufficient capacitance of the capacitor CA. The insulating layer 454 is preferably formed using a film formation method with good coverage, such as an ALD method or a CVD method.

[0500] Furthermore, it is preferable to use a laminated structure of insulators made of the above materials, and it is preferable to use a laminated structure of a material with a high dielectric constant (high-k) and a material with a higher dielectric strength than the high dielectric constant (high-k) material. For example, the insulating layer 454 can be an insulator laminated in the order of zirconium oxide, aluminum oxide, and zirconium oxide. Alternatively, it can be an insulator laminated in the order of zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide. Alternatively, it can be an insulating film laminated in the order of hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide. By using a laminated structure of insulators with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength is improved, and electrostatic breakdown of the capacitance element CA can be suppressed.

[0501] The insulating layer 454 may also be made of a material capable of exhibiting ferroelectricity, as described in Embodiment 1. A ferroelectric material is an insulator that generates polarization internally when an external electric field is applied, and the polarization remains even when the electric field is removed. Therefore, a nonvolatile memory element can be formed using a capacitor element (hereinafter sometimes referred to as a ferroelectric capacitor) using such a material as a dielectric. A nonvolatile memory element using a ferroelectric capacitor is sometimes called a Ferroelectric Random Access Memory (FeRAM), a ferroelectric memory, or the like. For example, a ferroelectric memory includes a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor is connected to one terminal of the ferroelectric capacitor. Therefore, when a ferroelectric capacitor is used as the capacitor element CA, the memory device described in this embodiment functions as a ferroelectric memory.

[0502] The deeper the depth of the openings provided in the insulating layers 271a, 275, 280, 282, 283, and 285 (i.e., the thicker the thickness of one or more of the insulating layers 271a, 275, 280, 282, 283, and 285), the larger the capacitance of the capacitor CA. For example, the capacitance of the capacitor CA can be set by adjusting the thickness of the insulating layer 285. Specifically, it is preferable to set the thickness of the insulating layer 285 to a range of 50 nm to 250 nm and to set the depth of the openings to a range of 150 nm to 350 nm. Forming the capacitor CA within such a range ensures that the capacitor CA has sufficient capacitance and prevents the height of one layer from becoming excessively high in a semiconductor device in which multiple memory cell layers are stacked. Note that the capacitance of the capacitors provided in each of the multiple memory cell layers may be different. In this configuration, for example, the thickness of the insulating layer 285 provided in each memory cell layer can be made different.

[0503] Note that in the opening provided in the insulating layer 285 or the like where the capacitor element CA is arranged, the sidewall of the opening may be perpendicular or approximately perpendicular to the top surface of the insulating layer 222, or may have a tapered shape. By making the sidewall tapered, coverage of the conductive layer 453 or the like provided in the opening of the insulating layer 285 or the like can be improved, and defects such as voids can be reduced.

[0504] 28 , the conductive layer 242b provided so as to overlap the oxide semiconductor layer 230 functions as a wiring connected to the conductive layer 243b. For example, in FIG. 28 , the upper surface and side end portions of the conductive layer 242b are connected to the conductive layer 243b extending in the Z direction.

[0505] By directly contacting the conductive layer 243b with at least one of the upper surface and side end of the conductive layer 242b, there is no need to provide a separate electrode for connection, and therefore the area occupied by the memory array can be reduced. Furthermore, the integration density of memory cells can be improved, and the memory capacity of the memory device can be increased. It is preferable that the conductive layer 243b be in contact with a portion of the upper surface and side end of the conductive layer 242b. By contacting the conductive layer 243b with multiple surfaces of the conductive layer 242b, the contact resistance between the conductive layer 243b and the conductive layer 242b can be reduced.

[0506] The conductive layer 243b is provided in openings formed in the insulating layer 212, the insulating layer 214, the insulating layer 216, the insulating layer 221, the insulating layer 222, the insulating layer 224, the oxide layer 227, the insulating layer 271b, the insulating layer 275, the insulating layer 280, the insulating layer 282, the insulating layer 283, the insulating layer 285, and the insulating layer 284.

[0507] 28 , an insulating layer 241b is preferably provided in contact with a side surface of the conductive layer 243b. Specifically, the insulating layer 241b is provided in contact with inner walls of the openings of the insulating layer 212, the insulating layer 214, the insulating layer 216, the insulating layer 221, the insulating layer 222, the insulating layer 224, the oxide layer 227, the insulating layer 271b, the insulating layer 275, the insulating layer 280, the insulating layer 282, the insulating layer 283, the insulating layer 285, and the insulating layer 284. The insulating layer 241b is also formed on a side surface of the oxide semiconductor layer 230, which is formed to protrude into the opening. Here, at least a part of the conductive layer 242b is exposed from the insulating layer 241b and is in contact with the conductive layer 243b. That is, the conductive layer 243b is provided to fill the openings via the insulating layer 241b.

[0508] 28 , the uppermost part of the insulating layer 241b formed below the conductive layer 242b is preferably located below the top surface of the conductive layer 242b. With this structure, the conductive layer 243b can be in contact with at least a part of the side edge of the conductive layer 242b. Note that the insulating layer 241b formed below the conductive layer 242b preferably has a region in contact with the side surface of the oxide semiconductor layer 230. With this structure, impurities such as water and hydrogen contained in the insulating layer 280 or the like can be prevented from being mixed into the oxide semiconductor layer 230 through the conductive layer 243b.

[0509] In the opening where the conductive layer 243b and the insulating layer 241b are disposed, the sidewall of the opening may be perpendicular or approximately perpendicular to the top surface of the insulating layer 222, or may have a tapered shape. By making the sidewall tapered, coverage of the opening with the insulating layer 241b or the like provided therein is improved.

[0510] 27C shows an example circuit configuration of a gain cell type memory cell having two transistors and one capacitor. The memory cell 953 includes a transistor M2, a transistor M3, and a capacitor CB. In this specification and the like, a storage device having a gain cell type memory cell in which the transistor M2 is an OS transistor is referred to as a nonvolatile oxide semiconductor RAM (NOSRAM).

[0511] The first terminal of transistor M2 is connected to the first terminal of capacitance element CB, the second terminal of transistor M2 is connected to wiring WBL, and the gate of transistor M2 is connected to wiring WOL. The second terminal of capacitance element CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitance element CB.

[0512] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CB. When writing data, while retaining data, and when reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0513] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M2, and connecting the wiring WBL to the first terminal of the capacitor CB. Specifically, when the transistor M2 is on, a potential corresponding to the information to be recorded is applied to the wiring WBL, and the potential is written to the first terminal of the capacitor CB and the gate of the transistor M3. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M2, thereby maintaining the potential of the first terminal of the capacitor CB and the potential of the gate of the transistor M3.

[0514] Data is read by applying a predetermined potential to the wiring SL. The current flowing between the source and drain of the transistor M3 and the potential of the first terminal of the transistor M3 are determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3. Therefore, by reading the potential of the wiring RBL connected to the first terminal of the transistor M3, the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3) can be read. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3).

[0515] Alternatively, for example, the wiring WBL and the wiring RBL may be combined into a single wiring BIL. An example circuit configuration of such a memory cell is shown in FIG. 27D. The memory cell 954 is configured such that the wiring WBL and the wiring RBL of the memory cell 953 are combined into a single wiring BIL, and the second terminal of the transistor M2 and the first terminal of the transistor M3 are connected to the wiring BIL. In other words, the memory cell 954 is configured to operate as a write bit line and a read bit line using a single wiring BIL.

[0516] 27E is an example in which the capacitor element CB and the wiring CAL are omitted from the memory cell 953. Also, the memory cell 956 shown in Fig. 27F is an example in which the capacitor element CB and the wiring CAL are omitted from the memory cell 954. With such a configuration, the integration degree of the memory cells can be increased.

[0517] Note that at least the transistor M2 is preferably the OS transistor described in Embodiment 1. In particular, the transistors M2 and M3 are preferably the OS transistors described in Embodiment 1. By using the OS transistor described in Embodiment 1, the operation speed of the memory device can be improved. In addition, the area occupied by the memory cell can be reduced.

[0518] Since the OS transistor has an extremely low off-state current, written data can be held by the transistor M2 for a long time, which reduces the frequency of refreshing the memory cell. Alternatively, the refresh operation of the memory cell can be eliminated. Furthermore, since the leakage current is extremely low, multilevel data or analog data can be held in the memory cell 953, the memory cell 954, the memory cell 955, and the memory cell 956.

[0519] The memory cell 953, the memory cell 954, the memory cell 955, and the memory cell 956, each of which uses an OS transistor as the transistor M2, are one embodiment of an NOSRAM.

[0520] Note that a Si transistor may be used as the transistor M3. The Si transistor can increase the field effect mobility and can also be used as a p-channel transistor, thereby increasing the degree of freedom in circuit design.

[0521] When an OS transistor is used as the transistor M3, the memory cell can be configured as a unipolar circuit.

[0522] 27G shows a three-transistor, one-capacitor gain cell type memory cell 957. The memory cell 957 has transistors M4 to M6 and a capacitor CC.

[0523] The first terminal of transistor M4 is connected to the first terminal of capacitor CC, the second terminal of transistor M4 is connected to wiring BIL, and the gate of transistor M4 is connected to wiring WOL. The second terminal of capacitor CC is connected to the first terminal of transistor M5 and wiring GNDL. The second terminal of transistor M5 is connected to the first terminal of transistor M6, and the gate of transistor M5 is connected to the first terminal of capacitor CC. The second terminal of transistor M6 is connected to wiring BIL, and the gate of transistor M6 is connected to wiring RWL.

[0524] The wiring BIL functions as a bit line, the wiring WOL functions as a write word line, and the wiring RWL functions as a read word line. The wiring GNDL is a wiring that applies a low-level potential.

[0525] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M4, and connecting the wiring BIL to the first terminal of the capacitor CC. Specifically, when the transistor M4 is turned on, a potential corresponding to the information to be recorded is applied to the wiring BIL, and the potential is written to the first terminal of the capacitor CC and the gate of the transistor M5. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M4, thereby holding the potential of the first terminal of the capacitor CC and the potential of the gate of the transistor M5.

[0526] Data is read by precharging the wiring BIL to a predetermined potential, then electrically floating the wiring BIL, and applying a high-level potential to the wiring RWL. Because the wiring RWL is at a high-level potential, the transistor M6 is turned on, and the wiring BIL is connected to the second terminal of the transistor M5. At this time, the potential of the wiring BIL is applied to the second terminal of the transistor M5. The potential of the second terminal of the transistor M5 and the potential of the wiring BIL change depending on the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5). By reading the potential of the wiring BIL, the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5) can be read. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5).

[0527] Note that at least the transistor M4 is preferably the OS transistor described in Embodiment 1. By using the OS transistor described in Embodiment 1, the area occupied by the memory cell can be reduced.

[0528] Note that Si transistors may be used as the transistors M5 and M6. As described above, Si transistors may have higher field-effect mobility than OS transistors depending on the crystalline state of silicon used in the semiconductor layer.

[0529] When OS transistors are used as the transistors M5 and M6, the memory cell can be configured as a unipolar circuit.

[0530] 27H shows an example of an SRAM (Static Random Access Memory) using an OS transistor. In this specification and the like, an SRAM using an OS transistor is referred to as an OS-SRAM (Oxide Semiconductor-SRAM). Note that a memory cell 958 shown in FIG. 27H is a memory cell of an SRAM capable of backing up data.

[0531] The memory cell 958 includes transistors M7 to M10, transistors MS1 to MS4, and capacitors CD1 and CD2. Note that the transistors MS1 and MS2 are p-channel transistors, and the transistors MS3 and MS4 are n-channel transistors.

[0532] A first terminal of transistor M7 is connected to wiring BIL, and a second terminal of transistor M7 is connected to a first terminal of transistor MS1, a first terminal of transistor MS3, the gate of transistor MS2, the gate of transistor MS4, and a first terminal of transistor M10. The gate of transistor M7 is connected to wiring WOL. A first terminal of transistor M8 is connected to wiring BILB, and a second terminal of transistor M8 is connected to a first terminal of transistor MS2, the first terminal of transistor MS4, the gate of transistor MS1, the gate of transistor MS3, and a first terminal of transistor M9. The gate of transistor M8 is connected to wiring WOL.

[0533] A second terminal of the transistor MS1 is connected to the wiring VDL. A second terminal of the transistor MS2 is connected to the wiring VDL. A second terminal of the transistor MS3 is connected to the wiring GNDL. A second terminal of the transistor MS4 is connected to the wiring GNDL.

[0534] A second terminal of the transistor M9 is connected to a first terminal of the capacitor CD1, and a gate of the transistor M9 is connected to the wiring BRL. A second terminal of the transistor M10 is connected to a first terminal of the capacitor CD2, and a gate of the transistor M10 is connected to the wiring BRL.

[0535] A second terminal of the capacitance element CD1 is connected to the wiring GNDL, and a second terminal of the capacitance element CD2 is connected to the wiring GNDL.

[0536] The wirings BIL and BILB function as bit lines, the wiring WOL functions as a word line, and the wiring BRL is a wiring that controls the conductive state and non-conductive state of the transistors M9 and M10.

[0537] The wiring VDL is a wiring that applies a high-level potential, and the wiring GNDL is a wiring that applies a low-level potential.

[0538] Data is written by applying a high-level potential to the wiring WOL and a high-level potential to the wiring BRL. Specifically, when the transistor M10 is in a conductive state, a potential corresponding to information to be recorded is applied to the wiring BIL, and the potential is written to the second terminal of the transistor M10.

[0539] Since the memory cell 958 includes an inverter loop formed by the transistors MS1 and MS2, an inverted signal of the data signal corresponding to the potential is input to the second terminal of the transistor M8. Because the transistor M8 is conductive, the potential applied to the wiring BIL, i.e., the inverted signal of the signal input to the wiring BIL, is output to the wiring BILB. Because the transistors M9 and M10 are conductive, the potentials of the second terminals of the transistors M7 and M8 are held in the first terminals of the capacitors CD2 and CD1, respectively. After that, a low-level potential is applied to the wiring WOL and a low-level potential is applied to the wiring BRL to turn off the transistors M7 to M10, thereby holding the potentials of the first terminals of the capacitors CD1 and CD2.

[0540] Data is read by precharging the wirings BIL and BILB to a predetermined potential in advance, and then applying a high-level potential to the wiring WOL and a high-level potential to the wiring BRL. The potential of the first terminal of the capacitor CD1 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BILB. The potential of the first terminal of the capacitor CD2 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BIL. The potentials of the wirings ...

Claims

having a transistor, the transistor includes an oxide semiconductor layer, the oxide semiconductor layer has a source region, a drain region, and a channel formation region located between the source region and the drain region; the oxide semiconductor layer contains indium oxide, a concentration of the first element in the source region and the drain region is higher than a concentration of the first element in the channel formation region; The semiconductor device, wherein the first element is at least one of yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, and a light rare earth element. 　 In claim 1, A first layer and a second layer, the first layer is in contact with a top surface of the oxide semiconductor layer in a region between the source region and the channel formation region; the second layer is in contact with an upper surface of the oxide semiconductor layer in a region between the drain region and the channel formation region; a source electrode of the transistor having a region in contact with the source region and a region located on the first layer; The drain electrode of the transistor has a region in contact with the drain region and a region located on the second layer. 　 a transistor, a first layer, and a second layer; the transistor includes an oxide semiconductor layer, the oxide semiconductor layer has a source region, a drain region, and a channel formation region located between the source region and the drain region; the oxide semiconductor layer contains indium oxide, the first layer is in contact with a top surface of the oxide semiconductor layer in a region between the source region and the channel formation region; the second layer is in contact with an upper surface of the oxide semiconductor layer in a region between the drain region and the channel formation region; a source electrode of the transistor having a region in contact with the source region and a region located on the first layer; a drain electrode of the transistor having a region in contact with the drain region and a region located on the second layer; a gate insulating layer of the transistor having a region located between the first layer and the second layer and a region located between the source electrode and the drain electrode; a gate electrode of the transistor is provided on the gate insulating layer so as to overlap the channel formation region; a concentration of the first element in the source region and the drain region is higher than a concentration of the first element in the channel formation region; The semiconductor device, wherein the first element is at least one of yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, and a light rare earth element. 　 In any one of claims 1 to 3, The semiconductor device, wherein the first element is at least one of yttrium, zirconium, silver, cadmium, tin, and antimony. 　 In claim 2 or claim 3, the first layer and the second layer are oxide layers each containing indium, zinc, and a second element; The semiconductor device, wherein the second element is one or more of gallium, aluminum, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. 　 In any one of claims 1 to 3, having an oxide layer, the oxide semiconductor layer is provided so as to be in contact with an upper surface of the oxide layer, The oxide layer has cubic crystal grains. 　 In claim 6, The semiconductor device, wherein a lattice mismatch between the crystal grains of the oxide layer and the crystal grains of the oxide semiconductor layer is 0% or more and 10% or less. 　 In claim 6, The oxide layer comprises yttrium, zirconium, and oxygen.

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