Doherty amplifier

Abstract

This Doherty amplifier is configured comprising: a first output circuit (6) having a first transmission line for transmitting a first signal output from a carrier amplifier (4), and outputting the first signal after transmission by the first transmission line to a load (9); and a second output circuit (7) having a second transmission line for transmitting a second signal output from a peak amplifier (5), and outputting the second signal after transmission by the second transmission line to the load (9). The first transmission line is provided with: a first T-type circuit (11) having one end connected to the output side of the carrier amplifier (4) and having the load (9) and the other end connected thereto; and a first capacitor (12) having one end connected to the other end of the first T-type circuit (11) and the other end grounded. The second transmission line is provided with: a second T-type circuit (21) having one end connected to the output side of the peak amplifier (5); a second capacitor (22) having one end connected to the other end of the second T-type circuit (21) and having a load (9) and the other end connected thereto; and a third capacitor (23) having one end connected to the other end of the second T-type circuit (21) and the other end grounded.

Description

Doherty Amplifier

[0001] The present disclosure relates to Doherty amplifiers.

[0002] There is a Doherty amplifier that includes a carrier amplifier and a peak amplifier. For example, Patent Document 1 discloses a Doherty amplifier that includes a first output circuit that transmits a first signal output from the carrier amplifier and a second output circuit that transmits a second signal output from the peak amplifier. The second output circuit includes a high-pass circuit to cancel the influence of the parasitic capacitance of the peak amplifier.

[0003] International Publication No. 2022-118445

[0004] In the Doherty amplifier disclosed in Patent Document 1, the frequency characteristics during back-off operation are improved by providing the second output circuit with a high-pass circuit, but there is a problem in that the effect of widening the bandwidth is limited when the second output circuit is simply provided with a high-pass circuit.

[0005] The present disclosure has been made to solve the above-described problems, and aims to obtain a Doherty amplifier that can achieve wider bandwidth characteristics than the Doherty amplifier disclosed in Patent Document 1.

[0006] A Doherty amplifier according to the present disclosure includes a first output circuit having a first transmission line for transmitting a first signal output from a carrier amplifier and outputting the first signal after transmission via the first transmission line to a load, and a second output circuit having a second transmission line for transmitting a second signal output from a peak amplifier and outputting the second signal after transmission via the second transmission line to the load. The first transmission line includes a first T-type circuit having one end connected to the output side of the carrier amplifier and the other end connected to the load, and a first capacitor having one end connected to the other end of the first T-type circuit and the other end grounded. The second transmission line includes a second T-type circuit having one end connected to the output side of the peak amplifier, a second capacitor having one end connected to the other end of the second T-type circuit and the other end connected to the load, and a third capacitor having one end connected to the other end of the second T-type circuit and the other end grounded.

[0007] According to the present disclosure, it is possible to achieve wider bandwidth characteristics than the Doherty amplifier disclosed in Patent Document 1.

[0008] 1 is a configuration diagram showing a Doherty amplifier according to a first embodiment; FIG. 2 is a configuration diagram showing the inside of each of a first output circuit 6 and a second output circuit 7; FIG. 3 is a circuit diagram showing each of a first output circuit 6 and a second output circuit 7; ｓ１ , C ｓ２ 1 is a circuit diagram showing a first output circuit 6 and a second output circuit 7, with characteristic impedance Z １ , Z ２ , Z ３ 1 is a circuit diagram showing a circuit in which the first output circuit 6 and the second output circuit 7 are replaced by two T-type matching circuits and a lumped parameter network C ｍ , C ３ , C ａ FIG. 1 is a circuit diagram showing the implementation of the above-described configuration. FIG. 2 is an explanatory diagram showing a simulation result of mismatch on the first transmission line side during saturation. FIG. 3 is an explanatory diagram showing a simulation result of mismatch on the second transmission line side during saturation. FIG. 4 is an explanatory diagram showing a simulation result of mismatch on the first transmission line side during back-off. FIG. 5 is an explanatory diagram showing a simulation result of saturated output power of a Doherty amplifier. FIG. 6 is an explanatory diagram showing a simulation result of saturation efficiency of a Doherty amplifier. FIG. 7 is an explanatory diagram showing a simulation result of back-off efficiency of a Doherty amplifier. In the first output circuit 6 and the second output circuit 7, Z １ = 77 Ω, Z ２ = 77Ω, R Ｌ = 50Ω, R ｏｐｔ 1 is a circuit diagram when the capacitance C of the second capacitor 22 is 60Ω. ３ and characteristic impedance Z ３ and phase θ ３FIG. 1 is an explanatory diagram showing a correspondence relationship between the mismatch on the first transmission line side during saturation. FIG. 2 is an explanatory diagram showing a simulation result of the mismatch on the second transmission line side during saturation. FIG. 3 is an explanatory diagram showing a simulation result of the loss of the Doherty amplifier during saturation. FIG. 4 is an explanatory diagram showing a simulation result of the mismatch on the first transmission line side during back-off. FIG. 5 is an explanatory diagram showing a simulation result of the loss of the Doherty amplifier during back-off. FIG. 6 is an explanatory diagram showing a simulation result of the saturated output power of the Doherty amplifier. FIG. 7 is an explanatory diagram showing a simulation result of the saturation efficiency of the Doherty amplifier. FIG. 8 is an explanatory diagram showing a simulation result of the back-off efficiency of the Doherty amplifier.

[0009] In order to explain the present disclosure in more detail, embodiments of the present disclosure will be described below with reference to the accompanying drawings.

[0010] 1 is a configuration diagram showing a Doherty amplifier according to embodiment 1. The Doherty amplifier shown in Fig. 1 includes a distributor 1, a first input circuit 2, a second input circuit 3, a carrier amplifier 4, a peak amplifier 5, a first output circuit 6, a second output circuit 7, and a combining point 8.

[0011] The divider 1 divides the power of an input signal, which is a signal to be amplified. Hereinafter, the signal distributed to the carrier amplifier 4 side will be referred to as a first signal. The signal distributed to the peak amplifier 5 side will be referred to as a second signal. The divider 1 outputs the first signal to a first input circuit 2 and outputs the second signal to a second input circuit 3.

[0012] The first input circuit 2 delays the first signal output from the divider 1 and outputs the delayed first signal to the carrier amplifier 4. The second input circuit 3 delays the second signal output from the divider 1 and outputs the delayed second signal to the peak amplifier 5.

[0013] The carrier amplifier 4 includes an input matching circuit 4a and a first transistor 4b. The carrier amplifier 4 is provided with a first signal delayed by the first input circuit 2 as a signal to be amplified. The carrier amplifier 4 operates, for example, with a class A bias or a class AB bias, amplifies the first signal delayed by the first input circuit 2, and outputs the amplified first signal to the first output circuit 6. The input matching circuit 4a matches the impedance on the input side of the first transistor 4b. The first transistor 4b is realized, for example, by a field effect transistor (FET). The first transistor 4b amplifies the first signal delayed by the first input circuit 2.

[0014] The peak amplifier 5 includes an input matching circuit 5a and a second transistor 5b. The peak amplifier 5 receives the second signal delayed by the second input circuit 3 as the signal to be amplified. The peak amplifier 5 operates, for example, with a class C bias, amplifies the second signal delayed by the second input circuit 3, and outputs the amplified second signal to the second output circuit 7. The input matching circuit 5a matches the impedance on the input side of the second transistor 5b. The second transistor 5b is realized, for example, by an FET. The second transistor 5b amplifies the second signal delayed by the second input circuit 3.

[0015] The first output circuit 6 has a first transmission line for transmitting the first signal output from the carrier amplifier 4. The first output circuit 6 outputs the first signal after transmission over the first transmission line to a combining point 8. The second output circuit 7 has a second transmission line for transmitting the second signal output from the peak amplifier 5. The second output circuit 7 outputs the second signal after transmission over the second transmission line to a combining point 8.

[0016] The combining point 8 is connected to the output side of the first output circuit 6, the output side of the second output circuit 7, and the input side of the load 9. The load 9 is driven by the signal amplified by the Doherty amplifier.

[0017] 2 is a configuration diagram showing the internal configuration of each of the first output circuit 6 and the second output circuit 7. The first output circuit 6 includes a first T-type circuit 11 and a first capacitor 12 as a first transmission line. The first T-type circuit 11 is, for example, a high-pass circuit and includes transmission lines 11a, 11b, and 11c. One end of the first T-type circuit 11 is connected to the output side of the carrier amplifier 4. The other end of the first T-type circuit 11 is connected to one end of the first capacitor 12 and the combining point 8. The first T-type circuit 11 blocks low-frequency signals included in the first signal output from the carrier amplifier 4 and passes high-frequency signals included in the first signal.

[0018] One end of the transmission line 11a is connected to the output side of the carrier amplifier 4. The other end of the transmission line 11a is connected to one end of the transmission line 11b and one end of the transmission line 11c. The characteristic impedance of the transmission line 11a is Z Ａ and the phase of the transmission line 11a is θ Ａ is.

[0019] One end of the transmission line 11b is connected to the other end of the transmission line 11a and one end of the transmission line 11c. The other end of the transmission line 11b is connected to one end of the first capacitor 12 and the combining point 8. The characteristic impedance of the transmission line 11b is Z Ｂ and the phase of the transmission line 11b is θ Ｂ is.

[0020] One end of the transmission line 11c is connected to the other end of the transmission line 11a and one end of the transmission line 11b. The other end of the transmission line 11c is grounded. The characteristic impedance of the transmission line 11c is Z Ｃ and the phase of the transmission line 11c is θ Ｃ is.

[0021] One end of the first capacitor 12 is connected to the other end of the transmission line 11b and the combining point 8. The other end of the first capacitor 12 is grounded. The capacitance of the first capacitor 12 is C ｍ is.

[0022] The second output circuit 7 includes a second transmission line, which includes a second T-type circuit 21, a second capacitor 22, and a third capacitor 23. The second T-type circuit 21 is, for example, a high-pass circuit and includes transmission lines 21a, 21b, and 21c. One end of the second T-type circuit 21 is connected to the output side of the peak amplifier 5. The other end of the second T-type circuit 21 is connected to one end of the second capacitor 22 and one end of the third capacitor 23. The second T-type circuit 21 blocks low-frequency signals included in the second signal output from the peak amplifier 5 and passes high-frequency signals included in the second signal.

[0023] One end of the transmission line 21a is connected to the output side of the peak amplifier 5. The other end of the transmission line 21a is connected to one end of the transmission line 21b and one end of the transmission line 21c. The characteristic impedance of the transmission line 21a is Z Ｄ and the phase of the transmission line 21a is θ Ｄ is.

[0024] One end of the transmission line 21b is connected to the other end of the transmission line 21a and one end of the transmission line 21c. The other end of the transmission line 21b is connected to one end of the second capacitor 22 and one end of the third capacitor 23. The characteristic impedance of the transmission line 21b is Z Ｅ and the phase of the transmission line 21b is θ Ｅ is.

[0025] One end of the transmission line 21c is connected to the other end of the transmission line 21a and one end of the transmission line 21b. The other end of the transmission line 21c is grounded. The characteristic impedance of the transmission line 21c is Z Ｆ and the phase of the transmission line 21c is θ Ｆ is.

[0026] One end of the second capacitor 22 is connected to the other end of the transmission line 21b and one end of the third capacitor 23. The other end of the second capacitor 22 is connected to the combining point 8. The capacitance of the second capacitor 22 is C ３ is.

[0027] One end of the third capacitor 23 is connected to the other end of the transmission line 21b and one end of the second capacitor 22. The other end of the third capacitor 23 is grounded. The capacitance of the third capacitor 23 is C ａ is.

[0028] Next, we will explain the operation of the Doherty amplifier shown in Fig. 1. In the Doherty amplifier shown in Fig. 1, for example, it is assumed that the equivalent electrical length of the second transmission line is −20 degrees and the difference in phase between the signal to be amplified by the carrier amplifier 4 and the signal to be amplified by the peak amplifier 5 is 90 degrees + 20 degrees.

[0029] When an input signal to be amplified is provided, the divider 1 divides the power of the input signal, and outputs a first signal, which is one of the divided signals, to the carrier amplifier 4 side, and outputs a second signal, which is the other of the divided signals, to the peak amplifier 5 side.

[0030] When the first input circuit 2 receives a first signal from the divider 1, it delays the first signal and outputs the delayed first signal to the carrier amplifier 4. When the second input circuit 3 receives a second signal from the divider 1, it delays the second signal and outputs the delayed second signal to the peak amplifier 5.

[0031] The carrier amplifier 4 amplifies the first signal delayed by the first input circuit 2 and outputs the amplified first signal to the first output circuit 6. The peak amplifier 5 amplifies the second signal delayed by the second input circuit 3 and outputs the amplified second signal to the second output circuit 7.

[0032] When the first output circuit 6 receives the amplified first signal from the carrier amplifier 4, it transmits the amplified first signal to a combining point 8. When the second output circuit 7 receives the amplified second signal from the peak amplifier 5, it transmits the amplified second signal to the combining point 8. At the combining point 8, the amplified first signal and the amplified second signal are combined, and the combined signal of the first signal and the second signal is provided to a load 9.

[0033] Here, the first transistor 4b of the carrier amplifier 4 has a parasitic capacitance C ｓ１ The second transistor 5b of the peak amplifier 5 has a parasitic capacitance C ｓ２ These parasitic capacitances C ｓ１ , C ｓ２ These parasitic capacitances C ｓ１ , C ｓ２ In order to reduce the influence of the above, the first output circuit 6 includes a first T-type circuit 11 and a first capacitor 12, and the second output circuit 7 includes a second T-type circuit 21, a second capacitor 22, and a third capacitor 23.

[0034] The following describes the circuit implementation of the first output circuit 6 and the second output circuit 7. First, as shown in FIG. 3, the first output circuit 6 is configured as a MOSFET with a characteristic impedance of Z １ , the phase is θ １ The second output circuit 7 is represented by a circuit having a characteristic impedance of Z ２ , the phase is θ ２ A circuit with a characteristic impedance of Z ３ , the phase is θ ３ 3 is a circuit diagram showing the first output circuit 6 and the second output circuit 7. In the example of FIG. 3, １ =90 degrees, θ ２ =90 degrees, θ ３ = -90 degrees. At this time, the characteristic impedance Z １ satisfies the following equation (1), and the characteristic impedance Z ３ Characteristic impedance Z ２ The ratio is expressed as in the following equation (2).

[0035] In formulas (1) and (2), R Ｌ is the resistance of the load 9, R ｏｐｔis the optimum load of the first transistor 4b, and α is the optimum load ratio between the first transistor 4b and the second transistor 5b.

[0036] Next, as shown in FIG. 4, the parasitic capacitance C ｓ１ and the parasitic capacitance C of the second transistor 5b. ｓ２ is added to the circuit shown in FIG. ｓ１ Coil L for compensating ｓ１ and parasitic capacitance C ｓ２ Coil L for compensating ｓ２ is added to the circuit shown in FIG. ｓ１ , C ｓ２ 10A and 10B are circuit diagrams showing the first output circuit 6 and the second output circuit 7, respectively, with reference numerals such as "1" and "2" added.

[0037] Next, as shown in FIG. 5, the characteristic impedance Z １ , Z ２ , Z ３ is replaced by a lumped parameter network. １ , Z ２ , Z ３ FIG. 1 is a circuit diagram showing a circuit in which is replaced by a lumped parameter network.

[0038] Next, as shown in Fig. 6, a part of the first output circuit 6 is represented by a T-type matching circuit using a distributed constant circuit, and a part of the second output circuit 7 is represented by a T-type matching circuit using a distributed constant circuit. As a result, the first output circuit 6 and the second output circuit 7 are represented by two T-type matching circuits and a C ｍ , C ３ , C ａ 6 shows a configuration in which the first output circuit 6 and the second output circuit 7 are implemented by two T-type matching circuits and a lumped constant network C ｍ , C ３ , C ａ FIG. 1 is a circuit diagram showing the above-described implementation.

[0039] FIG. 7 is an explanatory diagram showing the simulation results of mismatch on the first transmission line side during saturation. FIG. 8 is an explanatory diagram showing the simulation results of mismatch on the second transmission line side during saturation. In FIGS. 7 and 8 , the horizontal axis represents frequency, and the vertical axis represents mismatch. As is clear from FIGS. 7 and 8 , the first output circuit 6 includes the first T-type circuit 11 and the first capacitor 12, and the second output circuit 7 includes the second T-type circuit 21, the second capacitor 22, and the third capacitor 23. As a result, the Doherty amplifier shown in FIG. 1 has improved mismatch bandwidth characteristics during saturation compared to the Doherty amplifier of Patent Document 1.

[0040] 9 is an explanatory diagram showing simulation results of mismatch on the first transmission line side during backoff. In FIG. 9, the horizontal axis represents frequency, and the vertical axis represents mismatch. As is clear from FIG. 9, the first output circuit 6 includes the first T-type circuit 11 and the first capacitor 12, and the second output circuit 7 includes the second T-type circuit 21, the second capacitor 22, and the third capacitor 23. As a result, the Doherty amplifier shown in FIG. 1 has improved mismatch bandwidth characteristics during backoff compared to the Doherty amplifier of Patent Document 1.

[0041] FIG. 10 is an explanatory diagram showing simulation results of saturated output power of a Doherty amplifier. FIG. 11 is an explanatory diagram showing simulation results of saturation efficiency of a Doherty amplifier. FIG. 12 is an explanatory diagram showing simulation results of back-off efficiency of a Doherty amplifier. In FIGS. 10, 11, and 12, the horizontal axis represents frequency. In FIG. 10, the vertical axis represents saturated output power, in FIG. 11, the vertical axis represents saturation efficiency, and in FIG. 12, the vertical axis represents back-off efficiency. As is clear from FIGS. 10, 11, and 12, the Doherty amplifier shown in FIG. 1 achieves wider bandwidths of saturated output power, wider bandwidths of saturation efficiency, and wider bandwidths of back-off efficiency compared to the Doherty amplifier of Patent Document 1.

[0042] In the first embodiment described above, the Doherty amplifier is configured to include a first output circuit 6 having a first transmission line for transmitting a first signal output from the carrier amplifier 4 and outputting the first signal after transmission via the first transmission line to the load 9, and a second output circuit 7 having a second transmission line for transmitting a second signal output from the peak amplifier 5 and outputting the second signal after transmission via the second transmission line to the load 9. The first transmission line includes a first T-type circuit 11 having one end connected to the output side of the carrier amplifier 4 and the other end connected to the load 9, and a first capacitor 12 having one end connected to the other end of the first T-type circuit 11 and the other end grounded. The second transmission line includes a second T-type circuit 21 having one end connected to the output side of the peak amplifier 5, a second capacitor 22 having one end connected to the other end of the second T-type circuit 21 and the other end connected to the load 9, and a third capacitor 23 having one end connected to the other end of the second T-type circuit 21 and the other end grounded. Therefore, the Doherty amplifier can achieve wider bandwidth characteristics than the Doherty amplifier disclosed in Patent Document 1.

[0043] In the second embodiment, specific circuit conditions for realizing the wideband characteristics of the Doherty amplifier will be described. In the second embodiment, as shown in FIG. １ = 77 Ω, Z ２ = 77Ω, R Ｌ = 50Ω, R ｏｐｔ = 60Ω, the capacitance C of the second capacitor 22 ３ By selecting one of the capacitances shown in Figure 14, the characteristic impedance Z ３ and phase θ ３ The capacitance C of the second capacitor 22 is determined. ３ For example, if 81 fF is selected, the characteristic impedance Z ３ becomes 100Ω, and the phase θ ３ The capacitance C of the second capacitor 22 is −90 degrees. ３ For example, if 59 fF is selected, the characteristic impedance Z ３ becomes 145Ω, and the phase θ ３ At this time, the characteristic impedance Z２ Characteristic impedance Z ３ The ratio of Z to Z is 1.88≒2. １ = 77 Ω, Z ２ = 77Ω, R Ｌ = 50Ω, R ｏｐｔ 14 is a circuit diagram when the capacitance C of the second capacitor 22 is 60Ω. ３ and characteristic impedance Z ３ and phase θ ３ 14 is an explanatory diagram showing the correspondence relationship between the parameter (C ３ , Z ３ , θ ３ ) is determined, the circuit of the Doherty amplifier is modified in the same manner as in FIGS. 4 to 6.

[0044] Fig. 15 is an explanatory diagram showing the simulation results of mismatch on the first transmission line side at saturation. Fig. 16 is an explanatory diagram showing the simulation results of mismatch on the second transmission line side at saturation. Fig. 17 is an explanatory diagram showing the simulation results of loss in the Doherty amplifier at saturation. In Figs. 15 and 16, the horizontal axis represents frequency and the vertical axis represents mismatch. In Fig. 17, the horizontal axis represents frequency and the vertical axis represents loss. As is clear from Figs. 15 and 16, the capacitance C of the second capacitor 22 ３ As is clear from FIG. 17, the bandwidth characteristics of the mismatch at saturation change when the capacitance C of the second capacitor 22 is adjusted. ３ It can be seen that the loss at saturation changes as a result of adjusting

[0045] Fig. 18 is an explanatory diagram showing the simulation results of mismatch on the first transmission line side during back-off. Fig. 19 is an explanatory diagram showing the simulation results of loss in the Doherty amplifier during back-off. In Fig. 18, the horizontal axis represents frequency, and the vertical axis represents mismatch. In Fig. 19, the horizontal axis represents frequency, and the vertical axis represents loss. As is clear from Fig. 18, the capacitance C of the second capacitor 22 ３ As is clear from FIG. 19, the bandwidth characteristics of the mismatch during backoff change when the capacitance C of the second capacitor 22 is adjusted. ３ It can be seen that the loss during backoff changes as a result of adjusting

[0046] Fig. 20 is an explanatory diagram showing the simulation results of the saturated output power of the Doherty amplifier. Fig. 21 is an explanatory diagram showing the simulation results of the saturation efficiency of the Doherty amplifier. Fig. 22 is an explanatory diagram showing the simulation results of the back-off efficiency of the Doherty amplifier. In Figs. 20, 21, and 22, the horizontal axis represents frequency. In Fig. 20, the vertical axis represents saturated output power, in Fig. 21, the vertical axis represents saturation efficiency, and in Fig. 22, the vertical axis represents back-off efficiency. As is clear from Figs. 20, 21, and 22, the capacitance C of the second capacitor 22 ３ It can be seen that the bandwidth characteristics of the saturated output power, the bandwidth characteristics of the saturation efficiency, and the bandwidth characteristics of the back-off efficiency are all changed by adjusting the capacitance C of the second capacitor 22. ３ When 59 fF is selected as the capacitance, the effect of the wideband characteristic becomes prominent. ３ When C is 59 fF, the efficiency at high frequencies is improved the most. ３ <59 fF (θ ３ <-110°), the effect of improving efficiency on the high frequency side is not obtained, and it can be seen that the bandwidth is not widened.

[0047] In the second embodiment, the capacitance C of the second capacitor 22 ３ The capacitance C of the second capacitor 22 is３ For example, when 59 fF is selected as the capacitance of the second capacitor 22, the same 59 fF may be used as the capacitance of the first capacitor 12 and the capacitance of the third capacitor 23. ｍ =C ａ =C ３ The capacitance value of the first capacitor 12, the capacitance value of the second capacitor 22, and the capacitance value of the third capacitor 23 may be set to the same capacitance value so that:

[0048] In addition, the present disclosure allows for free combination of the respective embodiments, modification of any of the components of the respective embodiments, or omission of any of the components of the respective embodiments.

[0049] The present disclosure is suitable for Doherty amplifiers.

[0050] 1 distributor, 2 first input circuit, 3 second input circuit, 4 carrier amplifier, 4a input matching circuit, 4b first transistor, 5 peak amplifier, 5a input matching circuit, 5b first transistor, 6 first output circuit, 7 second output circuit, 8 combining point, 9 load, 11 first T-type circuit, 11a transmission line, 11b transmission line, 11c transmission line, 12 first capacitor, 21 second T-type circuit, 21a transmission line, 21b transmission line, 21c transmission line, 22 second capacitor, 23 third capacitor.

Claims

1. A first output circuit has a first transmission line for transmitting a first signal output from a carrier amplifier, and outputs the first signal after transmission by the first transmission line to a load; and a second output circuit has a second transmission line for transmitting a second signal output from a peak amplifier, and outputs the second signal after transmission by the second transmission line to the load, wherein the first transmission line comprises: a first T-type circuit having one end connected to the output side of the carrier amplifier and the other end connected to the load; and a first capacitor having one end connected to the other end of the first T-type circuit and the other end grounded; and the second transmission line comprises: a second T-type circuit having one end connected to the output side of the peak amplifier; and a second capacitor having one end connected to the other end of the second T-type circuit and the other end connected to the load. a third capacitor having one end connected to the other end of the second T-type circuit and the other end grounded.

2. A Doherty amplifier according to claim 1, characterized in that the equivalent electrical length of the second transmission line is -20 degrees, and the difference in phase between the signal to be amplified by the carrier amplifier and the signal to be amplified by the peak amplifier is 90 degrees +20 degrees.

3. The Doherty amplifier according to claim 1, wherein the capacitance value of the first capacitor, the capacitance value of the second capacitor, and the capacitance value of the third capacitor are the same.

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