Multilayer ceramic capacitor and method for producing multilayer ceramic capacitor

Abstract

The present invention inhibits the intrusion of moisture or hydrogen into a capacitance generation region even if the entirety of a dielectric layer has not been densified. The main body of this multilayer ceramic capacitor is divided into: a capacitance generation region in which a plurality of first internal electrodes and a plurality of second internal electrodes face each other in a first direction; a first outer peripheral region surrounding the capacitance generation region; and a second outer peripheral region surrounding the first outer peripheral region. A first porosity indicating the porosity of the first outer peripheral region is lower than a second porosity indicating the porosity of the second outer peripheral region. The first outer peripheral region has a cover part adjacent to the capacitance generation region in the first direction and a margin part adjacent to the capacitance generation region in a second direction orthogonal to the first direction. A second thickness indicating the thickness of the margin part in the second direction is greater than a first thickness indicating the thickness of the cover part in the first direction.

Description

Multilayer ceramic capacitor and method of manufacturing the same

[0001] The disclosure of this specification primarily relates to multilayer ceramic capacitors and methods for manufacturing multilayer ceramic capacitors.

[0002] Multilayer ceramic capacitors are installed in various electronic devices. Multilayer ceramic capacitors have multiple internal electrode layers stacked with dielectric layers interposed between them. When a multilayer ceramic capacitor is in use, a voltage is applied to the internal electrode layers, generating capacitance in the capacitance generating region where the internal electrode layers face each other.

[0003] In recent years, dielectric layers have been made thinner to improve the capacitance of multilayer ceramic capacitors. By making the dielectric layers thinner, the spacing between internal electrode layers is reduced and the number of layers can be increased for a given external dimension, thereby efficiently improving the capacitance of the multilayer ceramic capacitor. Furthermore, the thickness of the internal electrode layers has also been reduced. For example, as described in JP 2021-158132 A (Patent Document 1), a sputtering method can be used to form thin internal electrode layers that have high adhesion to the dielectric layers.

[0004] In multilayer ceramic capacitors, moisture from the external atmosphere easily penetrates into the capacitance generating region through voids in the dielectric layers. Furthermore, when a multilayer ceramic capacitor is in use, hydrogen is generated from the external electrodes, and this hydrogen easily penetrates into the capacitance generating region. Therefore, it is necessary to increase the density of the dielectric layers to ensure moisture resistance and prevent hydrogen penetration.

[0005] Multilayer ceramic capacitors are fabricated by firing a green laminate, which is a stack of dielectric green sheets, which are precursors of the dielectric layers, and internal electrode patterns, which are precursors of the internal electrode layers. Dense dielectric layers are obtained by firing the green laminate at high temperatures.

[0006] Japanese Patent Application Laid-Open No. 2021-158132

[0007] When a laminate including an internal electrode pattern is fired, metal elements such as Ni contained in the internal electrode pattern are sintered. Therefore, the internal electrode layer contains a sintered body of the metal element. High firing temperatures promote the sintering of the metal element, causing the sintered body of the metal element to take on a spherical shape. Therefore, high firing temperatures tend to cause non-conductive voids to form between the spherical sintered bodies of the metal element in the internal electrode layer. Thus, firing at high temperatures reduces the continuity of the internal electrode layer. A reduction in the continuity of the internal electrode layer is undesirable because it leads to a reduction in capacitance. Thinner internal electrode patterns are more likely to reduce the continuity of the internal electrode layer.

[0008] Firing the green laminate at a low firing temperature can suppress a decrease in the continuity ratio of the internal electrode layers, but firing the green laminate at a low temperature makes it difficult to sufficiently densify the dielectric layers.

[0009] The object of the invention disclosed in this specification is to solve or alleviate at least some of the above-mentioned problems. A more specific object of the invention disclosed in this specification is to provide a multilayer ceramic capacitor that can suppress the intrusion of moisture and hydrogen into the capacitance generation region even if the entire dielectric layer is not densified.

[0010] Objects of the present invention other than those mentioned above will become clear throughout the entire specification. The inventions disclosed in this specification may solve problems that are understood from other than those described in the "Problems to be Solved by the Invention" section. When the present specification describes the effects of an embodiment, the problems of the invention corresponding to that embodiment can be understood from those effects. The various inventions disclosed in this specification may be collectively referred to as "the present invention."

[0011] A multilayer ceramic capacitor according to one aspect of the present invention includes a main body, a first external electrode provided on the main body, and a second external electrode provided on the main body. The main body has a plurality of dielectric layers and a plurality of internal electrode layers stacked in a first direction via at least one of the plurality of dielectric layers. The first external electrode is provided on the main body so as to be electrically connected to each of a plurality of first internal electrode layers among the plurality of internal electrode layers. The second external electrode is provided on the main body so as to be electrically connected to each of a plurality of second internal electrode layers among the plurality of internal electrode layers. In one aspect of the present invention, the main body is partitioned into a capacitance generating region in which the plurality of first internal electrodes and the plurality of second internal electrodes face each other in the first direction, a first outer peripheral region surrounding the capacitance generating region, and a second outer peripheral region surrounding the first outer peripheral region. In one aspect, a first porosity indicating the porosity of the first outer peripheral region is smaller than a second porosity indicating the porosity of the second outer peripheral region. In one aspect, the first outer peripheral region has a cover portion adjacent to the capacitance generating region in a first direction and a margin portion adjacent to the capacitance generating region in a second direction perpendicular to the first direction, and a second thickness indicating the thickness of the margin portion in the second direction is greater than a first thickness indicating the thickness of the cover portion in the first direction.

[0012] According to one aspect of the invention disclosed in this specification, the first outer peripheral region, which is a part of the dielectric layer, can suppress the intrusion of moisture and hydrogen into the capacitance generating region.

[0013] 1 is a perspective view schematically showing a multilayer ceramic capacitor according to an embodiment of the present invention; FIG. 2 is a cross-sectional view schematically showing a cross section of the multilayer ceramic capacitor of FIG. 1 cut along an end face; FIG. 3 is a schematic view showing a first outer peripheral region extracted from the cross section of the multilayer ceramic capacitor shown in FIG. 2; FIG. 4 is an enlarged cross-sectional view schematically showing a partial enlargement of the cross section of the multilayer ceramic capacitor shown in FIG. 2; FIG. 5 is a cross-sectional view schematically showing a cross section of the multilayer ceramic capacitor 101 according to another embodiment of the present invention cut along an end face; FIG. 6 is a schematic view showing a first outer peripheral region extracted from the cross section of the multilayer ceramic capacitor 101 shown in FIG. 5; FIG. 7 is a cross-sectional view schematically showing a cross section of the multilayer ceramic capacitor 201 according to yet another embodiment of the present invention cut along an end face; FIG. 8 is a schematic view showing a first outer peripheral region extracted from the cross section of the multilayer ceramic capacitor 201 shown in FIG. 7; FIG. 9 is a cross-sectional view schematically showing a cross section of the multilayer ceramic capacitor 301 according to yet another embodiment of the present invention cut along an end face; FIG. 1 is a flow diagram showing a method for manufacturing a multilayer ceramic capacitor 1 according to one embodiment of the present invention; FIG. 2 is a schematic diagram showing sheet units U1 to U3 produced in a process for manufacturing a multilayer ceramic capacitor 1 according to one embodiment of the present invention; FIG. 3 is a schematic diagram showing a part of a manufacturing process for a multilayer ceramic capacitor 1 according to one embodiment of the present invention; FIG. 4 is a schematic diagram showing a laminated sheet unit U10 produced in a process for manufacturing a multilayer ceramic capacitor 1 according to one embodiment of the present invention; FIG. 5 is a schematic diagram showing a chip laminate 90 produced in a process for manufacturing a multilayer ceramic capacitor 1 according to one embodiment of the present invention; and FIG. 6 is a schematic diagram showing a chip laminate 90 being fired in a process for manufacturing a multilayer ceramic capacitor 1 according to one embodiment of the present invention.

[0014] Various embodiments of the present invention will be described below with appropriate reference to the drawings. Components common to multiple drawings are designated by the same or similar reference numerals. Please note that the drawings are not necessarily drawn to scale for the sake of convenience. The embodiments described below do not necessarily limit the invention according to the claims. Elements described in the following embodiments are not necessarily essential to the solution of the invention.

[0015] For ease of explanation, each drawing may include an L-axis, a W-axis, and a T-axis that are perpendicular to each other. In this specification, the dimensions, arrangement, shape, and other characteristics of each component of the multilayer ceramic capacitor 1 may be described based on the L-axis, W-axis, and T-axis.

[0016] 1. Description of Multilayer Ceramic Capacitor 1 (First Embodiment) The basic structure of a multilayer ceramic capacitor 1 according to one embodiment of the present invention will be described mainly with reference to Figures 1 and 2. Figure 1 is a perspective view of the multilayer ceramic capacitor 1 according to one embodiment. Figure 2 is a cross-sectional view schematically showing the cross section of the multilayer ceramic capacitor 1 taken along line II.

[0017] 1-1 Basic Structure of Multilayer Ceramic Capacitor 1 The multilayer ceramic capacitor 1 includes a body 10, and a first external electrode 31 and a second external electrode 32 provided on the body 10. The first external electrode 31 is disposed spaced apart from the second external electrode 32.

[0018] The main body 10 includes a plurality of dielectric layers 11, a plurality of first internal electrode layers 21, and a plurality of second internal electrode layers 22. In this specification, when it is not necessary to distinguish between the first internal electrode layers 21 and the second internal electrode layers 22, the first internal electrode layers 21 and the second internal electrode layers 22 may be collectively referred to as "internal electrode layers." The dielectric layer 11 is disposed between adjacent internal electrode layers. For example, the first internal electrode layer 21 is disposed on the upper surface of the dielectric layer 11, and the second internal electrode layer 22 is disposed on the lower surface of the dielectric layer 11.

[0019] In the main body 10, the dielectric layers 11, the first internal electrode layers 21, and the second internal electrode layers 22 are stacked along a stacking direction (for example, the T-axis direction). At least one dielectric layer 11 is disposed between adjacent ones of the first internal electrode layers 21 and the second internal electrode layers 22. The stacking direction may be along the T-axis as shown in the figure. The stacking direction may also be along the L-axis or W-axis.

[0020] The main body 10 has an upper surface 10a, a lower surface 10b, a first end surface 10c, a second end surface 10d, a first side surface 10e, and a second side surface 10f. The outer surface of the main body 10 is defined by the upper surface 10a, the lower surface 10b, the first end surface 10c, the second end surface 10d, the first side surface 10e, and the second side surface 10f.

[0021] The top surface 10a and the bottom surface 10b respectively form the surfaces at both ends of the main body 10 in the height direction (T-axis direction). The top surface 10a and the bottom surface 10b face each other in the T-axis direction. The first end surface 10c and the second end surface 10d respectively form the surfaces at both ends of the main body 10 in the length direction (L-axis direction). The first end surface 10c and the second end surface 10d face each other in the L-axis direction. The first side surface 10e and the second side surface 10f respectively form the surfaces at both ends of the main body 10 in the width direction (W-axis direction). The first side surface 10e and the second side surface 10f face each other in the W-axis direction. The top surface 10a and the bottom surface 10b are spaced apart by the height dimension of the main body 10, the first end surface 10c and the second end surface 10d are spaced apart by the length dimension of the main body 10, and the first side surface 10e and the second side surface 10f are spaced apart by the width dimension of the main body 10.

[0022] One end of the first internal electrode layer 21 is extended toward the outside of the main body 10. The first internal electrode layer 21 is connected to a first external electrode 31 provided on the surface of the main body 10. One end of the second internal electrode layer 22 is extended toward the outside of the main body 10. The second internal electrode layer 22 is connected to a second external electrode 32 provided on the surface of the main body 10. In the embodiment shown in FIG. 2 , the first internal electrode layer 21 is extended toward the outside of the main body 10 from the first end face 10c. The first internal electrode layer 21 is connected to the first external electrode 31 at one end of the main body 10 in the L-axis direction. The second internal electrode layer 22 is extended toward the outside of the main body 10 from the second end face 10d. The second internal electrode layer 22 is connected to the second external electrode 32 at the other end of the main body 10 in the L-axis direction. 2, the first internal electrode layer 21 and the second internal electrode layer 22 are respectively drawn to the opposing first end face 10c and second end face 10d, but the first internal electrode layer 21 and the second internal electrode layer 22 may be drawn from various surfaces of the main body 10 depending on the arrangement and shape of the first external electrode 31 and the second external electrode 32. For example, if the first external electrode 31 and the second external electrode 32 are both arranged on the lower surface 10b, then both the first external electrode 31 and the second external electrode 32 are drawn from the lower surface. The first external electrode 31 and the second external electrode 32 may be provided on any surface of the main body 10 as long as they are spaced apart from each other.

[0023] In one embodiment, the multilayer ceramic capacitor 1 may be configured to have a rectangular parallelepiped shape. In this specification, the terms "rectangular parallelepiped" or "rectangular parallelepiped shape" do not necessarily mean "rectangular parallelepiped" in the strict mathematical sense. As will be described later, the corners and / or sides of the main body 10 may be curved. The dimensions and shape of the main body 10 are not limited to those explicitly stated in this specification.

[0024] In one embodiment, the dimension (length dimension) of the multilayer ceramic capacitor 1 in the L-axis direction is in the range of 0.1 mm to 3.5 mm, the dimension (width dimension) in the W-axis direction is in the range of 0.1 mm to 2.5 mm, and the dimension (height dimension) in the T-axis direction is in the range of 0.1 mm to 3.0 mm. In one embodiment, the length dimension of the multilayer ceramic capacitor 1 may be greater than the width dimension. In one embodiment, the height dimension of the multilayer ceramic capacitor 1 may be greater than the width dimension. In one embodiment, the width dimension of the multilayer ceramic capacitor 1 may be greater than the length dimension.

[0025] The multilayer ceramic capacitor 1 can be mounted on an electronic circuit board. An electronic circuit board on which the multilayer ceramic capacitor 1 is mounted is sometimes called a circuit module. Various electronic components other than the multilayer ceramic capacitor 1 can also be mounted on the circuit module. This circuit module can be mounted in various electronic devices. Electronic devices in which the circuit module can be mounted include smartphones, tablets, game consoles, automotive electrical components, servers, and various other electronic devices.

[0026] The multilayer ceramic capacitor 1 is mounted on the surface of the electronic circuit board so that the lower surface 10b of the body 10 faces the surface of the electronic circuit board. For this reason, the lower surface 10b of the body 10 is sometimes referred to as the mounting surface (mounting surface 10b). The multilayer ceramic capacitor 1 is joined by solder to lands provided on the surface of the electronic circuit board 2. The lands are provided on the surface of the electronic circuit board at positions corresponding to the first external electrode 31 and the second external electrode 32.

[0027] 1-2 Division of the Main Body 10 The main body 10 is divided into a plurality of regions based on the stacking direction. Specifically, the main body 10 is divided into a capacitance generating region Rc in which the first internal electrode layers 21 and the second internal electrode layers 22 are arranged so as to face each other via the dielectric layer 11, a cover region adjacent to the capacitance generating region Rc in the stacking direction, and a margin region adjacent to the capacitance generating region Rc in a direction perpendicular to the stacking direction. The cover region is arranged to sandwich the capacitance generating region Rc in the stacking direction. The margin region is arranged to surround the capacitance generating region Rc. In the embodiment shown in FIG. 2, the first internal electrode layers 21 and the second internal electrode layers 22 are stacked along the T-axis, so the T-axis direction is the stacking direction. Therefore, in the embodiment shown in FIG. 2 , the main body 10 is partitioned, in a cross section taken along a WT plane (a plane parallel to the first end face 10 c or the second end face 10 d), into at least a capacitance generating region Rc, an upper cover region C1 adjacent to the capacitance generating region Rc from one side of the stacking direction (T-axis direction), a lower cover region C2 adjacent to the capacitance generating region Rc from the other side of the stacking direction (T-axis direction), and a margin region adjacent to the capacitance generating region Rc in a direction perpendicular to the stacking direction. The margin region includes a first side margin region Sm1 and a second side margin region Sm2 adjacent to the capacitance generating region Rc from the W-axis direction. A portion of the margin region is adjacent to the capacitance generating region Rc from the L-axis direction. The margin region surrounds the capacitance generating region Rc in a direction perpendicular to the T-axis direction. The margin region may surround not only the capacitance generating region Rc but also the upper cover region C1 and the lower cover region C2 in a direction perpendicular to the T-axis direction. The stacking direction corresponds to the "first direction" in the claims, and the direction perpendicular to the stacking direction corresponds to the "second direction" in the claims. In the embodiment shown in Figure 2, the T-axis direction corresponds to the "first direction" in the claims, and the direction along the WL plane (for example, the W-axis direction or the L-axis direction) corresponds to the "second direction" in the claims.

[0028] In the capacitance generating region Rc, the first internal electrode layer 21 and the second internal electrode layer 22 are arranged to face each other in the stacking direction via the dielectric layer 11. When a voltage is applied between the first external electrode 31 and the second external electrode 32, a capacitance is generated between the first internal electrode layer 21 and the second internal electrode layer 22. In other words, the capacitance generating region Rc is a region where the first internal electrode layer 21 and the second internal electrode layer 22 face each other in the stacking direction, and is a region where a capacitance is generated.

[0029] The first side margin region Sm1 and the second side margin region Sm2 are regions in which neither the first internal electrode layer 21 nor the second internal electrode layer 22 exists when viewed from the stacking direction. In the illustrated embodiment, the first side margin region Sm1 is located between the capacitance generating region Rc and the first side surface 10e of the main body 10. The second side margin region Sm2 is located between the capacitance generating region Rc and the second side surface 10f of the main body 10. In this specification, when there is no need to distinguish between the first side margin region Sm1 and the second side margin region Sm2, they may be collectively referred to as the "side margin region Sm."

[0030] The upper cover region C1 is located between the capacitance generating region Rc and the upper surface 10a of the main body 10. The upper cover region C1 is arranged above the capacitance generating region Rc in the stacking direction. The lower cover region C2 is located between the capacitance generating region Rc and the lower surface 10b of the main body 10. The upper cover region C1 contacts the capacitance generating region Rc from above. The lower cover region C2 contacts the capacitance generating region Rc from below. The lower cover region C2 is arranged below the capacitance generating region Rc in the stacking direction. In a cut surface obtained by cutting the main body 10 along the first end surface 10c or the second end surface 10d, neither the first internal electrode layer 21 nor the second internal electrode layer 22 is arranged in the upper cover region C1, and neither the first internal electrode layer 21 nor the second internal electrode layer 22 is arranged in the lower cover region C2.

[0031] Although not shown, in a cross section of the main body 10 taken along a plane parallel to the first side surface 10e or the second side surface 10f, the main body 10 is divided into a capacitance generating region Rc, an upper cover region C1, a lower cover region C2, and an end margin region. The end margin region refers to a region including the lead-out portions of the first internal electrode layers 21 between the capacitance generating region Rc and the surface (first end face 10c) on which the external electrodes of the main body 10 are formed, and a region including the lead-out portions of the second internal electrode layers 22 between the capacitance generating region Rc and the surface (second end face 10d) on which the external electrodes of the main body 10 are formed. The first internal electrode layers 21 extend through a first end margin region of the end margin region to the surface (first end face 10c) on which the external electrodes of the main body 10 are formed. The second internal electrode layers 22 extend through a second end margin region of the end margin region to the surface (second end face 10d) on which the external electrodes of the main body 10 are formed. In this specification, when there is no need to distinguish between the first end margin region and the second end margin region, they may be collectively referred to as "end margin region."

[0032] As described above, in a cross section taken along a cutting plane parallel to the first end face 10c or the second end face 10d, the region of the main body 10 other than the capacitance generating region Rc can be divided into a first side margin region Sm1, a second side margin region Sm2, an upper cover region C1, and a lower cover region C2. The main body 10 can also be divided from a different perspective. That is, in one aspect of the present invention, a portion of the region of the main body 10 other than the capacitance generating region Rc is configured to have relatively fewer voids (i.e., be denser) than other portions, making it possible to divide the main body 10 into a region with relatively more voids and a region with relatively fewer voids. In the embodiment shown in FIG. 2 , a region with relatively fewer voids is provided near the capacitance generating region Rc outside the capacitance generating region Rc, and a region with relatively more voids is provided further outside the region with fewer voids. 2 is divided into a capacitance generating region Rc, a first outer peripheral region R1 that surrounds the capacitance generating region Rc and has few voids, and a second outer peripheral region R2 that surrounds the first outer peripheral region R1. The first porosity indicating the porosity of the first outer peripheral region R1 is smaller than the second porosity indicating the porosity of the second outer peripheral region R2. Therefore, the first outer peripheral region R1 is denser than the second outer peripheral region R2.

[0033] In this specification, the ratio of the area of ​​voids to a predetermined region of the cross section of the main body 10 is referred to as the areal porosity, or simply the porosity. The area of ​​voids in the cross section of the main body 10 can be calculated, for example, as follows. First, the main body 10 is cut along its stacking direction (T-axis direction) to expose the cross section, and the cross section is photographed using a scanning electron microscope (SEM) at a predetermined magnification (e.g., 10,000x) to obtain an SEM image with a portion of the cross section of the main body 10 as the observation field. Next, the SEM image obtained by this photograph is subjected to image processing such as binarization to distinguish between voids and non-void regions, and the area of ​​the regions classified as voids is calculated. Multi-level processing may be performed instead of binarization. The areal porosity is then calculated by summing the areas of voids within the observation field calculated in this way and dividing the total area of ​​voids in this observation field by the area of ​​the observation field. The areal porosity expressed as a percentage is expressed by the following formula. Area porosity (%) = (total area of ​​voids within the observation field / total area of ​​the observation field) x 100

[0034] When the first internal electrode layer 21 and the second internal electrode layer 22 are mainly composed of Ni, the first outer peripheral region R1 contains Ni at a higher concentration than the second outer peripheral region R2. When the dielectric green sheet is fired to form the dielectric layer 11, the Ni contained in the dielectric green sheet promotes densification of the dielectric layer 11. Therefore, the first outer peripheral region R1, which contains Ni at a higher concentration than the second outer peripheral region R2, is densified more than the second outer peripheral region R2 during the manufacturing process.

[0035] The Ni concentration in the first outer peripheral region R1 is preferably 10 at% or less. If the Ni concentration in the first outer peripheral region R1 is too high, the dielectric layer 11 may be over-sintered in the first outer peripheral region. An over-sintered dielectric layer 11 leads to a decrease in insulation reliability. For this reason, the Ni concentration in the first outer peripheral region is preferably 10 at% or less.

[0036] In one embodiment, the second outer peripheral region R2 does not contain Ni. Therefore, densification due to Ni does not occur in the second outer peripheral region R2 during firing. The second outer peripheral region R2 may be defined as a region that does not contain Ni.

[0037] The concentration of Ni in the main body 10 can be quantified by known analytical methods, such as TEM-EDS, STEM-EDS, 3DAP (3 Dimensional Atom Probe) analysis, and secondary ion mass spectrometry (SIMS).

[0038] 1-3 First Outer Region R1 The first outer region R1 will be further described with reference to Fig. 3. As shown in Fig. 3, the first outer region R1 has cover portions R1h adjacent to the capacitance generating region Rc on both sides in the T-axis direction and margin portions R1v adjacent to the capacitance generating region Rc on both sides in the W-axis direction.

[0039] The first outer peripheral region R1 and the second outer peripheral region R2, which are sections of the main body 10 in terms of porosity, overlap with the upper cover region C1, the lower cover region C2, the first side margin region Sm1, and / or the second side margin region Sm2, which are sections of the main body 10 in terms of their arrangement relative to the capacitance generating region Rc. In the example shown in FIGS. 2 and 3 , the cover portion R1h of the first outer peripheral region R1, which contacts the capacitance generating region Rc from the upper side of the paper (the positive side in the T-axis direction), is included in the upper cover region C1. Furthermore, the cover portion R1h of the first outer peripheral region R1, which contacts the capacitance generating region Rc from the lower side of the paper (the negative side in the T-axis direction), is included in the lower cover region C2. Furthermore, the margin portion R1v of the first outer peripheral region R1, which contacts the capacitance generating region Rc from the left side of the paper (the negative side in the W-axis direction), is included in the first side margin region Sm1. The margin portion R1v of the first outer peripheral region R1, which contacts the capacitance generating region Rc from the right side of the drawing (the positive side in the W-axis direction), is included in the second side margin region Sm2.

[0040] As shown in FIG. 3 , the first outer peripheral region R1 is configured so that the thickness dimension W11 of the margin portion R1v in the W-axis direction is larger than the thickness dimension T11 of the cover portion R1h in the T-axis direction. If the thickness dimension of the margin portion R1v in the W-axis direction is not uniform, the dimension of the margin portion R1v along the W-axis direction can be measured at five different points in the T-axis direction, and the average of the dimensions at these five points can be used as the thickness dimension W11 of the margin portion R1v. If the thickness dimension of the cover portion R1h in the T-axis direction is not uniform, the dimension of the cover portion R1h along the T-axis direction can be measured at five different points in the W-axis direction, and the average of the dimensions at these five points can be used as the thickness dimension T11 of the cover portion R1h.

[0041] In the multilayer ceramic capacitor 1, the capacitance generation region Rc is surrounded by the dense first outer peripheral region R1, which can prevent hydrogen contained in the first external electrode 31 and the second external electrode 32 provided on the surface of the main body 10 from penetrating into the capacitance generation region Rc. The first outer peripheral region R1 also prevents moisture from penetrating into the main body 10 from the outside. Because the first internal electrode layers 21 and the second internal electrode layers 22 are provided at the upper and lower ends (both ends in the T-axis direction) of the capacitance generation region Rc, hydrogen and moisture are more likely to penetrate into the capacitance generation region Rc from the W-axis direction or the L-axis direction rather than the T-axis direction. The thickness dimension W11 of the first outer peripheral region R1 in the W-axis direction is greater than the thickness dimension T11 in the T-axis direction, which can more reliably prevent hydrogen and moisture from penetrating into the capacitance generation region Rc. Although not shown, in a cross section of the main body 10 taken along a cut plane parallel to the first side surface 10e or the second side surface 10f, the first outer peripheral region R1 is provided to surround the capacitance generating region Rc, and the thickness dimension of the first outer peripheral region R1 in the L-axis direction in the cross section is greater than the thickness dimension T11 of the first outer peripheral region R1 in the T-axis direction. The thickness dimension of the first outer peripheral region R1 in the L-axis direction may be the same as the thickness dimension W11 of the first outer peripheral region R1 in the W-axis direction.

[0042] 1-4 Dielectric Layer 11 The dielectric layer 11 may include a ceramic material having a high dielectric constant. The dielectric layer 11 may include, for example, an oxide represented by the chemical formula ABO3 as a main component. In the chemical formula ABO3, "A" is, for example, at least one element selected from the group consisting of Ba (barium), Sr (strontium), Ca (calcium), and Mg (magnesium). In the chemical formula ABO3, "B" is, for example, at least one element selected from the group consisting of Ti (titanium), Zr (zirconium), and Hf (hafnium). Examples of oxides included as a main component in the dielectric layer 11 include BaTiO3 (barium titanate), CaZrO3 (calcium zirconate), CaTiO3 (calcium titanate), SrTiO3 (strontium titanate), and MgTiO3 (magnesium titanate).

[0043] The dielectric layer 11 may contain elements derived from known sintering aids in addition to the oxides of the main components.

[0044] The dielectric layer 11 may contain an additive element. In one embodiment, the additive element contained in the dielectric layer 11 is at least one element selected from the group consisting of Ni (nickel), Mo (molybdenum), Nb (niobium), Ta (tantalum), W (tungsten), V (vanadium), and Cr (chromium). The dielectric layer 11 may contain two or more types of the additive elements.

[0045] Dielectric layer 11 may contain an oxide of a rare earth element in addition to the oxide of the main component. The oxide of the rare earth element contained in dielectric layer 11 may be an oxide of at least one rare earth element selected from the group consisting of Y (yttrium), Sm (samarium), Eu (europium), Gd (gadolinium), Tb (terbium), Dy (dysprosium), Ho (holmium), Er (erbium), Tm (thulium), and Yb (ytterbium). Dielectric layer 11 may contain two or more types of oxides of rare earth elements.

[0046] The dielectric layer 11 may further contain another type of oxide. For example, the dielectric layer 11 may contain an oxide of at least one element selected from the group consisting of Co (cobalt), Li (lithium), B (boron), Na (sodium), K (potassium), and Si (silicon). The dielectric layer 11 may contain two or more types of oxides of these elements.

[0047] The dielectric layer 11 may contain a glass containing at least one element selected from the group consisting of Co, Ni, Li, B, Na, K, and Si.

[0048] In one embodiment, the film thickness (dimension in the T-axis direction) of the dielectric layer 11 is 0.1 to 5 μm. When the dielectric layer 11 is formed by sputtering, the lower limit of the film thickness of the dielectric layer 11 may be 0.1 μm, and the upper limit may be 1 μm. When the dielectric layer 11 is formed by a printing method, the lower limit of the film thickness of the dielectric layer 11 may be 0.4 μm, and the upper limit may be 5 μm.

[0049] 2 and 3, for the sake of simplicity, five first internal electrode layers 21 and five second internal electrode layers 22 are shown. The multilayer ceramic capacitor 1 may include more than five first internal electrode layers 21 and second internal electrode layers 22, and may include, for example, 300 to 1000 first internal electrode layers 21 and second internal electrode layers 22. In other words, the number of stacked layers in the multilayer ceramic capacitor 1 may be 300 to 1000.

[0050] The first internal electrode layer 21 and the second internal electrode layer 22 can each be formed by a vacuum film formation method such as sputtering. In one aspect, the film thickness (dimension in the T-axis direction) of the first internal electrode layer 21 and the film thickness (dimension in the T-axis direction) of the second internal electrode layer 22 are both 0.1 μm or more and 2 μm or less. Preferably, the first internal electrode layer 21 and the second internal electrode layer 22 are each 0.25 μm or less. Since it is difficult to form the first internal electrode layer 21 and the second internal electrode layer 22 with a film thickness of 0.25 μm or less, the first internal electrode layer 21 and the second internal electrode layer 22 with a film thickness of 0.25 μm or less are formed by a vacuum film formation method such as sputtering.

[0051] In one embodiment, the first internal electrode layers 21 contain a base metal such as Ni (nickel) or Sn (tin), or an alloy of these base metals, as a main component. Based on the total mass of the first internal electrode layers 21, a component contained in the first internal electrode layers 21 at 50 wt % or more can be the main component of the first internal electrode layers 21.

[0052] 4, the first internal electrode layer 21 includes a plurality of electrode regions 21a containing Ni and non-electrode regions 21b present between the electrode regions 21a. The non-electrode regions 21b are regions with higher insulating properties than the electrode regions 21a. The non-electrode regions 21b are occupied by, for example, oxides of elements contained in the first internal electrode layers 21, parts of the dielectric layers 11, and / or voids. The non-electrode regions 21b can be generated by vaporization of a binder resin contained in the precursor of the first internal electrode layers 21 during degreasing treatment of the precursor of the first internal electrode layers 21, or by oxidation of elements contained in the precursor of the first internal electrode layers 21 during firing.

[0053] The continuity ratio of each of the first internal electrode layer 21 and the second internal electrode layer 22 is preferably 75% or more. The continuity ratio of the first internal electrode layer 21 can be calculated as follows. First, the multilayer ceramic capacitor 1 is polished so that the WT surface becomes the observation surface. Next, a region A within the capacitance generating region of this observation surface is observed with a SEM (scanning electron microscope), and the Ni distribution region is examined by EDS mapping. The region where Ni is distributed is identified as the electrode region 21a. The length of this electrode region 21a is then measured, and the side lengths W1, W2, ..., Wn are summed. The value obtained by dividing the sum of the lengths of the electrode regions 21a in this region A by the length W0 of the measurement region (i.e., (W1 + W2 + ... Wn) / W0) can be defined as the continuity ratio of one first internal electrode layer 21. The main body 10 includes multiple first internal electrode layers 21, and the continuity ratio may vary depending on which of the multiple first internal electrode layers 21 is focused on. Therefore, ten different first internal electrode layers 21 are selected, and the average of the continuity rates calculated for each of the selected first internal electrode layers 21 can be defined as the continuity rate of the first internal electrode layers 21 in the multilayer ceramic capacitor 1. The continuity rate of the second internal electrode layers 22 can also be defined in the same way as the continuity rate of the first internal electrode layers 21.

[0054] In this specification, the description of the first internal electrode layer 21 also applies to the second internal electrode layer 22 unless a contradiction occurs.

[0055] 1-6 First External Electrode 31 and Second External Electrode 32 In one aspect, the first external electrode 31 and the second external electrode 32 are formed by applying a conductive paste to the main body 10 and heating the conductive paste. The conductive paste may include at least one material selected from the group consisting of Ag (silver), Pd (palladium), Au (gold), Pt (platinum), Ni (nickel), Sn (tin), Cu (copper), W (tungsten), Ti (titanium), and alloys thereof.

[0056] 1-7 Summary In the multilayer ceramic capacitor 1, the capacitance generation region Rc is surrounded by the dense first outer peripheral region R1, which prevents hydrogen and moisture from penetrating into the capacitance generation region Rc. This prevents deterioration of the insulation reliability of the capacitance generation region Rc due to hydrogen and moisture. The first outer peripheral region R1 is formed so that the thickness dimension W11 in the W-axis direction is greater than the thickness dimension T11 in the T-axis direction. This more reliably prevents hydrogen and moisture from penetrating into the capacitance generation region Rc in the direction perpendicular to the stacking direction (the direction along the WL plane).

[0057] The first outer peripheral region R1 is denser than the second outer peripheral region R2, and therefore, by providing the first outer peripheral region R1, the mechanical strength of the multilayer ceramic capacitor 1 can be improved.

[0058] 2. Multilayer Ceramic Capacitor 101 (Second Embodiment) Next, a multilayer ceramic capacitor 101 according to another embodiment of the present invention will be described with reference to Fig. 5 and Fig. 6. Fig. 5 is a cross-sectional view showing a cross section of the multilayer ceramic capacitor 101 taken along a plane parallel to the WT plane (i.e., a plane parallel to the first end face 10c or the second end face 10d), and Fig. 6 is a schematic view showing the first outer peripheral region extracted from the cross section of the multilayer ceramic capacitor 101 shown in Fig. 5. The multilayer ceramic capacitor 101 differs from the multilayer ceramic capacitor 1 in that it includes a first outer peripheral region R11 instead of the first outer peripheral region R1.

[0059] 5, the body 10 of the multilayer ceramic capacitor 101 is partitioned into a capacitance generating region Rc, a first outer peripheral region R11 surrounding the capacitance generating region Rc, and a second outer peripheral region R2 surrounding the first outer peripheral region R11. The first porosity indicating the porosity of the first outer peripheral region R11 is smaller than the second porosity indicating the porosity of the second outer peripheral region R2. Therefore, the first outer peripheral region R11 is denser than the second outer peripheral region R2.

[0060] The first outer peripheral region R11 has a thick portion RP1 at one end in the T-axis direction and a thick portion RP2 at the other end in the T-axis direction. The thickness W21 of the thick portion RP1 in the W-axis direction is greater than the thickness W11 of the margin portion R1v in the W-axis direction. If the thickness dimension of the thick portion RP1 in the W-axis direction is not uniform, the dimension of the thick portion RP1 along the W-axis direction can be measured at five different points in the T-axis direction, and the average of the dimensions at these five points can be used as the thickness dimension W21 of the thick portion RP1. The first outer peripheral region R11 may have only one of the thick portion RP1 and the thick portion RP2.

[0061] The thick portion RP1 and the thick portion RP2 may be disposed near the center of the first outer peripheral region R11 in the T-axis direction.

[0062] In the multilayer ceramic capacitor 101, the margin portion R1v of the first outer peripheral region R11 has thick portions RP1 and RP2 at positions corresponding to both ends of the capacitance generating region Rc in the T-axis direction, so that the stress acting on the first outer peripheral region R11 is dispersed, thereby suppressing breakage of the main body 10.

[0063] In the multilayer ceramic capacitor 101, the dense thick portions RP1 and RP2 are provided at both ends of the capacitance generating region Rc in the T-axis direction, so that the corners of the capacitance generating region Rc, where stress tends to concentrate, can be reinforced by the thick portions RP1 and RP2, thereby suppressing the occurrence of cracks near the corners of the capacitance generating region Rc.

[0064] In the multilayer ceramic capacitor 101, the thick portion RP1 is provided at a position corresponding to one end (upper end) of the capacitance generating region Rc in the T-axis direction, and this thick portion RP1 can prevent hydrogen generated from a portion of the first external electrode 31 that is in contact with the upper surface 10 a of the main body 10 and a portion of the second external electrode 32 that is in contact with the upper surface 10 a of the main body 10 from penetrating into the capacitance generating region Rc. In addition, the thick portion RP2 is provided at a position corresponding to the other end (lower end) of the capacitance generating region Rc in the T-axis direction, and this thick portion RP2 can prevent hydrogen generated from a portion of the first external electrode 31 that is in contact with the lower surface 10 b of the main body 10 and a portion of the second external electrode 32 that is in contact with the lower surface 10 b of the main body 10 from penetrating into the capacitance generating region Rc.

[0065] 3. Multilayer ceramic capacitor 201 (third embodiment) Next, a multilayer ceramic capacitor 201 according to yet another embodiment of the present invention will be described with reference to Fig. 7 and Fig. 8. Fig. 7 is a cross-sectional view showing a cross section of the multilayer ceramic capacitor 201 taken along a plane parallel to the WT plane, and Fig. 8 is a schematic view showing the first outer periphery region extracted from the cross section of the multilayer ceramic capacitor 201 shown in Fig. 7. The multilayer ceramic capacitor 201 differs from the multilayer ceramic capacitor 1 in that it includes a first outer periphery region R21 instead of the first outer periphery region R1.

[0066] 7 , the body 10 of the multilayer ceramic capacitor 201 is partitioned into a capacitance generating region Rc, a first outer peripheral region R21 surrounding the capacitance generating region Rc, and a second outer peripheral region R2 surrounding the first outer peripheral region R21. The first porosity indicating the porosity of the first outer peripheral region R21 is smaller than the second porosity indicating the porosity of the second outer peripheral region R2. Therefore, the first outer peripheral region R21 is denser than the second outer peripheral region R2.

[0067] The first outer peripheral region R21 has thick portions RP3 and RP4 near the center of the capacitance generating region Rc in the T-axis direction. Therefore, the margin portion R1v of the first outer peripheral region R21 protrudes in the W-axis direction near the center of the capacitance generating region in the T-axis direction. In the illustrated embodiment, the margin portion R1v of the first outer peripheral region R21 has two thick portions (thick portion RP3 and thick portion RP4) that differ from each other in thickness (dimension in the W-axis direction), but the margin portion R1v may have three or more thick portions that differ from each other in thickness.

[0068] In the multilayer ceramic capacitor 201, the margin portion R1v of the first outer peripheral region R21 is configured to gradually increase in thickness toward the center of the capacitance generating region Rc in the T-axis direction, thereby preventing stress from concentrating at a specific location in the margin portion R1v, thereby preventing cracks from occurring around the first outer peripheral region R21 when stress acts on the main body 10.

[0069] 4. Multilayer ceramic capacitor 301 (fourth embodiment) Next, a multilayer ceramic capacitor 301 according to yet another embodiment of the present invention will be described with reference to Fig. 9 and Fig. 10. Fig. 9 is a cross-sectional view showing a cross section of the multilayer ceramic capacitor 301 taken along a plane parallel to the WT plane, and Fig. 10 is a schematic view showing the first outer periphery region extracted from the cross section of the multilayer ceramic capacitor 301 shown in Fig. 9. The multilayer ceramic capacitor 301 differs from the multilayer ceramic capacitor 1 in that it includes a first outer periphery region R31 instead of the first outer periphery region R1.

[0070] 9 , the body 10 of the multilayer ceramic capacitor 301 is partitioned into a capacitance generating region Rc, a first outer peripheral region R31 surrounding the capacitance generating region Rc, and a second outer peripheral region R2 surrounding the first outer peripheral region R31. The first porosity indicating the porosity of the first outer peripheral region R21 is smaller than the second porosity indicating the porosity of the second outer peripheral region R2. Therefore, the first outer peripheral region R31 is denser than the second outer peripheral region R2.

[0071] The first outer peripheral region R31 has thick portions RP5 to RP10 at multiple positions in the T-axis direction of the capacitance generating region Rc. In the illustrated embodiment, six thick portions RP5 to RP10 are provided in the margin portion R1v of the first outer peripheral region R31, but the number of thick portions provided in the margin portion R1v is not limited to six. Seven or more thick portions, or five or fewer thick portions, may be provided in the margin portion R1v. The margin portion R1v may be provided with the same number of thick portions as the total number of first internal electrode layers 21 and second internal electrode layers 22. For example, if 300 layers each of the first internal electrode layers 21 and the second internal electrode layers 22 are stacked, 600 thick portions may be provided in the margin portion R1v.

[0072] In the multilayer ceramic capacitor 301, multiple thick portions (in the illustrated example, thick portions RP5 to RP10) are provided in the margin portion R1v of the first outer peripheral region R31 at multiple positions in the T-axis direction of the capacitance generating region Rc, so that the stress acting on the first outer peripheral region R31 can be dispersed, thereby suppressing breakage of the main body 10.

[0073] 5. Method for Manufacturing Multilayer Ceramic Capacitor Next, a method for manufacturing a multilayer ceramic capacitor 1 according to one embodiment of the present invention will be described with reference to Fig. 11 to Fig. 17. Fig. 11 is a flow diagram showing the flow of a method for manufacturing a multilayer ceramic capacitor according to one embodiment of the present invention, and Fig. 12 to Fig. 17 are schematic diagrams showing the manufacturing process of a multilayer ceramic capacitor.

[0074] (Step S01: Preparation of Dielectric Green Sheets) In step S01, a plurality of dielectric green sheets 50a are prepared. The dielectric green sheets 50a are unsintered dielectric green sheets whose main component is a dielectric ceramic, and serve as precursors for the dielectric layers 11. The dielectric green sheets 50a can be obtained, for example, as follows. First, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer are added to a dielectric powder and wet-mixed to obtain a slurry. Next, this slurry is applied to a substrate film by, for example, a die coater method or a doctor blade method. The slurry applied to the substrate film is then dried to obtain a dielectric green sheet. The dielectric powder, which is the raw material powder for the dielectric green sheets, is, for example, barium titanate (BaTiO3) powder. Barium titanate powder is synthesized by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate using a known method such as a solid-phase method, a sol-gel method, or a hydrothermal method. The thickness of the dielectric green sheet 50a can be adjusted as appropriate.

[0075] (Step S02: Setting Mask) Next, in step S02, in preparation for forming an internal electrode pattern that will be a precursor of the first internal electrode layer 21 and the second internal electrode layer 22 on the dielectric green sheet 50a prepared in step S01, a mask M1 is set on the dielectric green sheet 50a as shown in Fig. 13. It is assumed that an internal electrode pattern that will be a precursor of the first internal electrode layer 21 is formed on the dielectric green sheet 50a shown in Fig. 13. In this case, the green sheet 50a is partitioned into an electrode formation region 51 where the first internal electrode layer 21 is formed and an electrode non-formation region 52 where the first internal electrode layer 21 is not formed. Similarly, the dielectric green sheet 50a where the second internal electrode layer 22 is formed is partitioned into an electrode formation region where the second internal electrode layer 22 is formed and an electrode non-formation region where the second internal electrode layer 22 is not formed (illustration omitted).

[0076] The mask M1 has an opening pattern M1a formed therein, which exposes the electrode formation region 51 when the mask M1 is placed on the dielectric green sheet 50a. The mask M1 is placed on the dielectric green sheet 50a so that the opening pattern M1a faces the electrode formation region 51. The electrode non-formation region 52 is covered by the portions of the mask M1 other than the opening pattern M1a. The mask M1 is, for example, a metal mask. The opening pattern M1a of the mask M1 is formed in the base material of the mask M1 by a known processing method such as laser processing or punching.

[0077] The mask M1 is placed on the dielectric green sheet 50a at a position spaced a gap G1 from the surface of the dielectric green sheet 50a. The gap G1 is controlled to be between 0.1 and 1.0 mm. The gap G1 can be adjusted by vertically moving a mask holder (not shown) supporting the mask M1 relative to the dielectric green sheet 50a. The gap G1 may also be adjusted by vertically moving a substrate holder supporting the dielectric green sheet 50a relative to the mask M1. Typically, a mask used during film formation is positioned so as to be in close contact with the film formation surface (in the example of FIG. 13, the upper surface of the dielectric green sheet 50a). In a method for manufacturing a multilayer ceramic capacitor according to one aspect of the present invention, the position of the mask M1 relative to the film formation surface of the dielectric green sheet 50a is adjusted so that a gap G1 of a controlled width exists between the dielectric green sheet 50a and the mask M1.

[0078] (Step S03: Film formation) Next, in step S03, an internal electrode pattern 60a is formed on the dielectric green sheet 50a prepared in step S01, thereby obtaining the first sheet unit U1 shown in FIG. 12. The internal electrode pattern 60a is a precursor of the first internal electrode layer 21. The internal electrode pattern 60a is formed by a vacuum film formation method such as sputtering on the dielectric green sheet 50a on which a mask M1 is arranged. Since the multilayer ceramic capacitor 1, which is a finished product, comprises a plurality of first internal electrode layers 21, a number of first sheet units U1 corresponding to the number of first internal electrode layers 21 comprised in the multilayer ceramic capacitor 1 are produced.

[0079] The method for forming the internal electrode pattern 60a will be further described with reference to Fig. 14. When the internal electrode pattern 60a is formed by sputtering, as shown in Fig. 14, metal atoms recoiled from a metal target pass through the opening pattern M1a of the mask M1 and are deposited in the electrode formation region 51 of the dielectric green sheet 50a, and these deposited metal atoms become the internal electrode pattern 60a.

[0080] Furthermore, because a gap G1 is provided between the dielectric green sheet 50a and the mask M1, metal atoms recoiled from the metal target penetrate from the electrode formation region 51 into the non-electrode formation region 52. Therefore, a gradation film 61 thinner than the gap G1 is formed in the region of the non-electrode formation region 52 that is continuous with the electrode formation region 51. The gradation film 61 is formed integrally with the internal electrode pattern 60a. Because the gradation film 61 is formed by metal atoms recoiled from the metal target penetrating the gap G1, it is much thinner than the internal electrode pattern 60a and, like the internal electrode pattern 60a, contains Ni as its main component. The thickness of the gradation film 61 in the T-axis direction is in the range of 0.01 to 0.2 μm. The gradation film 61 becomes thinner the further away from the internal electrode pattern 60a. If the thickness of the gradation film 61 in the T-axis direction is too thick, Ni crystal grains will form during firing and become part of the internal electrode pattern 60a. If the Ni contained in the gradation film 61 grows as crystal grains during the firing process (step S06 described below), the dimensions of the internal electrode pattern 60a will become larger in the L-axis and W-axis directions than the opening pattern M1a of the mask M1. Therefore, the maximum thickness dimension of the gradation film 61 in the T-axis direction is determined so that Ni crystal grains are not generated during the firing process. Specifically, the maximum thickness dimension of the gradation film 61 in the T-axis direction is preferably less than 0.5 μm, and more preferably less than 0.25 μm. The smaller the ratio of the maximum thickness dimension of the gradation film 61 in the T-axis direction to the thickness dimension of the internal electrode pattern 60a, the smaller the dimensional deviation of the internal electrode pattern 60a in the L-axis and W-axis directions (deviation from the dimensions defined by the opening pattern M1a of the mask M1) during firing. The maximum thickness dimension of the gradation film 61 in the T-axis direction is, for example, 20% or less, 10% or less, or 5% or less of the thickness dimension of the internal electrode pattern 60a. The Ni contained in the gradation film 61 diffuses into the dielectric green sheet 50a around the gradation film 61 during firing, and functions as a sintering aid that promotes sintering of the ceramic material in the dielectric green sheet 50a. In order to allow the Ni contained in the gradation film 61 to function as a sintering aid, a lower limit may be set for the maximum thickness dimension of the gradation film 61 in the T-axis direction.The maximum thickness of the gradation film 61 in the T-axis direction is, for example, 0.01 μm or more, 0.02 μm or more, or 0.03 μm or more. The thickness of the gradation film 61 and the width of the internal electrode pattern 60a (dimensions in the W-axis direction and L-axis direction) vary depending on the size of the gap G1. Specifically, by increasing the gap G1, the thickness and width of the gradation film 61 can be increased. Conversely, by decreasing the gap G1, the thickness and width of the gradation film 61 can be decreased.

[0081] In step S03, the second sheet unit U2 shown in FIG. 12 is obtained by forming the internal electrode patterns 80a on a plurality of dielectric green sheets 50a other than the dielectric green sheet 50a on which the internal electrode patterns 60a are formed. The internal electrode patterns 80a are precursors of the second internal electrode layers 22. Since the finished multilayer ceramic capacitor 1 includes a plurality of second internal electrode layers 22, the number of second sheet units U2 produced corresponds to the number of second internal electrode layers 22 included in the multilayer ceramic capacitor 1. Although not shown in the figure, a gradation film (a gradation film 81 described later) is also formed between the dielectric green sheet 50a and the mask when the internal electrode patterns 80a are formed on the dielectric green sheet 50a. The explanation regarding the gradation film 61 also applies to the gradation film 81.

[0082] Some of the dielectric green sheets 51a do not have internal electrode patterns formed thereon, and the dielectric green sheets 51a on which no internal electrode patterns are formed are referred to as cover sheet units U3.

[0083] 12, cutting lines X1 and X2 are shown on the first sheet unit U1, the second sheet unit U2, and the cover sheet unit U3, respectively, to indicate the cutting positions for singulation. The cutting line X1 extends in a direction parallel to the W axis, and the cutting line X2 extends in a direction parallel to the L axis.

[0084] 15, in step S04, the first sheet units U1 and second sheet units U2 obtained in step S03 are alternately stacked, and a plurality of cover sheet units U3 are stacked on each of the upper and lower surfaces in the T-axis direction of the alternately stacked first sheet units U1 and second sheet units U2 to obtain a laminate. Then, by pressing this laminate in the T-axis direction, a laminated sheet unit U10 is obtained in which the first sheet units U1, second sheet units U2, and cover sheet units U3 are stacked.

[0085] (Step S05: Cutting) In step S05, the laminated sheet unit U10 obtained in step S05 is cut along cutting lines X1 and X2 shown in FIG. 12 to produce singulated unsintered chip stacks 90 as shown in FIG. 16. For example, a press cutter blade or a rotary blade can be used to cut the laminated sheet unit U10. In the chip stack 90, the internal electrode pattern 60a and the internal electrode pattern 80a are stacked with the dielectric green sheet 50a interposed therebetween. A gradation film 61 is provided on both ends of the internal electrode pattern 60a in the W-axis direction. A gradation film 81 is provided on both ends of the internal electrode pattern 80a in the W-axis direction.

[0086] (Step S06: Firing) In step S06, the chip laminate 90 obtained in step S05 is fired to produce the body 10 of the multilayer ceramic capacitor 1. In this firing process, the dielectric green sheet 50a is fired to become the dielectric layer 11, the internal electrode pattern 60a is fired to become the first internal electrode layer 21, and the internal electrode pattern 80a is fired to become the second internal electrode layer 22.

[0087] Because the gradation films 61 and 81 are very thin, the Ni contained in the gradation films 61 and 81 does not form Ni crystal grains but diffuses into the surrounding dielectric green sheet 50a and functions as a sintering aid that promotes sintering of the ceramic material in the dielectric green sheet 50a. Because the gradation films 61 and 81 are formed very thin and contain only trace amounts of Ni, the range into which the Ni contained in the gradation films 61 and 81 diffuses is limited to a Ni-containing region 91 in the dielectric green sheet 50a near the internal electrode pattern 60a and the internal electrode pattern 80a, as shown in Fig. 17 . The Ni-containing region 91 is a region containing Ni diffused from the internal electrode pattern 60a, the internal electrode pattern 80a, the gradation film 61, or the gradation film 81. The Ni-containing region 91 surrounds the area where the internal electrode pattern 60a and the internal electrode pattern 80a face each other. The Ni-containing region 91 diffuses into the dielectric green sheet 50a not only from the internal electrode pattern 60a and the internal electrode pattern 80a but also from the gradation film 61 extending from the internal electrode pattern 60a in the W-axis direction (and L-axis direction) and the gradation film 81 extending from the internal electrode pattern 80a in the W-axis direction (and L-axis direction). Therefore, the thickness of the Ni-containing region 91 in the W-axis direction (and L-axis direction) is greater than the thickness in the T-axis direction. Because the Ni-containing region 91 contains Ni, sintering of the ceramic material contained in the dielectric green sheet 50a is promoted in the Ni-containing region 91. By the firing process in step S06, the Ni-containing region 91 of the stacked dielectric green sheets 50a included in the chip stack 90 becomes the first outer peripheral region R1, and the remaining regions (regions not containing Ni) become the second outer peripheral region R2.

[0088] The firing temperature in step S06 can be determined based on the sintering temperature of the ceramic material that constitutes the dielectric layer 11. For example, when a barium titanate (BaTiO)-based material is used as the material for the dielectric layer 11, the firing temperature can be approximately 1000 to 1300° C. Furthermore, firing can be performed, for example, in a reducing atmosphere or a low oxygen partial pressure atmosphere.

[0089] (Step S07: Forming External Electrodes) In step S07, a first external electrode 31 is formed at one end in the L-axis direction of the main body obtained in step S06, and a second external electrode 32 is formed at the other end. The first external electrode 31 is provided on the surface of the main body 10 so as to be electrically connected to the first internal electrode layer 21. The second external electrode 32 is provided on the surface of the main body 10 so as to be electrically connected to the second internal electrode layer 22. In this manner, the multilayer ceramic capacitor 1 is obtained.

[0090] The multilayer ceramic capacitors 101, 201, and 301 can also be fabricated in the same manner as the multilayer ceramic capacitor 1. However, the multilayer ceramic capacitors 101, 201, and 301 have a different shape of the first outer peripheral region R1 from the multilayer ceramic capacitor 1. For example, the shape of the first outer peripheral region R11 provided in the multilayer ceramic capacitor 101 is realized by increasing the gap G1 between the mask M1 and the dielectric green sheet 50a when forming the internal electrode pattern 60a and / or the internal electrode pattern 80a on the dielectric green sheet 50a arranged near the upper and lower ends of the capacitance generating region Rc compared to when forming the internal electrode pattern on the dielectric green sheet 50a arranged in other locations. By increasing the gap G1 between the mask M1 and the dielectric green sheet 50a when depositing the internal electrode pattern 60a and / or the internal electrode pattern 80a on the dielectric green sheet 50a located near the upper and lower ends of the capacitance generating region Rc, the thickness and width of the gradation film 61 and / or the gradation film 81 can be increased, thereby allowing Ni to be supplied to a wider area within the dielectric green sheet 50a in the regions near the upper and lower ends of the capacitance generating region Rc during firing. Therefore, thick portions RP1 and RP2 can be formed in the first outer peripheral region R11 near the upper and lower ends of the capacitance generating region Rc, respectively. The shape of the first outer peripheral region R21 of the multilayer ceramic capacitor 201 is achieved by increasing the gap G1 between the mask M1 and the dielectric green sheet 50a when depositing the internal electrode pattern 60a and / or the internal electrode pattern 80a on the dielectric green sheet 50a located near the center in the T-axis direction of the capacitance generating region Rc, compared to when depositing on the dielectric green sheet 50a located in other locations. The shape of the first outer peripheral region R31 of the multilayer ceramic capacitor 301 is realized by increasing the gap G1 between the mask M1 and the dielectric green sheet 50a when depositing the internal electrode pattern 60a and / or the internal electrode pattern 80a on the dielectric green sheet 50a that is positioned in the T-axis direction of the capacitance generating region Rc at a position where the thick portions RP5 to RP10 are provided, compared to when depositing on the dielectric green sheet 50a that is positioned in other locations.

[0091] 11 may be performed to manufacture the multilayer ceramic capacitors 1, 101, and 201. For example, the multilayer ceramic capacitor 1 produced in step S07 may be subjected to a reoxidation treatment at 600°C to 1000°C in an N2 gas atmosphere. Furthermore, a plating layer of Cu, Ni, Sn, or the like may be provided on the surfaces of the first external electrode 31 and the second external electrode 32. This plating layer may be formed by electrolytic plating or electroless plating.

[0092] 6 Example 6: A multilayer ceramic capacitor was manufactured according to the above manufacturing method. By observing the cross section of the multilayer ceramic capacitor, it was confirmed that a dense first peripheral region R1 was formed around the capacitance generating region Rc. Specifically, first, multiple dielectric green sheets 50a primarily composed of barium titanate were prepared. Then, a mask M1 was placed on the dielectric green sheet 50a so that the gap G1 between the top surface of the dielectric green sheet 50a was 0.1 mm. Internal electrode patterns 60a and 80a were formed on the dielectric green sheet 50a by sputtering using Ni metal as a target, thereby producing 13 sheet units U1 and U2. Five layers of the dielectric green sheet 50a (sheet unit U3) were stacked, and then sheet units U1 and U2 were alternately stacked on top of them to produce a laminated sheet unit U10. Next, the laminated sheet unit U10 was singulated to produce a chip stack 90. Next, this chip stack 90 was fired at 1210° C. to produce the main body 10 .

[0093] This sintered body was cut along the WT surface to expose the cross section, and the cross section was photographed at 10,000x magnification using a scanning electron microscope (SEM) to obtain an SEM image of a portion of the cross section of the main body 10. Next, the SEM image obtained by this photograph was subjected to binarization processing, and the porosity was calculated for multiple regions surrounding the capacitance generation region Rc within the cross section. As a result, it was confirmed that the porosity was lower in the region adjacent to and surrounding the capacitance generation region Rc than in the region separated from the capacitance generation region Rc. In other words, it was confirmed that a first outer peripheral region R1 with a low porosity was formed around the capacitance generation region Rc.

[0094] Furthermore, in the cross section, the lengths in the W-axis direction of the electrode regions 21 a and non-electrode regions 21 b of the first internal electrode layers 21 and the electrode regions 22 a and non-electrode regions 22 b of the second internal electrode layers 22 were measured, and the continuity rate of the first internal electrode layers 21 was calculated based on the measured lengths in the W-axis direction of the electrode regions 21 a and non-electrode regions 21 b. Furthermore, the continuity rate of the second internal electrode layers 22 was calculated based on the lengths in the W-axis direction of the electrode regions 22 a and non-electrode regions 22 b. As a result, the continuity rate was 75% or more for both the 13-layer first internal electrode layers 21 and the 13-layer second internal electrode layers 22. Therefore, it was confirmed that even if the chip stack 90 is manufactured at a low temperature that does not reduce the continuity rate of the internal electrode layers, a main body 10 in which the periphery of the capacitance generating region Rc is surrounded by a dense first outer peripheral region R1 can be obtained.

[0095] In addition, other multilayer ceramic capacitors were manufactured by changing the gap G1 between the dielectric green sheet 50a and the mask M1 to 0.6 mm, 0.8 mm, and 1.0 mm, and cross-sectional observations were also performed for each of these multilayer ceramic capacitors. As a result, it was confirmed that even in the multilayer ceramic capacitors manufactured with the gap G1 set to 0.6 mm, 0.8 mm, and 1.0 mm, a first outer peripheral region R1 with a low porosity was formed around the capacitance generating region Rc, and that the continuity ratio of each internal electrode layer was 75% or more.

[0096] In one aspect of the present invention, the capacitance generation region Rc is surrounded by the dense first outer peripheral region R1, which can prevent hydrogen and moisture from penetrating into the capacitance generation region Rc, thereby preventing a decrease in the insulation reliability of the capacitance generation region Rc due to hydrogen and moisture.

[0097] In one aspect of the present invention, the first outer peripheral region R1 is formed so that the thickness dimension W11 in the W-axis direction is thicker than the thickness dimension T11 in the T-axis direction, thereby more reliably preventing hydrogen and moisture from penetrating into the capacitance generation region Rc in a direction perpendicular to the stacking direction (a direction along the WL plane).

[0098] In one aspect of the present invention, the first outer peripheral region R1 is denser than the second outer peripheral region R2, and therefore, by providing the first outer peripheral region R1, the mechanical strength of the multilayer ceramic capacitor 1 can be improved.

[0099] In one aspect of the present invention, a thick portion RP1 is provided at a position corresponding to the upper end of the capacitance generation region Rc in the T-axis direction, and this thick portion RP1 can prevent hydrogen generated from the portion of the first external electrode 31 that is in contact with the upper surface 10a of the main body 10 and the portion of the second external electrode 32 that is in contact with the upper surface 10a of the main body 10 from entering the capacitance generation region Rc.

[0100] In one aspect of the present invention, a thick portion RP2 is provided at a position corresponding to the lower end of the capacitance generation region Rc in the T-axis direction, and this thick portion RP2 can prevent hydrogen generated from the portion of the first external electrode 31 that is in contact with the lower surface 10b of the main body 10 and the portion of the second external electrode 32 that is in contact with the lower surface 10b of the main body 10 from entering the capacitance generation region Rc.

[0101] In one aspect of the present invention, the margin portion R1v of the first outer peripheral region R21 is configured to gradually increase in thickness toward the center of the capacitance generating region Rc in the T-axis direction, thereby preventing stress from concentrating at a specific location in the margin portion R1v, thereby preventing cracks from occurring around the first outer peripheral region R21 when stress is applied to the main body 10.

[0102] In one aspect of the present invention, multiple thick portions RP5 to RP10 are provided in the margin portion R1v of the first outer peripheral region R31 at multiple positions in the T-axis direction of the capacitance generation region Rc, thereby dispersing the stress acting on the first outer peripheral region R31 and thereby suppressing breakage of the main body 10.

[0103] In one aspect of the present invention, instead of densifying the entire main body 10, only the first outer peripheral region R1 of the main body 10 that surrounds the capacitance generation region Rc is densified, thereby preventing hydrogen and moisture from penetrating into the capacitance generation region Rc.

[0104] In one aspect of the present invention, the chip stack 90 is fired at a low temperature of approximately 1000 to 1300°C, rather than at a high temperature that would densify the entire main body 10, to form a dense first outer peripheral region surrounding the capacitance generating region Rc, thereby suppressing the penetration of hydrogen and moisture into the capacitance generating region Rc without reducing the continuity rate of the internal electrode layer.

[0105] 8. Note The dimensions, materials, and arrangements of each component described in the various embodiments above are not limited to those explicitly described in each embodiment, and each component can be modified to have any dimensions, materials, and arrangements that may fall within the scope of the present invention.

[0106] Components not explicitly described in this specification may be added to each of the above-described embodiments, and some of the components described in each embodiment may be omitted.

[0107] The terms "first," "second," "third," and the like used in this specification are used to identify components and do not necessarily limit the number, order, or content of the components. Furthermore, numbers used to identify components are used in different contexts, and a number used in one context does not necessarily indicate the same configuration in another context. Furthermore, this does not prevent a component identified by a certain number from also serving the function of a component identified by another number.

[0108] In this specification, when a certain component is referred to as "comprising" another component, it does not mean that other components are excluded, but that other components may be further included, unless it is inconsistent with the content of the present invention.

[0109] For example, the main body 10 may be configured such that the first end face 10c and the second end face 10d are parallel to two legs of a trapezoid that defines the outer edge of the capacitance generating region Ra in the LT plane, as shown in Fig. 8, and the first side face 10e and the second side face 10f are parallel to two legs of a trapezoid that defines the outer edge of the capacitance generating region Ra in the WT plane, as shown in Fig. 9.

[0110] 9. Supplementary Notes The embodiments disclosed in this specification also include the following.

[0111] [Supplementary Note 1] A main body having a plurality of dielectric layers (11) and a plurality of internal electrode layers (21, 22) stacked in a first direction (T-axis) via at least one of the plurality of dielectric layers; a first external electrode (31) provided on the main body so as to be electrically connected to each of a plurality of first internal electrode layers (21) of the plurality of internal electrode layers; and a second external electrode (32) provided on the main body so as to be electrically connected to each of a plurality of second internal electrode layers (22) of the plurality of internal electrode layers, wherein the main body is partitioned into a capacitance generating region (Rc) in which the plurality of first internal electrodes and the plurality of second internal electrodes face each other in the first direction, a first outer peripheral region (R1) surrounding the capacitance generating region, and a second outer peripheral region (R2) surrounding the first outer peripheral region, wherein a first porosity indicating the porosity of the first outer peripheral region is smaller than a second porosity indicating the porosity of the second outer peripheral region, The first outer peripheral region has a cover portion (R1h) adjacent to the capacitance generating region in the first direction and a margin portion (R1v) adjacent to the capacitance generating region in a second direction (W-axis) perpendicular to the first direction, and a second thickness (W1) indicating the thickness of the margin portion in the second direction is greater than a first thickness (T1) indicating the thickness of the cover portion in the first direction.

[0112] [Appendix 2] The multilayer ceramic capacitor according to [Appendix 1], wherein the plurality of internal electrode layers contain Ni as a main component, and the first outer peripheral region contains Ni at a higher concentration than the second outer peripheral region.

[0113] [Appendix 3] The multilayer ceramic capacitor according to [Appendix 2], wherein the concentration of Ni in the first outer peripheral region is 10 at % or less.

[0114] [Appendix 4] The multilayer ceramic capacitor according to [Appendix 2] or [Appendix 3], wherein the second outer peripheral region does not contain Ni.

[0115] [Supplementary Note 5] The multilayer ceramic capacitor according to any one of [Supplementary Note 1] to [Supplementary Note 4], wherein the thickness of each of the plurality of internal electrode layers in the first direction is 0.25 μm or less.

[0116] [Appendix 6] The multilayer ceramic capacitor according to any one of [Appendix 1] to [Appendix 5], wherein the continuity rate of each of the plurality of internal electrode layers is 75% or more.

[0117] [Supplementary Note 7] The multilayer ceramic capacitor according to any one of [Supplementary Note 1] to [Supplementary Note 6], wherein the margin portion has a first thick portion (RP1) at a first position in the first direction, and a third thickness (W21) indicating a thickness of the first thick portion in the second direction is greater than the second thickness (W11) of the margin portion.

[0118] [Supplementary Note 8] The multilayer ceramic capacitor according to [Supplementary Note 7], wherein the first position is a position corresponding to one end of the capacitance generating region in the first direction.

[0119] [Supplementary Note 9] The multilayer ceramic capacitor according to [Supplementary Note 7], wherein the first position is a position corresponding to a center of the capacitance generating region in the first direction.

[0120] [Supplementary Note 10] The multilayer ceramic capacitor according to [Supplementary Note 7], wherein the margin portion further includes a second thick portion (RP4) protruding from the first thick portion (RP3) in the second direction.

[0121] [Supplementary Note 11] The multilayer ceramic capacitor according to any one of [Supplementary Note 7] to [Supplementary Note 10], wherein the margin portion has a second thick portion at a second position in the first direction, and the thickness of the second thick portion in the second direction is greater than the average thickness of the margin portion in the second direction.

[0122] [Supplementary Note 12] The multilayer ceramic capacitor according to [Supplementary Note 11], wherein the first position is a position corresponding to one end of the capacitance generating region in the first direction, and the second position is a position corresponding to the other end of the capacitance generating region in the first direction.

[0123] [Appendix 13] The multilayer ceramic capacitor according to [Appendix 11], wherein the margin portion has a third thick portion at a third position in the first direction, and the thickness of the third thick portion in the second direction is greater than an average thickness of the margin portion in the second direction.

[0124] [Supplementary Note 14] The multilayer ceramic capacitor according to any one of [Supplementary Note 1] to [Supplementary Note 13], wherein none of the plurality of first internal electrode layers and the second internal electrode layers are present in the margin portion when viewed from the first direction.

[0125] [Supplementary Note 15] A main body having a plurality of dielectric layers (11) and a plurality of internal electrode layers (21, 22) stacked in a first direction (T) via at least one of the plurality of dielectric layers, the plurality of internal electrode layers being mainly composed of Ni; a first external electrode (31) provided on the main body so as to be electrically connected to each of a plurality of first internal electrode layers (21) of the plurality of internal electrode layers; and a second external electrode (32) provided on the main body so as to be electrically connected to each of a plurality of second internal electrode layers (22) of the plurality of internal electrode layers, the main body being partitioned into a capacitance generating region where the plurality of first internal electrodes and the plurality of second internal electrodes face each other in the first direction, a first outer peripheral region surrounding the capacitance generating region, and a second outer peripheral region surrounding the first outer peripheral region, the first outer peripheral region containing Ni at a higher concentration than the second outer peripheral region, the first outer peripheral region has a cover portion adjacent to the capacitance generating region in the first direction and a margin portion adjacent to the capacitance generating region in a second direction perpendicular to the first direction, and a second thickness indicating the thickness of the margin portion in the second direction is greater than a first thickness indicating the thickness of the cover portion in the first direction.

[0126] [Appendix 16] A method for manufacturing a multilayer ceramic capacitor, comprising: a step of preparing a dielectric green sheet; a step of arranging a mask on the dielectric green sheet so as to be spaced 0.1 to 1.0 mm above an upper surface of the dielectric green sheet; a step of forming an internal electrode pattern by a sputtering method on the dielectric green sheet on which the mask has been arranged, thereby preparing a laminate unit; a step of laminating a plurality of the multilayer units to form a laminate; and a firing step of firing the laminate.

[0127] 1, 10, 201, 301 Multilayer ceramic capacitor 10 Body 11 Dielectric layer 21 First internal electrode layer 22 Second internal electrode layer 31 First external electrode 32 Second external electrode R1 First outer peripheral region R1 R2 Second outer peripheral region

Claims

1. A main body having a plurality of dielectric layers and a plurality of internal electrode layers stacked in a first direction via at least one of the plurality of dielectric layers; a first external electrode provided on the main body so as to be electrically connected to each of a plurality of first internal electrode layers of the plurality of internal electrode layers; and a second external electrode provided on the main body so as to be electrically connected to each of a plurality of second internal electrode layers of the plurality of internal electrode layers, wherein the main body is partitioned into a capacitance generating region where the plurality of first internal electrodes and the plurality of second internal electrodes face each other in the first direction, a first outer peripheral region surrounding the capacitance generating region, and a second outer peripheral region surrounding the first outer peripheral region, wherein a first porosity indicating the porosity of the first outer peripheral region is smaller than a second porosity indicating the porosity of the second outer peripheral region, and the first outer peripheral region has a cover portion adjacent to the capacitance generating region in the first direction and a margin portion adjacent to the capacitance generating region in a second direction perpendicular to the first direction, a first thickness indicating the thickness of the cover portion in the first direction and a second thickness indicating the thickness of the margin portion in the second direction, the second thickness being greater than the first thickness indicating the thickness of the cover portion in the first direction.

2. The multilayer ceramic capacitor according to claim 1, wherein the plurality of internal electrode layers are composed mainly of Ni, and the first outer peripheral region contains Ni at a higher concentration than the second outer peripheral region.

3. The multilayer ceramic capacitor according to claim 2, wherein the concentration of Ni in the first outer peripheral region is 10 at % or less.

4. The multilayer ceramic capacitor according to claim 2, wherein the second outer peripheral region does not contain Ni.

5. The multilayer ceramic capacitor according to claim 1, wherein the thickness of each of the plurality of internal electrode layers in the first direction is 0.25 μm or less.

6. The multilayer ceramic capacitor according to claim 1, wherein the continuity rate of each of the plurality of internal electrode layers is 75% or more.

7. The multilayer ceramic capacitor according to claim 1, wherein the margin portion has a first thick portion at a first position in the first direction, and a third thickness indicating the thickness of the first thick portion in the second direction is greater than the second thickness (W11) of the margin portion.

8. The multilayer ceramic capacitor according to claim 7, wherein the first position is a position corresponding to one end of the capacitance generating region in the first direction.

9. The multilayer ceramic capacitor according to claim 7, wherein the first position is a position corresponding to the center of the capacitance generating region in the first direction.

10. The multilayer ceramic capacitor according to claim 7, wherein the margin portion further includes a second thick portion protruding from the first thick portion in the second direction.

11. The multilayer ceramic capacitor according to claim 7, wherein the margin portion has a second thick portion at a second position in the first direction, and the thickness of the second thick portion in the second direction is greater than the thickness of the first thick portion in the second direction.

12. The multilayer ceramic capacitor according to claim 11, wherein the first position is a position corresponding to one end of the capacitance generating region in the first direction, and the second position is a position corresponding to the other end of the capacitance generating region in the first direction.

13. The multilayer ceramic capacitor according to claim 11, wherein the margin portion has a third thick portion at a third position in the first direction, and the thickness of the third thick portion in the second direction is greater than the average thickness of the margin portion in the second direction.

14. The multilayer ceramic capacitor according to claim 1, wherein none of the plurality of first internal electrode layers and the second internal electrode layers are present in the margin portion when viewed from the first direction.

15. A main body having a plurality of dielectric layers and a plurality of internal electrode layers stacked in a first direction via at least one of the plurality of dielectric layers and containing Ni as a main component; a first external electrode provided on the main body so as to be electrically connected to each of a plurality of first internal electrode layers of the plurality of internal electrode layers; and a second external electrode provided on the main body so as to be electrically connected to each of a plurality of second internal electrode layers of the plurality of internal electrode layers, wherein the main body is partitioned into a capacitance generating region where the plurality of first internal electrodes and the plurality of second internal electrodes face each other in the first direction, a first outer peripheral region surrounding the capacitance generating region, and a second outer peripheral region surrounding the first outer peripheral region, wherein the first outer peripheral region contains Ni at a higher concentration than the second outer peripheral region, and the first outer peripheral region has a cover portion adjacent to the capacitance generating region in the first direction and a margin portion adjacent to the capacitance generating region in a second direction perpendicular to the first direction, a second thickness indicating a thickness of the margin portion in the second direction is greater than a first thickness indicating a thickness of the cover portion in the first direction.

16. A method for manufacturing a multilayer ceramic capacitor, comprising: a step of preparing a dielectric green sheet; a step of placing a mask on the dielectric green sheet, floating 0.1 to 1.0 mm from the upper surface of the dielectric green sheet; a step of forming an internal electrode pattern by a sputtering method on the dielectric green sheet on which the mask has been placed, thereby preparing a laminate unit; a step of laminating a plurality of the laminate units to form a laminate; and a firing step of firing the laminate.

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