Communication device, communication method for robot, and robot

Abstract

The present technology relates to a communication device that improves the transmission efficiency of data in a robot, a communication method for a robot, and a robot. The communication device, which is provided in a robot, comprises: a master communication unit; a plurality of slave communication units daisy-chained to the master communication unit; a master memory space which is a memory space the master communication unit can access; and a plurality of slave memory spaces which are memory spaces the respective slave communication units can access individually. The master memory space includes a master write region, which is a region for storing write data that is data to be transmitted to each slave communication unit, and a master readout region, which is a region for storing readout data that is data received from each slave communication unit. Each slave memory space includes a slave write region, which is a region for storing write data received from the master communication unit, and a slave readout region, which is a region for storing readout data to be transmitted to the master communication unit. The present technology can be applied, for example, to robots.

Description

Communication device, robot communication method, and robot

[0001] The present technology relates to a communication device, a robot communication method, and a robot, and in particular to a communication device, a robot communication method, and a robot that are configured to improve the transmission efficiency of data within the robot.

[0002] Conventional communication systems used in industrial robots and the like use communication protocols that are optimized for transmitting and receiving small amounts of limited data, such as torque, current, speed, and position (see, for example, Patent Document 1).

[0003] Japanese Patent Application Laid-Open No. 2017-192301

[0004] Meanwhile, some modern robots are controlled using AI and machine learning based on large volumes of multimodal data, such as sensor data and video data. To transmit large volumes of multimodal data, wiring and a communication system separate from the conventional communication system for controlling robots is required.

[0005] The present technology has been made in view of such circumstances, and aims to improve the transmission efficiency of data within a robot.

[0006] A communication device according to a first aspect of the present technology is provided on a robot and includes a master communication unit, a plurality of slave communication units daisy-chain connected to the master communication unit, a master memory space that is a memory space accessible by the master communication unit, and a plurality of slave memory spaces that are memory spaces individually accessible by each of the slave communication units, wherein the master memory space includes a master write area that is an area for storing write data that is data to be transmitted to each of the slave communication units, and a master read area that is an area for storing read data that is data received from each of the slave communication units, and each of the slave memory spaces includes a slave write area that is an area for storing the write data received from the slave communication unit, and a slave read area that is an area for storing the read data to be transmitted to the slave communication unit.

[0007] A robot communication method according to a second aspect of the present technology includes daisy-chaining a plurality of slave communication units to a master communication unit, providing a master memory space that is memory space accessible by the master communication unit with a master write area that is an area for storing write data that is data to be transmitted to the slave communication unit, and a master read area that is an area for storing read data that is data received from the slave communication unit, and providing a plurality of slave memory spaces that are memory spaces individually accessible by each of the slave communication units with a slave write area that is an area for storing the write data received from the slave communication unit, and a slave read area that is an area for storing the read data to be transmitted to the slave communication unit, and the master communication unit and each of the slave communication units transmit and receive the write data and the read data.

[0008] A robot according to a third aspect of the present technology includes a control unit that controls the operation of each unit, a master communication unit connected to the control unit, a plurality of slave communication units daisy-chain connected to the master communication unit, a master memory space that is a memory space accessible by the master communication unit, and a plurality of slave memory spaces that are memory spaces individually accessible by each of the slave communication units, wherein the master memory space includes a master write area that is an area for storing write data that is data to be transmitted to each of the slave communication units, and a master read area that is an area for storing read data that is data received from each of the slave communication units, and each of the slave memory spaces includes a slave write area that is an area for storing the write data received from the slave communication unit, and a slave read area that is an area for storing the read data to be transmitted to the slave communication unit.

[0009] In a first aspect of the present technology, a plurality of slave communication units are daisy-chain connected to a master communication unit, and a master memory space, which is a memory space accessible by the master communication unit, is provided with a master write area, which is an area for storing write data, which is data to be sent to the slave communication unit, and a master read area, which is an area for storing read data, which is data received from the slave communication unit, and a plurality of slave memory spaces, which are memory spaces individually accessible by each of the slave communication units, are provided with a slave write area, which is an area for storing the write data received from the slave communication unit, and a slave read area, which is an area for storing the read data to be sent to the slave communication unit.

[0010] In a second aspect of the present technology, a plurality of slave communication units are daisy-chain connected to a master communication unit, and a master memory space, which is a memory space accessible by the master communication unit, is provided with a master write area, which is an area for storing write data, which is data to be transmitted to the slave communication unit, and a master read area, which is an area for storing read data, which is data received from the slave communication unit, and a plurality of slave memory spaces, which are memory spaces individually accessible by each of the slave communication units, are provided with a slave write area, which is an area for storing the write data received from the master communication unit, and a slave read area, which is an area for storing the read data to be transmitted to the master communication unit, and the write data and the read data are transmitted and received between the master communication unit and each of the slave communication units.

[0011] In a third aspect of the present technology, a master communication unit is connected to a control unit that controls the operation of each unit, and multiple slave communication units are daisy-chained to the master communication unit, and a master memory space that is memory space accessible by the master communication unit is provided with a master write area that is an area for storing write data that is data to be sent to each of the slave communication units, and a master read area that is an area for storing read data that is data received from each of the slave communication units, and multiple slave memory spaces that are memory spaces that are individually accessible by each of the slave communication units are provided with a slave write area that is an area for storing the write data received from the master communication unit, and a slave read area that is an area for storing the read data to be sent to the master communication unit, respectively.

[0012] 1 is a diagram showing an example of a configuration of the appearance of a robot arm to which the present technology is applied. FIG. 2 is a diagram showing an example of a configuration of the appearance of an actuator. FIG. 3 is a block diagram showing an example of a configuration of an arm electrical system provided in a robot arm. FIG. 4 is a diagram showing an example of a format of a write packet. FIG. 5 is a diagram showing an example of a format of a read packet. FIG. 6 is a timing chart showing an example of operation of a slave FPGA during reading in cyclic communication mode. FIG. 7 is a diagram showing an example of a configuration of the appearance of a robot hand to which the present technology is applied. FIG. 8 is a block diagram showing a first example of a configuration of a hand electrical system when a robot hand is attached to a robot arm. FIG. 9 is a block diagram showing a second example of a configuration of a hand electrical system when a robot hand is attached to a robot arm. FIG. 10 is a block diagram showing an example of a configuration of an electrical system to which the present technology is applied. FIG. 11 is a diagram showing an example of a configuration of a write area of ​​a master FPGA. FIG. 12 is a diagram showing an example of a configuration of a write area of ​​a slave FPGA. FIG. 13 is a diagram showing an example of a configuration of a read area of ​​a slave FPGA. FIG. 14 is a diagram for explaining a method of controlling the read area of ​​the master FPGA. FIG. 15 is a diagram for explaining a method of controlling the read area of ​​the master FPGA. FIG. 16 is a flowchart for explaining cyclic communication processing executed by an electrical system. FIG. 17 is a diagram for explaining a method for transmitting large amounts of data. 1 is a diagram for explaining a method for transmitting a large amount of data.

[0013] Hereinafter, embodiments of the present technology will be described in the following order: 1. First embodiment 2. Second embodiment 3. Third embodiment 4. Modification 5. Other

[0014] <<1. First Embodiment>> A first embodiment of the present technology will be described with reference to FIGS. 1 to 6 .

[0015] <Configuration Example of Robot Arm 1> FIG. 1 shows a configuration example of the exterior of a robot arm 11 to which the present technology is applied.

[0016] The robot arm 11 is a seven-axis single-arm robot arm in which a total of seven actuators, actuator 21-1 to actuator 21-7, are provided at each joint.

[0017] Hereinafter, when there is no need to distinguish between the actuators 21-1 to 21-7, they will be simply referred to as actuators 21.

[0018] FIG. 2 shows an example of the external configuration of the actuator 21.

[0019] FIG. 3 shows an example of the configuration of an arm electrical system 51, which is an information processing system equipped with a communication function and which is provided in the robot arm 11.

[0020] In addition to the above-mentioned actuators 21-1 to 21-7, the arm electrical system 51 includes a host PC 61, a master FPGA (Field Programmable Gate Array) 62, slave FPGAs 63-1 to 63-7, control MCUs 64-1 to 64-7, and motor drivers 65-1 to 65-7.

[0021] The slave FPGAs 63-1 to 63-7 are daisy-chain connected to the master FPGA 62 via communication lines.

[0022] The control MCU 64-1, motor driver 65-1, and actuator 21-1 are connected in series to the slave FPGA 63-1. The slave FPGA 63-1, control MCU 64-1, motor driver 65-1, and actuator 21-1 are used to control the first joint of the robot arm 11.

[0023] The control MCU 64-2, motor driver 65-2, and actuator 21-2 are connected in series to the slave FPGA 63-2. The slave FPGA 63-2, control MCU 64-2, motor driver 65-2, and actuator 21-2 are used to control the second joint of the robot arm 11.

[0024] The control MCU 64-3, motor driver 65-3, and actuator 21-3 are connected in series to the slave FPGA 63-3. The slave FPGA 63-3, control MCU 64-3, motor driver 65-3, and actuator 21-3 are used to control the third joint of the robot arm 11.

[0025] The control MCU 64-4, motor driver 65-4, and actuator 21-4 are connected in series to the slave FPGA 63-4. The slave FPGA 63-4, control MCU 64-4, motor driver 65-4, and actuator 21-4 are used to control the fourth joint of the robot arm 11.

[0026] The control MCU 64-5, motor driver 65-5, and actuator 21-5 are connected in series to the slave FPGA 63-5. The slave FPGA 63-5, control MCU 64-5, motor driver 65-5, and actuator 21-5 are used to control the fifth joint of the robot arm 11.

[0027] The control MCU 64-6, motor driver 65-6, and actuator 21-6 are connected in series to the slave FPGA 63-6. The slave FPGA 63-6, control MCU 64-6, motor driver 65-6, and actuator 21-6 are used to control the sixth joint of the robot arm 11.

[0028] The control MCU 64-7, motor driver 65-7, and actuator 21-7 are connected in series to the slave FPGA 63-7. The slave FPGA 63-7, control MCU 64-7, motor driver 65-7, and actuator 21-7 are used to control the seventh joint of the robot arm 11.

[0029] Hereinafter, when there is no need to distinguish between the slave FPGAs 63-1 to 63-7, they will simply be referred to as slave FPGAs 63. Hereinafter, when there is no need to distinguish between the control MCUs 64-1 to 64-7, they will simply be referred to as control MCUs 64. Hereinafter, when there is no need to distinguish between the motor drivers 65-1 to 65-7, they will simply be referred to as motor drivers 65.

[0030] The host PC 61 is configured, for example, by an IC in which an FPGA and a SoC (System on a Chip) are integrated. The host PC 61 communicates with each control MCU 64 via a master FPGA 62 and a slave FPGA 63, and controls the operation of the robot arm 11.

[0031] For example, high-speed serial communication such as PCI Express is used for communication between the host PC 61 and the master FPGA 62. This makes it possible to send and receive large amounts of data.

[0032] The master FPGA 62 constitutes a master communication unit that takes the lead (controls) communication of each slave FPGA 63 .

[0033] Each slave FPGA 63 constitutes a slave communication unit that communicates with the master FPGA 62 under the leadership of the master FPGA 62 .

[0034] The communication between the master FPGA 62 and each slave FPGA 63 can be achieved by using the high-speed transceiver function of the FPGA or high-speed serial communication using differential signals such as LVDS (Low Voltage Differential Signaling), which enables high-speed transmission of large amounts of data.

[0035] The control MCU 64 controls the motor driver 65 in accordance with instructions from the host PC 61, based on information such as the encoder angle fed back from the actuator 21 and the current value fed back from the motor driver 65. This controls the movement of the corresponding joint of the robot arm 11.

[0036] The motor driver 65 drives the motor in the actuator 21 under the control of the control MCU 64 to drive the corresponding joint of the robot arm 11 .

[0037] <Communication Protocol Between FPGAs> Next, communication protocols between FPGAs will be described with reference to FIGS.

[0038] Two communication modes are provided for communication between FPGAs: a periodic communication mode and a one-shot mode. The periodic communication mode is a mode in which data is transmitted periodically to operate the robot arm 11. The one-shot mode is a mode in which data is transmitted one-off, such as for initial setting.

[0039] FIG. 4 shows an example of the format of a write packet used when the master FPGA 62 transmits data (hereinafter referred to as write data) to the slave FPGA 63 (hereinafter referred to as write time).

[0040] The write packet includes a preamble field and a protocol datagram field.

[0041] The preamble field is an 8-byte field in which a specific pattern value is set to identify the write packet, allowing each slave FPGA 63 to recognize the start position of the write packet and the Protocol Datagram field.

[0042] The Protocol Datagram area includes a 1st Datagram area, a 2nd Datagram area, ..., an Nth Datagram area. That is, the same number of Protocol Datagram areas as the number of slave FPGAs 63 are provided, and in the case of the robot arm 11, for example, N=7.

[0043] Each Datagram area includes a Datagram Header area and a Payload area.

[0044] The Datagram Header area is an 8-byte area that stores Start information, Board ID information, Buffer No. information, Type information, Size information, and the like.

[0045] The Start information is set to a value indicating the beginning of the Datagram Header area.

[0046] The board ID information is destination information of the write data and indicates a board ID, which is an ID for identifying the slave FPGA 63 that is the destination of the write data. For example, the board ID indicates the number of the daisy chain connection of each slave FPGA 63 from the master FPGA 62. Each slave FPGA 63 recognizes its own board ID in advance.

[0047] The Buffer No. information indicates the number of an area in the memory space of the slave FPGA 63 that stores the write data stored in the payload area. Specifically, as will be described later with reference to FIG. 12, an area for write data (hereinafter referred to as the write area) is provided in the memory space of the slave FPGA 63. Furthermore, the write area is provided with an area (hereinafter referred to as the function area) for each function that uses the write data. For example, the Buffer No. information indicates a number for identifying the function area that stores the write data stored in the payload area.

[0048] The type information indicates communication error information.

[0049] The size information indicates the data size of the payload area.

[0050] The payload area stores write data used by the control MCU 162 connected to the slave FPGA 63 having the board ID indicated in the board ID information.

[0051] In communication between FPGAs, the payload area is a black box, and the master FPGA 62 and each slave FPGA 63 are not particularly involved. The payload area is processed based on the communication protocol determined between the host PC 61 and each control MCU 64.

[0052] Each slave FPGA 63 recognizes the data addressed to it based on the Board ID information stored in the Datagram Header area at the beginning of each Datagram area of ​​the write packet, and obtains the write data stored in the Datagram area addressed to it.

[0053] FIG. 5 shows an example of the format of a read packet used when the master FPGA 62 receives data (hereinafter referred to as read data) from the slave FPGA 63 (hereinafter referred to as read).

[0054] The read packet includes a preamble area, a datagram header area, and a payload area.

[0055] The preamble field is an 8-byte field in which a specific pattern value is set to identify a read packet, allowing the master FPGA 62 to recognize the start position of the read packet and the datagram header.

[0056] The Datagram Header area is an 8-byte area that stores Start information, Board ID information, Buffer No. information, Type information, Size information, and the like.

[0057] The Start information is set to a value indicating the beginning of the Datagram Header area.

[0058] The board ID information indicates a board ID that is an ID for identifying the slave FPGA 63 that is the sender of the read data.

[0059] The Buffer No. information indicates the number of an area in the memory space of the master FPGA 62 that stores the read data stored in the Payload area. Specifically, as will be described later with reference to FIG. 14, an area for read data (hereinafter referred to as the read area) is provided in the memory space of the master FPGA 62. Furthermore, the read area is provided with an area (hereinafter referred to as the function area) for each function that uses the read data. For example, the Buffer No. information indicates a number for identifying the function area that stores the read data stored in the Payload area.

[0060] The type information indicates communication error information.

[0061] The size information indicates the data size of the payload area.

[0062] The payload area stores read data used by the host PC 61 .

[0063] In communication between FPGAs, the payload area is a black box, and the master FPGA 62 and each slave FPGA 63 are not particularly involved. The payload area is processed based on the communication protocol determined between the host PC 61 and each control MCU 64.

[0064] As described above, the read packet stores the read data transmitted from each slave FPGA 63. Therefore, each slave FPGA 63 can transmit the read data to the master FPGA 62 without timing restrictions.

[0065] 6 is a timing chart showing an example of the operation of the slave FPGA 63 during read in the periodic communication mode. Specifically, FIG. 6 shows a timing chart of the internal clock signal of the slave FPGA 63, the periodic communication trigger signal received from the master FPGA 62, and the periodic communication interrupt signal transmitted from the slave FPGA 63 to the control MCU 64.

[0066] Each slave FPGA 63 transmits a periodic communication interrupt signal to the control MCU 64 in accordance with the periodic communication trigger signal received from the master FPGA 62. While the periodic communication interrupt signal is on, the control MCU 64 acquires control data such as the encoder angle used to control the actuator 21 and the current value of the motor driver 65, and supplies the data to the slave FPGA 63.

[0067] In this case, since the slave FPGAs 63 are daisy-chain connected, there is a difference in the timing at which each slave FPGA 63 receives the periodic communication trigger signal from the master FPGA 62 .

[0068] In response to this, each slave FPGA 63 adjusts the timing of turning on the periodic communication interrupt signal relative to the periodic communication trigger signal based on the internal clock signal (according to the number of clocks) so that the timing of turning on the periodic communication interrupt signal is synchronized between the slave FPGAs 63.

[0069] This allows each slave FPGA 63 to synchronize the timing of executing an interrupt to a downstream device (in this case, the control MCU 64) based on an internal clock signal with other slave FPGAs 63. For example, the timing at which each slave FPGA 63 acquires control data for the actuator 21 of each joint is synchronized, and the control of each joint of the robot arm 11 can be synchronized.

[0070] <<2. Second Embodiment>> Next, a second embodiment of the present technology will be described with reference to FIGS.

[0071] FIG. 7 shows an example of the external configuration of a robot hand 101 that can be attached to and detached from the robot arm 11 of FIG.

[0072] The robot hand 101 is attached to a base portion 111 so that the gripper 112L and the gripper 112R face each other.

[0073] The gripper 112L is driven by an actuator 113L, and the gripper 112R is driven by an actuator 113R.

[0074] A proximity sensor 114C is provided on the inner surface (the surface that grips the target object) of the base portion 111. A proximity sensor 114L is provided on the inner surface (the surface that grips the target object) of the gripper 112L. A proximity sensor 114R is provided on the inner surface (the surface that grips the target object) of the gripper 112R.

[0075] The proximity sensors 114C, 114L, and 114R each include a plurality of sensors, each capable of detecting distance information and sensor sensitivity information. The proximity sensors 114C, 114L, and 114R can measure the distance to an object to be grasped. This allows the robotic hand 101 to be controlled so that it grasps the object at its center position rather than by its edge, thereby improving the success rate of grasping.

[0076] A tactile sensor 115L is provided on the inner surface of the gripper 112L. A tactile sensor 115R is provided on the inner surface of the gripper 112R. The tactile sensors 115L and 115R detect slippage of the object by recognizing the deformation direction of a gel placed on the surface using a pressure distribution sensor with multiple nodes that is placed below the gel. This enables, for example, the robot hand 101 to grasp an object with minimal force, enabling it to grasp the object softly.

[0077] Hereinafter, when there is no need to distinguish between the grippers 112L and 112R, they will simply be referred to as grippers 112. Hereinafter, when there is no need to distinguish between the proximity sensors 114C, 114L, and 114R, they will simply be referred to as proximity sensors 114. Hereinafter, when there is no need to distinguish between the tactile sensors 115L and 115R, they will simply be referred to as tactile sensors 115.

[0078] FIG. 8 shows an example of the configuration of a hand electrical system 151 a which is a first embodiment of an electrical system when the robot hand 101 is attached to the robot arm 11 .

[0079] The hand electrical system 151a includes the arm electrical system 51 described above with reference to FIG. 3, the actuator 113R, the actuator 113L, the proximity sensor 114R, the proximity sensor 114L, the proximity sensor 114C, the tactile sensor 115R, and the tactile sensor 115L described above with reference to FIG. 8, as well as slave FPGAs 161-1 to 161-5, control MCU 162-1, control MCU 162-3, motor drivers 163R, and motor drivers 163L.

[0080] The slave FPGAs 161-1 to 161-5 are daisy-chained via communication lines to the slave FPGA 63-7 of the arm electrical system 51. Therefore, the slave FPGAs 63-1 to 63-7 and the slave FPGAs 161-1 to 161-5 are daisy-chained to the master FPGA 62 of the arm electrical system 51.

[0081] The control MCU 162-1, the motor driver 163R, and the actuator 113R are connected in series to the slave FPGA 161-1. The slave FPGA 161-1, the control MCU 162-1, the motor driver 163R, and the actuator 113R are used to control the joints of the gripper 112R.

[0082] The proximity sensor 114R and the tactile sensor 115R are connected to the slave FPGA 161-2.

[0083] The control MCU 162-3, the motor driver 163L, and the actuator 113L are connected in series to the slave FPGA 161-3. The slave FPGA 161-3, the control MCU 162-3, the motor driver 163L, and the actuator 113L are used to control the joints of the gripper 112L.

[0084] The proximity sensor 114L and the tactile sensor 115L are connected to the slave FPGA 161-4.

[0085] The proximity sensor 114C is connected to the slave FPGA 161-5.

[0086] Hereinafter, when there is no need to distinguish between the slave FPGAs 161-1 to 161-5, they will be simply referred to as slave FPGAs 161.

[0087] The proximity sensor 114 has many sensors, and stores distance information and sensor sensitivity information for each sensor, resulting in a large volume of sensor data. The tactile sensor 115 has a pressure distribution sensor with many nodes, and stores pressure information for each node, resulting in a large volume of sensor data.

[0088] 4 and 5, unlike conventional industrial fieldbuses, there is no limit to the data size of the payload area. Therefore, the write packet and read packet can easily store sensor data from the proximity sensor 114 and sensor data from the tactile sensor 115. Therefore, as shown in FIG. 8, the daisy-chain connection of the slave FPGA can be extended to the robot hand 101 side.

[0089] In addition, in the hand electrical system 151a, the proximity sensor 114 and the tactile sensor 115 are directly connected to the slave FPGA 161. Therefore, each slave FPGA 161 can acquire large amounts of sensor data from the proximity sensor 114 and the tactile sensor 115 at high speed.

[0090] On the other hand, similar to the arm electrical system 51, each slave FPGA 161 may acquire sensor data from the proximity sensor 114 and the tactile sensor 115 via the control MCU.

[0091] 9 shows an example of the configuration of a hand electrical system 151b in which each slave FPGA 161 acquires sensor data from the proximity sensor 114 and tactile sensor 115 via the control MCU. In the figure, parts corresponding to those in the hand electrical system 151a in FIG. 8 are given the same reference numerals, and their explanation will be omitted where appropriate.

[0092] Comparing the hand electric system 151b with the hand electric system 151a, the hand electric system 151b differs in that a control MCU 162-2, a control MCU 162-4, and a control MCU 162-5 are added.

[0093] The controlling MCU 162-2 is connected to the slave FPGA 161-2, the proximity sensor 114R, and the tactile sensor 115R. The slave FPGA 161-2 acquires sensor data from the proximity sensor 114R and the tactile sensor 115R via the controlling MCU 162-2.

[0094] The controlling MCU 162-4 is connected to the slave FPGA 161-4, the proximity sensor 114L, and the tactile sensor 115L. The slave FPGA 161-4 acquires sensor data from the proximity sensor 114L and the tactile sensor 115L via the controlling MCU 162-4.

[0095] The control MCU 162-5 is connected to the slave FPGA 161-5 and the proximity sensor 114C. The slave FPGA 161-5 acquires sensor data from the proximity sensor 114C via the control MCU 162-5.

[0096] <<3. Third Embodiment>> Next, a third embodiment of the present technology will be described with reference to FIGS. 10 to 19 .

[0097] <Configuration Example of Electrical System 201> FIG. 10 shows a configuration example of an electrical system 201 that is an information processing system equipped with a communication function and that is provided in a robot (not shown) to which the present technology is applied.

[0098] The robot is assumed to have, for example, a head, a waist, a right arm, a left arm, and legs. The legs are assumed to be, for example, carts.

[0099] The electrical system 201 includes a host PC 211, a master FPGA 212, slave FPGAs 213A-0 to 213A-N, slave FPGAs 213B-0 to 213B-N, slave FPGAs 213C-0 to 213C-N, slave FPGAs 213D-0 to 213D-N, control MCUs 214A-0 to 214A-N, control MCUs 214B-0 to 214B-N, control MCUs 214C-0 to 214C-N, and control MCUs 214D-0 to 214D-N.

[0100] In addition, in this figure, motor drivers, actuators, sensors, etc. connected downstream of control MCU 214A-0 to control MCU 214A-N, control MCU 214B-0 to control MCU 214B-N, control MCU 214C-0 to control MCU 214C-N, and control MCU 214D-0 to control MCU 214D-N are omitted from the illustration.

[0101] Hereinafter, when there is no need to distinguish between the slave FPGAs 213A-0 to 213A-N, they will simply be referred to as slave FPGAs 213A. Hereinafter, when there is no need to distinguish between the slave FPGAs 213B-0 to 213B-N, they will simply be referred to as slave FPGAs 213B. Hereinafter, when there is no need to distinguish between the slave FPGAs 213C-0 to 213C-N, they will simply be referred to as slave FPGAs 213C. Hereinafter, when there is no need to distinguish between the slave FPGAs 213D-0 to 213D-N, they will simply be referred to as slave FPGAs 213D. Hereinafter, when there is no need to individually distinguish between the slave FPGAs 213A-0 to 213A-N, 213B-0 to 213B-N, 213C-0 to 213C-N, and 213D-0 to 213D-N, they will be simply referred to as slave FPGAs 213.

[0102] Hereinafter, when there is no need to distinguish between the control MCUs 214A-0 to 214A-N, they will simply be referred to as control MCUs 214A. Hereinafter, when there is no need to distinguish between the control MCUs 214B-0 to 214B-N, they will simply be referred to as control MCUs 214B. Hereinafter, when there is no need to distinguish between the control MCUs 214C-0 to 214C-N, they will simply be referred to as control MCUs 214C. Hereinafter, when there is no need to distinguish between the control MCUs 214D-0 to 214D-N, they will simply be referred to as control MCUs 214D. Hereinafter, when there is no need to individually distinguish between the control MCU 214A-0 to control MCU 214A-N, control MCU 214B-0 to control MCU 214B-N, control MCU 214C-0 to control MCU 214C-N, and control MCU 214D-0 to control MCU 214D-N, they will be simply referred to as control MCU 214.

[0103] 1, the host PC 211 is configured by, for example, an IC in which an FPGA and an SoC are integrated. The host PC 211 controls the operation of a robot equipped with the electrical system 201. The host PC 211 communicates with each control MCU 214 via a master FPGA 212 and a slave FPGA 213.

[0104] High-speed serial communication such as PCI Express is used for communication between the host PC 211 and the master FPGA 212. This makes it possible to send and receive large amounts of data, including branching.

[0105] In the electrical system 201, the communication lane branches from the master FPGA 212 into four lanes, Lane A to Lane D, and each communication lane is star-connected to the master FPGA 212. Lane A is, for example, a communication lane for the right arm. Lane B is, for example, a communication lane for the left arm. Lane C is, for example, a communication lane for the head, waist, and arms. Lane D is, for example, a communication lane for the legs.

[0106] The slave FPGAs 213A-0 to 213A-N are daisy-chain connected to the master FPGA 212 to form lane A. The control MCUs 214A-i (i=0 to N) are connected to the slave FPGAs 213A-i (i=0 to N), respectively.

[0107] The slave FPGAs 213B-0 to 213B-N are daisy-chain connected to the master FPGA 212 to form lane B. The control MCUs 214B-i (i = 0 to N) are connected to the slave FPGAs 213B-i (i = 0 to N), respectively.

[0108] The slave FPGAs 213C-0 to 213C-N are daisy-chain connected to the master FPGA 212 to form lane C. The control MCUs 214C-i (i=0 to N) are connected to the slave FPGAs 213C-i (i=0 to N), respectively.

[0109] The slave FPGAs 213D-0 to 213D-N are daisy-chain connected to the master FPGA 212 to form lane D. The control MCUs 214D-i (i = 0 to N) are connected to the slave FPGAs 213D-i (i = 0 to N), respectively.

[0110] <Configuration Example of Memory Space of Each FPGA> Each FPGA (master FPGA 212 and slave FPGA 213) is equipped with RAM, and the RAM of each FPGA configures a memory space that each FPGA can access individually. Each FPGA temporarily stores data to be transmitted (write data and read data) in its own memory space before transmitting it. The memory space of each FPGA includes a write area and a read area.

[0111] FIG. 11 shows an example of the configuration of a write area in the memory space of the master FPGA 212.

[0112] The write area is divided into areas for each communication lane. Specifically, the write area includes an area for lane A, an area for lane B, an area for lane C, and an area for lane D. The lane A area is an area for storing write data to be sent to each slave FPGA 213A in lane A. The lane B area is an area for storing write data to be sent to each slave FPGA 213B in lane B. The lane C area is an area for storing write data to be sent to each slave FPGA 213C in lane C. The lane D area is an area for storing write data to be sent to each slave FPGA 213D in lane D.

[0113] The lane A area is divided into areas for each function supported by each slave FPGA 213 of communication lane A. Specifically, the lane A area includes areas for function 1 to function 4. The function 1 area is an area where write data used by function 1 is stored. The function 2 area is an area where write data used by function 2 is stored. The function 3 area is an area where write data used by function 3 is stored. The function 4 area is an area where write data used by function 4 is stored.

[0114] The classification of functions can be set arbitrarily. For example, the function areas can be classified into areas for one-shot communication, actuator control using periodic communication, tactile sensor using periodic communication, proximity sensor using periodic communication, etc.

[0115] The size of the area for function 1 (payload size) is large enough to store write data for function 1 for the number of slave FPGAs 213 in communication lane A. For example, the area for function 1 can store, at one time, the write data for function 1 addressed to each slave FPGA 213A in communication lane A, which is stored in the payload area of ​​the write packet for function 1 ( FIG. 4 ).

[0116] The size of the area for function 2 (payload size) is large enough to store write data for function 2 equal to the number of slave FPGAs 213 in communication lane A. For example, the area for function 2 can store, at one time, write data for function 2 addressed to each slave FPGA 213A in communication lane A, which is stored in the payload area of ​​the write packet for function 2.

[0117] The size of the area for function 3 (payload size) is large enough to store write data for function 3 equal to the number of slave FPGAs 213 in communication lane A. For example, the area for function 3 can store, at one time, write data for function 3 addressed to each slave FPGA 213A in communication lane A, which is stored in the payload area of ​​the write packet for function 3.

[0118] The size of the area for function 4 (payload size) is large enough to store write data for function 4 equal to the number of slave FPGAs 213 in communication lane A. For example, the area for function 4 can store, at one time, the write data for function 4 addressed to each slave FPGA 213A in communication lane A, which is stored in the payload area of ​​the write packet for function 4.

[0119] The area for lane B has the same configuration as the area for lane A. That is, the area for lane B has areas for functions 1 to 4. Then, the write data to be transmitted to each slave FPGA 213B of communication lane B is divided by function and stored in the area for lane B.

[0120] The area for lane C has the same configuration as the area for lane A and the area for lane B. That is, the area for lane C has areas for functions 1 to 4. Then, the write data to be transmitted to each slave FPGA 213C of communication lane C is divided by function and stored in the area for lane C.

[0121] The area for lane D has the same configuration as the areas for lane A to lane C. That is, the area for lane D has areas for function 1 to function 4. Then, the write data to be transmitted to each slave FPGA 213D of communication lane D is divided by function and stored in the area for lane D.

[0122] FIG. 12 shows an example of the configuration of the write area in the memory space of each slave FPGA 213, which corresponds to the write area in the memory space of the master FPGA 212 in FIG.

[0123] The write area of ​​each slave FPGA 213 in each communication lane is divided into areas for the functions supported by each slave FPGA 213. Specifically, the write area of ​​each slave FPGA 213 includes areas for functions 1 to 4.

[0124] The area for function 1 stores write data for function 1 of the corresponding slave FPGA 213 transmitted from the master FPGA 212 .

[0125] The area for function 2 stores write data for function 2 of the corresponding slave FPGA 213 transmitted from the master FPGA 212 .

[0126] The area for function 3 stores write data for function 3 of the corresponding slave FPGA 213 transmitted from the master FPGA 212 .

[0127] The area for function 4 stores write data for function 4 of the corresponding slave FPGA 213 transmitted from the master FPGA 212 .

[0128] FIG. 13 shows an example of the configuration of the read area of ​​the memory space in each slave FPGA 213.

[0129] The read area of ​​each slave FPGA 213 in each communication lane is divided into areas for the functions supported by each slave FPGA 213. Specifically, the read area of ​​each slave FPGA 213 includes areas for functions 1 to 4.

[0130] The area for function 1 stores read data for function 1 to be sent to the master FPGA 212 .

[0131] The area for function 2 stores read data for function 2 to be sent to the master FPGA 212 .

[0132] The area for function 3 stores read data for function 3 to be transmitted to the master FPGA 212 .

[0133] The area for function 4 stores read data for function 4 to be sent to the master FPGA 212 .

[0134] FIG. 14 shows an example of the configuration of a read area in the memory space of the master FPGA 212, which corresponds to the read area in the memory space of each slave FPGA 213 in FIG.

[0135] The read area is divided into areas for each communication lane. Specifically, the read area includes an area for lane A, an area for lane B, an area for lane C, and an area for lane D. The lane A area is an area for storing read data received from each slave FPGA 213A in lane A. The lane B area is an area for storing read data received from each slave FPGA 213B in lane B. The lane C area is an area for storing read data received from each slave FPGA 213C in lane C. The lane D area is an area for storing read data received from each slave FPGA 213D in lane D.

[0136] The lane A area is divided into areas for each function supported by each slave FPGA 213 of communication lane A. Specifically, the lane A area includes areas for function 1 to function 4. The function 1 area is an area where read data used by function 1 is stored. The function 2 area is an area where read data used by function 2 is stored. The function 3 area is an area where read data used by function 3 is stored. The function 4 area is an area where read data used by function 4 is stored.

[0137] The size of the area for function 1 (payload size) is large enough to store read data for function 1 equal to the number of slave FPGAs 213 in communication lane A. For example, the area for function 1 can simultaneously store the read data for function 1 stored in the payload area of ​​each read packet for function 1 ( FIG. 5 ) received from each slave FPGA 213A in communication lane A. As will be described later, the read data for function 1 received from each slave FPGA 213A in communication lane A is stored in the area for function 1 in the order in which it was received.

[0138] The size of the area for function 2 (payload size) is large enough to store read data for function 2 equal to the number of slave FPGAs 213 in communication lane A. For example, the area for function 2 can simultaneously store the read data for function 2 stored in the payload area of ​​each read packet for function 2 received from each slave FPGA 213A in communication lane A. As will be described later, the read data for function 2 received from each slave FPGA 213A in communication lane A is stored in the area for function 2 in the order in which it was received.

[0139] The size of the area for function 3 (payload size) is large enough to store read data for function 3 equal to the number of slave FPGAs 213 in communication lane A. For example, the area for function 3 can simultaneously store the read data for function 3 stored in the payload area of ​​each read packet for function 3 received from each slave FPGA 213A in communication lane A. As will be described later, the read data for function 3 received from each slave FPGA 213A in communication lane A is stored in the area for function 3 in the order in which it was received.

[0140] The size of the area for function 4 (payload size) is large enough to store read data for function 4 equal to the number of slave FPGAs 213 in communication lane A. For example, the area for function 4 can simultaneously store the read data for function 4 stored in the payload area of ​​each read packet for function 4 received from each slave FPGA 213A in communication lane A. As will be described later, the read data for function 4 received from each slave FPGA 213A in communication lane A is stored in the area for function 4 in the order in which it was received.

[0141] The area for lane B has the same configuration as the area for lane A. That is, the area for lane B has areas for functions 1 to 4. The read data received from each slave FPGA 213B of lane B is divided by function in the order in which it is received and stored in the area for lane B.

[0142] The area for lane C has the same configuration as the area for lane A and the area for lane B. That is, the area for lane C has areas for functions 1 to 4. The read data received from each slave FPGA 213B of lane C is divided by function in the order in which it is received and stored in the area for lane C.

[0143] The area for lane D has the same configuration as the areas for lane A to lane C. That is, the area for lane C has areas for function 1 to function 4. The read data received from each slave FPGA 213B of lane D is stored in the area for lane D, separated by function in the order in which it is received.

[0144] For example, the master FPGA 212 generates write packets (FIG. 4) for each communication lane and for each function. That is, each write packet stores write data for a target function and is addressed to each slave FPGA 213 connected to the target communication lane. The master FPGA 212 transmits the generated write packet to the target communication lane.

[0145] For example, write data for a plurality of functions may be stored in one write packet.

[0146] For example, each slave FPGA 213 generates a read packet (FIG. 4) for each function. That is, each write packet stores read data for the corresponding function. Each slave FPGA 213 transmits the generated read packet to the master FPGA 212.

[0147] For example, read data for a plurality of functions may be stored in one read packet.

[0148] Here, the number of branching communication lanes, the number of slave FPGAs 213 in each communication lane, the number of function areas (number of types of functions), the size of write data for each function, and the size of read data for each function can be set arbitrarily.

[0149] Furthermore, in the above description, an example is shown in which the number of slave FPGAs 213 in each communication lane is the same, but this does not necessarily have to be the case. For example, there may be a communication lane with one slave FPGA 213. In the above description, an example is shown in which the number of types of functions in each communication lane is the same, but this does not necessarily have to be the case. For example, the functions of each communication lane may differ from one another.

[0150] For example, the host PC 211 can arbitrarily set the number of branching communication lanes and the number of slave FPGAs 213 for each communication lane.

[0151] Furthermore, for example, the host PC 211 can arbitrarily set the configuration of the memory space of the master FPGA 212 and each slave FPGA 213. That is, for example, the host PC 211 can set the write area, read area, communication lane areas in the write area, communication lane areas in the read area, and each function area in each communication lane area in the memory space of the master FPGA 212. For example, the host PC 211 can set the write area, read area, function areas in the write area, and each function area in the read area in the memory space of each slave FPGA 213.

[0152] Specifically, for example, the host PC 211 writes the number of branching communication lanes and the number of slave FPGAs 213 for each communication lane to a register of the master FPGA 212. The host PC 211 writes the write start address of each lane area in the write area of ​​the master FPGA 212, the write start address of each function area within each lane area, and the payload size of each function area to a register of the master FPGA 212. The host PC 211 writes the write start address of each lane area in the read area of ​​the master FPGA 212, the write start address of each function area within each lane area, and the payload size of each function area to a register of the master FPGA 212.

[0153] As a result, a write area and a read area are created in the memory space of the master FPGA 212 .

[0154] For example, the host PC 211 writes the write start address of each function area in the write area of ​​each slave FPGA 213 and the payload size of each function area to a register of the master FPGA 212. For example, the host PC 211 writes the write start address of each function area in the read area of ​​each slave FPGA 213 and the payload size of each function area to a register of the master FPGA 212.

[0155] For example, based on the information written to the register, the master FPGA 212 writes the write start address of each function area in the write area and the payload size of each function area to the register of each slave FPGA 213. The master FPGA 212 writes the write start address of each function area in the read area and the payload size of each function area to the register of each slave FPGA 213.

[0156] As a result, a write area and a read area are created in the memory space of each slave FPGA 213 .

[0157] In this way, the efficiency of data transmission within the robot can be improved.

[0158] For example, the communication lanes are branched and data is allocated to each communication lane. This eliminates the need to transmit all data to each slave FPGA 213, and only the necessary data is transmitted and received in an optimized manner in each communication lane. This allows the communication bandwidth to be used efficiently in each communication lane.

[0159] Furthermore, the communication lanes can be appropriately branched depending on the configuration of the robot, such as a single-arm robot, a dual-arm robot, a legged robot, or a humanoid robot. For example, in the case of a four-legged robot, the communication lanes are branched into the right front leg, the left front leg, the right hind leg, and the left hind leg. This reduces the amount of wiring required for the robot, improving the degree of freedom in robot design. It also allows the robot to be made smaller.

[0160] For example, by setting the number of communication lanes for a single-arm robot to 1 and the number of communication lanes for a dual-arm robot to 2, the configuration and control method of each arm can be made common between the single-arm robot and the dual-arm robot.

[0161] Furthermore, by providing communication protocols not only between the host PC 211 and the control MCU 214 but also between the master FPGA 212 and each slave FPGA 213, each slave FPGA 213 can efficiently send and receive only its own data.

[0162] <Method for Controlling Readout Area of ​​Master FPGA 212> Next, a method for controlling the readout area of ​​the master FPGA 212 will be described with reference to FIGS. 15 and 16. FIG.

[0163] The order in which the read data is transmitted from each slave FPGA 213 is not set.

[0164] In response to this, as shown in FIG. 15, the master FPGA 212 separates the read data received from each slave FPGA 213 by function in the order in which it is received, and stores the data in the respective function areas of the read area.

[0165] Therefore, for example, it is conceivable that the master FPGA 212 may receive read data from duplicate slave FPGAs 213 for a certain function before receiving read data from all slave FPGAs 213 in the communication lane.

[0166] For example, FIG. 16 shows an example in which six slave FPGAs 213 are connected to a certain communication lane, and the master FPGA 212 receives data #0 to #5 for function 1 from each slave FPGA 213.

[0167] For example, first, when the master FPGA 212 receives data #0, it stores it in the first area of ​​the area for function 1 (hereinafter referred to as the slave 0 area).

[0168] Next, when the master FPGA 212 receives data #1, it stores it in the area next to the slave 0 area in the area for function 1 (hereinafter referred to as the slave 1 area).

[0169] Next, when the master FPGA 212 receives data #2, it stores it in the area next to the slave 1 area in the area for function 1 (hereinafter referred to as the slave 2 area).

[0170] Next, when the master FPGA 212 receives data #0, it stores it in the slave 0 area for function 1. That is, the address where the read data is written is rewound, and data #0 stored in the slave 0 area is overwritten with the subsequently received data #0.

[0171] Next, when the master FPGA 212 receives data #5, it stores it in the area next to the slave 2 area in the area for function 1 (hereinafter referred to as the slave 3 area). That is, since data #5 does not overlap with the read data received so far, the address to write the read data is restored (hereinafter referred to as address skipping), and the data is stored in slave area 3 next to slave area 2 where the received read data is stored.

[0172] Next, when the master FPGA 212 receives data #3, it stores it in the area next to the slave 3 area in the area for function 1 (hereinafter referred to as the slave 4 area).

[0173] Next, when the master FPGA 212 receives data #4, it stores it in the area next to the slave 4 area in the area for function 1 (hereinafter referred to as the slave 5 area).

[0174] At this point, all of data #0 to #5 for function 1 have been received, and a predetermined size of read data for function 1 has been stored in the area for function 1.

[0175] The read data stored in the read area of ​​the master FPGA 212 is read by the host PC 211. Therefore, if the read data in the read area of ​​the master FPGA 212 is updated before the host PC 211 completes reading, the host PC 211 will end up reading the updated read data instead of the read data before the update.

[0176] For example, if the master FPGA 212 subsequently receives data #0 and stores it as is in the slave 0 area for function 1, there is a risk that the updated data #0 will be read out instead of the pre-update data #0.

[0177] 16, the readout area of ​​the master FPGA 212 may be provided on two surfaces, surface A and surface B. The readout areas on surfaces A and B have the same configuration.

[0178] For example, when data #0 to #5 for function 1 are stored in the area for function 1 on side A, if the master FPGA 212 receives data 0 for function 1, it stores it in the slave 0 area of ​​the area for function 1 on side B.

[0179] Next, when the master FPGA 212 receives data 1, it stores it in the slave 1 area of ​​the area for function 1 on the B side.

[0180] This prevents the read data stored in the area for function 1 on side A from being updated before being read by the host PC 211 .

[0181] For example, the host PC 211 attempts to read data by specifying an address in a read area of ​​the master FPGA 212 without regard to sides A and B. In response to this, the master FPGA 212 controls the reading of data from sides A and B by offsetting the address specified by the host PC 211 as necessary.

[0182] <Periodic Communication Processing> Next, with reference to the flowchart of FIG. 17, the cyclic communication processing executed by the electrical system 201 of FIG. 10 will be described.

[0183] This process starts, for example, when the power supply to the robot body including the electrical system 201 is turned on.

[0184] In step S1, the host PC 211 and the master FPGA 212 are powered on.

[0185] In step S2, communication between the host PC 211 and the master FPGA 212 is established.

[0186] In step S3, the host PC 211 sets the configuration of the memory space of each FPGA.

[0187] For example, the host PC 211 writes the number of branched communication lanes and the number of slave FPGAs 213 for each communication lane to a register of the master FPGA 212. The host PC 211 writes the write start address of each lane area in the write area of ​​the master FPGA 212, the write start address of each function area within each lane area, and the payload size of each function area to a register of the master FPGA 212. The host PC 211 writes the write start address of each lane area in the read area on side A of the master FPGA 212, the write start address of each function area within each lane area, and the payload size of each function area to a register of the master FPGA 212. The host PC 211 writes the write start address of each lane area in the read area on side B of the master FPGA 212, the write start address of each function area within each lane area, and the payload size of each function area to a register of the master FPGA 212.

[0188] As a result, a write area and a read area are created in the memory space of the master FPGA 212 .

[0189] The host PC 211 writes the write start address of the write area of ​​each slave FPGA 213 and the payload size of each function area to a register of the master FPGA 212. For example, the host PC 211 writes the write start address of the read area of ​​each slave FPGA 213 and the payload size of each function area to a register of the master FPGA 212.

[0190] The host PC 211 writes the communication cycle of each communication lane to a register of the master FPGA 212 .

[0191] Then, the process proceeds to step S6.

[0192] In step S4, in parallel with the processing of step S3, the slave FPGA 213 and the controlling MCU 214 are powered on. At this time, for example, an auxiliary power switch may be used to power on the slave FPGA 213 and the controlling MCU 214. Alternatively, for example, the power of the slave FPGA 213 and the controlling MCU 214 may be powered on after the master FPGA 212 establishes communication with the host PC 211.

[0193] In step S5, communication between the master FPGA 212 and the slave FPGA 213 is initialized, thereby confirming that communication between them has been established.

[0194] For example, based on the information written to the register, the master FPGA 212 writes the write start address of the write area and the payload size of each function area to the register of each slave FPGA 213. The master FPGA 212 writes the write start address of the read area and the payload size of each function area to the register of each slave FPGA 213.

[0195] As a result, a write area and a read area are created in the memory space of each slave FPGA 213 .

[0196] Then, the process proceeds to step S6.

[0197] In step S6, the host PC 211 instructs the master FPGA 212 to issue a periodic communication.

[0198] In step S7, the master FPGA 212 determines whether or not a communication error has occurred. If it is determined that a communication error has not occurred, the process proceeds to step S8.

[0199] In step S8, the master FPGA 212 transmits write packets at a predetermined cycle. Specifically, the master FPGA 212 transmits write packets in the format described above with reference to Fig. 4 to each communication lane at a predetermined cycle. At this time, the master FPGA 212 transmits write packets for each slave FPGA 213 of each communication lane separately for each communication lane.

[0200] In step S9, the host PC 211 determines whether or not to terminate the communication. If it is determined not to terminate the communication, the process returns to step S7.

[0201] Thereafter, the processes of steps S7 to S9 are repeatedly executed until it is determined in step S7 that a communication error has occurred or until it is determined in step S9 that communication should be terminated.

[0202] On the other hand, if it is determined in step S7 that a communication error has occurred, the process proceeds to step S10.

[0203] In step S10, the master FPGA 212 notifies the host PC 211 of a communication error.

[0204] Thereafter, the process returns to step S6, and steps S6 to S10 are repeatedly executed until it is determined in step S9 that communication should be terminated.

[0205] On the other hand, if it is determined in step S9 that the communication is to be terminated, the process proceeds to step S11.

[0206] In step S11, the host PC 211 instructs the master FPGA 212 to stop periodic communication.

[0207] In response to this, the master FPGA 212 stops the periodic communication.

[0208] Then, the periodic communication process ends.

[0209] <Method for Handling Large-Volume Data Transmission> Next, a method for handling large-volume data transmission between FPGAs will be described with reference to FIGS. 18 and 19. FIG.

[0210] For example, when the slave FPGA 213 transmits a large amount of data such as video data from a camera, it is conceivable that the video data cannot be stored due to insufficient memory space within the slave FPGA 213. In this case, for example, an external memory may be connected to the slave FPGA 213, and at least one of the write area and the read area may be provided in the memory space configured by the external memory.

[0211] FIG. 18 shows an example in which a stereo camera 301 including a camera 301L and a camera 301R is connected to a slave FPGA 213, and the slave FPGA 213 transmits video data of the stereo camera 301.

[0212] An external memory 302 configured by, for example, a RAM is connected to the slave FPGA 213. For example, read data that exceeds the capacity of the memory space in the slave FPGA 213 is stored in the memory 302. In this case, the memory space in the slave FPGA 213 and the memory space of the memory 302 may be used together, or only the memory space of the memory 302 may be used.

[0213] For example, if the frame rate of the stereo camera 301 is 60 Hz, the video data is updated approximately every 16 ms.

[0214] On the other hand, if the control cycle of the entire body of a robot equipped with the slave FPGA 213 is 1 kHz, for example, the slave FPGA 213 transmits read data to the master FPGA 212 at 1 ms intervals. Therefore, the slave FPGA 213 transmits one frame of video data to the master FPGA 212 at 16 ms intervals, which is 16 cycles.

[0215] In this case, for example, as shown in FIG. 19, the memory space formed by the memory 302 is divided into 16 areas, ie, areas 302A-1 to 302A-16.

[0216] 13, to the memory 302. Furthermore, the slave FPGA 213 may store the read data of the video data to be transmitted to the master FPGA 212 in the order of the area 302A-1, the area 302A-2, ..., the area 302A-16 of the memory 302.

[0217] Furthermore, the slave FPGA 213 may divide the video data stored in the memory 302 into 16 parts and transmit the divided data to the master FPGA 212. That is, the slave FPGA 213 may transmit the video data divided and stored in the areas 302A-1 to 302A-16 to the master FPGA 212 individually.

[0218] This makes it possible to reduce the capacity of the memory 302 required for transmitting video data.

[0219] As described above, the present technology can improve the efficiency of data transmission within a robot. For example, it can reduce the amount of wiring required for the robot and transmit large amounts of data. This can be applied to robots that operate using AI or machine learning based on multimodal information obtained from multiple sensors such as cameras.

[0220] <<4. Modifications>> Modifications of the above-described embodiments of the present technology will now be described.

[0221] In the above description, an example has been shown in which the master communication unit and the slave communication unit are configured by FPGAs, but they may also be configured by LSIs or the like.

[0222] For example, when the number of communication lanes is 1, the write area of ​​the master FPGA 212 in Fig. 11 does not have to be divided for each communication lane. Similarly, when the number of communication lanes is 1, the read area of ​​the master FPGA 212 in Fig. 14 does not have to be divided for each communication lane.

[0223] For example, when there is only one type of function, the write area of ​​the master FPGA 212 in Fig. 11 and the write area of ​​the slave FPGA 213 in Fig. 12 do not need to be separated by function. Similarly, when there is only one type of function, the read area of ​​the slave FPGA 213 in Fig. 13 and the read area of ​​the master FPGA 212 in Fig. 14 do not need to be separated by function.

[0224] For example, in the embodiment of FIG. 16, the readout area of ​​the master FPGA 212 may be provided on three or more sides.

[0225] For example, the host PC does not necessarily have to be provided inside the robot, but may be provided outside the robot.Furthermore, for example, the functions of the host PC may be divided, with some of the functions being provided inside the robot and the rest being provided outside the robot.

[0226] The robots to which the present technology can be applied are not particularly limited. For example, the present technology is particularly effective for robots that require reduced wiring and miniaturization. Examples of such robots include arm-type robots with one or more joints, leg-type robots, humanoid robots, and biological robots.

[0227] <<5. Others>> <Example of Computer Configuration> The above-described series of processes can be executed by hardware or software. When the series of processes is executed by software, the programs that make up the software are installed on a computer. Here, the computer includes a computer built into dedicated hardware, and a general-purpose personal computer, for example, that can execute various functions by installing various programs.

[0228] FIG. 20 is a block diagram showing an example of the hardware configuration of a computer that executes the above-described series of processes by a program.

[0229] In the computer 1000 , a CPU (Central Processing Unit) 1001 , a ROM (Read Only Memory) 1002 , and a RAM (Random Access Memory) 1003 are interconnected by a bus 1004 .

[0230] An input / output interface 1005 is further connected to the bus 1004. An input unit 1006, an output unit 1007, a storage unit 1008, a communication unit 1009, and a drive 1010 are connected to the input / output interface 1005.

[0231] The input unit 1006 includes input switches, buttons, a microphone, an image sensor, etc. The output unit 1007 includes a display, a speaker, etc. The storage unit 1008 includes a hard disk, a non-volatile memory, etc. The communication unit 1009 includes a network interface, etc. The drive 1010 drives removable media 1011 such as a magnetic disk, an optical disk, a magneto-optical disk, or a semiconductor memory.

[0232] In the computer 1000 configured as described above, the CPU 1001 performs the above-described series of processes by, for example, loading a program recorded in the memory unit 1008 into the RAM 1003 via the input / output interface 1005 and the bus 1004 and executing it.

[0233] The program executed by the computer 1000 (CPU 1001) can be provided by being recorded on a removable medium 1011 such as a package medium, for example. The program can also be provided via a wired or wireless transmission medium such as a local area network, the Internet, or digital satellite broadcasting.

[0234] In the computer 1000, the program can be installed in the storage unit 1008 via the input / output interface 1005 by inserting the removable medium 1011 into the drive 1010. The program can also be received by the communication unit 1009 via a wired or wireless transmission medium and installed in the storage unit 1008. Alternatively, the program can be installed in the ROM 1002 or the storage unit 1008 in advance.

[0235] The program executed by the computer may be a program that processes in chronological order according to the order described in this specification, or may be a program that processes in parallel or at the required timing, such as when called.

[0236] In this specification, a system refers to a collection of multiple components (devices, modules (components), etc.), regardless of whether all of the components are housed in the same housing. Therefore, multiple devices housed in separate housings and connected via a network, and a single device housed in a single housing with multiple modules, are both systems.

[0237] Furthermore, the embodiments of the present technology are not limited to the above-described embodiments, and various modifications are possible within the scope of the gist of the present technology.

[0238] For example, the present technology can be configured as a cloud computing system in which a single function is shared and processed collaboratively by a plurality of devices via a network.

[0239] Furthermore, each step described in the above flowchart can be executed by one device, or can be shared and executed by a plurality of devices.

[0240] Furthermore, when one step includes multiple processes, the multiple processes included in that one step can be executed by one device or can be shared and executed by multiple devices.

[0241] <Examples of Combinations of Configurations> The present technology can also have the following configurations.

[0242] (1) A communication device provided on a robot, comprising: a master communication unit; a plurality of slave communication units daisy-chain connected to the master communication unit; a master memory space that is a memory space accessible by the master communication unit; and a plurality of slave memory spaces that are memory spaces individually accessible by each of the slave communication units, wherein the master memory space includes a master write area that is an area for storing write data that is data to be transmitted to each of the slave communication units, and a master read area that is an area for storing read data that is data received from each of the slave communication units, and each of the slave memory spaces includes a slave write area that is an area for storing the write data received from the master communication unit, and a slave read area that is an area for storing the read data to be transmitted to the master communication unit. (2) The communication device described in (1), wherein each of the slave communication units is connected to the master communication unit along a plurality of communication lanes, and the plurality of slave communication units are daisy-chain connected to the master communication unit in at least one of the communication lanes, and the master write area includes a plurality of lane write areas that are areas separated for each of the communication lanes, and the master read area includes a plurality of lane read areas that are areas separated for each of the communication lanes. (3) The communication device described in (2), wherein each of the lane write areas includes a plurality of master function write areas that are areas separated for each function, and each of the lane read areas includes a plurality of master function read areas that are areas separated for each function. (4) The communication device described in (3), wherein each of the master function write areas has a size capable of storing the write data for the corresponding function equal to the number of the slave communication units connected to the corresponding communication lane, and each of the master function read areas has a size capable of storing the read data for the corresponding function equal to the number of the slave communication units connected to the corresponding communication lane.(5) The communication device according to (4), further comprising a control unit that sets the number of communication lanes, each of the lane write areas, each of the lane read areas, each of the master function write areas, and each of the master function read areas. (6) The communication device according to any of (1) to (5), wherein each of the master write areas includes a plurality of master function write areas that are areas separated by function, and each of the master read areas includes a plurality of master function read areas that are areas separated by function. (7) The communication device according to (6), wherein each of the master function write areas has a size that can store the write data for the corresponding function equal to the number of the slave communication units, and each of the master function read areas has a size that can store the read data for the corresponding function equal to the number of the slave communication units. (8) The communication device according to (6) or (7), wherein the slave write area includes a plurality of slave function write areas that are areas separated by function, and the slave read area includes a plurality of slave function read areas that are areas separated by function. (9) The communication device according to (1), wherein the master write area has a size capable of storing the write data for the number of slave communication units, and the master read area has a size capable of storing the read data for the number of slave communication units. (10) The communication device according to (9), wherein the master communication unit stores the read data in the master read area in the order received from each of the slave communication units. (11) The communication device according to (10), wherein the master memory space includes a plurality of the master read areas. (12) The plurality of master read areas include a first master read area and a second master read area, and wherein the master communication unit stores the read data from all of the slave communication units in the first master read area, and then, when it receives the read data from any of the slave communication units, stores the received read data in the second master read area.(13) The communication device according to any of (10) to (12), wherein, when the master communication unit receives first read data from a first slave communication unit that has already received the read data before receiving the read data from all of the slave communication units, the master communication unit stores the first read data in an area in the master read area where the read data previously received from the first slave communication unit is stored. (14) The communication device according to (13), wherein, when the master communication unit receives second read data from a second slave communication unit that has not yet received the read data among the plurality of slave communication units after receiving the first read data, the master communication unit stores the second read data in an area in the master read area next to the area where the received read data is stored. (15) The communication device according to any of (1) to (14), wherein the slave read area is provided in a memory provided outside the slave communication unit, and the slave communication unit divides the read data stored in the slave read area and transmits the divided data to the master communication unit. (16) The communication device according to any one of (1) to (15), wherein the slave communication unit synchronizes the timing of executing an interrupt to a downstream device with the other slave communication units based on an internal clock signal. (17) The communication device according to any one of (1) to (16), wherein the master communication unit transmits packets including the write data addressed to each of the slave communication units and destination information for each of the write data, and each of the slave communication units obtains the write data addressed to itself based on the destination information in the packet. (18) The communication device according to any one of (1) to (17), wherein at least one of the slave communication units transmits and receives data used to control joints of the robot.(19) A robot communication method comprising: connecting a plurality of slave communication units to a master communication unit in a daisy chain; providing a master memory space, which is memory space accessible by the master communication unit, with a master write area, which is an area for storing write data, which is data to be transmitted to the slave communication unit, and a master read area, which is an area for storing read data, which is data received from the slave communication unit; providing a plurality of slave memory spaces, which are memory spaces individually accessible by each of the slave communication units, with a slave write area, which is an area for storing the write data received from the master communication unit, and a slave read area, which is an area for storing the read data to be transmitted to the master communication unit; and transmitting and receiving the write data and the read data between the master communication unit and each of the slave communication units. (20) A robot comprising: a control unit that controls the operation of each unit; a master communication unit connected to the control unit; a plurality of slave communication units daisy-chain connected to the master communication unit; a master memory space that is a memory space accessible by the master communication unit; and a plurality of slave memory spaces that are memory spaces individually accessible by each of the slave communication units, wherein the master memory space includes a master write area that is an area for storing write data that is data to be transmitted to each of the slave communication units, and a master read area that is an area for storing read data that is data received from each of the slave communication units, and each of the slave memory spaces includes a slave write area that is an area for storing the write data received from the master communication unit, and a slave read area that is an area for storing the read data to be transmitted to the master communication unit.

[0243] The effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0244] 11 Robot arm, 21-1 to 21-7 Actuator, 51 Arm electrical system, 61 Host PC, 62 Master FPGA, 63-1 to 63-7 Slave FPGA, 64-1 to 64-7 Control MCU, 65-1 to 65-8 Motor driver, 101 Robot hand, 111 Base unit, 112L, 112R Gripper, 113L, 113R Actuator, 114C to 114R Proximity sensor, 115L, 115R Tactile sensor, 151a, 151b Hand electrical system, 161-1 to 161-5 Slave FPGA, 162-1 to 162-5 Control MCU, 163L, 163R Motor driver, 201 Electrical system, 211 Host PC, 212 Master FPGA, 213A-0 to 213D-N Slave FPGA, 214A-0 to 214D-N Control MCU, 302 Memory, 302A-1 to 302A-16 Area

Claims

1. A communication device provided on a robot, comprising: a master communication unit; a plurality of slave communication units daisy-chain connected to the master communication unit; a master memory space that is a memory space accessible by the master communication unit; and a plurality of slave memory spaces that are memory spaces individually accessible by each of the slave communication units, wherein the master memory space includes a master write area that is an area for storing write data that is data to be transmitted to each of the slave communication units, and a master read area that is an area for storing read data that is data received from each of the slave communication units, and each of the slave memory spaces includes a slave write area that is an area for storing the write data received from the master communication unit, and a slave read area that is an area for storing the read data to be transmitted to the master communication unit.

2. The communication device according to claim 1, wherein each of the slave communication units is divided into a plurality of communication lanes and connected to the master communication unit, and in at least one of the communication lanes, a plurality of the slave communication units are daisy-chain connected to the master communication unit, the master write area includes a plurality of lane write areas which are areas separated for each of the communication lanes, and the master read area includes a plurality of lane read areas which are areas separated for each of the communication lanes.

3. The communication device according to claim 2, wherein each of the lane write areas includes a plurality of master function write areas, which are areas separated by function, and each of the lane read areas includes a plurality of master function read areas, which are areas separated by function.

4. The communication device described in claim 3, wherein each of the master function write areas has a size capable of storing the write data for the corresponding function in the number of slave communication units connected to the corresponding communication lane, and each of the master function read areas has a size capable of storing the read data for the corresponding function in the number of slave communication units connected to the corresponding communication lane.

5. The communication device according to claim 4, further comprising a control unit that performs settings related to the number of communication lanes, each of the lane write areas, each of the lane read areas, each of the master function write areas, and each of the master function read areas.

6. A communication device according to claim 1, wherein each of the master write areas includes a plurality of master function write areas which are areas separated by function, and each of the master read areas includes a plurality of master function read areas which are areas separated by function.

7. The communication device according to claim 6, wherein each of the master function write areas has a size capable of storing the write data for the corresponding function in the number of the slave communication units, and each of the master function read areas has a size capable of storing the read data for the corresponding function in the number of the slave communication units.

8. The communication device according to claim 6, wherein the slave write area includes a plurality of slave function write areas, which are areas separated by function, and the slave read area includes a plurality of slave function read areas, which are areas separated by function.

9. The communication device according to claim 1, wherein the master write area has a size capable of storing the write data in the number of the slave communication units, and the master read area has a size capable of storing the read data in the number of the slave communication units.

10. The communication device according to claim 9, wherein the master communication unit stores the read data in the master read area in the order in which the data is received from each of the slave communication units.

11. The communication device according to claim 10, wherein the master memory space includes a plurality of the master read areas.

12. The communication device described in claim 11, wherein the plurality of master read areas include a first master read area and a second master read area, and when the master communication unit receives read data from any of the slave communication units after storing the read data from all of the slave communication units in the first master read area, the master communication unit stores the received read data in the second master read area.

13. The communication device described in claim 10, wherein when the master communication unit receives the first read data from a first slave communication unit that is a slave communication unit that has already received the read data before receiving the read data from all of the slave communication units, the master communication unit stores the first read data in an area in the master read area in which the read data previously received from the first slave communication unit is stored.

14. The communication device described in claim 13, wherein, after receiving the first read data, the master communication unit receives second read data from a second slave communication unit that is a slave communication unit among the plurality of slave communication units that has not yet received the read data, the master communication unit stores the second read data in an area in the master read area next to the area in which the received read data is stored.

15. The communication device according to claim 1, wherein the slave read area is provided in a memory provided outside the slave communication unit, and the slave communication unit divides the read data stored in the slave read area and transmits the divided data to the master communication unit.

16. The communication device according to claim 1, wherein the slave communication unit synchronizes the timing of executing an interrupt to a downstream device with other slave communication units based on an internal clock signal.

17. The communication device according to claim 1, wherein the master communication unit transmits a packet including the write data addressed to each of the slave communication units and destination information for each of the write data, and each of the slave communication units acquires the write data addressed to it based on the destination information in the packet.

18. The communication device according to claim 1, wherein at least one of the slave communication units transmits and receives data used to control the joints of the robot.

19. A robot communication method in which a plurality of slave communication units are daisy-chained to a master communication unit, and a master memory space that is memory space accessible by the master communication unit is provided with a master write area that is an area for storing write data that is data to be transmitted to the slave communication units, and a master read area that is an area for storing read data that is data received from the slave communication units, and a plurality of slave memory spaces that are memory spaces individually accessible by each of the slave communication units are provided with a slave write area that is an area for storing the write data received from the master communication unit, and a slave read area that is an area for storing the read data to be transmitted to the master communication unit, and the master communication unit and each of the slave communication units transmit and receive the write data and the read data.

20. A robot comprising: a control unit that controls the operation of each unit; a master communication unit connected to said control unit; a plurality of slave communication units daisy-chain connected to said master communication unit; a master memory space that is a memory space accessible by said master communication unit; and a plurality of slave memory spaces that are memory spaces individually accessible by said slave communication units, wherein said master memory space includes a master write area that is an area for storing write data that is data to be transmitted to each of said slave communication units, and a master read area that is an area for storing read data that is data received from each of said slave communication units, and each of said slave memory spaces includes a slave write area that is an area for storing said write data received from said master communication unit, and a slave read area that is an area for storing said read data to be transmitted to said master communication unit.

Images