Display method for display panel, display panel and display apparatus

Abstract

A display method for a display panel, a display panel and a display apparatus. The method comprises: receiving first display data of a plurality of frames, wherein the resolution of the first display data is the same as the resolution of a display panel (step S401); and in a dual line gate mode, compressing the number of lines of first display data of each frame by half to serve as second display data of each frame, outputting second display data of some of the frames to the display panel to perform picture display, and translating second display data of at least one of the remaining frames by at least one pixel in a line direction and then outputting same to the display panel to perform picture display, wherein at least one of some of the frames is alternately output with at least one of the remaining frames (step S402).

Description

Display method of display panel, display panel and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display method of a display panel, a display panel, and a display device. Background Art

[0002] With the rapid development of display panel technology, users have higher and higher requirements for the refresh rate of display panels. A high refresh rate that can support entertainment mode while meeting users' normal viewing needs effectively improves the functionality of display panels.

[0003] The dual-line drive (DLG) mode is a mode in which two rows of gate lines in the pixel area are opened simultaneously for pixel refresh. This can increase the refresh time of a single pixel or double the refresh rate of the entire display panel while keeping the refresh time of a single pixel unchanged. It is a technology that effectively doubles the refresh rate without increasing costs.

[0004] Summary of the Invention

[0005] The display method, display panel, and display device provided by the embodiments of the present disclosure are specifically described as follows:

[0006] In one aspect, an embodiment of the present disclosure provides a display method of a display panel, comprising:

[0007] receiving a plurality of frames of first display data, where a resolution of the first display data is the same as a resolution of the display panel;

[0008] In the dual-row drive mode, the number of rows of the first display data in each frame is compressed by half and then used as the second display data of each frame, and the second display data of some frames is output to the display panel for screen display, and the second display data of at least one frame of the remaining frames is shifted by at least one pixel along the row direction and then output to the display panel for screen display; wherein, at least one frame in the partial frames and at least one frame in the remaining frames are output alternately.

[0009] In some embodiments, in the display method provided by an embodiment of the present disclosure, compressing the number of rows of the first display data of each frame by half and then using the result as the second display data of each frame specifically includes:

[0010] The odd-numbered rows of the first display data in each frame are used as the second display data in each frame.

[0011] In some embodiments, in the display method provided by an embodiment of the present disclosure, compressing the number of rows of the first display data of each frame by half and then using the result as the second display data of each frame specifically includes:

[0012] The even-numbered row data of the first display data in each frame is used as the second display data in each frame.

[0013] In some embodiments, in the display method provided by an embodiment of the present disclosure, compressing the number of rows of the first display data of each frame by half and then using the result as the second display data of each frame specifically includes:

[0014] Calculate the first display data of each frame according to the following formula to obtain the second display data of each frame;

[0015] D iz =O iz ×q+E iz ×(1-q), or, D iz =(O iz +E iz ) / 2; where 0≤q≤1, D iz is the zth (z is a positive integer) data of the ith (i is a positive integer) row in the second display data, O iz is the zth data in the (2i-1)th row of the first display data, E iz It is the zth data in the 2ith row in the first display data.

[0016] In some embodiments, in the display method provided by an embodiment of the present disclosure, the second display data of at least one frame of the remaining frames is shifted by at least one pixel along the row direction, specifically including:

[0017] The second display data of at least one frame of the remaining frames is shifted by at least one pixel toward the first column of pixels or the last column of pixels.

[0018] In some embodiments, in the display method provided in the embodiments of the present disclosure, the display panel includes a plurality of gate lines extending in a row direction and arranged in a column direction, with two gate lines forming a gate line group. The dual-row driving mode specifically includes:

[0019] Within one frame time, each gate line group is driven one by one, and two gate lines of the same gate line group are driven simultaneously.

[0020] In some embodiments, in the display method provided by the embodiments of the present disclosure, simultaneously driving two gate lines of the same gate line group specifically includes:

[0021] The nth and (n+m)th gate lines are driven simultaneously in one of the partial frames and the remaining frames, and the (n+m)th and (n+2m)th gate lines are driven simultaneously in the other time, wherein n is an integer greater than or equal to 1 and less than or equal to N / 2, m is a positive integer less than or equal to 3, and N is the total number of the gate lines.

[0022] In some embodiments, in the display method provided by the embodiments of the present disclosure, simultaneously driving two gate lines of the same gate line group specifically includes:

[0023] In each frame time, the nth and (n+m)th gate lines are driven simultaneously, where n is an integer greater than or equal to 1 and less than or equal to N / 2, m is a positive integer less than or equal to 3, and N is the total number of the gate lines.

[0024] In some embodiments, in the display method provided by the embodiments of the present disclosure, the display panel includes a plurality of sub-pixels of different colors, and while driving two gate lines of the same gate line group, further includes: writing the second display data into sub-pixels of the same color.

[0025] In some embodiments, the display method provided in the embodiments of the present disclosure further includes: in a row-by-row driving mode, directly outputting each frame of the first display data to the display panel for image display.

[0026] On the other hand, an embodiment of the present disclosure provides a display panel, comprising a plurality of gate lines extending along the row direction and arranged along the column direction, a plurality of data lines extending along the column direction and arranged along the row direction, and a plurality of sub-pixels located in a defined area where each of the gate lines and each of the data lines intersects, at least two of the sub-pixels forming a pixel, the sub-pixels being electrically connected to the gate lines and the data lines, respectively, and the display panel adopts the above-mentioned display method provided by the embodiment of the present disclosure for display.

[0027] In some embodiments, in the display panel provided by the embodiments of the present disclosure, every at least two adjacent sub-pixels in a row direction constitute a pixel.

[0028] In some embodiments, in the display panel provided by the embodiments of the present disclosure, every at least two adjacent sub-pixels in the column direction constitute a pixel.

[0029] In some embodiments, in the display panel provided by the embodiments of the present disclosure, one gate line is electrically connected to a row of sub-pixels, and one data line is electrically connected to a column of sub-pixels.

[0030] In some embodiments, in the display panel provided by the embodiments of the present disclosure, two gate lines are electrically connected to a row of sub-pixels, and the sub-pixels in adjacent rows electrically connected to the same data line are located in adjacent columns.

[0031] On the other hand, an embodiment of the present disclosure provides a display device, including the above-mentioned display panel provided by an embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] FIG1 is a schematic diagram of the structure of a display panel with a single gate pixel architecture;

[0033] FIG2 is a timing diagram of gate line scanning of the display panel shown in FIG1 in the DLG mode;

[0034] Figure 3 is the red oblique line graph corresponding to Figure 2;

[0035] FIG4 is a flow chart of a display method of a display panel provided by an embodiment of the present disclosure;

[0036] FIG5 is a red oblique line graph corresponding to the first display data inputted by the display panel shown in FIG1 in the DLG mode provided by an embodiment of the present disclosure;

[0037] FIG6 is a red oblique line graph corresponding to the second display data of the odd frame inputted by the display panel shown in FIG1 in the DLG mode provided by an embodiment of the present disclosure;

[0038] FIG7 is a red oblique line graph corresponding to the second display data of an even frame inputted by the display panel shown in FIG1 in the DLG mode provided by an embodiment of the present disclosure;

[0039] FIG8 is a superimposed diagram of the red oblique line diagram shown in FIG6 and the red oblique line diagram shown in FIG7;

[0040] FIG9 is a gate line scanning timing diagram corresponding to FIG6 ;

[0041] FIG10 is a gate line scanning timing diagram corresponding to FIG7;

[0042] FIG11 is a gate line scanning timing diagram corresponding to an even-numbered frame of the display panel shown in FIG1 in a DLG mode according to an embodiment of the present disclosure;

[0043] Figure 12 is the red oblique line graph corresponding to Figure 11;

[0044] FIG13 is a superimposed diagram of the red oblique line diagram shown in FIG6 and the red oblique line diagram shown in FIG12;

[0045] FIG14 is a schematic diagram of the structure of a display panel with a dual gate pixel architecture;

[0046] FIG15 is a gate line scanning timing diagram of the display panel shown in FIG14 in the DLG mode;

[0047] Figure 16 is the red oblique line graph corresponding to Figure 15;

[0048] FIG17 is a red oblique line graph corresponding to the first display data inputted by the display panel shown in FIG14 in the DLG mode provided by an embodiment of the present disclosure;

[0049] FIG18 is a red oblique line graph corresponding to the second display data of the odd frame inputted by the display panel shown in FIG14 in the DLG mode provided by an embodiment of the present disclosure;

[0050] FIG19 is a red oblique line graph corresponding to the second display data of the even frame inputted by the display panel shown in FIG14 in the DLG mode provided by an embodiment of the present disclosure;

[0051] FIG20 is a superimposed diagram of the red oblique line diagram shown in FIG18 and the red oblique line diagram shown in FIG19 ;

[0052] FIG21 is a gate line scanning timing diagram corresponding to FIG18;

[0053] FIG22 is a gate line scanning timing diagram corresponding to FIG19;

[0054] FIG23 is a gate line scanning timing diagram corresponding to an even-numbered frame of the display panel shown in FIG14 in the DLG mode provided by an embodiment of the present disclosure;

[0055] Figure 24 is the red oblique line graph corresponding to Figure 23;

[0056] FIG25 is a superimposed diagram of the red oblique line diagram shown in FIG18 and the red oblique line diagram shown in FIG24 ;

[0057] FIG26 is a schematic diagram of the structure of a display panel with a triple gate pixel architecture;

[0058] FIG27 is a gate line scanning timing diagram of the display panel shown in FIG26 in the DLG mode;

[0059] Figure 28 is the red oblique line graph corresponding to Figure 27;

[0060] FIG29 is a red oblique line graph corresponding to the first display data inputted by the display panel shown in FIG26 in the DLG mode provided by an embodiment of the present disclosure;

[0061] FIG30 is a red oblique line graph corresponding to the second display data of the odd frame inputted by the display panel shown in FIG26 in the DLG mode provided by an embodiment of the present disclosure;

[0062] FIG31 is a red oblique line graph corresponding to the second display data of the even frame inputted by the display panel shown in FIG26 in the DLG mode provided by an embodiment of the present disclosure;

[0063] FIG32 is a superimposed diagram of the red oblique line diagram shown in FIG30 and the red oblique line diagram shown in FIG31;

[0064] FIG33 is a gate line scanning timing diagram corresponding to FIG30;

[0065] FIG34 is a gate line scanning timing diagram corresponding to FIG31;

[0066] FIG35 is a gate line scanning timing diagram corresponding to an even-numbered frame of the display panel shown in FIG26 in the DLG mode provided by an embodiment of the present disclosure;

[0067] Figure 36 is the red oblique line graph corresponding to Figure 35;

[0068] FIG37 is a superimposed diagram of the red oblique line diagram shown in FIG30 and the red oblique line diagram shown in FIG36;

[0069] FIG38 is a gate line scanning timing diagram of the display panel shown in FIG1 in a row-by-row driving mode provided by an embodiment of the present disclosure;

[0070] Figure 39 is the red oblique line graph corresponding to Figure 38;

[0071] FIG40 is a gate line scanning timing diagram of the display panels shown in FIG14 and FIG26 in a row-by-row driving mode provided by an embodiment of the present disclosure;

[0072] FIG41 is a red oblique line diagram corresponding to the display panel shown in FIG14 and FIG40 ;

[0073] FIG42 is a red oblique line diagram corresponding to the display panel shown in FIG26 and FIG40 . DETAILED DESCRIPTION

[0074] To further clarify the objectives, technical solutions, and advantages of the embodiments of the present disclosure, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below in conjunction with the accompanying drawings of the embodiments of the present disclosure. It should be noted that in the drawings, the thicknesses of layers, films, panels, regions, etc. are exaggerated for clarity. In this disclosure, exemplary embodiments are described with reference to cross-sectional views that are schematic representations of idealized embodiments. As such, deviations from the shapes shown in the drawings are to be expected, for example, as a result of manufacturing techniques and / or tolerances. Therefore, the embodiments described in this disclosure should not be construed as limited to the specific shapes of the regions shown in this disclosure, but rather include deviations in shape resulting from, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features; a sharp angle illustrated may be rounded, etc. Therefore, the regions shown in the drawings are schematic in nature, and their sizes and shapes are not intended to illustrate the precise shapes of the regions or reflect true scale, but are intended solely to illustrate the present disclosure. Throughout, identical or similar reference numerals denote identical or similar elements or elements having identical or similar functions. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components.

[0075] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second" and similar terms used in the present disclosure and the claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Inside", "outside", "upper", "lower" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0076] In the following description, when an element or layer is referred to as being “on” or “connected to” another element or layer, the element or layer may be directly on, directly connected to, the other element or layer, or there may be intermediate elements or intermediate layers. When an element or layer is referred to as being “disposed on one side of” another element or layer, the element or layer may be directly on, directly connected to, the other element or layer, or there may be intermediate elements or intermediate layers. However, when an element or layer is referred to as being “directly on” or “directly connected to” another element or layer, there are no intermediate elements or intermediate layers. The term “and / or” includes any and all combinations of one or more of the associated listed items.

[0077] In DLG mode, since two rows of gate lines are turned on at the same time, the corresponding two pixels will write the same data, resulting in the actual display resolution being halved, making the jagged edges of the displayed graphics more obvious. Taking the display panel with a single gate pixel architecture shown in Figure 1 showing a red diagonal line screen as an example, in Figure 1, a data line (for example, d1 to d18) is electrically connected to a column of sub-pixels (for example, red sub-pixels R, green sub-pixels G, and blue sub-pixels B), and a gate line (for example, G1 to G6) is electrically connected to a row of sub-pixels (for example, red sub-pixels R, green sub-pixels G, and blue sub-pixels B), and each adjacent red sub-pixel R, green sub-pixel G, and blue sub-pixel B along the row direction constitutes a pixel. Figure 2 is a gate line scanning timing diagram of the pixel area in DLG mode, and Figure 3 is a display effect diagram corresponding to the gate line scanning timing shown in Figure 2. The pattern-filled red sub-pixels in Figure 3 constitute the red diagonal line screen. Combining Figures 2 and 3, it can be seen that in the DLG mode, the scanning timing of the first gate line G1 and the second gate line G2 is the same, the scanning timing of the third gate line G3 and the fourth gate line G4 is the same, the scanning timing of the fifth gate line G5 and the sixth gate line G6 is the same, and so on; so that the red sub-pixels displaying the red oblique line picture in the first row of pixels and the second row of pixels controlled by the first gate line G1 and the second gate line G2 are written with the same first data D1, the red sub-pixels displaying the red oblique line picture in the third row of pixels and the fourth row of pixels controlled by the third gate line G3 and the fourth gate line G4 are written with the same second data D3, the red sub-pixels displaying the red oblique line picture in the fifth row of pixels and the sixth row of pixels controlled by the fifth gate line G5 and the sixth gate line G6 are written with the same third data D5, and so on. As a result, the actual resolution of the red oblique line picture is halved, and the edge jaggedness is more obvious.

[0078] In order to improve the above technical problems existing in the related art, an embodiment of the present disclosure provides a display method of a display panel. FIG4 is a flow chart of the display method of a display panel provided by an embodiment of the present disclosure.

[0079] As shown in FIG4 , the display method of the display panel provided by the embodiment of the present disclosure may include the following steps:

[0080] S401 : Receive multiple frames of first display data, where the resolution of the first display data is the same as the resolution of the display panel.

[0081] In some embodiments, the resolution of the first display data and the resolution of the display panel may be 4K2K, etc. The first display data with a 4K2K resolution includes 3840x2160 data, and the display panel with a 4K2K resolution includes 3840x2160 sub-pixels.

[0082] S402. In a dual-row driving mode, the number of rows of the first display data of each frame is compressed by half and then used as the second display data of each frame, and the second display data of some frames are output to the display panel for screen display, and the second display data of at least one frame of the remaining frames are shifted by at least one pixel along the row direction and then output to the display panel for screen display; wherein, at least one frame in the partial frames and at least one frame in the remaining frames are output alternately.

[0083] In some embodiments, the second display data of the odd frame can be directly output to the display panel for screen display, and the second display data of the even frame can be shifted by at least one pixel in the row direction and then output to the display panel for display; alternatively, the second display data of multiple consecutive frames (for example, 2 consecutive frames, 3 frames, etc.) can be output to the display panel for screen display, and then the second display data of multiple consecutive frames (for example, 2 consecutive frames, 3 frames, etc.) can be shifted by at least one pixel in the row direction and then output to the display panel for display.

[0084] In some embodiments, the second display data of at least one frame of the remaining frames is shifted along the row direction by at least one pixel and then output to the display panel for image display. Specifically, the second display data of at least one frame of the remaining frames can be shifted along the row direction (for example, shifted to the left, that is, shifted toward the first column of pixels; or shifted to the right, that is, shifted toward the last column of pixels) by one or two pixels and then output to the display panel for image display to avoid excessive blurring of the edge of the image.

[0085] In some embodiments, after the second display data of at least one frame of the remaining frames is shifted leftward (i.e., shifted toward the first column of sub-pixels) by one or two pixels, the second display data of the first to last pixel or the first to second to last pixel is missing. In this case, L0 grayscale data may be written to the first to last pixel or the first to second to last pixel, or the second display data of the third to last pixel may be written to the first to last pixel or the first to second to last pixel. Similarly, after the second display data of at least one frame of the remaining frames is shifted rightward (i.e., shifted toward the last column of sub-pixels) by one or two pixels, the second display data of the first pixel or the first to second to last pixel is missing. In this case, L0 grayscale data may be written to the first pixel or the first to second to last pixel, or the second display data of the third pixel may be written to the first pixel or the first to second to last pixel. Since the first two pixels and the first two pixels from the end are located at the edge of display area AA, and the effective display image (i.e., the display image that conveys effective information such as images or text) generally does not completely fill display area AA, writing the L0 grayscale or the grayscale data of the third and third-to-last pixels has little impact on the overall display effect. Based on this, in some embodiments, the present disclosure does not require additional data to be added for the first two pixels and the first two pixels from the end where the second display data is missing.

[0086] In some embodiments, in the above-mentioned display method provided by the embodiments of the present disclosure, by adopting a data writing method in which the number of rows of the first display data of each frame is compressed by half as the second display data of each frame in a dual-row driving mode, and the second display data of some frames is directly output to the display panel, and the second display data of at least one frame of the remaining frames is shifted and then output to the display panel, it is possible to achieve the effect that the edge pixels of the display graphics are actually displayed as data interpolation of the surrounding pixels (for example, left and right adjacent pixels), making the edge transition smoother, thereby improving the edge jagged problem.

[0087] In some embodiments, in the above-mentioned display method provided by the embodiments of the present disclosure, in the above-mentioned step S402, the number of rows of the first display data of each frame is compressed by half and used as the second display data of each frame. Specifically, the odd-numbered rows of data of the first display data of each frame can be used as the second display data of each frame, or the even-numbered rows of data of the first display data of each frame can be used as the second display data of each frame, or the odd-numbered and even-numbered rows of data of the first display data of each frame can be interpolated as the second display data of each frame.

[0088] Optionally, the interpolation of the odd and even row data of the first display data may be calculated according to the following formula:

[0089] D iz =O iz ×q+E iz ×(1-q), or, D iz =(O iz +E iz ) / 2; where 0≤q≤1, D iz

[0090] is the zth (z is a positive integer) data of the ith (i is a positive integer) row in the second display data, O iz is the zth data in the (2i-1)th row of the first display data, E iz It is the zth data in the 2ith row in the first display data.

[0091] For the single-gate display panel shown in Figure 1, the data in each odd-numbered row of the first display data of each frame is used as the second display data of each frame. The second display data of the odd-numbered frame is directly output to the display panel for displaying a red diagonal image, while the second display data of the even-numbered frame is shifted one pixel to the left and then output to the display panel for displaying a red diagonal image. Figure 5 shows the red diagonal image corresponding to the first display data, Figure 6 shows the red diagonal image corresponding to the second display data of the odd-numbered frame, Figure 7 shows the red diagonal image corresponding to the second display data of the even-numbered frame, and Figure 8 shows the overlay of the red diagonal image corresponding to the second display data of the odd-numbered frame and the red diagonal image corresponding to the second display data of the even-numbered frame. The red sub-pixels filled with the respective patterns in Figures 5 to 8 constitute the red diagonal image. As can be seen from Figures 6 to 8, the odd-numbered frames are written with the original odd-numbered row data, while the even-numbered frames are written with the original odd-numbered row data shifted one pixel to the left. The overlay of the two results in the display edge pixels actually appearing as interpolated data from adjacent pixels on the left and right, resulting in smoother edge transitions and effectively improving edge aliasing.

[0092] In some embodiments, in the above-mentioned display method provided in the embodiments of the present disclosure, in the DLG mode, the two gate lines driven simultaneously may be: in each frame time, the nth and (n+m)th gate lines are driven simultaneously, wherein n is an integer greater than or equal to 1 and less than or equal to N / 2, m is a positive integer less than or equal to 3, and N is the total number of gate lines. Exemplarily, the gate line scanning timing corresponding to FIG6 is shown in FIG9, and the gate line scanning timing corresponding to FIG7 is shown in FIG10. As can be seen from FIG9 and FIG10, the scanning timing of the first gate line G1 and the second gate line G2 is the same, the scanning timing of the third gate line G3 and the fourth gate line G4 is the same, the scanning timing of the fifth gate line G5 and the sixth gate line G6 is the same, and so on.

[0093] In some embodiments, in the above-mentioned display method provided by the embodiments of the present disclosure, in the DLG mode, the two gate lines driven simultaneously may be: the nth and (n+m)th gate lines are driven simultaneously in one of the partial frame and the remaining frame time, and the (n+m)th and (n+2m)th gate lines are driven simultaneously in the other time; for example, the nth and (n+m)th gate lines are driven simultaneously in the partial frame time, and the (n+m)th and (n+2m)th gate lines are driven simultaneously in the remaining frame time; for another example, the nth and (n+m)th gate lines are driven simultaneously in the remaining frame time, and the (n+m)th and (n+2m)th gate lines are driven simultaneously in the partial frame time; wherein n is an integer greater than or equal to 1 and less than or equal to N / 2, m is a positive integer less than or equal to 3, and N is the total number of gate lines.

[0094] For example, as shown in FIG9 , the nth and (n+1)th gate lines are driven simultaneously during the odd-numbered frame time; as shown in FIG11 , the (n+1)th and (n+2)th gate lines are driven simultaneously during the even-numbered frame time. The red oblique line diagram corresponding to FIG9 is FIG6 , the red oblique line diagram corresponding to FIG11 is FIG12 , and FIG13 is a superposition diagram of FIG6 and FIG12 , where D12, D32, and D52 of FIG11 correspond to R12, R32, and R52 of FIG12 , respectively. And. As can be seen from FIG6 , FIG12 and FIG13 , by superimposing the odd and even frames, an interpolation effect is exhibited for the adjacent upper and lower and left and right pixel points of the edge pixel points of the displayed graphics, the edge smoothing effect is better, and the effect of improving the edge jaggedness is better.

[0095] Figure 14 shows a display panel with a dual-gate pixel architecture. One data line (e.g., d1-d10) is electrically connected to two columns of subpixels (e.g., red subpixels R, green subpixels G, and blue subpixels B), and one gate line (e.g., G1-G12) is electrically connected to a row of subpixels (e.g., red subpixels R, green subpixels G, and blue subpixels B). Along the row, each adjacent red subpixel R, green subpixel G, and blue subpixel B constitutes a pixel. Comparing Figures 1 and 14, it can be seen that the number of gate lines (e.g., G1-G12) is doubled compared to a display panel with a single-gate pixel architecture, while the number of data lines (e.g., d1-d10) is halved. Therefore, one data line must simultaneously connect to two columns of subpixels in a corresponding row of pixels.

[0096] In the DLG mode, the red oblique line picture displayed by the display panel of the dual gate pixel architecture is shown in Figure 15, and the corresponding gate line scanning timing is shown in Figure 16. The red sub-pixels filled with the pattern in Figure 15 constitute the red oblique line picture. Combining Figures 15 and 16, it can be seen that the odd-numbered gate line scanning timings are identical in pairs, and the even-numbered gate line scanning timings are identical in pairs. For example, the scanning timings of the first gate line G1 and the third gate line G3 are identical, the scanning timings of the second gate line G2 and the fourth gate line G4 are identical, and so on. Similarly, since the data of two adjacent pixel rows in the DLG mode are the same, the actual resolution is halved and the edge jaggedness is more obvious.

[0097] The above-mentioned display method provided by the embodiment of the present disclosure can effectively improve the edge jagged problem. Specifically: for the dual gate display panel shown in Figure 14, take the data of each odd-numbered row of the first display data of each frame as the second display data of each frame, and the second display data of the odd-numbered frame is directly output to the display panel for red oblique line screen display, and the second display data of the even-numbered frame is shifted one pixel to the left and then output to the display panel for red oblique line screen display as an example. Figure 17 is a red oblique line image corresponding to the first display data, Figure 18 is a red oblique line image corresponding to the second display data of the odd-numbered frame, Figure 19 is a red oblique line image corresponding to the second display data of the even-numbered frame, and Figure 20 is an overlay of the red oblique line image corresponding to the second display data of the odd-numbered frame and the red oblique line image corresponding to the second display data of the even-numbered frame. The red sub-pixels filled with the respective patterns in Figures 17 to 20 constitute the red oblique line image. As can be seen from Figures 18 to 20, the odd frames write the data corresponding to the original odd rows, and the even frames write the data corresponding to the original odd rows shifted one pixel to the left. The two are superimposed, and the edge pixels of the displayed graphics are actually displayed as the interpolation effect of the data of the adjacent pixels on the left and right, making the edge transition smoother, thereby effectively improving the edge jagged problem.

[0098] In certain embodiments, the gate line driving timing that the red oblique line figure shown in Figure 18 corresponds to can be as shown in Figure 21, and the gate line driving timing that the red oblique line figure shown in Figure 19 corresponds to can be as shown in Figure 22.As can be seen from Figure 21 and Figure 22, drive the nth and (n+2)th gate lines simultaneously in each frame time.In certain embodiments, the disclosure also can drive the nth and (n+2)th gate lines simultaneously in the odd-numbered frame time as shown in Figure 21, but as shown in Figure 23, drive the (n+2)th and (n+4)th gate lines simultaneously in the even-numbered frame time.The red oblique line figure that Figure 23 corresponds to is Figure 24, and Figure 25 is the superposition diagram of Figure 18 and Figure 24.As can be seen from Figure 18, Figure 24 and Figure 25, by the superposition of odd and even two frames, all present interpolation effect for the adjacent upper and lower and left and right pixel points of display pattern edge pixel point, edge smoothing effect is better, and edge sawtooth improvement effect is better.

[0099] Figure 26 shows a display panel with a triple-gate pixel architecture. Along the column direction, each adjacent red sub-pixel R, green sub-pixel G, and blue sub-pixel B constitutes a pixel. One data line (e.g., d1-d6) is electrically connected to a column of sub-pixels (e.g., red sub-pixel R, green sub-pixel G, blue sub-pixel B), and one gate line (e.g., G1-G12) is electrically connected to a row of sub-pixels (e.g., red sub-pixel R, green sub-pixel G, blue sub-pixel B). Comparing Figure 1 with Figure 26, it can be seen that the number of gate lines (e.g., G1-G12) is tripled compared to a single-gate display panel, while the number of data lines (e.g., d1-d6) is reduced to one-third. Consequently, one data line connects to three sub-pixels in the same column.

[0100] In DLG mode, the gate line scanning timing of the display panel with a triple gate pixel architecture is shown in Figure 27, and the corresponding red oblique line picture is shown in Figure 28. The red sub-pixels filled with the pattern in Figure 28 constitute the red oblique line picture. Combining Figures 27 and 28, it can be seen that the scanning timing of the nth and (n+3)th gate lines is the same. For example, the scanning timing of the first gate line G1 and the fourth gate line G4 is the same, the scanning timing of the second gate line G2 and the fifth gate line G5 is the same, the scanning timing of the third gate line G3 and the sixth gate line G6 is the same, and so on. Similarly, since the data of two adjacent pixel rows in the DLG mode is the same, the actual resolution is halved and the edge jaggedness is more obvious.

[0101] The above-mentioned display method provided by the embodiment of the present disclosure can effectively improve the edge jagged problem. Specifically: for the triple gate display panel shown in Figure 26, take the data of each odd-numbered row of the first display data of each frame as the second display data of each frame, and the second display data of the odd-numbered frame is directly output to the display panel for red oblique line screen display, and the second display data of the even-numbered frame is shifted one pixel to the left and then output to the display panel for red oblique line screen display as an example. Figure 29 is a red oblique line image corresponding to the first display data, Figure 30 is a red oblique line image corresponding to the second display data of the odd-numbered frame, Figure 31 is a red oblique line image corresponding to the second display data of the even-numbered frame, and Figure 32 is an overlay of the red oblique line image corresponding to the second display data of the odd-numbered frame and the red oblique line image corresponding to the second display data of the even-numbered frame. The red sub-pixels filled with the respective patterns in Figures 29 to 32 constitute the red oblique line image. As can be seen from Figures 30 to 32, the odd-numbered frames write the data corresponding to the original odd-numbered rows, and the even-numbered frames write the data corresponding to the original odd-numbered rows shifted one pixel to the left. The two are superimposed, and the edge pixels of the displayed graphics are actually displayed as the interpolation effect of the data of the adjacent pixels on the left and right, making the edge transition smoother, thereby effectively improving the edge jagged problem.

[0102] In certain embodiments, the gate line driving timing that the red oblique line figure shown in Figure 30 corresponds to can be as shown in Figure 33, and the gate line driving timing that the red oblique line figure shown in Figure 31 corresponds to can be as shown in Figure 34.As seen from Figure 33 and Figure 34, can drive nth and (n+3)th gate line simultaneously in each frame time.In certain embodiments, the present disclosure also can drive nth and (n+3)th gate line simultaneously in odd frame time as shown in Figure 33, but drives (n+3)th and (n+6)th gate line simultaneously in even frame time, as shown in Figure 35.The red oblique line figure that Figure 36 corresponds to is Figure 35, and Figure 37 is the superposition diagram of Figure 30 and Figure 36.As seen from Figure 30, Figure 36 and Figure 37, by the superposition of odd and even two frames, all present interpolation effect for the adjacent upper and lower and left and right pixel points of display pattern edge pixel point, edge smoothing effect is better, and edge jaggedness is improved better.

[0103] In some embodiments, in the above-mentioned display method provided by the embodiments of the present disclosure, as shown in Figures 6, 7, 9 to 12, 18, 19, 21 to 24, 30, 31, and 33 to 36, while driving two gate lines of the same gate line group, the second display data is written into sub-pixels of the same color. For example, in Figures 18 and 21, the first gate line G1 and the third gate line G3 are turned on at the same time, and at this time, the two sub-pixels corresponding to the first gate line G1 and the third gate line G3 connected to the same data line have the same color, so that the same second display data (e.g., D11) is written into two red sub-pixels.

[0104] In some embodiments, in the above display method provided by the embodiment of the present disclosure, as shown in FIG4 , it may further include step S403 , directly outputting each frame of first display data to the display panel for image display in a row-by-row driving mode.

[0105] In some embodiments, for the single gate display panel shown in Figure 1, Figure 38 is a gate line scanning timing diagram in the row-by-row driving mode, and Figure 39 is a corresponding red oblique line display effect diagram of Figure 38; it can be seen from Figures 38 and 39 that D1, D2, D3, D4, D5, D6, etc. in the first display data are directly written into the display panel, realizing the display of the red oblique line diagram.

[0106] In some embodiments, for the dual gate display panel shown in Figure 14, Figure 40 is its gate line scanning timing diagram in the row-by-row drive mode, and Figure 41 is the corresponding red oblique line display effect diagram of Figure 40; it can be seen from Figures 40 and 41 that D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, etc. in the first display data are directly written into the display panel, realizing the display of the red oblique line diagram.

[0107] In some embodiments, for the triple gate display panel shown in Figure 26, Figure 40 is its gate line scanning timing diagram in the row-by-row driving mode, and Figure 42 is the corresponding red oblique line display effect diagram of Figure 40; it can be seen from Figures 40 and 42 that D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, etc. in the first display data are directly written into the display panel, realizing the display of the red oblique line diagram.

[0108] Those skilled in the art will appreciate that the embodiments of the present disclosure may be provided as methods, systems, or computer program products. Therefore, the present disclosure may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present disclosure may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0109] The present disclosure is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present disclosure. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0110] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0111] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0112] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0113] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if such changes and modifications of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such changes and modifications.

Claims

1. A display method for a display panel, wherein: include: receiving a plurality of frames of first display data, where a resolution of the first display data is the same as a resolution of the display panel; In the dual-row drive mode, the number of rows of the first display data in each frame is compressed by half and then used as the second display data of each frame, and the second display data of some frames is output to the display panel for screen display, and the second display data of at least one frame of the remaining frames is shifted by at least one pixel along the row direction and then output to the display panel for screen display; wherein, at least one frame in the partial frames and at least one frame in the remaining frames are output alternately.

2. The display method according to claim 1, wherein: The compressing the number of lines of the first display data of each frame by half and then using the resultant as the second display data of each frame specifically includes: The odd-numbered rows of the first display data in each frame are used as the second display data in each frame.

3. The display method according to claim 1, wherein: The compressing the number of lines of the first display data of each frame by half and then using the resultant as the second display data of each frame specifically includes: The even-numbered row data of the first display data in each frame is used as the second display data in each frame.

4. The display method according to claim 1, wherein: The compressing the number of lines of the first display data of each frame by half and then using the resultant as the second display data of each frame specifically includes: Calculate the first display data of each frame according to the following formula to obtain the second display data of each frame; D iz =O iz ×q+E iz ×(1-q), or, D iz =(O iz +E iz ) / 2; where 0≤q≤1, D iz is the zth (z is a positive integer) data of the ith (i is a positive integer) row in the second display data, O iz is the zth data in the (2i-1)th row of the first display data, E iz It is the zth data in the 2ith row in the first display data.

5. The display method according to any one of claims 1 to 4, wherein: The second display data of at least one frame of the remaining frames is shifted by at least one pixel along a row direction, specifically comprising: The second display data of at least one frame of the remaining frames is shifted by at least one pixel toward the first column of pixels or the last column of pixels.

6. The display method according to any one of claims 1 to 5, wherein: The display panel includes a plurality of gate lines extending in a row direction and arranged in a column direction, with two gate lines forming a gate line group. The dual-row driving mode specifically includes: Within one frame time, each gate line group is driven one by one, and two gate lines of the same gate line group are driven simultaneously.

7. The display method according to claim 6, wherein: Simultaneously driving two gate lines of the same gate line group specifically includes: The nth and (n+m)th gate lines are driven simultaneously in one of the partial frames and the remaining frames, and the (n+m)th and (n+2m)th gate lines are driven simultaneously in the other time, wherein n is an integer greater than or equal to 1 and less than or equal to N / 2, m is a positive integer less than or equal to 3, and N is the total number of the gate lines.

8. The display method according to claim 6, wherein: Simultaneously driving two gate lines of the same gate line group specifically includes: In each frame time, the nth and (n+m)th gate lines are driven simultaneously, where n is an integer greater than or equal to 1 and less than or equal to N / 2, m is a positive integer less than or equal to 3, and N is the total number of the gate lines.

9. The display method according to any one of claims 6 to 8, wherein: The display panel includes a plurality of sub-pixels of different colors, and while driving two gate lines of the same gate line group, further includes: writing the second display data into the sub-pixels of the same color.

10. The display method according to any one of claims 1 to 9, wherein: Also includes: In the row-by-row driving mode, each frame of the first display data is directly output to the display panel for image display.

11. A display panel, wherein: The display panel comprises a plurality of gate lines extending along the row direction and arranged along the column direction, a plurality of data lines extending along the column direction and arranged along the row direction, and a plurality of sub-pixels located in a defined area where each of the gate lines and each of the data lines intersects, at least two of the sub-pixels constitute a pixel, and the sub-pixels are electrically connected to the gate lines and the data lines, respectively. The display panel performs display using the display method according to any one of claims 1 to 10.

12. The display panel according to claim 11, wherein: Every at least two adjacent sub-pixels in the row direction constitute a pixel.

13. The display panel according to claim 11, wherein: Every at least two adjacent sub-pixels in the column direction constitute a pixel.

14. The display panel according to claim 12 or 13, wherein: One gate line is electrically connected to a row of sub-pixels, and one data line is electrically connected to a column of sub-pixels.

15. The display panel according to claim 12, wherein: Two gate lines are electrically connected to one row of sub-pixels, and the sub-pixels in adjacent rows electrically connected to the same data line are located in adjacent columns.

16. A display device, wherein: The display panel comprises the display panel according to any one of claims 11 to 15.

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