Display method for display panel, display panel and display apparatus

Abstract

A display method for a display panel, a display panel and a display apparatus. The method comprises: receiving first display data of a plurality of frames, wherein the resolution of the first display data is the same as the resolution of a display panel (step S401); and in a dual line gate mode, compressing the number of lines of first display data of each frame by half to serve as second display data of each frame, outputting second display data of some of the frames to the display panel to perform picture display, and translating second display data of at least one of the remaining frames by at least one pixel in a line direction and then outputting same to the display panel to perform picture display, wherein at least one of some of the frames is alternately output with at least one of the remaining frames (step S402).

Description

Display panel display method, display panel and display device Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display method, display panel, and display device for a display panel. Background Technology

[0002] With the rapid development of display panel technology, users have increasingly higher requirements for the refresh rate of display panels. While meeting the needs of users for normal movie watching, the ability to support high refresh rates in entertainment modes effectively improves the functionality of display panels.

[0003] Dual-line drive (DLG) mode is a mode in which two rows of grid lines in the pixel area are opened simultaneously to refresh the pixel. It can increase the refresh time of a single pixel or double the refresh rate of the entire display panel while keeping the refresh time of a single pixel unchanged. It is a technology that can effectively double the refresh rate without increasing costs.

[0004] Summary of the Invention

[0005] The display panel display method, display panel, and display device provided in this disclosure are as follows:

[0006] On one hand, embodiments of this disclosure provide a display method for a display panel, including:

[0007] Receive multiple frames of first display data, wherein the resolution of the first display data is the same as the resolution of the display panel;

[0008] In dual-line driving mode, the number of lines of the first display data of each frame is compressed by half and used as the second display data of each frame. The second display data of some frames is output to the display panel for display. The second display data of at least one frame of the remaining frames is shifted by at least one pixel along the line direction and then output to the display panel for display. The at least one frame of the partial frames is output alternately with the at least one frame of the remaining frames.

[0009] In some embodiments, in the display method provided in this disclosure, compressing the number of rows of the first display data in each frame by half to obtain the second display data for each frame specifically includes:

[0010] Each odd-numbered row of the first display data in each frame is used as the second display data in each frame.

[0011] In some embodiments, in the display method provided in this disclosure, compressing the number of rows of the first display data in each frame by half to obtain the second display data for each frame specifically includes:

[0012] Each even-numbered row of the first display data in each frame is used as the second display data for each frame.

[0013] In some embodiments, in the display method provided in this disclosure, compressing the number of rows of the first display data in each frame by half to obtain the second display data for each frame specifically includes:

[0014] The second display data for each frame is calculated using the following formula:

[0015] D iz =O iz ×q+E iz ×(1-q), or, D iz =(O iz +E iz ) / 2; where 0≤q≤1, D iz For the z-th (z is a positive integer) data in the i-th (i is a positive integer) row of the second displayed data, O iz E represents the z-th data in the (2i-1)-th row of the first displayed data. iz This refers to the z-th data in the 2i-th row of the first displayed data.

[0016] In some embodiments, in the display method provided in this disclosure, shifting the second display data of at least one of the remaining frames by at least one pixel along the line direction specifically includes:

[0017] In at least one of the remaining frames, the second display data is shifted at least one pixel toward the first or last column of pixels.

[0018] In some embodiments, in the display method provided in this disclosure, the display panel includes multiple grid lines extending along the row direction and arranged along the column direction, with two grid lines forming a grid line group. The dual-row driving mode specifically includes:

[0019] Within one frame, each of the gate line groups is driven one by one, and two gate lines of the same gate line group are driven simultaneously.

[0020] In some embodiments, the display method provided in this disclosure includes simultaneously driving two gate lines of the same gate line group, specifically comprising:

[0021] In one of the partial frames and the remaining frames, the nth and (n+m)th gate lines are driven simultaneously, and in another of the frames, the (n+m)th and (n+2m)th gate lines are driven simultaneously, where n is an integer greater than or equal to 1 and less than or equal to N / 2, m is a positive integer less than or equal to 3, and N is the total number of gate lines.

[0022] In some embodiments, the display method provided in this disclosure includes simultaneously driving two gate lines of the same gate line group, specifically comprising:

[0023] During each frame time, the nth and (n+m)th gate lines are driven simultaneously, where n is an integer greater than or equal to 1 and less than or equal to N / 2, m is a positive integer less than or equal to 3, and N is the total number of gate lines.

[0024] In some embodiments, in the display method provided in the present disclosure, the display panel includes a plurality of sub-pixels of different colors, and while driving two gate lines of the same gate line group, it also includes: writing the second display data to sub-pixels of the same color.

[0025] In some embodiments, the display method provided in this disclosure further includes: in progressive drive mode, directly outputting the first display data of each frame to the display panel for display.

[0026] On the other hand, embodiments of this disclosure provide a display panel including multiple gate lines extending in a row direction and arranged in a column direction, multiple data lines extending in a column direction and arranged in a row direction, and multiple sub-pixels located in the area defined by the intersection of each gate line and each data line, wherein at least two sub-pixels constitute one pixel, and the sub-pixels are electrically connected to the gate lines and the data lines respectively, and the display panel displays using the display method provided in the embodiments of this disclosure.

[0027] In some embodiments, in the display panel provided in the present disclosure, at least two adjacent sub-pixels in the row direction constitute one pixel.

[0028] In some embodiments, in the display panel provided in the present disclosure, at least two adjacent sub-pixels in the column direction constitute one pixel.

[0029] In some embodiments, in the display panel provided in the present disclosure, one of the gate lines is electrically connected to a row of the sub-pixels, and one of the data lines is electrically connected to a column of the sub-pixels.

[0030] In some embodiments, in the display panel provided in the present disclosure, two gate lines are electrically connected to a row of sub-pixels, and adjacent rows of sub-pixels electrically connected to the same data line are located in adjacent columns.

[0031] On the other hand, this disclosure provides a display device including the display panel described above. Attached Figure Description

[0032] Figure 1 is a schematic diagram of the display panel structure with a single-gate pixel architecture;

[0033] Figure 2 is a timing diagram of the relevant grid line scan of the display panel shown in Figure 1 in DLG mode;

[0034] Figure 3 is the red diagonal line diagram corresponding to Figure 2;

[0035] Figure 4 is a flowchart of the display panel display method provided in an embodiment of this disclosure;

[0036] Figure 5 is a red diagonal line diagram corresponding to the input of the first display data on the display panel shown in Figure 1 under the DLG mode provided in this embodiment of the present disclosure;

[0037] Figure 6 is a red diagonal line diagram corresponding to the second display data of odd-numbered frames input on the display panel shown in Figure 1 under the DLG mode provided in the embodiment of this disclosure;

[0038] Figure 7 is a red diagonal line diagram corresponding to the second display data of even-numbered frames input on the display panel shown in Figure 1 under the DLG mode provided in the embodiment of this disclosure;

[0039] Figure 8 is an overlay of the red diagonal line diagram shown in Figure 6 and the red diagonal line diagram shown in Figure 7;

[0040] Figure 9 is the gate line scan timing diagram corresponding to Figure 6;

[0041] Figure 10 is the gate line scan timing diagram corresponding to Figure 7;

[0042] Figure 11 is a timing diagram of the grid line scan corresponding to the even-numbered frames of the display panel shown in Figure 1 in the DLG mode provided in the embodiment of this disclosure;

[0043] Figure 12 is the red diagonal line diagram corresponding to Figure 11;

[0044] Figure 13 is an overlay of the red diagonal line graph shown in Figure 6 and the red diagonal line graph shown in Figure 12;

[0045] Figure 14 is a schematic diagram of the display panel structure of the dual gate pixel architecture;

[0046] Figure 15 is a timing diagram of the grid line scan of the display panel shown in Figure 14 in DLG mode;

[0047] Figure 16 is the red diagonal line diagram corresponding to Figure 15;

[0048] Figure 17 is a red diagonal line diagram corresponding to the input of the first display data on the display panel shown in Figure 14 under the DLG mode provided in this embodiment of the present disclosure.

[0049] Figure 18 is a red diagonal line diagram corresponding to the second display data of odd-numbered frames input on the display panel shown in Figure 14 under the DLG mode provided in the embodiment of this disclosure;

[0050] Figure 19 is a red diagonal line diagram corresponding to the second display data of even-numbered frames input on the display panel shown in Figure 14 under the DLG mode provided in this embodiment of the present disclosure.

[0051] Figure 20 is an overlay of the red diagonal line graph shown in Figure 18 and the red diagonal line graph shown in Figure 19;

[0052] Figure 21 is the gate line scan timing diagram corresponding to Figure 18;

[0053] Figure 22 is the gate line scan timing diagram corresponding to Figure 19;

[0054] Figure 23 is a timing diagram of the grid line scan corresponding to the even-numbered frames of the display panel shown in Figure 14 under the DLG mode provided in the embodiment of this disclosure.

[0055] Figure 24 is the red diagonal line diagram corresponding to Figure 23;

[0056] Figure 25 is an overlay of the red diagonal line graph shown in Figure 18 and the red diagonal line graph shown in Figure 24;

[0057] Figure 26 is a schematic diagram of the display panel structure of the triple gate pixel architecture;

[0058] Figure 27 is a timing diagram of the grid line scan of the display panel shown in Figure 26 in DLG mode;

[0059] Figure 28 is the red diagonal line diagram corresponding to Figure 27;

[0060] Figure 29 is a red diagonal line diagram corresponding to the input of the first display data on the display panel shown in Figure 26 under the DLG mode provided in the embodiment of this disclosure;

[0061] Figure 30 is a red diagonal line diagram corresponding to the second display data of odd-numbered frames input on the display panel shown in Figure 26 under the DLG mode provided in the embodiment of this disclosure;

[0062] Figure 31 is a red diagonal line diagram corresponding to the second display data of even-numbered frames input on the display panel shown in Figure 26 under the DLG mode provided in this embodiment of the present disclosure.

[0063] Figure 32 is an overlay of the red diagonal line graph shown in Figure 30 and the red diagonal line graph shown in Figure 31;

[0064] Figure 33 is the gate line scan timing diagram corresponding to Figure 30;

[0065] Figure 34 is the gate line scan timing diagram corresponding to Figure 31;

[0066] Figure 35 is a timing diagram of the grid line scan corresponding to the even-numbered frames of the display panel shown in Figure 26 under the DLG mode provided in the embodiment of this disclosure.

[0067] Figure 36 is the red diagonal line diagram corresponding to Figure 35;

[0068] Figure 37 is an overlay of the red diagonal line graph shown in Figure 30 and the red diagonal line graph shown in Figure 36;

[0069] Figure 38 is a timing diagram of the grid line scan of the display panel shown in Figure 1 in progressive drive mode according to an embodiment of the present disclosure;

[0070] Figure 39 is the red diagonal line diagram corresponding to Figure 38;

[0071] Figure 40 is a timing diagram of the grid line scan of the display panel shown in Figures 14 and 26 in progressive drive mode according to an embodiment of the present disclosure;

[0072] Figure 41 is a red diagonal line diagram of the display panel shown in Figure 14 and the corresponding figure in Figure 40;

[0073] Figure 42 is a red diagonal line diagram of the display panel shown in Figure 26 corresponding to Figure 40. Detailed Implementation

[0074] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be noted that, for clarity, the thickness of layers, films, panels, regions, etc., is enlarged in the drawings. Exemplary embodiments are described in this disclosure with reference to cross-sectional views as schematic diagrams of idealized embodiments. Thus, deviations from the shape of the figures will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described in this disclosure should not be construed as limited to the specific shape of the regions shown in this disclosure, but rather include deviations in shape caused, for example, by manufacturing processes. For example, a region illustrated or described as flat may typically have rough and / or non-linear characteristics; a sharp corner illustrated may be rounded, etc. Therefore, the regions shown in the figures are schematic in nature, and their dimensions and shapes are not intended to illustrate the precise shape of the regions or reflect true proportions; their purpose is merely to illustrate the content of this disclosure. And throughout, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0075] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “inner,” “outer,” “upper,” and “lower” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0076] In the following description, when an element or layer is referred to as "on" or "connected to" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. When an element or layer is referred to as "located on one side of" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. However, when an element or layer is referred to as "directly on" or "directly connected to" another element or layer, no intermediate elements or intermediate layers are present. The term "and / or" includes any and all combinations of one or more of the related listed items.

[0077] In DLG mode, because two rows of gate lines are opened simultaneously, the corresponding two pixels will write the same data, resulting in a halving of the actual display resolution and more obvious jagged edges on the displayed graphics. Taking the display panel with the single-gate pixel architecture shown in Figure 1 displaying a red diagonal line as an example, in Figure 1, one data line (e.g., d1~d18) is electrically connected to a column of sub-pixels (e.g., red sub-pixel R, green sub-pixel G, blue sub-pixel B), and one gate line (e.g., G1~G6) is electrically connected to a row of sub-pixels (e.g., red sub-pixel R, green sub-pixel G, blue sub-pixel B), and each adjacent red sub-pixel R, green sub-pixel G, and blue sub-pixel B along the row direction constitutes a pixel. Figure 2 is a gate line scanning timing diagram of the pixel area in DLG mode, and Figure 3 is a display effect diagram corresponding to the gate line scanning timing shown in Figure 2. In Figure 3, the pattern-filled red sub-pixels constitute the red diagonal line image. As shown in Figures 2 and 3, in DLG mode, the scanning timing of the first grid line G1 and the second grid line G2 is the same; the scanning timing of the third grid line G3 and the fourth grid line G4 is the same; the scanning timing of the fifth grid line G5 and the sixth grid line G6 is the same, and so on. Consequently, the red sub-pixels displaying the red diagonal lines in the first and second rows of pixels controlled by the first and second grid lines G1 and G2 are written with the same first data D1; the red sub-pixels displaying the red diagonal lines in the third and fourth rows of pixels controlled by the third and fourth grid lines G3 and G4 are written with the same second data D3; the red sub-pixels displaying the red diagonal lines in the fifth and sixth rows of pixels controlled by the fifth and sixth grid lines G5 are written with the same third data D5, and so on. This results in the actual resolution of the red diagonal lines being halved, and the jagged edges becoming more pronounced.

[0078] In order to improve the above-mentioned technical problems existing in the related technologies, this disclosure provides a display panel display method. Figure 4 is a flowchart of the display panel display method provided in this disclosure.

[0079] As shown in Figure 4, the display method of the display panel provided in this embodiment may include the following steps:

[0080] S401. Receive multiple frames of first display data, the resolution of the first display data being the same as the resolution of the display panel.

[0081] In some embodiments, the resolution of the first display data and the resolution of the display panel can be 4K2K, etc. The first display data with 4K2K resolution includes 3840x2160 data points, and the display panel with 4K2K resolution includes 3840x2160 sub-pixels.

[0082] S402. In the dual-line driving mode, the number of lines of the first display data of each frame is compressed by half and used as the second display data of each frame. The second display data of some frames is output to the display panel for display. The second display data of at least one frame of the remaining frames is shifted by at least one pixel along the line direction and then output to the display panel for display. Among them, at least one frame of some frames is output alternately with at least one frame of the remaining frames.

[0083] In some embodiments, the second display data of the odd-numbered frames can be directly output to the display panel for display, and the second display data of the even-numbered frames can be shifted along the line direction by at least one pixel before being output to the display panel for display; alternatively, the second display data of multiple consecutive frames (e.g., 2 consecutive frames, 3 consecutive frames, etc.) can be output to the display panel for display, and then the second display data of multiple consecutive frames (e.g., 2 consecutive frames, 3 consecutive frames, etc.) can be shifted along the line direction by at least one pixel before being output to the display panel for display.

[0084] In some embodiments, at least one frame of second display data of the remaining frames is shifted at least one pixel along the row direction before being output to the display panel for display. Specifically, at least one frame of second display data of the remaining frames may be shifted one or two pixels along the row direction (e.g., shifted to the left, i.e., shifted toward the first column of pixels; or shifted to the right, i.e., shifted toward the last column of pixels) before being output to the display panel for display, so as to avoid excessive blurring at the edges of the image.

[0085] In some embodiments, after at least one frame of second display data in the remaining frames is shifted to the left (i.e., shifted towards the first column of sub-pixels) by one or two pixels, the second display data of the last or last two pixels is missing. In this case, L0 grayscale data can be written for the last or last two pixels, or the second display data of the third pixel can be written for the last or last two pixels. Similarly, after at least one frame of second display data in the remaining frames is shifted to the right (i.e., shifted towards the last column of sub-pixels) by one or two pixels, the second display data of the first or last two pixels is missing. In this case, L0 grayscale data can be written for the first or last two pixels, or the second display data of the third pixel can be written for the first or last two pixels. Since the first and second pixels, as well as the last and second pixels, are located at the edge of the display area AA, and the effective display area (i.e., the display area conveying effective information such as images or text) usually does not completely fill the display area AA, the impact of writing L0 grayscale data or writing the grayscale data of the third and third-to-last pixels on the overall display effect is minimal. Therefore, in some embodiments, this disclosure does not require additional data to be added to the first and second pixels, as well as the last and second pixels, where the second display data is missing.

[0086] In some embodiments, in the above-described display method provided in the present disclosure, by using a data writing method in the dual-line driving mode, the number of rows of the first display data of each frame is compressed by half and used as the second display data of each frame, and the second display data of some frames is directly output to the display panel, and at least one frame of the second display data of the remaining frames is shifted and output to the display panel, the effect of displaying the edge pixels of the graphic as the data interpolation of the surrounding pixels (e.g., the left and right adjacent pixels) can be achieved, making the edge transition smoother, thereby improving the edge jaggedness problem.

[0087] In some embodiments, in the display method provided in the present disclosure, the step S402 of compressing the number of rows of the first display data of each frame by half and using it as the second display data of each frame can specifically be: using the odd-numbered rows of the first display data of each frame as the second display data of each frame; or using the even-numbered rows of the first display data of each frame as the second display data of each frame; or interpolating the odd and even rows of the first display data of each frame as the second display data of each frame.

[0088] Optionally, the odd and even row data interpolation of the first displayed data can be calculated according to the following formula;

[0089] D iz =O iz ×q+E iz ×(1-q), or, D iz =(O iz +E iz ) / 2; where 0≤q≤1, D iz

[0090] For the z-th (z is a positive integer) data in the i-th (i is a positive integer) row of the second display data, O iz E represents the z-th data in the (2i-1)-th row of the first displayed data. iz This refers to the z-th data in the 2i-th row of the first displayed data.

[0091] For the single-gate display panel shown in Figure 1, taking the odd-numbered rows of the first display data of each frame as the second display data of each frame, and the second display data of the odd-numbered frames being directly output to the display panel for displaying red diagonal lines, and the second display data of the even-numbered frames being shifted one pixel to the left before being output to the display panel for displaying red diagonal lines as an example, Figure 5 shows the red diagonal line diagram corresponding to the first display data, Figure 6 shows the red diagonal line diagram corresponding to the second display data of the odd-numbered frames, Figure 7 shows the red diagonal line diagram corresponding to the second display data of the even-numbered frames, and Figure 8 is a superimposed diagram of the red diagonal line diagrams corresponding to the second display data of the odd-numbered frames and the second display data of the even-numbered frames. The red sub-pixels filled by the patterns in Figures 5 to 8 constitute the red diagonal line diagram. As can be seen from Figures 6 to 8, the odd-numbered frames write the corresponding original odd-numbered rows of data, and the even-numbered frames write the data corresponding to the original odd-numbered rows shifted one pixel to the left. The two are superimposed, and the actual display of the edge pixels of the displayed graphic is the effect of interpolation of the data of the left and right adjacent pixels, making the edge transition smoother, thereby effectively improving the edge jaggedness problem.

[0092] In some embodiments, in the display method provided in this disclosure, under DLG mode, the two gate lines driven simultaneously can be: the nth and (n+m)th gate lines are driven simultaneously in each frame time, where n is an integer greater than or equal to 1 and less than or equal to N / 2, m is a positive integer less than or equal to 3, and N is the total number of gate lines. For example, the gate line scanning timing corresponding to FIG6 is shown in FIG9, and the gate line scanning timing corresponding to FIG7 is shown in FIG10. As can be seen from FIG9 and FIG10, the scanning timing of the first gate line G1 and the second gate line G2 is the same, the scanning timing of the third gate line G3 and the fourth gate line G4 is the same, the scanning timing of the fifth gate line G5 and the sixth gate line G6 is the same, and so on.

[0093] In some embodiments, in the display method provided in the present disclosure, in DLG mode, the two gate lines driven simultaneously can be: driving the nth and (n+m)th gate lines simultaneously in one time period during a partial frame and the remaining frames, and driving the (n+m)th and (n+2m)th gate lines simultaneously in another time period; for example, driving the nth and (n+m)th gate lines simultaneously during a partial frame time period, and driving the (n+m)th and (n+2m)th gate lines simultaneously during the remaining frame time period; or, driving the nth and (n+m)th gate lines simultaneously during the remaining frame time period, and driving the (n+m)th and (n+2m)th gate lines simultaneously during a partial frame time period; where n is an integer greater than or equal to 1 and less than or equal to N / 2, m is a positive integer less than or equal to 3, and N is the total number of gate lines.

[0094] For example, as shown in Figure 9, the nth and (n+1)th gate lines are driven simultaneously during odd-numbered frame times; as shown in Figure 11, the (n+1)th and (n+2)th gate lines are driven simultaneously during even-numbered frame times. The red diagonal diagram corresponding to Figure 9 is Figure 6, the red diagonal diagram corresponding to Figure 11 is Figure 12, and Figure 13 is a superimposed diagram of Figures 6 and 12. D12, D32, and D52 in Figure 11 correspond to R12, R32, and R52 in Figure 12, respectively. Furthermore, as can be seen from Figures 6, 12, and 13, by superimposing odd and even frames, an interpolation effect is achieved for adjacent vertical and horizontal pixels at the edge of the displayed graphic, resulting in better edge smoothing and improved edge jaggedness.

[0095] Figure 14 shows a display panel with a dual-gate pixel architecture. One data line (e.g., d1–d10) is electrically connected to two columns of sub-pixels (e.g., red sub-pixel R, green sub-pixel G, blue sub-pixel B). One gate line (e.g., G1–G12) is electrically connected to one row of sub-pixels (e.g., red sub-pixels R, green sub-pixels G, blue sub-pixels B). Each adjacent red sub-pixel R, green sub-pixel G, and blue sub-pixel B along the row direction constitutes one pixel. Comparing Figure 1 and Figure 14, it can be seen that the number of gate lines (e.g., G1–G12) is doubled compared to a single-gate pixel architecture display panel, while the number of data lines (e.g., d1–d10) is halved. Therefore, one data line needs to connect two columns of sub-pixels in the corresponding row of pixels simultaneously.

[0096] In DLG mode, the red diagonal line image displayed on the display panel of the dual-gate pixel architecture is shown in Figure 15, and the corresponding gate scan timing is shown in Figure 16. The red sub-pixels filled in the pattern in Figure 15 constitute the red diagonal line image. Combining Figures 15 and 16, it can be seen that the scan timing of odd-numbered gate lines is the same for every pair of adjacent pixels, and the scan timing of even-numbered gate lines is the same for every pair of adjacent pixels. For example, the scan timing of the first gate line G1 and the third gate line G3 is the same, the scan timing of the second gate line G2 and the fourth gate line G4 is the same, and so on. Similarly, because adjacent pixel rows have the same data in DLG mode, the actual resolution is halved, and the jagged edges are more noticeable.

[0097] The display method provided in this embodiment can effectively improve the edge jaggedness problem. Specifically: For the dual gate display panel shown in FIG14, taking the odd-numbered rows of the first display data of each frame as the second display data of each frame, and the second display data of the odd-numbered frames directly output to the display panel for displaying red diagonal lines, and the second display data of the even-numbered frames shifted one pixel to the left before being output to the display panel for displaying red diagonal lines. FIG17 is the red diagonal line diagram corresponding to the first display data, FIG18 is the red diagonal line diagram corresponding to the second display data of the odd-numbered frames, FIG19 is the red diagonal line diagram corresponding to the second display data of the even-numbered frames, FIG20 is the superimposed diagram of the red diagonal line diagram corresponding to the second display data of the odd-numbered frames and the red diagonal line diagram corresponding to the second display data of the even-numbered frames, and the red sub-pixels filled by the patterns in FIG17 to FIG20 constitute the red diagonal line diagram. As can be seen from Figures 18 to 20, odd-numbered frames write the corresponding original odd-numbered rows of data, and even-numbered frames write the data corresponding to the original odd-numbered rows shifted one pixel to the left. The two are superimposed, and the actual display of the edge pixels of the graphic is the interpolation of the data of the left and right adjacent pixels, which makes the edge transition smoother and can effectively improve the edge jaggedness problem.

[0098] In some embodiments, the gate line driving timing corresponding to the red diagonal diagram shown in Figure 18 can be as shown in Figure 21, and the gate line driving timing corresponding to the red diagonal diagram shown in Figure 19 can be as shown in Figure 22. As can be seen from Figures 21 and 22, the nth and (n+2)th gate lines are driven simultaneously within each frame time. In some embodiments, this disclosure can also drive the nth and (n+2)th gate lines simultaneously within odd-numbered frame time, as shown in Figure 21, but as shown in Figure 23, the (n+2)th and (n+4)th gate lines are driven simultaneously within even-numbered frame time. The red diagonal diagram corresponding to Figure 23 is Figure 24, and Figure 25 is a superimposed diagram of Figures 18 and 24. As can be seen from Figures 18, 24, and 25, by superimposing odd and even frames, an interpolation effect is achieved for the adjacent vertical and horizontal pixels of the edge pixels of the displayed graphic, resulting in better edge smoothing and improved edge jaggedness.

[0099] Figure 26 shows a display panel with a triple-gate pixel architecture. Along the column direction, each adjacent red sub-pixel R, green sub-pixel G, and blue sub-pixel B constitutes a pixel. One data line (e.g., d1–d6) is electrically connected to a column of sub-pixels (e.g., red sub-pixels R, green sub-pixels G, and blue sub-pixels B), and one gate line (e.g., G1–G12) is electrically connected to a row of sub-pixels (e.g., red sub-pixels R, green sub-pixels G, and blue sub-pixels B). Comparing Figure 1 and Figure 26, it can be seen that the number of gate lines (e.g., G1–G12) becomes three times that of a single-gate display panel, and the number of data lines (e.g., d1–d6) is reduced to one-third. Correspondingly, one data line needs to connect three sub-pixels in the same column.

[0100] In DLG mode, the scanning timing of the grid lines in the triple-gate pixel architecture display panel is shown in Figure 27, and the corresponding red diagonal line image is shown in Figure 28. The red sub-pixels filled in the pattern in Figure 28 constitute the red diagonal line image. Combining Figures 27 and 28, it can be seen that the scanning timing of the nth and (n+3th)th grid lines is the same. For example, the scanning timing of the first grid line G1 and the fourth grid line G4 is the same, the scanning timing of the second grid line G2 and the fifth grid line G5 is the same, the scanning timing of the third grid line G3 and the sixth grid line G6 is the same, and so on. Similarly, because the data of adjacent pixel rows is the same in DLG mode, the actual resolution is halved, and the jagged edges are more obvious.

[0101] The display method provided in this embodiment can effectively improve the edge jaggedness problem. Specifically, for the triple gate display panel shown in FIG26, taking the odd-numbered rows of the first display data of each frame as the second display data of each frame, and the second display data of the odd-numbered frames directly output to the display panel for displaying red diagonal lines, and the second display data of the even-numbered frames shifted one pixel to the left before being output to the display panel for displaying red diagonal lines. FIG29 is a red diagonal line diagram corresponding to the first display data, FIG30 is a red diagonal line diagram corresponding to the second display data of the odd-numbered frames, FIG31 is a red diagonal line diagram corresponding to the second display data of the even-numbered frames, FIG32 is a superimposed diagram of the red diagonal line diagrams corresponding to the second display data of the odd-numbered frames and the second display data of the even-numbered frames, and the red sub-pixels filled by the patterns in FIG29 to FIG32 constitute the red diagonal line diagram. As shown in Figures 30 to 32, odd-numbered frames write the corresponding original odd-numbered rows of data, while even-numbered frames write the data corresponding to the original odd-numbered rows shifted one pixel to the left. The two are superimposed, and the effect of interpolating the data of the left and right adjacent pixels is displayed at the edge of the graphic, making the edge transition smoother and thus effectively improving the edge jaggedness problem.

[0102] In some embodiments, the gate line driving timing corresponding to the red diagonal diagram shown in Figure 30 can be as shown in Figure 33, and the gate line driving timing corresponding to the red diagonal diagram shown in Figure 31 can be as shown in Figure 34. As can be seen from Figures 33 and 34, the nth and (n+3)th gate lines can be driven simultaneously within each frame time. In some embodiments, this disclosure can also drive the nth and (n+3)th gate lines simultaneously within odd-numbered frame time, as shown in Figure 33, but drive the (n+3)th and (n+6)th gate lines simultaneously within even-numbered frame time, as shown in Figure 35. The red diagonal diagram corresponding to Figure 36 is Figure 35, and Figure 37 is a superimposed diagram of Figures 30 and 36. As can be seen from Figures 30, 36, and 37, by superimposing odd and even frames, an interpolation effect is achieved for adjacent vertical and horizontal pixels at the edge of the displayed graphic, resulting in better edge smoothing and improved edge jaggedness.

[0103] In some embodiments, in the display method provided in this disclosure, as shown in Figures 6, 7, 9 to 12, 18, 19, 21 to 24, 30, 31, and 33 to 36, while driving two gate lines of the same gate line group, second display data is written to sub-pixels of the same color. For example, in Figures 18 and 21, the first gate line G1 and the third gate line G3 are turned on simultaneously. At this time, the two sub-pixels connected by the first gate line G1 and the third gate line G3 corresponding to the same data line have the same color, so that the same second display data (e.g., D11) is written to two red sub-pixels.

[0104] In some embodiments, the display method provided in the present disclosure, as shown in FIG4, may further include step S403: in progressive drive mode, directly outputting the first display data of each frame to the display panel for display.

[0105] In some embodiments, for the single gate display panel shown in FIG1, FIG38 is a timing diagram of the gate line scanning in progressive drive mode, and FIG39 is a corresponding red diagonal line display effect diagram of FIG38. As can be seen from FIG38 and FIG39, D1, D2, D3, D4, D5, D6, etc. in the first display data are directly written into the display panel, realizing the display of the red diagonal line diagram.

[0106] In some embodiments, for the dual gate display panel shown in FIG14, FIG40 is its gate line scanning timing diagram in progressive drive mode, and FIG41 is the corresponding red diagonal line display effect diagram of FIG40. As can be seen from FIG40 and FIG41, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12 and other data in the first display data are directly written into the display panel, realizing the display of the red diagonal line diagram.

[0107] In some embodiments, for the triple gate display panel shown in FIG26, FIG40 is a timing diagram of the gate line scanning in progressive drive mode, and FIG42 is a corresponding red diagonal line display effect diagram of FIG40. As can be seen from FIG40 and FIG42, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, etc. in the first display data are directly written into the display panel, realizing the display of the red diagonal line diagram.

[0108] Those skilled in the art will understand that embodiments of this disclosure can be provided as methods, systems, or computer program products. Therefore, this disclosure can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this disclosure can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0109] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more flowchart illustrations and / or one or more block diagrams.

[0110] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams.

[0111] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.

[0112] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0113] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. A display panel display method, wherein, include: Receive multiple frames of first display data, wherein the resolution of the first display data is the same as the resolution of the display panel; In dual-line driving mode, the number of lines of the first display data of each frame is compressed by half and used as the second display data of each frame. The second display data of some frames is output to the display panel for display. The second display data of at least one frame of the remaining frames is shifted by at least one pixel along the line direction and then output to the display panel for display. The at least one frame of the partial frames is output alternately with the at least one frame of the remaining frames.

2. The display method as described in claim 1, wherein, The step of compressing the number of rows of the first display data in each frame by half and using it as the second display data for each frame specifically includes: Each odd-numbered row of the first display data in each frame is used as the second display data in each frame.

3. The display method as described in claim 1, wherein, The step of compressing the number of rows of the first display data in each frame by half and using it as the second display data for each frame specifically includes: Each even-numbered row of the first display data in each frame is used as the second display data for each frame.

4. The display method as described in claim 1, wherein, The step of compressing the number of rows of the first display data in each frame by half and using it as the second display data for each frame specifically includes: The second display data for each frame is calculated using the following formula: D iz =O iz ×q+E iz ×(1-q), or, D iz =(O iz +E iz ) / 2; where 0≤q≤1, D iz For the z-th (z is a positive integer) data in the i-th (i is a positive integer) row of the second displayed data, O iz E represents the z-th data in the (2i-1)-th row of the first displayed data. iz This refers to the z-th data in the 2i-th row of the first displayed data.

5. The display method according to any one of claims 1 to 4, wherein, The second display data in at least one of the remaining frames is shifted by at least one pixel along the line direction, specifically including: In at least one of the remaining frames, the second display data is shifted at least one pixel toward the first or last column of pixels.

6. The display method according to any one of claims 1 to 5, wherein, The display panel includes multiple grid lines extending along the row direction and arranged along the column direction, with two grid lines forming a grid line group. The dual-row driving mode specifically includes: Within one frame, each of the gate line groups is driven one by one, and two gate lines of the same gate line group are driven simultaneously.

7. The display method as described in claim 6, wherein, Simultaneously driving two gate lines of the same gate line group specifically includes: In one of the partial frames and the remaining frames, the nth and (n+m)th gate lines are driven simultaneously, and in another of the frames, the (n+m)th and (n+2m)th gate lines are driven simultaneously, where n is an integer greater than or equal to 1 and less than or equal to N / 2, m is a positive integer less than or equal to 3, and N is the total number of gate lines.

8. The display method as described in claim 6, wherein, Simultaneously driving two gate lines of the same gate line group specifically includes: During each frame time, the nth and (n+m)th gate lines are driven simultaneously, where n is an integer greater than or equal to 1 and less than or equal to N / 2, m is a positive integer less than or equal to 3, and N is the total number of gate lines.

9. The display method according to any one of claims 6 to 8, wherein, The display panel includes multiple sub-pixels of different colors, and while driving two gate lines of the same gate line group, it also includes: writing the second display data to sub-pixels of the same color.

10. The display method according to any one of claims 1 to 9, wherein, Also includes: In progressive drive mode, the first display data of each frame is directly output to the display panel for image display.

11. A display panel, wherein, The display panel includes multiple gate lines extending in the row direction and arranged in the column direction, multiple data lines extending in the column direction and arranged in the row direction, and multiple sub-pixels located in the area defined by the intersection of each gate line and each data line. At least two sub-pixels constitute one pixel. The sub-pixels are electrically connected to the gate lines and the data lines respectively. The display panel is displayed using the display method described in any one of claims 1 to 10.

12. The display panel as claimed in claim 11, wherein, In the row direction, at least two adjacent sub-pixels constitute one pixel.

13. The display panel as claimed in claim 11, wherein, In the column direction, at least two adjacent sub-pixels constitute one pixel.

14. The display panel as claimed in claim 12 or 13, wherein, One of the gate lines is electrically connected to a row of the sub-pixels, and one of the data lines is electrically connected to a column of the sub-pixels.

15. The display panel as claimed in claim 12, wherein, The two gate lines are electrically connected to a row of the sub-pixels, and the sub-pixels in adjacent rows electrically connected by the same data line are located in adjacent columns.

16. A display device, wherein, Includes the display panel as described in any one of claims 11 to 15.

Images