Connector port multiplexing apparatus and method, and chip

Abstract

Provided in the present disclosure is a connector port multiplexing apparatus, comprising: a latch reset circuit, which is electrically connected to a first voltage source and a power terminal of a universal serial bus connector, and is configured to output a control signal on the basis of a first voltage that is output by the first voltage source and a second voltage from the universal serial bus connector; and an analog switch circuit, a control terminal of which is electrically connected to an output terminal of the latch reset circuit, a first terminal of which is electrically connected to a first signal transmission terminal of a universal serial bus controller, a second terminal of which is electrically connected to a second signal transmission terminal of the universal serial bus controller, and a third terminal of which is electrically connected to a multiplexing signal transmission terminal of the universal serial bus connector, wherein the analog switch circuit is configured to establish, on the basis of the control signal, a connection path between the first terminal and the third terminal of the analog switch circuit or a connection path between the second terminal and the third terminal of the analog switch circuit.

Description

Connector port multiplexing device, method and chip Technical Field

[0001] The present disclosure relates to the field of communication technology, and in particular to a connector port multiplexing device, method, and chip. Background Art

[0002] A Universal Serial Bus (USB) controller on a chip, typically a system-on-chip (SoC) or integrated circuit (IC), typically includes multiple USB ports, or signal transmission ports. These ports are used for different functions when the chip is in different communication modes, and each USB port is connected to its own USB connector. This results in a large number of USB connectors on the chip, high chip cost, and a large layout area on the printed circuit board (PCB).

[0003] Summary of the Invention

[0004] The present disclosure provides a connector port multiplexing device, method, and chip.

[0005] According to a first aspect, the present disclosure provides a connector port multiplexing device, comprising: a latch reset circuit, electrically connected to a first voltage source and a power supply terminal of a universal serial bus connector, the latch reset circuit being configured to output a control signal based on a first voltage output by the first voltage source and a second voltage from the universal serial bus connector; an analog switch circuit, wherein a control terminal of the analog switch circuit is electrically connected to an output terminal of the latch reset circuit, a first terminal of the analog switch circuit is electrically connected to a first signal transmission terminal of a universal serial bus controller, a second terminal of the analog switch circuit is electrically connected to a second signal transmission terminal of the universal serial bus controller, and a third terminal of the analog switch circuit is electrically connected to a multiplexing signal transmission terminal of the universal serial bus connector; the analog switch circuit is configured to establish a connection path between the first terminal and the third terminal of the analog switch circuit or establish a connection path between the second terminal and the third terminal of the analog switch circuit based on the control signal.

[0006] For example, the latch reset circuit includes: a first latch reset sub-circuit and a second latch reset sub-circuit; wherein, the output end of the first latch reset sub-circuit is electrically connected to the control end of the analog switch circuit, the input end of the first latch reset sub-circuit is electrically connected to the first voltage source and the output end of the second latch reset sub-circuit, and is configured to output the control signal according to the first voltage and the third voltage output by the second latch reset sub-circuit; the input end of the second latch reset sub-circuit is electrically connected to the power supply end of the universal serial bus connector and the output end of the first latch reset sub-circuit, and is configured to output the third voltage according to the second voltage and the control signal.

[0007] For example, the above-mentioned latch reset circuit includes: a first latch reset sub-circuit and a second latch reset sub-circuit; wherein, the output end of the above-mentioned second latch reset sub-circuit is electrically connected to the control end of the above-mentioned analog switch circuit, and the input end of the second latch reset sub-circuit is electrically connected to the power supply end of the above-mentioned universal serial bus connector and the output end of the above-mentioned first latch reset sub-circuit, and is configured to output the above-mentioned control signal according to the above-mentioned second voltage and the fourth voltage output by the above-mentioned first latch reset sub-circuit; the input end of the above-mentioned first latch reset sub-circuit is electrically connected to the above-mentioned first voltage source and the output end of the above-mentioned second latch reset sub-circuit, and is configured to output the above-mentioned fourth voltage according to the above-mentioned first voltage and the above-mentioned control signal.

[0008] For example, the second latch reset sub-circuit and the first latch reset sub-circuit are symmetrical in structure.

[0009] For example, the connector port multiplexing device further includes: a unidirectional conduction delay switch, the input end of the unidirectional conduction delay switch being electrically connected to the first voltage source, the output end of the single-phase conduction delay switch being electrically connected to the power supply end of the universal serial bus connector, and being configured to establish a connection path between the first voltage source and the power supply end of the universal serial bus connector after a first predetermined time period when the first voltage is at a first level.

[0010] For example, the first latch reset subcircuit includes: a first transistor, a second transistor, a first capacitor, a first resistor, a second resistor, a third resistor, a fourth resistor and a fifth resistor; wherein the control electrode of the first transistor is electrically connected to the first end of the first resistor, the first electrode of the first transistor is electrically connected to the first voltage source and the input end of the first diode, the second electrode of the first transistor is electrically connected to the first end of the second resistor and the first end of the third resistor, and the second electrode of the first transistor is the output end of the first latch reset subcircuit; the output end of the first diode is electrically connected to the second end of the first resistor, the second end of the third resistor is electrically connected to the first end of the fourth resistor, and the second end of the second resistor and the second end of the fourth resistor are both grounded; the control electrode of the second transistor is electrically connected to the first voltage dividing point between the third resistor and the fourth resistor, the first electrode of the second transistor is electrically connected to the first end of the fifth resistor, the second end of the fifth resistor is grounded, and the second electrode of the second transistor is electrically connected to the first end of the first resistor; the positive electrode of the first capacitor is electrically connected to the first voltage source, and the negative electrode of the first capacitor is electrically connected to the first voltage dividing point.

[0011] For example, the above-mentioned first latch reset subcircuit also includes: a second capacitor, a sixth resistor and a seventh resistor; wherein, the positive electrode of the above-mentioned second capacitor is electrically connected to the second electrode of the above-mentioned first transistor, and the negative electrode of the above-mentioned second capacitor is grounded; the first end of the above-mentioned sixth resistor is electrically connected to the control electrode of the above-mentioned first transistor, and the second end of the above-mentioned sixth resistor is electrically connected to the first end of the above-mentioned first resistor; the first end of the above-mentioned seventh resistor is electrically connected to the above-mentioned first voltage dividing point, and the second end of the above-mentioned seventh resistor is electrically connected to the control electrode of the above-mentioned second transistor.

[0012] For example, the first latch reset subcircuit further includes: a second diode; wherein the input end of the second diode is electrically connected to the output end of the second latch reset subcircuit, and the output end of the second diode is electrically connected to the first end of the first resistor.

[0013] For example, the second latch reset subcircuit includes: a third transistor, a fourth transistor, a third diode, a third capacitor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, and a twelfth resistor; wherein the control electrode of the third transistor is electrically connected to the first end of the eighth resistor, the first electrode of the third transistor is electrically connected to the power supply end of the universal serial bus connector and the input end of the third diode, the second electrode of the third transistor is electrically connected to the first end of the ninth resistor and the first end of the tenth resistor, the second electrode of the third transistor is the output end of the second latch reset subcircuit; the output end of the third diode is electrically connected to the The second end of the eighth resistor is electrically connected, the second end of the tenth resistor is electrically connected to the first end of the eleventh resistor, and the second end of the ninth resistor and the second end of the eleventh resistor are both grounded; the control electrode of the fourth transistor is electrically connected to the second voltage dividing point between the tenth resistor and the eleventh resistor, the first electrode of the fourth transistor is electrically connected to the first end of the twelfth resistor, the second end of the twelfth resistor is grounded, and the second electrode of the fourth transistor is electrically connected to the first end of the eighth resistor; the positive electrode of the third capacitor is electrically connected to the power supply terminal of the universal serial bus connector, and the negative electrode of the third capacitor is electrically connected to the second voltage dividing point.

[0014] For example, the second latch reset sub-circuit further includes: a fourth capacitor, a thirteenth resistor and a fourteenth resistor; wherein the positive electrode of the fourth capacitor is electrically connected to the second electrode of the third transistor, and the negative electrode of the fourth capacitor is grounded; the first end of the thirteenth resistor is electrically connected to the control electrode of the third transistor, and the second end of the thirteenth resistor is electrically connected to the first end of the eighth resistor; the first end of the fourteenth resistor is electrically connected to the second voltage dividing point, and the second end of the fourteenth resistor is electrically connected to the control electrode of the fourth transistor.

[0015] For example, the second latch reset subcircuit further includes: a fourth diode and a fifth diode; wherein, the input end of the fourth diode is electrically connected to the output end of the first latch reset subcircuit, and the output end of the fourth diode and the output end of the fifth diode are both electrically connected to the first end of the eighth resistor; when the chip is used as a slave device, the control signal is at the second level, and a connection path is established between the first end and the third end of the analog switch, the input end of the fifth diode is left floating; when the chip is used as a slave device, the control signal is at the first level, and a connection path is established between the first end and the third end of the analog switch, the fifth diode is electrically connected to the universal input / output interface of the universal serial bus controller.

[0016] According to a second aspect, the present disclosure provides a chip comprising: a universal serial bus controller comprising: a first signal transmission terminal and a second signal transmission terminal; a universal serial bus connector comprising: a multiplexed signal transmission terminal; and the above-mentioned connector port multiplexing device.

[0017] According to a third aspect, the present disclosure provides a connector port multiplexing method, which is applied to the above-mentioned connector port multiplexing device. The above-mentioned connector port multiplexing method includes: when the above-mentioned chip is used as a main control device, receiving a first voltage output by a first voltage source; after a first predetermined time period, receiving a second voltage from a universal serial bus connector; outputting a control signal based on the above-mentioned first voltage and the above-mentioned second voltage; and establishing a connection path between the second end and the third end of the analog switch based on the above-mentioned control signal.

[0018] According to a fourth aspect, the present disclosure provides a connector port multiplexing method, which is applied to the above-mentioned connector port multiplexing device. The above-mentioned connector port multiplexing method includes: when the above-mentioned chip is used as a slave device, receiving a second voltage from a universal serial bus connector; after a second predetermined time period, receiving a first voltage output by a first voltage source; outputting a control signal based on the above-mentioned first voltage and the above-mentioned second voltage; and establishing a connection path between the first end and the third end of the analog switch based on the above-mentioned control signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings are provided to facilitate a better understanding of the present invention and do not constitute a limitation of the present disclosure.

[0020] FIG1 is a schematic diagram showing the structure of a circuit formed by an example of a universal serial bus connector and a universal serial bus controller;

[0021] FIG2A is a schematic structural diagram of a connector port multiplexing device according to an embodiment of the present disclosure;

[0022] FIG2B is a schematic structural diagram of a connector port multiplexing device according to another embodiment of the present disclosure;

[0023] FIG3A is a schematic structural diagram of a connector port multiplexing device according to another embodiment of the present disclosure;

[0024] FIG3B is a schematic structural diagram of a connector port multiplexing device according to another embodiment of the present disclosure;

[0025] FIG4 is a schematic structural diagram of a latch reset circuit according to an embodiment of the present disclosure;

[0026] FIG5 is a schematic structural diagram of a latch reset circuit according to another embodiment of the present disclosure;

[0027] FIG6 is a signal timing diagram of the latch reset circuit in FIG5 ;

[0028] FIG7 is another signal timing diagram of the latch reset circuit in FIG5 ;

[0029] FIG8 is a schematic structural diagram of a connector port multiplexing device according to another embodiment of the present disclosure;

[0030] FIG9 is a schematic structural diagram of a chip according to an embodiment of the present disclosure;

[0031] FIG10 is a flowchart of a connector port multiplexing method according to an embodiment of the present disclosure;

[0032] 11 is a flowchart of a connector port multiplexing method according to another embodiment of the present disclosure;

[0033] FIG12 is an application scenario diagram of a connector port multiplexing device according to an embodiment of the present disclosure;

[0034] FIG13A is a circuit diagram of a latch reset circuit according to one embodiment of the present disclosure; and

[0035] FIG. 13B is a circuit diagram of an analog switch circuit according to one embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of them. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure. It should be noted that throughout the drawings, the same elements are represented by the same or similar figure marks. In the following description, some specific embodiments are only for descriptive purposes and should not be understood as any limitation to the present disclosure, but are only examples of the embodiments of the present disclosure. Conventional structures or configurations will be omitted when they may cause confusion in the understanding of the present disclosure. It should be noted that the shapes and sizes of the components in the figures do not reflect the actual size and proportion, but only illustrate the contents of the embodiments of the present disclosure.

[0037] Unless otherwise defined, technical or scientific terms used in the embodiments of the present disclosure shall have the same general meaning as those skilled in the art. The terms "first," "second," and similar terms used in the embodiments of the present disclosure do not denote any order, quantity, or importance, but are merely used to distinguish different components.

[0038] In addition, in the description of the embodiments of the present disclosure, the terms "connected to," "connected to," or "electrically connected to" may refer to a direct connection between two components or a connection between two components via one or more other components. Furthermore, the two components may be connected or coupled via a wired or wireless connection.

[0039] The transistors used in the embodiments of the present disclosure may be triodes or field-effect transistors. In the embodiments of the present disclosure, when the transistor is a field-effect transistor, based on its function, the gate may be referred to as the control electrode, one of the source and drain may be referred to as the first electrode, and the other of the source and drain may be referred to as the second electrode. When the transistor is a triode, based on its function, the base may be referred to as the control electrode, one of the emitter and collector may be referred to as the first electrode, and the other of the emitter and collector may be referred to as the second electrode.

[0040] In addition, in the description of the embodiments of the present disclosure, the terms "first voltage" and "second voltage" are only used to distinguish that the two voltages have different sources. For example, the following description uses the example of "first voltage" being the voltage output by the first voltage source and "second voltage" being the voltage output by the universal serial bus connector. Those skilled in the art will understand that the present disclosure is not limited to this. The terms "first level" and "second level" are only used to distinguish that the two levels have different amplitudes. For example, the following description uses the example of "first level" being a relatively high voltage and "second level" being a relatively low voltage. Those skilled in the art will understand that the present disclosure is not limited to this.

[0041] It should be noted that in the description of the embodiments of the present disclosure, the symbol VCC can represent both a first voltage source and a first voltage provided by the first voltage source. Similarly, VBUS can represent both a power supply terminal of a universal serial bus connector and a second voltage provided by the power supply terminal of the universal serial bus connector. The symbol DP can represent both a positive data signal and a positive data signal terminal. The symbol DM can represent both a negative data signal and a negative data signal terminal. SSRX+ / SSRX- can represent both a received differential signal and a differential signal receiving terminal. SSTX+ / SSTX- can represent both a transmitted differential signal and a differential signal transmitting terminal. SEL1 can represent both an output terminal of a first latch reset subcircuit and a signal output by the first latch reset subcircuit. SEL2 can represent both an output terminal of a second latch reset subcircuit and a signal output by the second latch reset subcircuit. The following embodiments are the same and will not be described in detail.

[0042] A SoC or IC typically includes a USB controller and a USB connector. A USB controller typically includes multiple USB ports. When the chip is in different communication modes, different USB ports are used for different functions, and each USB port is connected to its own USB connector. Communication modes include USB_Host mode and USB_OTG mode. USB_Host mode can include USB_3.X Host mode and USB_2.0 Host mode.

[0043] FIG1 is a schematic structural diagram of a circuit formed by an example of a universal serial bus connector and a universal serial bus controller.

[0044] Figure 1 shows a circuit formed by a USB connector and a USB controller 101. USB controller 101 may include signal transmission ports: Port 0, Port 1, and Port 2. Port 0 is electrically connected to USB connector 0. Port 1 is electrically connected to USB connector 1. Port 2 is electrically connected to USB connector 2.

[0045] In the example of Figure 1 , the number of port 0 and port 1 can be one or more. The interface types of USB connectors may include Type-A, Type-B, Type-C, mini, micro, and wafer types.

[0046] In USB_3.X Host mode, the chip can act as a host device, and an external device plugged into USB connector 0 can act as a slave device. A connection path can be established between port 0, USB connector 0, or the external device. The chip, acting as a host device, can communicate with the external device acting as a slave device. USB controller 101 uses two pairs of differential lines on port 0: a receive signal (SSRX+ / SSRX-) pair and a transmit signal (SSTX+ / SSTX-) pair. This allows data to be exchanged with external devices at SuperSpeed ​​speeds. The two pairs of differential lines, SSRX+ / SSRX- and SSTX+ / SSTX-, are combined with fixed USB 2.0 differential lines and connected to USB connector 0. USB3.X technologies include USB3.2Gen1, USB3.2Gen2x1, and USB3.2Gen2x2.

[0047] In USB_2.0 Host mode, the chip functions as a host device, and an external device plugged into USB connector 1 functions as a slave device. A connection path is established between port 1, USB connector 1, and the external device, allowing the chip, acting as a host, to communicate with the slave device. USB controller 101 uses a pair of differential lines, DP (Data Positive) and DM (Data Minus), on port 1 to exchange data with the external device at either high speed or full speed.

[0048] In USB_OTG mode, the chip can function as a slave device, and an external device plugged into USB connector 2 can function as a master device. A connection path can be established between port 2, USB connector 2, and the external device, allowing the chip, acting as a slave, to communicate with the external device, acting as a master. The external device can program and debug the chip through port 2 included in USB controller 101. At this point, USB controller 101 uses a pair of differential lines, namely, DP / DM lines, on port 2 to exchange data with the external device.

[0049] As shown in FIG. 1 , multiple USB ports on the USB controller 101 are connected to respective USB connectors, which results in a large number of USB connectors on the chip, high chip cost, and a large chip layout area on the PCB.

[0050] To address the above problems, the present disclosure provides a connector port multiplexing device that can, in USB_OTG mode, multiplex the connector ports corresponding to USB_2.0Host mode or the connector ports corresponding to USB_3.X Host mode, thereby reducing the number of USB connectors used, lowering chip costs and reducing the chip layout area on the PCB.

[0051] Related technologies achieve connector port multiplexing by eliminating the USB 2.0 Host differential line included in the connector corresponding to USB_3.x Host mode and replacing it with a differential line corresponding to USB_OTG mode. This USB connector compromises the integrity of the USB 3.x port and reduces system stability and reliability. Alternatively, switching between USB_2.0 Host and USB_OTG functions is achieved by using a USB connector with an ID (Identity Document) pin. This USB connector uses the ID pin included in the connector port to identify whether an external device acting as a host device is plugged into the USB connector. This imposes special requirements on the USB connector cable: the USB connector cable must have an ID pin, and the ID pin identification process is implemented by software, which does not work if the chip is not programmed. This port multiplexing method is primarily implemented on micro USB connectors and has a relatively limited scope of application. Furthermore, since Type-A USB connectors lack an ID pin, this port multiplexing method cannot be used on the widely used Type-A USB connector.

[0052] In response to the above problems, the present disclosure provides a connector port multiplexing device that can, in USB_OTG mode, multiplex the connector port corresponding to the USB_2.0 Host mode or the connector port corresponding to the USB_3.X Host mode. The connector port multiplexing device uses hardware automatic recognition technology to identify that an external device serving as a master device is inserted into the USB connector of the port multiplexing device, and automatically switches the USB_Host mode to the USB_OTG mode. The entire recognition process does not require software control, has no special requirements for the wire material of the USB connector, does not destroy the USB communication protocol, and does not require the USB connector to include an ID pin. At the same time, it can detect that the external device serving as the master device is unplugged and switch the USB_OTG mode to the USB_Host mode.

[0053] FIG2A is a schematic structural diagram of a connector port multiplexing device according to an embodiment of the present disclosure.

[0054] As shown in FIG. 2A , the connector port multiplexing device 210 may include a latch reset circuit 211 and an analog switch circuit 212 .

[0055] In the embodiment of the present disclosure, the latch reset circuit 211 can be electrically connected to the first voltage source VCC and the power supply terminal VBUS of the universal serial bus connector 202. The latch reset circuit 211 can be configured to output a control signal based on a first voltage output by the first voltage source VCC and a second voltage from the universal serial bus connector 202.

[0056] The universal serial bus connector 202 may be a USB connector corresponding to the USB-3.x host mode. An external device may be electrically connected to the universal serial bus connector 202. The first voltage source represents a power source provided by the chip. The control signal reflects the properties of the external device connected to the USB connector. The control signal reflects whether the external device connected to the USB connector is a master device or a slave device.

[0057] Since the latch reset circuit 211 can be electrically connected to the first voltage source VCC and the power supply terminal VBUS of the universal serial bus connector 202, the latch reset circuit 211 can output a control signal based on the first voltage output by the first voltage source VCC and the second voltage from the universal serial bus connector 202. The control signal reflects the properties of the external device connected to the connector, thereby achieving automatic identification of whether the external device is a master device or a slave device based on the hardware circuit.

[0058] The control terminal SEL of the analog switch circuit 212 can be electrically connected to the output terminal of the latch reset circuit 211. A first terminal of the analog switch circuit 212 can be electrically connected to a first signal transmission terminal of the universal serial bus controller 201. A second terminal of the analog switch circuit 212 can be electrically connected to a second signal transmission terminal of the universal serial bus controller 201. A third terminal of the analog switch circuit 212 can be electrically connected to a multiplexed signal transmission terminal of the universal serial bus connector 202.

[0059] The first signal transmission end represents a differential signal transmission end corresponding to the USB_OTG mode, and the second signal transmission end represents a differential signal transmission end corresponding to the USB_Host mode.

[0060] The first end of the analog switch circuit 212 may include a first data positive signal transmission terminal DP1 and a first data negative signal transmission terminal DM1. The second end of the analog switch circuit 212 may include a second data positive signal transmission terminal DP2 and a second data negative signal transmission terminal DM2. The third end of the analog switch circuit 212 may include a third data positive signal transmission terminal DP3 and a third data negative signal transmission terminal DM3. The first signal transmission end may include a data positive signal transmission terminal DP and a data negative signal transmission terminal DM corresponding to the USB_OTG mode. The second signal transmission end may include a data positive signal transmission terminal DP and a data negative signal transmission terminal DM corresponding to the USB_Host mode. The multiplexed signal transmission end may include a multiplexed data positive signal transmission terminal DP0 and a multiplexed data negative signal transmission terminal DM0.

[0061] DP1 and DM1 can be electrically connected to the data positive signal transmission terminal DP and the data negative signal transmission terminal DM corresponding to the USB_OTG mode, respectively. DP2 and DM2 can be electrically connected to the data positive signal transmission terminal DP and the data negative signal transmission terminal DM corresponding to the USB_Host mode, respectively. DP3 and DM3 can be electrically connected to DP0 and DM0, respectively.

[0062] For example, the second signal transmission terminal may include a data positive signal transmission terminal DP and a data negative signal transmission terminal DM corresponding to the USB_3.X Host mode. In this case, DP2 and DM2 may be electrically connected to the data positive signal transmission terminal DP and the data negative signal transmission terminal DM corresponding to the USB_3.X Host mode, respectively. Simultaneously, the signal terminals SSRX+, SSRX-, SSTX+, and SSTX- corresponding to the USB_3.X Host mode may be electrically connected to the signal terminals SSRX+, SSRX-, SSTX+, and SSTX- on the universal serial bus connector 202, respectively.

[0063] The analog switch circuit 212 may be configured to establish a connection path between the first terminal and the third terminal of the analog switch circuit 212 or to establish a connection path between the second terminal and the third terminal of the analog switch circuit 212 according to a control signal.

[0064] In the case of establishing a connection path between the first terminal and the third terminal of the analog switch circuit 212, DP1 and DM1 can be electrically connected to DP3 and DM3, respectively. In the case of establishing a connection path between the second terminal and the third terminal of the analog switch circuit 212, DP2 and DM3 can be electrically connected to DP3 and DM3, respectively.

[0065] The analog switch circuit 212 may be a double-pole double-throw switch. The analog switch circuit 212 may be an active-high circuit, i.e., when the control signal is high, the first terminal of the analog switch circuit 212 is electrically connected to the third terminal, and when the control signal is low, the second terminal of the analog switch circuit 212 is electrically connected to the third terminal. The analog switch circuit 212 may also be an active-low circuit, i.e., when the control signal is low, the first terminal of the analog switch circuit 212 is electrically connected to the third terminal, and when the control signal is high, the second terminal of the analog switch circuit 212 is electrically connected to the third terminal.

[0066] When the analog switch circuit 212 establishes a connection path between the first terminal and the third terminal of the analog switch circuit 212 according to the control signal, the chip enters the USB_OTG mode. When the analog switch circuit 212 establishes a connection path between the second terminal and the third terminal of the analog switch circuit 212 according to the control signal, the chip enters the USB_Host mode.

[0067] Since the third end of the analog switch circuit 212 can be electrically connected to the multiplexed signal transmission end of the universal serial bus connector 202, the analog switch circuit 212 can establish a connection path between the first end and the third end of the analog switch circuit 212 or establish a connection path between the second end and the third end of the analog switch circuit 212 according to the control signal, so that the multiplexed signal transmission end of the universal serial bus connector 202 is compatible with the USB_2.0 Host function, the USB_3.X Host function, and the USB_OTG function, thereby reducing the number of USB connectors in the chip and saving costs.

[0068] FIG2B is a schematic structural diagram of a connector port multiplexing device according to another embodiment of the present disclosure.

[0069] As shown in Figure 2B, the connector port multiplexing device 210 may include a latch reset circuit 211 and an analog switch circuit 212. The latch reset circuit 211 and the analog switch circuit 212 in Figures 2A and 2B are similar, and for simplicity, the same parts are not repeated here.

[0070] In the embodiment of the present disclosure, the latch reset circuit 211 can be electrically connected to the first voltage source VCC and the power supply terminal VBUS of the universal serial bus connector 203. The latch reset circuit 211 can be configured to output a control signal based on a first voltage output by the first voltage source VCC and a second voltage from the universal serial bus connector 203.

[0071] The USB connector 203 may be a USB connector corresponding to the USB_2.0 host mode, and an external device may be electrically connected to the USB connector 203 .

[0072] The second signal transmission terminal may include a data positive signal transmission terminal DP and a data negative signal transmission terminal DM corresponding to the USB_2.0 Host mode. DP2 and DM2 may be electrically connected to the data positive signal transmission terminal DP and the data negative signal transmission terminal DM corresponding to the USB_2.0 Host mode, respectively.

[0073] As shown in Figures 2A and 2B, the latch reset circuit provided by the present disclosure is electrically connected to a first voltage source and a power terminal of a universal serial bus connector. The latch reset circuit is configured to output a control signal based on a first voltage output by the first voltage source and a second voltage from the universal serial bus connector. The control signal reflects the properties of the external device connected to the connector. This achieves automatic hardware identification of whether a device connected to the universal serial bus connector is a master or slave device, without requiring software control, special requirements for USB connector wire material, disruption of the USB communication protocol, or the inclusion of an ID pin on the USB connector. Then, since the first end of the analog switch circuit is electrically connected to the first signal transmission end of the universal serial bus controller, the second end of the analog switch circuit is electrically connected to the second signal transmission end of the universal serial bus controller, and the third end of the analog switch circuit is electrically connected to the multiplexing signal transmission end of the universal serial bus connector, the analog switch circuit establishes a connection path between the first end and the third end of the analog switch circuit or establishes a connection path between the second end and the third end of the analog switch circuit according to the control signal, thereby achieving automatic connection of the paths corresponding to external devices with different attributes connected to the USB connector through hardware devices without destroying the USB communication protocol and without requiring the USB connector to include an ID pin, thereby multiplexing the multiplexing signal transmission end of the universal serial bus connector.

[0074] FIG3A is a schematic structural diagram of a connector port multiplexing device according to another embodiment of the present disclosure.

[0075] As shown in Figure 3A, the connector port multiplexing device 310 may include a latch reset circuit 311 and an analog switch circuit 312. The latch reset circuit 311 and the analog switch circuit 312 are similar to the latch reset circuit 211 and the analog switch circuit 212 mentioned above, respectively. For the sake of simplicity, the same parts are not repeated here in this disclosure.

[0076] In the embodiment of the present disclosure, the latch reset circuit 310 may include a first latch reset sub-circuit 3111 and a second latch reset sub-circuit 3112 .

[0077] The output terminal SEL1 of the first latch reset sub-circuit 3111 can be electrically connected to the control terminal SEL of the analog switch circuit 312. The input terminal of the first latch reset sub-circuit 3111 can be electrically connected to the first voltage source VCC and the output terminal SEL2 of the second latch reset sub-circuit 3112.

[0078] The first latch reset sub-circuit 3111 may be configured to output a control signal SEL1 according to the first voltage and a third voltage output by the second latch reset sub-circuit 3112 .

[0079] The input terminal of the second latch reset sub-circuit 3112 can be electrically connected to the power terminal VBUS of the USB connector 302 and the output terminal SEL1 of the first latch reset sub-circuit 3111. The second latch reset sub-circuit 3112 can be configured to output a third voltage according to the second voltage and the control signal SEL1.

[0080] The control signal SEL1 and the third voltage have opposite level logics, that is, when the control signal SEL1 is at a high level, the third voltage is at a low level; when the control signal SEL1 is at a low level, the third voltage is at a high level.

[0081] The connector port multiplexing device 310 shown in FIG3A can establish a connection path between the first terminal and the third terminal of the analog switch circuit 312 when the control signal SEL1 is at a low level, and establish a connection path between the second terminal and the third terminal of the analog switch circuit 312 when the control signal SEL1 is at a high level.

[0082] FIG3B is a schematic structural diagram of a connector port multiplexing device according to another embodiment of the present disclosure.

[0083] As shown in Figure 3B, the connector port multiplexing device 310 may include a latch reset circuit 311 and an analog switch circuit 312. The latch reset circuit 311 and the analog switch circuit 312 in Figures 3A and 3B have similar structures. For simplicity, the same parts are not repeated here.

[0084] In the embodiment of the present disclosure, the output terminal SEL2 of the second latch reset sub-circuit 3112 can be electrically connected to the control terminal SEL of the analog switch circuit 312. The input terminal of the second latch reset sub-circuit 3112 can be electrically connected to the power supply terminal VBUS of the universal serial bus connector 302 and the output terminal SEL1 of the first latch reset sub-circuit 3111.

[0085] The second latch reset sub-circuit 3112 may be configured to output a control signal SEL2 according to the second voltage and a fourth voltage output by the first latch reset sub-circuit 3111 .

[0086] An input terminal of the first latch reset sub-circuit 3111 may be electrically connected to the first voltage source VCC and an output terminal SEL2 of the second latch reset sub-circuit 3112. The first latch reset sub-circuit 3111 may be configured to output a fourth voltage according to the first voltage and the control signal SEL2.

[0087] The control signal SEL2 and the fourth voltage have opposite level logics, that is, when the control signal SEL2 is at a high level, the fourth voltage is at a low level; when the control signal SEL2 is at a low level, the fourth voltage is at a high level.

[0088] The connector port multiplexing device 310 shown in FIG3B can establish a connection path between the first terminal and the third terminal of the analog switch circuit 312 when the control signal SEL2 is at a high level. When the control signal SEL2 is at a low level, a connection path between the second terminal and the third terminal of the analog switch circuit 312 is established.

[0089] In FIG. 3A and FIG. 3B , the second latch reset sub-circuit 3112 and the first latch reset sub-circuit 3111 may have a symmetrical structure.

[0090] The second latch reset subcircuit 3112 is symmetrically structured with the first latch reset subcircuit 3111, resulting in opposite control logic between the output terminal SEL1 of the first latch reset subcircuit 3111 and the output terminal SEL2 of the second latch reset subcircuit 3112. Specifically, when SEL1 is high, SEL2 is low, and when SEL1 is low, SEL2 is high. Consequently, when the control signal of the analog switch circuit 312 is high and the first terminal and the third terminal of the analog switch circuit 312 are electrically connected, the output terminal SEL2 of the second latch reset subcircuit 3112 can be electrically connected to the control terminal SEL of the analog switch circuit 312. If the control logic of the analog switch circuit 312 is opposite to the aforementioned logic, the control terminal SEL need only be electrically connected to the output terminal SEL1 of the second latch reset subcircuit 3112. This makes the latch reset circuit 311 more adaptable.

[0091] Since the control logic of analog switch circuits manufactured by different manufacturers is not exactly the same, the second latch reset subcircuit 3112 and the first latch reset subcircuit 3111 are designed to have a symmetrical structure to facilitate the interchange of input and output signals according to the actual situation of the analog switch circuit.

[0092] FIG4 is a schematic structural diagram of a latch reset circuit according to an embodiment of the present disclosure.

[0093] As shown in Figure 4, the latch reset circuit may include a first latch reset subcircuit 4111 and a second latch reset subcircuit 4112. The latch reset circuit in Figure 4 is similar to the latch reset circuit 311. For the sake of simplicity, the same parts are not repeated here.

[0094] In an embodiment of the present disclosure, the first latch reset sub-circuit 4111 may include a first transistor Q1, a second transistor Q2, a first capacitor C1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4 and a fifth resistor R5.

[0095] The control electrode of the first transistor Q1 is electrically connected to the first end A of the first resistor R1. The first electrode of the first transistor Q1 is electrically connected to the first voltage source VCC and the input end of the first diode D1. The second electrode C of the first transistor Q1 is electrically connected to the first end of the second resistor R2 and the first end of the third resistor R3. The second electrode C of the first transistor Q1 serves as the output end SEL1 of the first latch reset sub-circuit 4111.

[0096] The output end of the first diode D1 is electrically connected to the second end of the first resistor R1 . The second end of the third resistor R3 is electrically connected to the first end of the fourth resistor R4 . The second ends of the second resistor R2 and the fourth resistor R4 are both grounded.

[0097] The control electrode of the second transistor Q2 is electrically connected to the first voltage dividing point B between the third resistor R3 and the fourth resistor R4, the first electrode of the second transistor Q2 is electrically connected to the first end of the fifth resistor R5, the second end of the fifth resistor R5 is grounded, and the second electrode of the second transistor Q2 is electrically connected to the first end A of the first resistor R1.

[0098] The positive electrode of the first capacitor C1 is electrically connected to the first voltage source VCC, and the negative electrode of the first capacitor C1 is electrically connected to the first voltage dividing point B.

[0099] In an embodiment of the present disclosure, the second latch reset subcircuit 4112 may include a third transistor Q3, a fourth transistor Q4, a third diode D3, a third capacitor C3, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11 and a twelfth resistor R12.

[0100] The control electrode of the third transistor Q3 is electrically connected to the first end D of the eighth resistor R8, the first electrode of the third transistor Q3 is electrically connected to the power supply terminal VBUS of the universal serial bus connector and the input end of the third diode D3, the second electrode F of the third transistor Q3 is electrically connected to the first end of the ninth resistor R9 and the first end of the tenth resistor R10, and the second electrode F of the third transistor Q3 is the output end of the second latch reset sub-circuit 4112.

[0101] The output end of the third diode D3 is electrically connected to the second end of the eighth resistor R8 , the second end of the tenth resistor R10 is electrically connected to the first end of the eleventh resistor R11 , and the second ends of the ninth resistor R9 and the eleventh resistor R11 are both grounded.

[0102] The control electrode of the fourth transistor Q4 is electrically connected to the second voltage dividing point E between the tenth resistor R10 and the eleventh resistor R11, the first electrode of the fourth transistor Q4 is electrically connected to the first end of the twelfth resistor R12, the second end of the twelfth resistor R12 is grounded, and the second electrode of the fourth transistor Q4 is electrically connected to the first end D of the eighth resistor R8.

[0103] The positive electrode of the third capacitor C3 is electrically connected to the power supply terminal VBUS of the universal serial bus connector, and the negative electrode of the third capacitor C3 is electrically connected to the second voltage dividing point E.

[0104] In FIG4 , the first transistor Q1 and the third transistor Q3 are both P-type transistors. The second transistor Q2 and the fourth transistor Q4 are both N-type transistors. For example, the first transistor Q1 and the third transistor Q3 can both be P-type transistors or P-type field-effect transistors. The second transistor Q2 and the fourth transistor Q4 can both be N-type transistors or N-type field-effect transistors. The first transistor Q1, the third transistor Q2, the third transistor Q3, and the fourth transistor Q4 are all used as switching transistors.

[0105] It should be noted that the first voltage dividing point B and the second voltage dividing point E do not represent actual components, but represent the junction points of related circuit connections in the circuit diagram.

[0106] FIG5 is a schematic structural diagram of a latch reset circuit according to another embodiment of the present disclosure.

[0107] 5 , the latch reset circuit may include a first latch reset subcircuit 5111 and a second latch reset subcircuit 5112. The first latch reset subcircuit 5111 and the second latch reset subcircuit 5112 are similar to the first latch reset subcircuit 4111 and the second latch reset subcircuit 4112 described above, respectively. For the sake of brevity, the same parts are not repeated herein.

[0108] In an embodiment of the present disclosure, the first latch reset sub-circuit 5111 may further include a second capacitor C2, a sixth resistor R6, and a seventh resistor R7.

[0109] The positive electrode of the second capacitor C2 is electrically connected to the second electrode C of the first transistor Q1, and the negative electrode of the second capacitor C2 is grounded. A first end of a sixth resistor R6 is electrically connected to the control electrode of the first transistor Q1, and a second end of the sixth resistor R6 is electrically connected to the first end A of the first resistor R1. A first end of a seventh resistor R7 is electrically connected to the first voltage dividing point B, and a second end of the seventh resistor R7 is electrically connected to the control electrode of the second transistor Q2.

[0110] The second capacitor C2 is used to filter out the instantaneous pulse transmitted to the output terminal SEL1 of the first latch reset sub-circuit 5111 , so that the output terminal SEL1 of the first latch reset sub-circuit 5111 can output a stable signal.

[0111] In an embodiment of the present disclosure, the first latch reset sub-circuit 5111 may further include a second diode D2.

[0112] An input end of the second diode D2 is electrically connected to the output end SEL2 of the second latch reset sub-circuit 5112 , and an output end of the second diode D2 is electrically connected to the first end A of the first resistor R1 .

[0113] The second diode D2 can prevent a reverse voltage signal from being input into the second latch reset sub-circuit 5112 , thereby protecting the second latch reset sub-circuit 5112 from being affected by the reverse voltage signal.

[0114] In an embodiment of the present disclosure, the second latch reset sub-circuit 5112 may further include a fourth capacitor C4, a thirteenth resistor R13, and a fourteenth resistor R14.

[0115] The positive electrode of the fourth capacitor C4 is electrically connected to the second electrode F of the third transistor Q3, and the negative electrode of the fourth capacitor C4 is grounded. A first end of a thirteenth resistor R13 is electrically connected to the control electrode of the third transistor Q3, and a second end of the thirteenth resistor R13 is electrically connected to the first end D of the eighth resistor R8. A first end of a fourteenth resistor R14 is electrically connected to the second voltage dividing point E, and a second end of the fourteenth resistor is electrically connected to the control electrode of the fourth transistor Q4.

[0116] The fourth capacitor C4 is used to filter out instantaneous pulses transmitted to the output terminal SEL2 of the second latch reset sub-circuit 5112 , so that the output terminal SEL2 of the second latch reset sub-circuit 5112 can output a stable signal.

[0117] In an embodiment of the present disclosure, the second latch reset sub-circuit may further include a fourth diode D4 and a fifth diode D5.

[0118] An input end of the fourth diode D4 is electrically connected to the output end SEL1 of the first latch reset sub-circuit 5111 , and an output end of the fourth diode D4 and an output end of the fifth diode D5 are both electrically connected to the first end D of the eighth resistor R8 .

[0119] When the chip functions as a slave device and the control signal is at the second level, establishing a connection path between the first and third terminals of the analog switch, the input terminal of the fifth diode D5 is left floating. When the chip functions as a slave device and the control signal is at the first level, establishing a connection path between the first and third terminals of the analog switch, the fifth diode D5 is electrically connected to a general-purpose input / output interface (GPIO) of the universal serial bus controller.

[0120] The first level is higher than the second level. The first level is a high level. For example, the first level may be 5V. The second level is a low level. For example, the second level may be 0V.

[0121] The fourth diode D4 can prevent a reverse voltage signal from being input to the first latch reset sub-circuit 5111, thereby protecting the first latch reset sub-circuit 5111 from being affected by the reverse voltage signal. The fifth diode D5 can prevent a reverse voltage signal from being input to the universal serial bus controller, thereby protecting the universal serial bus controller from being affected by the reverse voltage signal.

[0122] It should be noted that the latch reset circuit provided in the embodiments of the present disclosure can be applied not only to chips, but also to other circuits for path selection latch interfaces. The embodiments of the present disclosure do not limit the application direction of the latch reset circuit.

[0123] When the chip is used as the master device, the USB connector can be plugged in or out of an external device. After the chip is powered on, the VCC network on the chip board can provide a first voltage to the latch reset circuit. After a first preset delay, the voltage is output to the power supply terminal VBUS of the USB connector. The first voltage can be 5V. The signal timing diagram for this scenario is shown in Figure 6.

[0124] Figure 6 is a signal timing diagram for the latch reset circuit in Figure 5 . Figure 6 shows the timing waveforms of various signals in each phase when the chip is used as the master device. The following describes the operation of the latch reset circuit provided by the embodiments of the present disclosure, taking the structure of the latch reset circuit shown in Figure 5 as an example and combining it with the signal timing diagram shown in Figure 6 .

[0125] In Figure 6 , the voltage level at point A corresponds to the first terminal A of the first resistor R1 and the second terminal of the second transistor Q2. The voltage level at point C corresponds to the output terminal SEL1 of the first latch reset sub-circuit. The voltage level at point D corresponds to the first terminal D of the eighth resistor R8 and the second terminal of the fourth transistor. The voltage level at point F corresponds to the output terminal SEL2 of the second latch reset sub-circuit.

[0126] It should be noted that point A, point C, point D, and point F do not represent actual components, but represent the junction points of related circuit connections in the circuit diagram.

[0127] As shown in FIG6 , the operation process of the latch reset circuit includes two stages, namely the first stage t1 and the second stage t2 , and the first stage t1 can further include the stages t11 , t12 , and t13 .

[0128] In the first phase t1 , the chip is powered on, the first voltage source VCC outputs a high level, and the power supply terminal VBUS of the universal serial bus connector outputs a low level.

[0129] In phase t11, ignoring the voltage drop of the first diode D1, point A is at a high level. There is no voltage difference between the control electrode of the first transistor Q1 and the first electrode of the first transistor Q1, the first transistor Q1 is in the cut-off state, and point C is at a low level.

[0130] The voltages input to the input terminals of the second latch reset sub-circuit 5112 are all at a low level, and the voltages at points D, E, and F in the second latch reset sub-circuit 5112 are all at a low level.

[0131] The first voltage source VCC charges the first capacitor C1 , and a high-level pulse appears at a point B electrically connected to the negative electrode of the first capacitor C1 .

[0132] At stage t12, as the voltage level at point B increases, the voltage level at point B is able to turn on the second transistor Q2. As the second transistor Q2 gradually turns on, the voltage level at point A gradually changes from a high level to the voltage divided by the first resistor R1 and the fifth resistor R5, that is, V(A) = VCC*R5 / (R1+R5).

[0133] A voltage difference is formed between the control electrode and the first electrode of the first transistor Q1, and the first transistor Q1 is in the on state. The voltage level at point C gradually becomes a high level, and the voltage level at point B becomes the voltage divided by the third resistor R3 and the fourth resistor R4, V(B) = VCC*R4 / (R3+R4). V(B) keeps the second transistor Q2 on, forming a self-locking state.

[0134] The level at point D changes in the same way as the level at point C, and the level at point D gradually becomes a high level.

[0135] Since the power supply terminal VBUS of the universal serial bus connector is at a low level, the third transistor Q3 and the fourth transistor Q4 are both in a cut-off state, and the levels at point F and point E are both at a low level.

[0136] At stage t13, during the turn-on delay phase of the unidirectional conduction delay switch, the voltage level at point A is the voltage divided by the first resistor R1 and the fifth resistor R5. The voltage level at point B is the voltage divided by the third resistor R3 and the fourth resistor R4. The voltage levels at points C and D are both high. The voltage levels at points F and E are both low.

[0137] In the second phase t2 , the first voltage source VCC outputs a high level, and the power supply terminal VBUS of the universal serial bus connector outputs a high level, VBUS=VCC.

[0138] The power supply terminal VBUS of the universal serial bus connector charges the third capacitor C3, and a high level pulse appears at a point E electrically connected to the negative electrode of the third capacitor C3.

[0139] Since the voltage at point D is high, that is, V(D)=V(C)=VCC, there is no voltage difference between the control electrode and the first electrode of the third transistor Q3, the third transistor Q3 is in the cut-off state, and the voltage at point F is low, that is, V(F)=0.

[0140] After the high-level pulse at point E is consumed, point E becomes a low level, that is, V(E)=0.

[0141] The voltage level at point A is the voltage divided by the first resistor R1 and the fifth resistor R5. The voltage level at point B is the voltage divided by the third resistor R3 and the fourth resistor R4. The voltage level at point C is a high level.

[0142] After the second stage t2, the chip is powered off and the levels at all points become low.

[0143] According to the signal timing in FIG6 and the latch reset circuit in FIG5, when the USB connector is left floating or plugged into an external device, the output terminal SEL1 of the first latch reset subcircuit 5111 can output a stable high level, and the output terminal SEL2 of the second latch reset subcircuit 5112 can output a stable low level. The analog switch circuit can then establish a connection path between the second and third terminals of the analog switch based on the high level output from the output terminal SEL1 of the first latch reset subcircuit 5111 or the low level output from the output terminal SEL2 of the second latch reset subcircuit 5112, thereby causing the chip to enter USB_Host mode.

[0144] When the chip is used as a slave device, an external device acting as a master device can be plugged into the USB connector. The external device then supplies power to the VBUS terminal of the USB connector, which in turn provides a second voltage to the latch reset circuit. The chip is then powered up, and the VCC network on the chip board provides the first voltage to the latch reset circuit. The signal timing diagram for this scenario is shown in Figure 7.

[0145] Figure 7 is another signal timing diagram for the latch reset circuit in Figure 5 . Figure 7 shows the timing waveforms of various signals in each phase when the chip is used as a slave device. The following describes the operation of the latch reset circuit provided by the embodiments of the present disclosure, taking the structure of the latch reset circuit shown in Figure 5 as an example and combining it with the signal timing diagram shown in Figure 7 .

[0146] As shown in FIG7 , the operation process of the latch reset circuit includes two stages, namely the first stage t1 and the second stage t2 , and the first stage t1 can further include the stages t11 , t12 and t13 .

[0147] In the first stage t1, an external device serving as a master device is inserted into the USB connector. The external device supplies power to the power terminal VBUS of the universal serial bus connector. The power terminal VBUS of the universal serial bus connector outputs a high level. The chip is not powered on, and the first voltage source VCC provided by the chip outputs a low level.

[0148] In phase t11, ignoring the voltage drop of the third diode D3, the voltage level at point D is high. There is no voltage difference between the control electrode of the third transistor Q3 and the first electrode of the third transistor Q3, the third transistor Q3 is in the cut-off state, and the voltage level at point F is low.

[0149] The voltages input to the input terminals of the first latch reset sub-circuit 5111 are all at a low level, and the voltages at points A, B, and C in the first latch reset sub-circuit 5111 are all at a low level.

[0150] The power supply terminal VBUS of the universal serial bus connector charges the third capacitor C3, and a high level pulse appears at a point E electrically connected to the negative electrode of the third capacitor C3.

[0151] At stage t12, as the voltage level at point E increases, the voltage level at point E can turn on the fourth transistor Q4. As the fourth transistor Q4 gradually turns on, the voltage level at point D gradually changes from a high level to the voltage divided by the eighth resistor R8 and the twelfth resistor R12, that is, V(D) = VBUS * R12 / (R8 + R12).

[0152] A voltage difference is formed between the control electrode and the first electrode of the third transistor Q3, and the third transistor Q3 is in the on state. The voltage level at point F gradually becomes a high level, and the voltage level at point E becomes the voltage divided by the tenth resistor R10 and the eleventh resistor R11, V(E) = VBUS*R11 / (R10+R11). V(E) keeps the fourth transistor Q4 turned on, forming a self-locking state.

[0153] The level at point A changes in the same way as the level at point F, and the level at point A gradually becomes a high level.

[0154] Since the first voltage source VCC is at a low level, the first transistor Q1 and the second transistor Q2 are both in a cut-off state, and the levels at point C and point B are both low levels.

[0155] At stage t13, during the chip power-up process, the voltage level at point D is the voltage divided by the eighth resistor R8 and the twelfth resistor R12. The voltage level at point E is the voltage divided by the tenth resistor R10 and the eleventh resistor R11. The voltage levels at points F and A are both high. The voltage levels at points C and B are both low.

[0156] In the second phase t2 , the first voltage source VCC outputs a high level, and the power supply terminal VBUS of the universal serial bus connector outputs a high level, VBUS=VCC.

[0157] The first voltage source VCC charges the first capacitor C1 , and a high-level pulse appears at a point B electrically connected to the negative electrode of the first capacitor C1 .

[0158] Since the voltage at point A is high, that is, V(A)=V(F)=VBUS, there is no voltage difference between the control electrode and the first electrode of the first transistor Q1, the first transistor Q1 is in the cut-off state, and the voltage at point C is low, that is, V(C)=0.

[0159] After the high-level pulse at point B is consumed, point B becomes a low level, that is, V(B)=0.

[0160] The voltage level at point D is the voltage divided between the eighth resistor R8 and the twelfth resistor R12. The voltage level at point E is the voltage divided between the tenth resistor R10 and the eleventh resistor R11. The voltage levels at point F are all high.

[0161] After the second stage t2, the chip is powered off and the first voltage source VCC is at a low level. When the external device is still electrically connected to the USB connector, the power supply terminal VBUS of the universal serial bus connector continues to output a high level. Except for the first voltage source VCC becoming a low level, the levels at other points remain at the levels in the second stage t2. However, since the chip is powered off, the USB controller will not work.

[0162] According to the signal timing in FIG7 and the latch reset circuit in FIG5 , when the USB connector is plugged into an external device serving as a host, the output terminal SEL1 of the first latch reset subcircuit 5111 can output a stable low level, and the output terminal SEL2 of the second latch reset subcircuit 5112 can output a stable high level. The analog switch circuit can then establish a connection path between the first and third terminals of the analog switch based on the low level output by the output terminal SEL1 of the first latch reset subcircuit 5111 or the high level output by the output terminal SEL2 of the second latch reset subcircuit 5112, thereby enabling the chip to enter USB_OTG mode.

[0163] After the output terminal SEL2 of the second latch reset sub-circuit 5112 outputs a high level and the chip enters the USB_OTG mode, the USB_OTG mode can be ended in two ways to reset the chip to the USB_Host mode.

[0164] The first reset method is to unplug the external device that serves as the host device from the USB connector, power off the entire device where the chip is located, and then power it back on to restore the normal USB mode, that is, USB_Host mode.

[0165] The second reset mode is automatic mode. In automatic mode, after unplugging the external device serving as the host device from the USB connector, the chip can automatically detect the end of USB_OTG mode according to the USB protocol and automatically adjust to normal USB mode, i.e., USB_Host mode. The specific implementation of automatic mode is as follows: after unplugging the external device serving as the host device from the USB connector, the chip automatically detects the end of USB_OTG mode and controls the GPIO port of the USB controller to output a high-level pulse, such as a 5V pulse. The high-level pulse is transmitted to point D of the second latch reset subcircuit 5112 through the fifth diode D5 in FIG5 , thereby eliminating the voltage difference between the control electrode and the first electrode of the third transistor Q3, thereby turning off the third transistor Q3. At this time, the output terminal SEL2 of the second latch reset sub-circuit 5112 will change from a high level to a low level. At the same time, the first voltage source VCC will work, self-locking the latch reset circuit, so that the output terminal SEL2 of the second latch reset sub-circuit 5112 is maintained at a low level. The analog switch circuit establishes a connection path between the second terminal and the third terminal of the analog switch according to the low level output by the output terminal SEL2 of the second latch reset sub-circuit 5112, so that the chip enters the USB_Host mode.

[0166] As can be seen from Figures 5, 6 and 7, the latch reset circuit provided in the embodiment of the present disclosure uses simple devices such as capacitors, resistors, transistors and diodes. The circuit is simple to implement, has no complex control logic, and is low in cost.

[0167] When the latch reset circuit structure shown in FIG5 operates according to the timing sequence shown in FIG6 , a unidirectional on-delay switch can be connected between the first voltage source VCC and the power supply terminal VBUS of the universal serial bus connector to delay the first voltage output by the first voltage source VCC to the power supply terminal VBUS of the universal serial bus connector after a first preset time. A specific implementation of the first voltage source VCC, the unidirectional on-delay switch, and the power supply terminal VBUS of the universal serial bus connector is shown in FIG8 .

[0168] FIG8 is a schematic structural diagram of a connector port multiplexing device according to another embodiment of the present disclosure.

[0169] As shown in Figure 8 , a connector port multiplexing device 810 may include a latch reset circuit 811 and an analog switch circuit 812. The latch reset circuit 811 and the analog switch circuit 812 in Figure 8 are similar to the latch reset circuit 211 and the analog switch circuit 212 in Figure 2A . For the sake of simplicity, the same parts are not repeated here in this disclosure.

[0170] In the embodiment of the present disclosure, the connector port multiplexing device 810 may further include a unidirectional conduction delay switch 813. The input end of the unidirectional conduction delay switch 813 may be electrically connected to the first voltage source VCC, and the output end of the unidirectional conduction delay switch 813 may be electrically connected to the power supply terminal VBUS of the universal serial bus connector 802.

[0171] The single-phase on-delay switch 813 can be configured to establish a connection path between the first voltage source VCC and the power supply terminal VBUS of the universal serial bus connector 802 after a first predetermined time period when the first voltage VCC is at a first level.

[0172] The single-phase on-delay switch 813 may be a USB current-limiting switch. The first predetermined duration may be the on-time of the USB current-limiting switch. The single-phase on-delay switch 813 is unidirectional and can only conduct power from the first voltage source VCC to the power supply terminal VBUS of the universal serial bus connector 802, but not in the reverse direction.

[0173] By employing a technical approach in which, when the chip is used as a master device, the single-phase on-delay switch 813 establishes a connection path between the first voltage source VCC and the power supply terminal VBUS of the universal serial bus connector 802 after a first predetermined period of time when the first voltage is at a first level, the control logic of the input signal to the latch reset circuit 811 is controlled by a hardware circuit. This allows the latch reset circuit 811 to first receive the first level output by the first voltage source VCC, and then, after a first predetermined period of time, receive the first level input by the first voltage source VCC to the power supply terminal VBUS of the universal serial bus connector 802. The latch reset circuit 811 can output the first level through the output terminal of the first latch reset sub-circuit, and can output the second level through the output terminal of the second latch reset sub-circuit. A connection path is established between the second terminal and the third terminal of the analog switch circuit 812 based on the first level or the second level, thereby causing the chip to enter USB_Host mode.

[0174] FIG9 is a schematic structural diagram of a chip according to an embodiment of the present disclosure.

[0175] As shown in FIG. 9 , a chip 900 may include a universal serial bus controller 901 , a universal serial bus connector 902 , and a connector port multiplexing device 910 .

[0176] In the embodiment of the present disclosure, the USB controller 901 may include a first signal transmission terminal P1 and a second signal transmission terminal P2. The USB connector 902 may include a multiplexed signal transmission terminal P0.

[0177] In an embodiment of the present disclosure, the connector port multiplexing device 910 may be the connector port multiplexing device shown in Figures 2 to 6. The first signal transmission terminal P1 may include a data positive signal transmission terminal DP and a data negative signal transmission terminal DM corresponding to the USB_OTG mode. The second signal transmission terminal P2 may include a data positive signal transmission terminal DP and a data negative signal transmission terminal DM corresponding to the USB_Host mode. The multiplexed signal transmission terminal P0 may include a multiplexed data positive signal transmission terminal DP0 and a multiplexed data negative signal transmission terminal DM0.

[0178] For example, the second signal transmission terminal P2 may include a data positive signal transmission terminal DP and a data negative signal transmission terminal DM corresponding to the USB_3.X Host mode. The second signal transmission terminal P2 may also include a data positive signal transmission terminal DP and a data negative signal transmission terminal DM corresponding to the USB_2.0 Host mode.

[0179] FIG10 is a flowchart of a connector port multiplexing method according to an embodiment of the present disclosure.

[0180] As shown in Figure 10 , the connector port multiplexing method may include operations S1010 to S1040. The connector port multiplexing method in Figure 10 may be applied to the connector port multiplexing device described above.

[0181] In the case where the chip is used as a master device, in operation S1010 , a first voltage outputted by a first voltage source is received.

[0182] In operation S1020 , after a first predetermined time period has elapsed, a second voltage is received from the USB connector.

[0183] In operation S1030, a control signal is output according to the first voltage and the second voltage.

[0184] In operation S1040 , a connection path between the second terminal and the third terminal of the analog switch is established according to the control signal.

[0185] In the embodiment of the present disclosure, operations S1010 to S1040 are similar to the operations performed by the connector port multiplexing device 210 described above, and are not described in detail herein. The connector port multiplexing device 210 may include the latch reset circuit shown in FIG5 .

[0186] In the embodiment of the present disclosure, operation S1010 is similar to the working process of the latch reset circuit in Figure 5 in the first stage t1 in Figure 6, and operation S1020 and operation S1030 are similar to the working process of the latch reset circuit in Figure 5 in the second stage t2 in Figure 6. For the sake of simplicity, the same parts are not repeated here in this disclosure.

[0187] FIG11 is a flowchart of a connector port multiplexing method according to another embodiment of the present disclosure.

[0188] As shown in Figure 11 , the connector port multiplexing method may include operations S1110 to S1140. The connector port multiplexing method in Figure 11 may be applied to the connector port multiplexing device described above.

[0189] In a case where the chip serves as a slave device, in operation S1110 , a second voltage is received from the USB connector.

[0190] In operation S1120 , after a second predetermined time period has elapsed, a first voltage outputted by a first voltage source is received.

[0191] In operation S1130, a control signal is output according to the first voltage and the second voltage.

[0192] In operation S1140 , a connection path between the first terminal and the third terminal of the analog switch is established according to the control signal.

[0193] In the embodiment of the present disclosure, operations S1110 to S1240 are similar to the operations performed by the connector port multiplexing device 210 described above, and are not described in detail herein. The connector port multiplexing device 210 may include the latch reset circuit shown in FIG5 .

[0194] In the embodiment of the present disclosure, operation S1110 is similar to the working process of the latch reset circuit in Figure 5 in the first stage t1 in Figure 7, and operation S1120 and operation S1130 are similar to the working process of the latch reset circuit in Figure 5 in the second stage t2 in Figure 7. For the sake of simplicity, the same parts are not repeated here in this disclosure.

[0195] FIG12 is a diagram showing an application scenario of a connector port multiplexing device according to an embodiment of the present disclosure.

[0196] As shown in FIG12 , the connector port multiplexing device 1210 provided in an embodiment of the present disclosure can be electrically connected to a projection system 1220 to perform port multiplexing on the USB connector in projection system 1220. This allows the hardware device to automatically connect the path corresponding to the external device connected to the multiplexed signal transmission end of the USB connector without disrupting the USB communication protocol or requiring the USB connector to include an ID pin, multiplexing the multiplexed signal transmission end of the universal serial bus connector, enabling the multiplexed signal transmission end to implement USB_2.0 host functions, USB_3.x host functions, and USB_OTG functions. This reduces the number of USB connectors used in projection system 1220, lowers the cost of the chip included in projection system 1220, and reduces the chip layout area on the PCB.

[0197] Projection system 1220 can be a portable intelligent LCD projection system. To facilitate the mobility of the portable intelligent LCD projection system, the system is relatively small. Therefore, it is necessary to control the number of exposed USB connector ports of the portable intelligent LCD projection system. Usually, the USB connector has only one interface, which is generally a USB2.0 connector or a USB3.X connector depending on the product positioning. Therefore, when the connector port multiplexing device provided by the embodiment of the present disclosure is applied to the portable intelligent LCD projection system, the multiplexed signal transmission end on the USB2.0 connector or USB3.X connector can be reused to implement the USB_2.0Host function, USB_3.X Host function, and USB_OTG function. Without changing the size of the portable intelligent LCD projection system, a single USB connector is used to be compatible with the USB_2.0Host function, USB_3.X Host function, and USB_OTG function.

[0198] FIG. 13A is a circuit diagram of a latch reset circuit according to one embodiment of the present disclosure.

[0199] FIG. 13A is a circuit diagram of a latch reset circuit included in the connector port multiplexing device 1210 in FIG. 12 .

[0200] As shown in FIG13A , the latch reset circuit includes a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a first diode D1, a second diode D2, a third diode D3, and a fourth diode D4.

[0201] The components of the latch reset circuit in Figure 13A are electrically connected according to the connection method in Figure 5. The components other than the components of the latch reset circuit in Figure 13A are components for implementing other functions of the projection system 1220 in Figure 12.

[0202] FIG. 13B is a circuit diagram of an analog switch circuit according to one embodiment of the present disclosure.

[0203] FIG. 13B shows an analog switch circuit 1312 included in the connector port multiplexing device 1210 in FIG. 12 .

[0204] The latch reset circuit in FIG. 13A and the analog switch circuit 1312 in FIG. 13B may be electrically connected according to the connection method in FIG. 3A or according to the connection method in FIG. 3B .

[0205] The latch reset circuit in FIG13A and the analog switch circuit 1312 in FIG13B may be located on the same side of the chip or on different sides of the chip. For example, the latch reset circuit in FIG13A may be located on the first side of the chip, and the analog switch circuit 1312 in FIG13B may be located on the second side of the chip.

[0206] As shown in Figures 12, 13A, and 13B, the connector port multiplexing device provided in the disclosed embodiments includes a latch reset circuit and an analog switch circuit. These circuits utilize simple components, are simple to implement, require no complex control logic, and are relatively low cost. Furthermore, the connector port multiplexing device can reuse multiplexed signal transmission terminals on USB 2.0 or USB 3.X connectors, implementing USB 2.0 Host, USB 3.X Host, and USB On-The-Go (OTG) functions through these multiplexed signal transmission terminals. This reduces the number of USB connectors used, lowers the cost of the chips included in projection system 1220, and reduces the chip layout area on the PCB.

[0207] The following will take a USB_3.X connector as an example to illustrate the method of using the connector port multiplexing device provided by the embodiment of the present disclosure.

[0208] When the connector port multiplexing device provided by the embodiments of the present disclosure is applied to different chips, the motherboard containing the chip is in a bare die state after production. The chip has no internal program and can only be programmed in USB_OTG mode, i.e., via the USB OTG port corresponding to USB_OTG mode. Before powering on the motherboard, connect the only USB connector, namely the USB_3.X connector, to the computer host. In this case, the computer host acts as an external device serving as the master control device.

[0209] The USB interface of the computer host provides 5V power to the power supply end of the USB_3.X connector. The latch reset circuit on the chip mainboard detects that the second voltage on the power supply end VBUS of the USB_3.X connector is at a high level and detects that the first voltage VCC provided by the chip is at a low level of 0V. The latch reset circuit outputs a high level at the output end SEL2, controlling the analog switch circuit to electrically connect the first end and the third end, that is, connecting the multiplexed signal transmission end of the USB_3.X connector to the differential signal transmission end corresponding to the USB_OTG mode of the chip. At this time, the chip enters the debugging mode, that is, USB_OTG mode.

[0210] Then, the chip motherboard is powered on, the motherboard chip starts running, and after the bare chip is started, the burning process begins. The computer host detects that the USB OTG port is connected and starts the program burning through the USB link corresponding to the USB_OTG mode. After the burning is completed, the chip motherboard is disconnected from the computer host and the motherboard is powered on again. Since the USB_3.X connector is suspended, the power supply terminal VBUS of the USB_3.X connector is 0V. During the power-on process, the first voltage source VCC is started and outputs a high level, such as a 5V voltage, which pulls down the signal output by the latch reset circuit at the output terminal SEL2, and controls the analog switch circuit to electrically connect the second end with the third end, that is, connect the multiplexed signal transmission end of the USB_3.X connector to the differential signal transmission end corresponding to the USB_Host mode of the chip. At this time, it becomes the normal user mode, that is, the USB_Host mode, and the user can insert external devices such as a USB flash drive into the USB_3.X connector.

[0211] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, program segment, or a part of code, and the above-mentioned module, program segment, or a part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of boxes in the block diagram or flowchart, can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0212] Those skilled in the art will appreciate that various combinations and / or combinations of features described in the various embodiments and / or claims of this disclosure may be made, even if such combinations or combinations are not explicitly described in this disclosure. In particular, various combinations and / or combinations of features described in the various embodiments and / or claims of this disclosure may be made, without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0213] The embodiments of the present disclosure are described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although each embodiment has been described separately above, this does not mean that the measures in each embodiment cannot be used in combination to advantage. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A connector port multiplexing device, comprising: a latch reset circuit electrically connected to a first voltage source and a power terminal of the universal serial bus connector, the latch reset circuit being configured to output a control signal based on a first voltage output by the first voltage source and a second voltage from the universal serial bus connector; An analog switch circuit, wherein a control end of the analog switch circuit is electrically connected to an output end of the latch reset circuit, a first end of the analog switch circuit is electrically connected to a first signal transmission end of a universal serial bus controller, a second end of the analog switch circuit is electrically connected to a second signal transmission end of the universal serial bus controller, and a third end of the analog switch circuit is electrically connected to a multiplexed signal transmission end of the universal serial bus connector; the analog switch circuit is configured to establish a connection path between the first end and the third end of the analog switch circuit or establish a connection path between the second end and the third end of the analog switch circuit according to the control signal.

2. The connector port multiplexing device according to claim 1, wherein: The latch reset circuit comprises: a first latch reset sub-circuit and a second latch reset sub-circuit; The output terminal of the first latch reset sub-circuit is electrically connected to the control terminal of the analog switch circuit, and the input terminal of the first latch reset sub-circuit is electrically connected to the first voltage source and the output terminal of the second latch reset sub-circuit, and is configured to output the control signal according to the first voltage and a third voltage output by the second latch reset sub-circuit; The input terminal of the second latch reset sub-circuit is electrically connected to the power terminal of the universal serial bus connector and the output terminal of the first latch reset sub-circuit, and is configured to output the third voltage according to the second voltage and the control signal.

3. The connector port multiplexing device according to claim 1, wherein: The latch reset circuit comprises: a first latch reset sub-circuit and a second latch reset sub-circuit; The output terminal of the second latch reset sub-circuit is electrically connected to the control terminal of the analog switch circuit, and the input terminal of the second latch reset sub-circuit is electrically connected to the power terminal of the universal serial bus connector and the output terminal of the first latch reset sub-circuit, and is configured to output the control signal according to the second voltage and a fourth voltage output by the first latch reset sub-circuit; The input terminal of the first latch reset sub-circuit is electrically connected to the first voltage source and the output terminal of the second latch reset sub-circuit, and is configured to output the fourth voltage according to the first voltage and the control signal.

4. The connector port multiplexing device according to claim 2 or 3, wherein: The second latch reset sub-circuit and the first latch reset sub-circuit have a symmetrical structure.

5. The connector port multiplexing device according to any one of claims 1 to 3, further comprising: a unidirectional conduction delay switch, wherein the input end of the unidirectional conduction delay switch is electrically connected to the first voltage source, and the output end of the single-phase conduction delay switch is electrically connected to the power supply end of the universal serial bus connector, and is configured to establish a connection path between the first voltage source and the power supply end of the universal serial bus connector after a first predetermined time period when the first voltage is at a first level.

6. The connector port multiplexing device according to claim 2 or 3, wherein: The first latch reset subcircuit includes: a first transistor, a second transistor, a first capacitor, a first resistor, a second resistor, a third resistor, a fourth resistor and a fifth resistor; wherein the control electrode of the first transistor is electrically connected to the first end of the first resistor, the first electrode of the first transistor is electrically connected to the first voltage source and the input end of the first diode, the second electrode of the first transistor is electrically connected to the first end of the second resistor and the first end of the third resistor, and the second electrode of the first transistor is the output end of the first latch reset sub-circuit; The output end of the first diode is electrically connected to the second end of the first resistor, the second end of the third resistor is electrically connected to the first end of the fourth resistor, and the second end of the second resistor and the second end of the fourth resistor are both grounded; a control electrode of the second transistor electrically connected to a first voltage dividing point between the third resistor and the fourth resistor, a first electrode of the second transistor electrically connected to a first end of the fifth resistor, a second end of the fifth resistor being grounded, and a second electrode of the second transistor electrically connected to a first end of the first resistor; The positive electrode of the first capacitor is electrically connected to the first voltage source, and the negative electrode of the first capacitor is electrically connected to the first voltage dividing point.

7. The connector port multiplexing device according to claim 6, wherein: The first latch reset sub-circuit further includes: a second capacitor, a sixth resistor and a seventh resistor; The positive electrode of the second capacitor is electrically connected to the second electrode of the first transistor, and the negative electrode of the second capacitor is grounded; A first end of the sixth resistor is electrically connected to the control electrode of the first transistor, and a second end of the sixth resistor is electrically connected to the first end of the first resistor; A first end of the seventh resistor is electrically connected to the first voltage dividing point, and a second end of the seventh resistor is electrically connected to the control electrode of the second transistor.

8. The connector port multiplexing device according to claim 6 or 7, wherein: The first latch reset sub-circuit further includes: a second diode; The input end of the second diode is electrically connected to the output end of the second latch reset sub-circuit, and the output end of the second diode is electrically connected to the first end of the first resistor.

9. The connector port multiplexing device according to claim 2 or 3, wherein: The second latch reset sub-circuit includes: a third transistor, a fourth transistor, a third diode, a third capacitor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, and a twelfth resistor; wherein, a control electrode of the third transistor is electrically connected to a first end of the eighth resistor, a first electrode of the third transistor is electrically connected to a power supply terminal of the universal serial bus connector and an input end of the third diode, a second electrode of the third transistor is electrically connected to a first end of the ninth resistor and a first end of the tenth resistor, and a second electrode of the third transistor is an output end of the second latch reset sub-circuit; The output end of the third diode is electrically connected to the second end of the eighth resistor, the second end of the tenth resistor is electrically connected to the first end of the eleventh resistor, and the second end of the ninth resistor and the second end of the eleventh resistor are both grounded; a control electrode of the fourth transistor electrically connected to a second voltage dividing point between the tenth resistor and the eleventh resistor, a first electrode of the fourth transistor electrically connected to a first end of the twelfth resistor, a second end of the twelfth resistor being grounded, and a second electrode of the fourth transistor electrically connected to a first end of the eighth resistor; The positive electrode of the third capacitor is electrically connected to the power supply terminal of the universal serial bus connector, and the negative electrode of the third capacitor is electrically connected to the second voltage dividing point.

10. The connector port multiplexing device according to claim 9, wherein: The second latch reset sub-circuit further includes: a fourth capacitor, a thirteenth resistor, and a fourteenth resistor; Wherein, the positive electrode of the fourth capacitor is electrically connected to the second electrode of the third transistor, and the negative electrode of the fourth capacitor is grounded; A first end of the thirteenth resistor is electrically connected to the control electrode of the third transistor, and a second end of the thirteenth resistor is electrically connected to the first end of the eighth resistor; A first end of the fourteenth resistor is electrically connected to the second voltage dividing point, and a second end of the fourteenth resistor is electrically connected to the control electrode of the fourth transistor.

11. The connector port multiplexing device according to claim 10, wherein: The second latch reset sub-circuit further includes: a fourth diode and a fifth diode; The input end of the fourth diode is electrically connected to the output end of the first latch reset sub-circuit, and the output end of the fourth diode and the output end of the fifth diode are both electrically connected to the first end of the eighth resistor; When the chip is used as a slave device and the control signal is at the second level, a connection path between the first terminal and the third terminal of the analog switch is established, and the input terminal of the fifth diode is left floating; When the chip is used as a slave device, the control signal is at the first level, and a connection path is established between the first end and the third end of the analog switch, the fifth diode is electrically connected to the universal input / output interface of the universal serial bus controller.

12. A chip comprising: Universal Serial Bus The controller comprises: a first signal transmission end and a second signal transmission end; A universal serial bus connector, comprising: a multiplexed signal transmission terminal; The connector port multiplexing device according to any one of claims 1 to 11.

13. A connector port multiplexing method, applied to the connector port multiplexing device according to any one of claims 1 to 11, the connector port multiplexing method comprising: When the chip is used as a master device, receiving a first voltage output by a first voltage source; After a first predetermined time period, receiving a second voltage from the universal serial bus connector; outputting a control signal according to the first voltage and the second voltage; A connection path between the second terminal and the third terminal of the analog switch is established according to the control signal.

14. A connector port multiplexing method, applied to the connector port multiplexing device according to any one of claims 1 to 11, the connector port multiplexing method comprising: When the chip is used as a slave device, receiving a second voltage from a universal serial bus connector; After a second predetermined time period, receiving a first voltage output by a first voltage source; outputting a control signal according to the first voltage and the second voltage; A connection path between the first terminal and the third terminal of the analog switch is established according to the control signal.

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