Semiconductor packaging structure, manufacturing method and electronic device

Abstract

Disclosed in the present application are a semiconductor packaging structure, a manufacturing method and an electronic device. The semiconductor packaging structure comprises an interconnection layer, a plurality of semiconductor devices and at least one interposer. The plurality of semiconductor devices are arranged on the surface of one side of the interconnection layer, and the plurality of semiconductor devices comprise a first-type semiconductor device for processing a signal, and a second-type semiconductor device for transmitting the signal. The interconnection layer comprises a first interconnection trace and a second interconnection trace; the first-type semiconductor device is connected to the second-type semiconductor device by means of the first interconnection trace; at least part of the region of the interposer is located on the side of the interconnection layer that faces away from the plurality of semiconductor devices; the interposer is provided with a redistribution trace; the redistribution trace is connected to the second-type semiconductor device by means of the second interconnection trace; and the redistribution trace is further used for connecting to a connector, such that the second interconnection trace can transmit a signal between the second-type semiconductor device and the connector. The provision of the interposer facilitates the simplification of the structure of the second interconnection trace.

Description

Semiconductor packaging structure, manufacturing method and electronic equipment

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of the People's Republic of China on March 29, 2024, with application number 202410383656.X and invention name "Semiconductor packaging structure, manufacturing method and electronic device", the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of semiconductor technology, and in particular to a semiconductor packaging structure, a manufacturing method, and an electronic device. Background Art

[0004] With the development of technologies such as communications, cloud computing, big data, artificial intelligence, and autonomous driving, the demand for chip computing power continues to increase. A single chip cannot meet the computing power requirements of products. Currently, very super large package (VSLP) technology is being used to package multiple bare dies onto a large carrier, integrating a large amount of computing power into a single package. Currently, there are two mainstream technology approaches for VLSI packaging: the wafer scale engine (WSE). WSE interconnects dies across a wafer by adding an additional metal layer, enabling parallel computing among the interconnected dies, thereby increasing computing power. However, this approach has difficulty guaranteeing yield, carries significant process risks, and requires redundant design to prevent defects during production, which somewhat limits its integration. The second approach is system on wafer (SOW). SOW uses multi-layer redistribution layer (RDL) technology to integrate a known good die (KGD) array, power supply, and heat dissipation modules into a single package. However, this solution has high production costs and is difficult due to the large number of layers of redistribution lines, and product stability is difficult to guarantee. Summary of the Invention

[0005] The present application provides a semiconductor packaging structure, a manufacturing method and an electronic device for realizing ultra-large-scale integrated packaging of semiconductor devices, improving the signal transmission rate of the product and reducing the difficulty of the packaging process.

[0006] In a first aspect, embodiments of the present application provide a semiconductor packaging structure comprising an interconnect layer, a plurality of semiconductor devices, and at least one transfer substrate. The plurality of semiconductor devices are disposed on a surface of one side of the interconnect layer, and the plurality of semiconductor devices include a first type of semiconductor device and a second type of semiconductor device. The first type of semiconductor device is used to process signals, and the second type of semiconductor device is used to transmit signals. The interconnect layer includes interconnect traces, which include a first interconnect trace and a second interconnect trace. The first type of semiconductor device and the second type of semiconductor device are connected via the first interconnect trace, so that the first interconnect trace can transmit signals between the first type of semiconductor device and the second type of semiconductor device. At least a portion of the transfer substrate is located on a side of the interconnect layer facing away from the plurality of semiconductor devices. The transfer substrate is provided with a transfer trace, which is connected to the second type of semiconductor device via a second interconnect trace. The transfer trace is also used to connect to a connector, so that the second interconnect trace can transmit signals between the second type of semiconductor device and the connector, thereby enabling signal input and output of the semiconductor package device. The embodiment of the present application provides a transfer substrate and sets a transfer line in the transfer substrate to connect with the second interconnection line, which is beneficial to simplifying the structure of the second interconnection line and reducing the number of layers of the second interconnection line, thereby reducing the process difficulty of the interconnection layer.

[0007] In some embodiments of the present application, the surface of the interconnection layer facing the multiple semiconductor devices includes a first area and a second area, the second area surrounds the first area, the first type of semiconductor devices are located in the first area, and the second type of semiconductor devices are located in the second area; in a direction perpendicular to the interconnection layer, the positive projection of the adapter substrate and the second area have an overlapping area, that is, the second type of semiconductor devices for transmitting signals are arranged in the edge area of ​​the semiconductor packaging structure, and correspondingly, the adapter substrates are distributed in the edge area of ​​the semiconductor packaging structure, which is conducive to reducing the length of the second interconnection line, shortening the signal transmission distance, and realizing high-speed signal transmission.

[0008] In some embodiments of the present application, the multiple semiconductor devices also include a third type of semiconductor device, which is located on the side of the second type of semiconductor device away from the first type of semiconductor device; wherein the third type of semiconductor device may include redundant semiconductor devices, which are distributed at the edge of the semiconductor packaging structure and can be used to balance stress, improve the stability of the packaging structure, and reduce the risk of structural rupture.

[0009] In some embodiments of the present application, the semiconductor packaging structure also includes multiple first interconnect structures, which are located between the interconnect layer and the transfer substrate. The first interconnect structures are used to connect the transfer lines and the second interconnect lines, thereby connecting the second type of semiconductor devices and the connector to realize information input and output.

[0010] In some embodiments of the present application, in the direction perpendicular to the interconnection layer, the positive projection of the adapter substrate falls within the area of ​​the interconnection layer, and the side of the adapter substrate facing away from the interconnection layer is used to connect the connector. The adapter substrate is set based on the original size of the interconnection layer, which can effectively utilize the space. By reasonably designing the positions of multiple adapter substrates, it is also beneficial to balance stress and improve the stability of the packaging structure.

[0011] In some embodiments of the present application, the adapter substrate includes a first substrate portion and a second substrate portion that are connected to each other. In the direction perpendicular to the interconnection layer, the orthographic projection of the first substrate portion falls within the range of the interconnection layer, and the orthographic projection of the second substrate portion has no overlapping area with the interconnection layer. This design can set more types and a larger number of connectors on the adapter substrate, so that it can match more types of devices and improve the signal transmission rate.

[0012] In some embodiments of the present application, the first substrate portion is flush with the second substrate portion, and both side surfaces of the transfer substrate can be used to connect to the connector.

[0013] In some embodiments of the present application, one end of the second substrate portion is connected to the first substrate portion, and the other end of the second substrate portion extends along the side of the interconnection layer. While providing more connectors, the device product can have a smaller volume, thereby improving the integration of the packaging structure.

[0014] Exemplarily, the connector includes a first connector, and the side of the first substrate portion facing away from the interconnection layer is used to connect to the first connector, or the connector includes a second connector, and the side of the second substrate portion facing away from the interconnection layer is used to connect to the second connector.

[0015] Exemplarily, when the first substrate portion and the second substrate portion are flush, the connector further includes a third connector, and the side of the second substrate portion facing the interconnection layer is used to connect to the third connector.

[0016] In some embodiments of the present application, the interconnection layer includes a first wiring layer, a carrier board and a second wiring layer, the first wiring layer is located between multiple semiconductor devices and the carrier board, the second wiring layer is located between the carrier board and at least one adapter substrate, and the first interconnection trace is located in the first wiring layer; the second interconnection trace is located in the first wiring layer and the second wiring layer, the carrier board includes a first vertical interconnection structure, the first vertical interconnection structure is used to connect the second interconnection traces in the first wiring layer and the second wiring layer; the connector is connected to the second type of semiconductor device through the adapter trace, the second interconnection trace and the first vertical interconnection structure to realize signal input and output, and the specific structure of the interconnection layer is designed according to the process level.

[0017] In some embodiments of the present application, the second-type semiconductor devices are disposed in a one-to-one correspondence with the transfer substrate, and each second-type semiconductor device is connected to a plurality of first vertical interconnect structures. In a direction perpendicular to the interconnect layer, the orthographic projection of the first vertical interconnect structure corresponding to the same second-type semiconductor device falls within the area of ​​the corresponding transfer substrate. The provision of the first vertical interconnect structure can shorten the physical length of the traces between the second-type semiconductor device and the transfer substrate, thereby improving signal transmission efficiency.

[0018] In some embodiments of the present application, the semiconductor packaging structure further includes at least one power supply module, and the at least one power supply module is located on the side of the second wiring layer away from the multiple semiconductor devices; the interconnection line further includes a third interconnection line, and the third interconnection line is located in the first wiring layer and the second wiring layer, and the third interconnection line is used to connect the first type semiconductor device and the power supply module; the carrier also includes a second vertical interconnection structure, and the second vertical interconnection structure is used to connect the third interconnection line in the first wiring layer and the second wiring layer; the power supply module is connected to the first type semiconductor device through the third interconnection line and the second vertical structure to supply power to the first type semiconductor device, and different first type semiconductor devices can be connected to different power supply modules to meet the working requirements of different first type semiconductor devices.

[0019] In some embodiments of the present application, the density of the first vertical interconnection structure connected to each second-type semiconductor device is greater than the density of the second vertical interconnection structure connected to each first-type semiconductor device, and the interconnection structure connected to the second-type semiconductor devices for input and output signals is designed to be more dense to meet the requirements of high-speed signal transmission.

[0020] In some embodiments of the present application, the first vertical interconnection structure and the second vertical interconnection structure are conductive columns, and the diameter of the second vertical interconnection structure is greater than or equal to the diameter of the first vertical interconnection structure, which is beneficial to reducing the impedance of the second vertical interconnection line and has lower process difficulty.

[0021] In a second aspect, embodiments of the present application further provide an electronic device comprising a connector and a semiconductor package structure, wherein the connector is configured to connect to the semiconductor package structure via adapter traces within an adapter substrate, wherein the connector is the connector described in the first aspect or any possible implementation of the first aspect. The technical effects of the corresponding solutions in the second aspect may refer to the technical effects obtained by the corresponding solutions in the first aspect, and any repetitions are not detailed here.

[0022] In a third aspect, embodiments of the present application also provide a method for manufacturing a semiconductor packaging structure, comprising: providing an interconnection layer; having interconnection traces within the interconnection layer; disposing a plurality of semiconductor devices on a side surface of the interconnection layer; the plurality of semiconductor devices including a plurality of first-type semiconductor devices and a plurality of second-type semiconductor devices, the first-type semiconductor devices being used to process signals, and the second-type semiconductor structures being used to transmit signals; the interconnection traces including a first interconnection trace and a second interconnection trace; the first-type semiconductor devices and the second-type semiconductor devices being connected via the first interconnection traces, and the second-type semiconductor devices being connected to the second interconnection traces; connecting an adapter substrate to a side surface of the interconnection layer facing away from the plurality of semiconductor devices; the adapter substrate being provided with adapter traces, the adapter traces being connected to the second-type semiconductor devices via the second interconnection traces; the adapter traces also being used to connect to a connector. By providing an adapter substrate and disposing adapter traces within the adapter substrate to connect to the second interconnect traces, embodiments of the present application facilitate simplifying the structure of the second interconnect traces, reducing the number of layers of the second interconnect traces, and thereby reducing the processing difficulty of the interconnection layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] FIG1 is a schematic structural diagram of an electronic device provided in an embodiment of the present application;

[0024] FIG2 is a schematic structural diagram of a semiconductor packaging structure provided by an embodiment of the present application;

[0025] FIG3 is a flow chart of a method for manufacturing a semiconductor packaging structure provided by an embodiment of the present application;

[0026] FIG4 is a front view of a semiconductor package structure provided by an embodiment of the present application;

[0027] FIG5 is a front view of another semiconductor package structure provided by an embodiment of the present application;

[0028] FIG6 is a schematic structural diagram of another semiconductor packaging structure provided in an embodiment of the present application;

[0029] FIG7 is a schematic structural diagram of another semiconductor packaging structure provided in an embodiment of the present application;

[0030] FIG8 is a schematic structural diagram of another semiconductor packaging structure provided in an embodiment of the present application;

[0031] FIG9 is a schematic structural diagram of another packaging structure provided in an embodiment of the present application;

[0032] FIG10 is a schematic structural diagram of another packaging structure provided in an embodiment of the present application;

[0033] FIG11 is a schematic structural diagram of another packaging structure provided in an embodiment of the present application;

[0034] FIG12 is a flow chart of a method for manufacturing another semiconductor packaging structure provided by an embodiment of the present application;

[0035] Description of reference numerals:

[0036] 100-connector, 101-first connector, 102-second connector, 103-third connector, 200-semiconductor packaging structure, 1-interconnection layer, 11-first interconnection trace, 12-second interconnection trace, 13-third interconnection trace, N1-first dielectric layer, E-conductive layer, 2-semiconductor device, 21-first type semiconductor device, 22-second type semiconductor device, 23-third type semiconductor device, 3-transfer substrate, 30-transfer trace, 31-first substrate portion, 32-second substrate portion, 41-first interconnection structure, 42-second interconnection structure, 43-third interconnection structure, 5-power supply module, Q1-first region, Q2-second region, 61-first wiring layer, 62-carrier board, 63-second wiring layer, 7-vertical interconnection structure, 71-first vertical interconnection structure, 72-second vertical interconnection structure, 8-heat sink, 9-bolt, M-seed layer, N2-second dielectric layer, G-protective substrate. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings. The specific operating methods in the method embodiments can also be applied to device embodiments or system embodiments. It should be noted that in the description of the present application, "multiple" can be understood as "at least two". In addition, it should be understood that in the description of the present application, words such as "first" and "second" are only used to distinguish the purpose of description, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order. In addition, in the embodiments of the present application, "connection" refers to electrical connection, and the connection between two electrical elements can be a direct or indirect connection between the two electrical elements. For example, A and B are connected, which can be either A and B directly connected, or A and B indirectly connected through one or other electrical elements, such as A and B are connected, or A and C are directly connected, C is directly connected to B, and A and B are connected through C.

[0038] It should be noted that the same reference numerals in the drawings of this application represent the same or similar structures, and thus their repeated description will be omitted. The words expressing positions and directions described in this application are all explained using the drawings as examples, but they can be modified as needed, and such modifications are included in the scope of protection of this application. The drawings of this application are only for illustrative purposes and do not represent true proportions.

[0039] In order to facilitate the understanding of the technical solutions provided by the embodiments of the present application, its application scenarios are first described below. The semiconductor packaging structure provided by the embodiments of the present application can be widely used in electronic devices in various fields, and its application fields include but are not limited to: communication fields, such as 4G, 5G, and 6G communication chips; computer fields, such as central processing units (CPUs), graphics cards, etc.; embedded system fields, such as computer network equipment, medical equipment, aerospace equipment, smart homes, smart watches, smart wearable devices, etc.; automotive electronics fields, such as automatic driving, intelligent driving assistance, body electronic control, power electronic control, etc. It can be understood that the specific implementation of the electronic device can be determined according to the actual application scenario and is not limited here.

[0040] FIG1 is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. As shown in FIG1 , the electronic device includes a connector 100 and a semiconductor package structure 200. The types of connector 100 include, but are not limited to, plug-in connectors, terminal connectors, board-to-board connectors, wire-to-wire connectors, or one or more specialized connectors specifically designed for the devices or electronic devices to be connected. Connector 100 can be used to connect other devices or electronic devices to semiconductor package structure 200, forming a signal input and output channel between semiconductor package structure 200 and the outside world.

[0041] FIG2 is a schematic diagram of a semiconductor package structure provided in an embodiment of the present application. As shown in FIG2 , the semiconductor package structure 200 includes an interconnect layer 1 , a plurality of semiconductor devices 2 , and at least one transfer substrate 3 .

[0042] Among them, a plurality of semiconductor devices 2 are arranged on the surface of one side of the interconnection layer 1, including a first type semiconductor device 21 and a second type semiconductor device 22. Among them, the first type semiconductor device 21 is used to process signals, for example, it can realize digital signal processing, signal conversion, data storage, clock control and other functions. In order to meet the demand for greater computing power, the semiconductor packaging structure usually includes a large number of first type semiconductor devices 21, and at least some of the first type semiconductor devices 21 in the plurality of first type semiconductor devices 21 need to be interconnected to process signals in parallel. The second type semiconductor device 22 is used to transmit signals, for example, it can realize the function of inputting and outputting signals, or it can also have the function of temporarily storing data. Exemplarily, each second type semiconductor device 22 can be connected to one or more first type semiconductor devices 21, which is not limited here.

[0043] The interconnect layer 1 includes interconnect traces, including a first interconnect trace 11 and a second interconnect trace 12. The first semiconductor device 21 and the second semiconductor device 22 are connected via the first interconnect trace 11, so that the first interconnect trace 11 can transmit signals between the first semiconductor device 21 and the second semiconductor device 22. For example, a signal processed by the first semiconductor device 21 can be transmitted to the second semiconductor device 22 via the first interconnect trace 11, and then output by the second semiconductor device 22 to other connected devices or components. Alternatively, other devices or components connected to the second semiconductor device 22 first input a signal to the second semiconductor device 22, which then transmits the signal to the first semiconductor device 21 via the first interconnect trace 11 for processing.

[0044] At least a portion of the transfer substrate 3 is located on a side of the interconnect layer 1 away from the plurality of semiconductor devices 2, and the transfer substrate 3 is provided with a transfer trace 30. Exemplarily, the transfer trace 30 can be provided inside the transfer substrate 3, or can be provided on the surface of the transfer substrate 3. Moreover, the transfer trace 30 is connected to the second type of semiconductor device 22 through the second interconnect trace 12. In some embodiments of the present application, the semiconductor packaging structure 200 further includes a plurality of first interconnect structures 41, the plurality of first interconnect structures 41 being located between the interconnect layer 1 and the transfer substrate 3, and the transfer trace 30 and the second interconnect trace 12 being connected through the first interconnect structure 41. The semiconductor packaging structure 200 may further include a plurality of second interconnect structures 42, the second interconnect structure 42 being located between the interconnect layer 1 and the semiconductor device 2, and being used to connect the semiconductor device 2 to the interconnect trace. Exemplarily, the first interconnect structure 41 and the second interconnect structure 42 include but are not limited to micro bumps.

[0045] The transfer trace 30 is also used to connect to the connector 100, so that the second interconnect trace 12 can transmit signals between the second-type semiconductor device 22 and the connector 100. The connector 100 is then connected to other external devices or electronic components. Based on this connection relationship, a signal transmission path can be established between the first-type semiconductor device 21, the second-type semiconductor device 22, and other external devices or electronic components, enabling signal input and output within the semiconductor package structure 200.

[0046] Due to the large number of semiconductor devices 2 in the packaging structure and the complex signal transmission lines, its wiring structure usually needs to include more conductive layers, which makes the packaging process more difficult. In the embodiment of the present application, a transfer substrate 3 is provided, and a transfer line 30 is provided in the transfer substrate 3 to connect with the second interconnection line 12. The transfer substrate 3 and the second interconnection line 12 constitute the input and output lines of the signal, which is conducive to simplifying the structure of the second interconnection line 12 and reducing the number of layers of the second interconnection line 12, thereby reducing the process difficulty and production cost of the interconnection layer 1.

[0047] As shown in FIG2 , the semiconductor package structure 200 further includes at least one power supply module 5, which is located on a side of the interconnect layer 1 facing away from the plurality of semiconductor devices 2. The power supply module 5 is used to supply power to the first-type semiconductor device 21, enabling the first-type semiconductor device 21 to function properly. Correspondingly, the interconnect traces further include third interconnect traces 13, which are located on the first wiring layer 61 and the second wiring layer 63 and are used to connect the first-type semiconductor device 21 to the power supply module 5.

[0048] Based on the same concept, the embodiment of the present application further provides a method for manufacturing a semiconductor package structure 200. FIG3 is a flow chart of a method for manufacturing a semiconductor package structure provided by the embodiment of the present application. As shown in FIG3 , the method for manufacturing a semiconductor package structure includes:

[0049] Step S11: forming an interconnection layer 1. For example, referring to FIG. 3( a ), the interconnection layer 1 has interconnection traces therein. The interconnection layer 1 includes a first dielectric layer N1 and a plurality of conductive layers 102 located within the first dielectric layer N1. The substrate of the first dielectric layer N1 may be, for example, polyimide (PI).

[0050] Step S12: Multiple semiconductor devices 2 are disposed on one side surface of the interconnect layer 1. For example, referring to FIG. 3( b ), a second interconnect structure 42 may be formed on the surface of the interconnect layer 1. The semiconductor devices 2 are then attached to the one side surface of the interconnect layer 1 by, for example, thermal compression bonding (TCB). A reflow process is then performed to connect the second interconnect structure 42 and the semiconductor devices 2. Thus, the second interconnect structure 42 can connect the semiconductor devices 2 to the interconnect traces.

[0051] The semiconductor device 2 in this step can be a known good die (KGD) chip with good performance after testing, so that the semiconductor device 2 used for signal processing (i.e., the first type of semiconductor device 21) does not need to be redundantly designed in the packaging structure. A larger number and type of semiconductor devices 2 can be set under the same size, thereby improving the integration of the packaging structure, and at the same time facilitating the realization of more diversified functions and improving product performance.

[0052] Step S13: Connecting the transfer substrate 3 to the surface of the interconnect layer 1 facing away from the multiple semiconductor devices 2. For example, referring to FIG3(c), multiple first interconnect structures 41 can be formed on the surface of the interconnect layer 1 facing away from the semiconductor devices 2, for example, using a TCB and reflow process. The transfer substrate 3 is connected to the interconnect layer 1 via the first interconnect structures 41. Referring to FIG3(c), in this step, multiple third interconnect structures 43 can also be formed using the above process. The third interconnect structures 43 are used to connect the power supply module 5 and the interconnect layer 1.

[0053] FIG4 is a front view of a semiconductor package structure provided by an embodiment of the present application. As shown in FIG4 , when viewing the package structure from the Z1 direction perpendicular to the interconnect layer 1, the surface of the interconnect layer 1 facing the plurality of semiconductor devices 2 includes a first region Q1 and a second region Q2. The second region Q2 surrounds the first region Q1. The first-type semiconductor devices 21 are located within the first region Q1, and the second-type semiconductor devices 22 are located within the second region Q2. The second-type semiconductor devices 22 are disposed in the second region Q2, relatively closer to the edge of the semiconductor package structure 200, while the first-type semiconductor devices 21 are concentrated in the first region Q1. This facilitates interconnection between the first-type semiconductor devices 21. Furthermore, the wiring structure connecting the first-type semiconductor devices 21 can be made more regular. For example, when using photolithography to produce these wiring patterns, the photomask can be reused, reducing the number of required masks and thus reducing process difficulty and manufacturing costs.

[0054] FIG5 is a front view of another semiconductor package structure provided in an embodiment of the present application. Referring to FIG2 and FIG5 , when viewing the package structure from the Z2 direction, perpendicular to the interconnect layer 1, the orthographic projection of the transfer substrate 3 overlaps with the second region Q2, or alternatively, the orthographic projection of the transfer substrate 3 falls within the second region Q2. The second-type semiconductor devices 22 are arranged in a one-to-one correspondence with the transfer substrates 3, and the orthographic projections of the second-type semiconductor devices 22 fall within the range of the corresponding transfer substrates 3. This reduces the distance between the second-type semiconductor devices 22 and the transfer substrates 3, facilitating a reduction in the length of the second interconnect traces 12, shortening the signal transmission distance, and enabling high-speed signal transmission.

[0055] It is understandable that the boundary line between the first region Q1 and the second region Q2 shown in FIG. 4 and FIG. 5 is only for the purpose of explaining the layout of the semiconductor device 2 and the transfer substrate 3 , and does not represent the actual range.

[0056] FIG6 is a schematic diagram of another semiconductor package structure provided in an embodiment of the present application. As shown in FIG6 , the plurality of semiconductor devices 2 further include a third type of semiconductor device 23 . The third type of semiconductor device 23 is located within the second region Q2 and on the side of the second type of semiconductor device 22 facing away from the first type of semiconductor device 21 .

[0057] In some embodiments of the present application, the third type semiconductor device 23 may include a redundant semiconductor device. The redundant semiconductor device may be a device that is not connected to the interconnection traces in the interconnection layer, that is, the redundant semiconductor device is equivalent to a dummy semiconductor device. In addition, the redundant semiconductor devices are distributed at the edge of the semiconductor package structure 200. By rationally designing the position distribution of the redundant semiconductor devices, stress can be balanced, the stability of the package structure can be improved, and the risk of structural rupture can be reduced. For example, the redundant semiconductor device can have the same or different structure as the second type semiconductor device 22 or the first type semiconductor device 21.

[0058] In some other embodiments of the present application, the third-type semiconductor device 23 may further include a semiconductor device with a set function, which is used to implement information exchange with other devices or electronic devices. For example, the third-type semiconductor device 23 may be a wireless communication module, an antenna, etc., for wireless communication, or the third-type semiconductor device 23 may be the same as the first-type semiconductor device 21. In addition, the third-type semiconductor device 23 may be connected to the second-type semiconductor device 22, the first-type semiconductor device 21, or the power supply module 5 through other interconnection traces in the interconnection layer.

[0059] In the present application, the shape of the transfer substrate 3 in the packaging structure can have various forms to match the needs for different numbers, sizes and types of connectors. In some embodiments of the present application, as shown in Figures 2 and 6, in the direction perpendicular to the interconnection layer 1, the orthographic projection of the transfer substrate 3 falls within the area of ​​the interconnection layer 1, and the side of the transfer substrate 3 facing away from the interconnection layer 1 is used to connect the connector 100. Since in the process of making the packaging structure, the interconnection layer 1 is formed first and then the transfer substrate 3 is connected to the interconnection layer 1, the transfer substrate 3 structure shown in Figures 2 or 6 can be set on the basis of the original size of the interconnection layer 1, effectively utilizing the space in the direction perpendicular to the interconnection layer 1, and by rationally designing the positions of multiple transfer substrates 3, it is also beneficial to balance stress and improve the stability of the packaging structure.

[0060] FIG7 is a schematic diagram of the structure of another semiconductor packaging structure provided by an embodiment of the present application; FIG8 is a schematic diagram of the structure of another semiconductor packaging structure provided by an embodiment of the present application. As shown in FIG7 and FIG8, the transfer substrate 3 includes a first substrate portion 31 and a second substrate portion 32 connected to each other. In the direction perpendicular to the interconnection layer 1, the orthographic projection of the first substrate portion 31 falls within the range of the interconnection layer 1, and the orthographic projection of the second substrate portion 32 does not have an overlapping area with the interconnection layer 1. In other words, the transfer substrate 3 is extended based on the original size of the interconnection layer 1, increasing the space available for setting the connector 100 on the transfer substrate 3. More types and more numbers of connectors 100 are set on the transfer substrate 3, so that it can match more types and more numbers of devices or electronic devices. Correspondingly, more types of semiconductor devices 2 can also be set in the packaging structure, so that it can achieve richer functions. At the same time, increasing the number of connectors 100 is also conducive to improving the signal transmission rate.

[0061] In some embodiments of the present application, as shown in FIG7 , the first substrate portion 31 is flush with the second substrate portion 32, and both sides of the interposer substrate 3 can be used to connect to the connector 100. Exemplarily, the connector 100 includes a first connector 101, with the side of the first substrate portion 31 facing away from the interconnect layer 1 being used to connect to the first connector 101. Alternatively, the connector 100 includes a second connector 102, with the side of the second substrate portion 32 facing away from the interconnect layer 1 being used to connect to the second connector 102. Exemplarily, when the first substrate portion 31 and the second substrate portion 32 are flush, the connector 100 may further include a third connector 103, with the side of the second substrate portion 32 facing the interconnect layer 1 being used to connect to the third connector 103.

[0062] In some embodiments of the present application, as shown in Figure 8, one end of the second substrate portion 32 is connected to the first substrate portion 31, and the other end of the second substrate portion 32 extends along the side of the interconnection layer 1. This design can provide more connectors 100 while making the product have a smaller volume, thereby improving the integration of the packaging structure.

[0063] FIG9 is a schematic diagram of the structure of another packaging structure provided by an embodiment of the present application. As shown in FIG9 , the interconnection layer 1 includes a first wiring layer 61, a carrier 62, and a second wiring layer 63. The first wiring layer 61 is located between the plurality of semiconductor devices 2 and the carrier 62, and the second wiring layer 63 is located between the carrier 62 and at least one transfer substrate 3. The substrates of the first and second wiring layers 61, 63 can be the same or different. Each of the first and second wiring layers 61, 63 can include multiple conductive layers to form interconnect lines. The first interconnect line 11 is located in the first wiring layer 61, and the second interconnect line 12 is located in the first and second wiring layers 61, 63. The substrate of the carrier 62 can be a rigid substrate including, but not limited to, silicon (Si) or glass to support the first and second wiring layers 61, 63. Exemplarily, the carrier 62 can be a wafer to meet the large-scale carrier requirements of the packaging structure provided by the embodiment of the present application. The carrier 62 includes a first vertical interconnect structure 71, which can be used to connect the second interconnect lines in the first and second wiring layers 61, 63. Based on this, the connector 100 can be connected to the second-type semiconductor device 22 through the transfer trace 30 , the second interconnect trace and the first vertical interconnect structure 71 to achieve signal input and output.

[0064] In the embodiment of the present application, each second-type semiconductor device 22 is connected to multiple first vertical interconnection structures 71. In the direction perpendicular to the interconnection layer 1, the positive projection of the first vertical interconnection structure 71 corresponding to the same second-type semiconductor device 22 falls within the range of the corresponding transfer substrate 3. The first vertical interconnection structure 71 connects the second interconnection lines in the first wiring layer 61 and the second wiring layer 62 in the direction perpendicular to the interconnection layer 1, which is beneficial to reducing the overall length of the lines between the second-type semiconductor device 22 and the interconnection substrate 3, thereby facilitating improving the signal transmission rate.

[0065] As shown in FIG9 , the semiconductor package structure 200 further includes at least one power supply module 5, which is located on a side of the second wiring layer 63 facing away from the plurality of semiconductor devices 2. The power supply module 5 is used to supply power to the first-type semiconductor device 21, enabling the first-type semiconductor device 21 to operate normally. Correspondingly, referring to FIG9 , the interconnection traces further include third interconnection traces 13, which are located between the first wiring layer 61 and the second wiring layer 63. The third interconnection traces are used to connect the first-type semiconductor device 21 and the power supply module 5. In this case, the carrier 62 further includes a second vertical interconnection structure 72, which is used to connect the third interconnection traces 13 in the first wiring layer 61 and the second wiring layer 63. Based on this, the power supply module 5 can connect to the first-type semiconductor device 21 via the third interconnection trace and the second vertical structure to supply power to the first-type semiconductor device 21. Furthermore, different first-type semiconductor devices 21 can be connected to different power supply modules 5 to meet the operating requirements of different first-type semiconductor devices 21.

[0066] Because the first vertical interconnect structure 71 performs signal input and output functions, while the second vertical interconnect structure 72 performs power supply functions, to meet the requirements of high-speed signal transmission, in the embodiment of the present application, the density of the first vertical interconnect structures 71 connected to each second-type semiconductor device 22 can be greater than the density of the second vertical interconnect structures 72 connected to each first-type semiconductor device 21. At the same time, the density of the second vertical interconnect structures 72 is relatively low, which also helps reduce the difficulty of the drilling process. For example, the first vertical interconnect structure 71 and the second vertical interconnect structure 72 can be conductive pillars.

[0067] To meet the requirement of low impedance, the line width of the first interconnection line 11 needs to be relatively larger, and to meet the requirement of high-speed signal transmission, the line width of the second interconnection line 12 needs to be relatively smaller. Correspondingly, the diameter of the second vertical interconnection structure 72 can be greater than or equal to the diameter of the first vertical interconnection structure 71, which is beneficial to reducing the impedance of the second vertical interconnection structure 72 and has lower process difficulty.

[0068] It is understandable that the specific structure of the interconnection layer 1 can be designed according to the process level, and the combination of the interconnection layer 1 and the transfer substrate 3 can also be determined according to the needs. Figure 10 is a structural schematic diagram of another packaging structure provided in an embodiment of the present application, and Figure 11 is a structural schematic diagram of another packaging structure provided in an embodiment of the present application. As shown in Figures 10 and 11, the interconnection layer 1 includes a first wiring layer 61, a carrier 62, and a second wiring layer 63. The corresponding technical effects can be obtained by referring to the technical effects of the solution shown in Figure 9. The transfer substrate 3 includes a first substrate portion 31 and a second substrate portion 32. The corresponding technical effects can be obtained by referring to the technical effects of the corresponding solutions of Figures 7 or 8. The repeated parts will not be described in detail.

[0069] In addition, as shown in Figures 2 and 6-9, the packaging structure may further include a heat sink 8, which is located on the side of the multiple semiconductor devices 2 away from the interconnection layer 1 and is used to dissipate heat from the semiconductor devices 2 to prevent the semiconductor devices 2 from overheating during operation, thereby protecting the semiconductor devices 2 and extending the service life of the semiconductor devices 2.

[0070] The packaging structure provided in the embodiment of the present application is applied to ultra-large-scale integrated packaging. The size of the packaging structure is relatively large, so the packaging structure can also include multiple bolts 9. The bolts 9 pass through the interconnection layer 1 and the heat sink 8, which can ensure the stability and safety of the packaging structure and improve product reliability.

[0071] FIG12 is a flow chart of a method for manufacturing another semiconductor package structure provided in an embodiment of the present application. As shown in FIG12 , the method for manufacturing the semiconductor package structure 200 includes:

[0072] Step S21: Through silicon via (TSV) processing and semiconductor back-end processing can produce the structure shown in FIG12(a). This structure includes a carrier 62 and a first wiring layer 61. The carrier 62 includes multiple vertical interconnect structures 7 formed using the TSV process, and the first wiring layer 61 includes, for example, first interconnect traces, portions of second interconnect traces, and interconnect traces connecting different first semiconductor devices 2. Before proceeding to subsequent steps, the semi-finished product may be pre-baked and cleaned to remove process residues, improve surface cleanliness, and enhance surface adhesion.

[0073] Step S22: A plurality of second interconnect structures 42 are formed on the first wiring layer 61. Referring to (b) in FIG12 , a seed layer M may be first sputter-deposited on the first wiring layer 61 by a physical vapor deposition (PVD) process, and then the seed layer M may be photolithographically, dry-etched, or wet-etched to form the plurality of second interconnect structures 42. The seed layer M may be a single-layer or multi-layer metal structure. Optionally, the seed layer M may be formed by stacking titanium (Ti) and copper (Cu), or stacking tin (Sn) and silver (Ag), or stacking copper (Cu), tin (Sn), and silver (Ag), or stacking nickel (Ni), tin (Sn), and silver (Ag), or stacking nickel (Ni), copper (Cu), tin (Sn), and silver (Ag), or copper (Cu).

[0074] Step S23: Connecting multiple semiconductor devices 2 on the second interconnect structure 42. For example, referring to (c) in FIG. 12 , the semiconductor devices 2 and the second interconnect structure 42 may be connected by TCB and reflow processes to connect the semiconductor devices 2 to the interconnect traces.

[0075] Step S24: Referring to (d) in FIG. 12 , a dielectric material is filled between the semiconductor devices 2 to form a second dielectric layer N2. The second dielectric layer N2 may be made of an organic resin polymer material such as PI, or an inorganic material such as SiO, SiO2, SiN, or SiCN.

[0076] Step S25: Optionally, referring to (e) in FIG. 12 , the dielectric layer N is thinned. The thinning process may include but is not limited to rough grinding, chemical mechanical polishing (CMP), wet etching, dry etching, and the like.

[0077] Step S26: Referring to (f) in FIG. 12 , a protective substrate G is bonded on the dielectric layer, such as mounting glass, to improve the overall structural strength so as to facilitate subsequent process flows and ensure structural stability.

[0078] Step S27 : Referring to (g) in FIG. 12 , thinning the carrier 62 to expose the vertical interconnection structure 7 in the carrier 62 .

[0079] Step S28: Referring to (h) in Figure 12, a second wiring layer 63 can be formed on the side of the carrier 62 away from the first wiring layer 61 through multiple photolithography and electroplating processes, and then a chemical mechanical planarization (CMP) process is performed to smooth the surface of the second wiring layer 63. The wiring in the second wiring layer 63 is connected to the wiring in the first wiring layer 61 through the vertical interconnection structure 7 in the carrier 62. The first wiring layer 61, the carrier 62 and the second wiring layer 63 constitute the interconnection layer 1.

[0080] Step S29: Referring to (i) in FIG12 , a plurality of first interconnect structures 41 and a plurality of third interconnect structures 43 are formed on the surface of the second wiring layer 63 facing away from the carrier 62. The first interconnect structures 41 are used to connect to the transfer substrate 3, and the third interconnect structures 43 are used to connect to the power supply module. The manufacturing method and materials of the first interconnect structures 41 and the third interconnect structures 43 can be referred to as the manufacturing method and materials of the second interconnect structure 42 in step S22, and are not further described here.

[0081] Step S210 : Referring to (j) in FIG. 12 , the transfer substrate 3 may be connected to the plurality of first interconnect structures 41 and the power supply module 5 may be connected to the plurality of third interconnect structures 43 through TCB and reflow processes.

[0082] Among them, the adapter substrate 3 has a adapter trace 30, which is connected to the second type semiconductor device 22 through the second interconnect trace 12 in the interconnect layer 1, and the power supply module is connected to the first type semiconductor device 21 through the third interconnect trace 13 in the interconnect layer 1.

[0083] Step S211 : Referring to (k) in FIG. 12 , the protective substrate is removed.

[0084] Step S212: Referring to (1) in FIG12 , a heat sink 8 is provided on a side of the plurality of semiconductor devices 2 facing away from the interconnection layer 1 , for example, by mounting, to improve the heat dissipation efficiency of the packaging structure.

[0085] In the embodiment of the present application, the adapter substrate 3 has a transfer line. By setting the adapter substrate 3, the number of layers of the interconnection layer 1, especially the conductive layer E in the second wiring layer 63, can be reduced, which is conducive to simplifying the manufacturing process of the interconnection layer 1 and reducing the process difficulty.

[0086] In the various embodiments of the present application, unless otherwise specified or there is a logical conflict, the terms and / or descriptions between different embodiments are consistent and can be referenced by each other. The technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationships.

[0087] The above content is only a specific implementation method of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with this technical field can easily think of changes or replacements within the technical scope disclosed in this application, and they should all be covered by the protection scope of the present application.

Claims

1. A semiconductor packaging structure, characterized in that: include: an interconnect layer, the interconnect layer including interconnect traces; a plurality of semiconductor devices disposed on a surface of one side of the interconnection layer, the plurality of semiconductor devices including a first type of semiconductor device and a second type of semiconductor device, the first type of semiconductor device being used to process signals, and the second type of semiconductor device being used to transmit signals; the interconnection traces including a first interconnection trace and a second interconnection trace; the first type of semiconductor device and the second type of semiconductor device being connected via the first interconnection trace; At least one transfer substrate, at least a portion of the transfer substrate is located on a side of the interconnect layer away from the plurality of semiconductor devices, the transfer substrate is provided with a transfer trace, the transfer trace is connected to the second type of semiconductor device through the second interconnect trace, and the transfer trace is also used to connect a connector.

2. The semiconductor package structure according to claim 1, wherein: The surface of the interconnection layer facing the plurality of semiconductor devices includes a first region and a second region, the second region surrounds the first region, the first type of semiconductor devices are located in the first region, and the second type of semiconductor devices are located in the second region; In a direction perpendicular to the interconnection layer, an orthographic projection of the transfer substrate and the second region have an overlapping area.

3. The semiconductor package structure according to claim 2, wherein: The plurality of semiconductor devices further include a third type of semiconductor device, the third type of semiconductor device being located on a side of the second type of semiconductor device facing away from the first type of semiconductor device; the third type of semiconductor device includes a redundant semiconductor device.

4. The semiconductor package structure according to any one of claims 1 to 3, wherein: The semiconductor package structure further includes a plurality of first interconnect structures, which are located between the interconnect layer and the transfer substrate. The first interconnect structures are used to connect the transfer traces and the second interconnect traces.

5. The semiconductor package structure according to claim 4, wherein: In a direction perpendicular to the interconnection layer, an orthographic projection of the transfer substrate falls within a region of the interconnection layer, and a side of the transfer substrate facing away from the interconnection layer is used for connecting a connector.

6. The semiconductor package structure according to claim 4, wherein: The transfer substrate includes a first substrate portion and a second substrate portion connected to each other. In a direction perpendicular to the interconnection layer, the orthographic projection of the first substrate portion falls within the range of the interconnection layer, and the orthographic projection of the second substrate portion has no overlapping area with the interconnection layer.

7. The semiconductor package structure according to claim 6, wherein: The first substrate portion is flush with the second substrate portion.

8. The semiconductor package structure according to claim 6, wherein: One end of the second substrate portion is connected to the first substrate portion, and the other end of the second substrate portion extends along a side surface of the interconnection layer.

9. The semiconductor package structure according to claim 7 or 8, wherein: The connector includes a first connector, and a side of the first substrate portion facing away from the interconnection layer is used to connect to the first connector, or the connector includes a second connector, and a side of the second substrate portion facing away from the interconnection layer is used to connect to the second connector.

10. The semiconductor package structure according to claim 9, wherein: When the first substrate portion and the second substrate portion are flush with each other, the connector further includes a third connector, and a side of the second substrate portion facing the interconnection layer is used to connect to the third connector.

11. The semiconductor package structure according to any one of claims 1 to 10, wherein: The interconnection layer includes a first wiring layer, a carrier board, and a second wiring layer, wherein the first wiring layer is located between the plurality of semiconductor devices and the carrier board, and the second wiring layer is located between the carrier board and the at least one transfer substrate; The first interconnection trace is located in the first wiring layer; the second interconnection trace is located in the first wiring layer and the second wiring layer, and the carrier includes a first vertical interconnection structure, which is used to connect the second interconnection traces in the first wiring layer and the second wiring layer.

12. The semiconductor package structure according to claim 11, wherein: The second-type semiconductor devices are arranged in a one-to-one correspondence with the transfer substrate, and each of the second-type semiconductor devices is connected to a plurality of the first vertical interconnection structures. In the direction perpendicular to the interconnection layer, the orthographic projection of the first vertical interconnection structure corresponding to the same second-type semiconductor device falls within the range of the corresponding transfer substrate.

13. The semiconductor package structure according to claim 11 or 12, wherein: The semiconductor package structure further includes at least one power supply module, and the at least one power supply module is located on a side of the second wiring layer away from the plurality of semiconductor devices; The interconnection trace further includes a third interconnection trace, the third interconnection trace is located in the first wiring layer and the second wiring layer, and the third interconnection trace is used to connect the first type semiconductor device and the power supply module; The carrier board further includes a second vertical interconnect structure, and the second vertical interconnect structure is used to connect the first wiring layer and the third interconnect trace in the second wiring layer.

14. The semiconductor package structure according to claim 13, wherein: The density of the first vertical interconnection structures to which each of the second-type semiconductor devices is connected is greater than the density of the second vertical interconnection structures to which each of the first-type semiconductor devices is connected.

15. The semiconductor package structure according to any one of claims 11 to 14, wherein: The first vertical interconnection structure and the second vertical interconnection structure are conductive pillars, and a diameter of the second vertical interconnection structure is greater than or equal to a diameter of the first vertical interconnection structure.

16. An electronic device, characterized in that: include: A connector and a semiconductor package structure as described in any one of claims 1 to 15, wherein the connector is used to connect to the semiconductor package structure through a transfer trace in a transfer substrate.

17. A method for manufacturing a semiconductor packaging structure, characterized in that: include: Provides an interconnection layer; The interconnection layer has interconnection wiring; A plurality of semiconductor devices are provided on a surface of one side of the interconnection layer; the plurality of semiconductor devices include a plurality of first-type semiconductor devices and a plurality of second-type semiconductor devices, the first-type semiconductor devices are used to process signals, and the second-type semiconductor devices are used to transmit signals; the interconnection traces include a first interconnection trace and a second interconnection trace; the first-type semiconductor devices and the second-type semiconductor devices are connected via the first interconnection trace, and the second-type semiconductor devices are connected to the second interconnection trace; A transfer substrate is connected to the surface of the interconnect layer facing away from the multiple semiconductor devices; the transfer substrate is provided with a transfer trace, and the transfer trace is connected to the second type of semiconductor device through the second interconnect trace; the transfer trace is also used to connect a connector.

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