Semiconductor structure, preparation method therefor, and electronic device

Abstract

Embodiments of the present application belong to the technical field of semiconductors, and specifically relate to a semiconductor structure, a preparation method therefor, and an electronic device, which are used for solving the problem of low on-currents of vertical field effect transistors in the related art. The semiconductor structure comprises a first electrode layer, a gate layer, a second electrode layer, a channel layer, and a first buffer layer. The first electrode layer, the gate layer, and the second electrode layer are sequentially stacked in a first direction. At least part of the channel layer is located between the first electrode layer and the second electrode layer, and penetrates through the gate layer in the first direction. At least part of the first buffer layer is located between the first electrode layer and the channel layer, the first buffer layer is in contact with the channel layer, and the concentration of N-type ions in the first buffer layer is greater than the concentration of N-type ions in the channel layer. By means of the described configuration, the N-type ions in the first buffer layer are diffused into the channel layer, so that the doping concentration of the N-type ions in the channel layer close to the first buffer layer is increased, facilitating an increase in the on-current of a transistor structure.

Description

Semiconductor structure and preparation method thereof, and electronic device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on March 26, 2024, with application number 202410358183.8 and application name “Semiconductor structure and its preparation method, electronic device”, all contents of which are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present application belong to the field of semiconductor technology, and in particular, relate to a semiconductor structure and a preparation method thereof, and an electronic device. Background Art

[0003] In order to further reduce the size of the memory cell in the dynamic random access memory, a vertical fielded effect transistor (VFET) is usually set in the memory cell. The vertical transistor may include a first electrode layer, a gate layer, and a second electrode layer stacked in sequence. The vertical transistor also includes a channel layer, at least a portion of the channel layer is located between the first electrode layer and the second electrode layer, and the channel layer passes through the gate layer along the stacking direction of the first electrode layer, the gate layer, and the second electrode layer. However, the vertical transistor in the related art still has the problem of low turn-on current. Summary of the Invention

[0004] The purpose of the embodiments of the present application is to provide a semiconductor structure and a manufacturing method thereof, and an electronic device, which are used to improve the problem of low turn-on current of vertical transistors in related technologies.

[0005] In order to achieve the above objectives, the present invention provides the following solutions:

[0006] A semiconductor structure is provided, comprising: a first electrode layer, a gate layer, a second electrode layer, a channel layer, and a first buffer layer. The first electrode layer, the gate layer, and the second electrode layer are stacked in sequence along a first direction. At least a portion of the channel layer is located between the first electrode layer and the second electrode layer, extending along the first direction, and the channel layer penetrates the gate layer. At least a portion of the first buffer layer is located between the first electrode layer and the channel layer, and the first buffer layer contacts the channel layer. The concentration of N-type ions in the first buffer layer is greater than the concentration of N-type ions in the channel layer.

[0007] Through the above-mentioned setting, the N-type ions in the first buffer layer can diffuse into the channel layer, so that the doping concentration of the N-type ions in the channel layer near the first buffer layer increases, resulting in a decrease in the resistance of the region of the channel layer located between the first electrode layer and the gate layer, which is beneficial to increasing the turn-on current of the transistor structure.

[0008] At the same time, the N-type ions in the first buffer layer diffuse into the channel layer, which can also form a graded junction at the contact portion of the first buffer layer and the channel layer, avoiding the formation of a large Schottky barrier between the first buffer layer and the channel layer, which is beneficial to reducing the contact resistance between the first buffer layer and the channel layer, and is beneficial to increasing the turn-on current of the transistor structure.

[0009] In some embodiments, the concentration of N-type ions in the first buffer layer ranges from 1e 18 -1e 21 Through the above arrangement, the concentration of N-type ions in the first buffer layer is greater than the concentration of N-type ions in the channel layer, so that the N-type ions in the first buffer layer can diffuse into the channel layer, thereby increasing the doping concentration of N-type ions in the second portion, resulting in a decrease in the resistance of the region of the channel layer between the first electrode layer and the gate layer, which is beneficial to increasing the turn-on current of the transistor structure.

[0010] In some embodiments, the first buffer layer includes a first sublayer and a second sublayer that are stacked, at least a portion of the first sublayer is located between the second sublayer and the channel layer, and the second sublayer and the channel layer are in contact with the first sublayer, respectively. The concentration of N-type ions in the second sublayer is greater than the concentration of N-type ions in the first sublayer, and the concentration of N-type ions in the first sublayer is greater than the concentration of N-type ions in the channel layer. Through the above arrangement, the N-type ions in the second sublayer diffuse into the first sublayer, and the N-type ions in the first sublayer diffuse into the channel layer, so that the concentration of N-type ions in the second sublayer, the first sublayer, and the channel layer gradually decreases in the direction close to the gate layer, which is beneficial to further reduce the Schottky barrier between the first buffer layer and the channel layer, forming a better ohmic contact, and further beneficial to improving the turn-on current of the semiconductor structure.

[0011] In some embodiments, the material of the second sublayer includes at least one of InSnO, F:SnO, AlZnO, AlSnO, In2O3, InGaZnO, InZnO, InZnSnO, H:a-Si, or D:a-Si. Through the above configuration, the concentration of N-type ions in the second sublayer is greater than the concentration of N-type ions in the first sublayer. The N-type ions in the second sublayer can diffuse into the first sublayer, forming a graded junction at the contact between the first and second sublayers, avoiding the formation of a large Schottky barrier between the first and second sublayers, and facilitating reduced contact resistance between the first and second sublayers.

[0012] In some embodiments, the material of the first sublayer includes IZO and / or IGO. This configuration allows the concentration of N-type ions in the first sublayer to be greater than the concentration of N-type ions in the channel layer. The N-type ions in the first sublayer can diffuse into the channel layer, forming a graded junction at the contact between the first sublayer and the channel layer. This prevents the formation of a large Schottky barrier between the first sublayer and the channel layer, thereby reducing the contact resistance between the first sublayer and the channel layer.

[0013] In some embodiments, the semiconductor structure further comprises a second buffer layer, the second buffer layer being located between the first buffer layer and the first electrode layer, and the first buffer layer and the first electrode layer being in contact with the second buffer layer, respectively. The material of the second buffer layer comprises at least one of a metal and a conductive metal oxide. By disposing the second buffer layer between the first buffer layer and the first electrode layer, when the first buffer layer is formed on the second buffer layer, the metal in the second buffer layer is partially oxidized. Since the metal oxide in the second buffer layer is conductive, an increase in the contact resistance between the first buffer layer and the second buffer layer is avoided, thereby facilitating an increase in the turn-on current of the semiconductor structure.

[0014] In some embodiments, the channel layer includes a first portion and a second portion that are interconnected, with the first portion being arranged around the edge of the second portion; the semiconductor structure further includes an insulating layer, which is located within a groove jointly enclosed by the first portion and the second portion. At least a portion of the first buffer layer is located between the second portion and the first electrode layer, and the first buffer layer and the second portion are in contact. Through the above arrangement, N-type ions in the first buffer layer can diffuse into the second portion of the channel layer, thereby increasing the doping concentration of N-type ions in the fourth sub-portion of the second portion, resulting in a decrease in the resistance of the region of the channel layer located between the first electrode layer and the gate layer, which is beneficial to increasing the turn-on current of the transistor structure.

[0015] In some embodiments, the orthographic projection of the first buffer layer on the first electrode layer is located within the first electrode layer. The above configuration is helpful in reducing the occupied area of ​​the first buffer layer, thereby helping to reduce the material used in the first buffer layer.

[0016] In some embodiments, the first electrode layer has a groove on one side close to the channel layer, and the first buffer layer is located in the groove. The above configuration is helpful in reducing the size of the semiconductor structure along the first direction, thereby further helping to achieve size miniaturization of the memory.

[0017] In some embodiments, the semiconductor structure further includes a third buffer layer, the third buffer layer being located between the first portion and the second electrode layer and in contact with the first portion, wherein the concentration of N-type ions in the third buffer layer is greater than the concentration of N-type ions in the channel layer. Through this configuration, the N-type ions in the third buffer layer can diffuse into the channel layer, increasing the doping concentration of N-type ions in the channel layer near the third buffer layer. This results in a lower resistance in the region of the channel layer between the second electrode layer and the gate layer, which is beneficial for further increasing the turn-on current of the transistor structure.

[0018] In some embodiments, the third buffer layer and the second electrode layer are located in a groove enclosed by the first portion and the insulating layer. The above configuration is beneficial for reducing the size of the semiconductor structure along the first direction, thereby facilitating the miniaturization of the memory.

[0019] In some embodiments, the first portion includes a first sub-portion and a second sub-portion, the second sub-portion being located between the first sub-portion and the second sub-portion, the second sub-portion being disposed around an edge of the second portion, the first sub-portion being disposed around an edge of the second sub-portion, one side of the first sub-portion being connected to the second sub-portion, and the other side of the first sub-portion extending away from the second sub-portion. At least a portion of the third buffer layer is located between the first sub-portion and the second electrode layer, and the third buffer layer is in contact with the first sub-portion. This arrangement facilitates reducing the size of the semiconductor structure along the first direction, thereby facilitating memory device miniaturization.

[0020] In some embodiments, the third buffer layer includes a third sublayer and a fourth sublayer that are stacked, at least a portion of the third sublayer is located between the fourth sublayer and the channel layer, and the fourth sublayer and the channel layer are in contact with the third sublayer, respectively. The concentration of N-type ions in the fourth sublayer is greater than the concentration of N-type ions in the third sublayer, and the concentration of N-type ions in the third sublayer is greater than the concentration of N-type ions in the channel layer. Through the above arrangement, the N-type ions in the fourth sublayer diffuse into the third sublayer, and the N-type ions in the third sublayer diffuse into the channel layer, so that the concentration of N-type ions in the third sublayer, the fourth sublayer, and the channel layer gradually decreases in the direction close to the gate layer, which is beneficial to further reduce the Schottky barrier between the second buffer layer and the channel layer, forming a better ohmic contact, and further beneficial to improving the turn-on current of the semiconductor structure.

[0021] In some embodiments, the semiconductor structure further includes a fourth buffer layer, the fourth buffer layer being located between the third buffer layer and the second electrode layer, and the third buffer layer and the second electrode layer are respectively in contact with the fourth buffer layer. The material of the fourth buffer layer includes at least one of a metal and a conductive metal oxide. By providing the fourth buffer layer between the third buffer layer and the second electrode layer, when the third buffer layer is formed on the fourth buffer layer, the metal in the fourth buffer layer is partially oxidized. Since the metal oxide in the fourth buffer layer is conductive, an increase in the contact resistance between the fourth buffer layer and the third buffer layer is avoided, thereby facilitating an increase in the turn-on current of the semiconductor structure.

[0022] In some embodiments, the material of the channel layer includes oxide semiconductor, which is an N-type channel material with good uniformity, low preparation temperature, no need for doping, high mobility, and wide energy band gap, which is beneficial for improving the performance of the semiconductor structure.

[0023] An embodiment of the present application also provides a method for preparing a semiconductor structure, comprising: forming a first electrode layer, a first buffer layer, and a gate layer stacked in sequence along a first direction. A channel layer is formed, the channel layer penetrates the gate layer along the first direction, wherein the first buffer layer is in contact with the channel layer, and the concentration of N-type ions in the first buffer layer is greater than the concentration of N-type ions in the channel layer. A second electrode layer is formed on the side of the channel layer away from the first electrode layer. Through the above arrangement, the N-type ions in the first buffer layer can diffuse into the channel layer, so that the doping concentration of N-type ions in the channel layer near the first buffer layer increases, resulting in a decrease in the resistance of the region of the channel layer between the first electrode layer and the gate layer, which is beneficial to increasing the turn-on current of the transistor structure.

[0024] At the same time, the N-type ions in the first buffer layer diffuse into the channel layer, which can also form a graded junction at the contact portion of the first buffer layer and the channel layer, avoiding the formation of a large Schottky barrier between the first buffer layer and the channel layer, which is beneficial to reducing the contact resistance between the first buffer layer and the channel layer, and is beneficial to increasing the turn-on current of the transistor structure.

[0025] In some embodiments, forming a first electrode layer, a first buffer layer, and a gate layer stacked in sequence along a first direction includes: forming a stacked first electrode layer and a first buffer layer; performing a patterning process on the first electrode layer and the first buffer layer simultaneously; and forming a stacked first isolation layer, a gate layer, and a second isolation layer on a side of the first buffer layer facing away from the first electrode layer. The above configuration ensures that the first electrode layer, the second buffer layer, and the first buffer layer have the same shape.

[0026] In some embodiments, forming a first electrode layer, a first buffer layer, and a gate layer stacked sequentially along a first direction includes: patterning the first electrode layer to form a groove; forming the first buffer layer within the groove; and forming a first isolation layer, a gate layer, and a second isolation layer stacked sequentially on a side of the first buffer layer facing away from the first electrode layer. This arrangement facilitates reducing the size of the semiconductor structure along the first direction, thereby facilitating memory device miniaturization.

[0027] In some embodiments, forming a channel layer includes: forming a first channel hole extending through a second isolation layer and a gate layer; sequentially forming a gate dielectric layer and a sacrificial layer, the gate dielectric layer and the sacrificial layer covering the walls and bottom of the first channel hole, and the gate dielectric layer and the sacrificial layer also being located on a side of the second isolation layer facing away from the gate layer; forming a second channel hole extending through the first isolation layer, the second channel hole extending through the first buffer layer; removing the sacrificial layer; and forming a channel layer, the channel layer comprising a first portion and a second portion, the first portion covering the walls and bottom of the first channel hole, the first portion also being located on a side of the second isolation layer facing away from the gate layer, and the second portion covering the walls and bottom of the second channel hole. With the above arrangement, the channel material covering one side of the second isolation layer constitutes a first sub-portion, the channel material covering the walls and bottom of the first channel hole constitutes a second sub-portion, and the first and second sub-portions together constitute the first portion. The channel material covering the walls of the second channel hole constitutes a third sub-portion, and the channel material covering the bottom of the second channel hole constitutes a fourth sub-portion, and the third and fourth sub-portions together constitute the second portion. The first portion and the second portion together constitute a channel layer.

[0028] In some embodiments, after forming the channel layer and before forming the second electrode layer on the side of the channel layer facing away from the first electrode layer, the method further includes: filling the first channel hole and the second channel hole with an insulating material to form an insulating layer, wherein the insulating layer and the first portion enclose a first groove. A third buffer layer is formed in the first groove, the third buffer layer contacts the first portion, and the concentration of N-type ions in the third buffer layer is greater than the concentration of N-type ions in the channel layer. The second electrode layer is formed on the side of the channel layer facing away from the first electrode layer, including: forming the second electrode layer in the first groove. The above-mentioned arrangement is conducive to reducing the size of the semiconductor structure along the first direction, thereby facilitating the miniaturization of the memory.

[0029] In some embodiments, after forming the channel layer and before forming the second electrode layer on a side of the channel layer facing away from the first electrode layer, the method further includes: filling the first channel hole and the second channel hole with an insulating material to form an insulating layer; forming a third buffer layer, the third buffer layer being located on a side of the first portion facing away from the second isolation layer, the third buffer layer also being located on a side of the insulating layer facing away from the second portion, the third buffer layer being in contact with the first portion, and the concentration of N-type ions in the third buffer layer being greater than the concentration of N-type ions in the channel layer; and forming the second electrode layer on a side of the channel layer facing away from the first electrode layer, including: forming the second electrode layer on a side of the third buffer layer facing away from the first portion. Through the above arrangement, the third buffer layer is in contact between the second electrode layer and the channel layer.

[0030] The present application also provides an electronic device including a circuit board and a semiconductor structure as described in any of the above embodiments, wherein the semiconductor structure is electrically connected to the circuit board. The electronic device provided in the present application includes the semiconductor structure described above, and thus has all the aforementioned beneficial effects, which are not further elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] FIG1 is a schematic diagram of the architecture of an electronic device provided in an embodiment of the present application;

[0032] FIG2 is a structural diagram of a vertical transistor provided by some embodiments;

[0033] FIG3 is a structural diagram of a semiconductor structure provided in an embodiment of the present application;

[0034] FIG4 is a cross-sectional view of the semiconductor structure along section line AA in FIG3 ;

[0035] FIG5 is a structural diagram of another semiconductor structure provided in an embodiment of the present application;

[0036] FIG6 is a structural diagram of another semiconductor structure provided in an embodiment of the present application;

[0037] FIG7 is a structural diagram of another semiconductor structure provided in an embodiment of the present application;

[0038] FIG8 is a structural diagram of another semiconductor structure provided in an embodiment of the present application;

[0039] FIG9 is a cross-sectional view of the semiconductor structure along section line BB in FIG8 ;

[0040] FIG10 is a structural diagram of another semiconductor structure provided in an embodiment of the present application;

[0041] FIG11a is a structural diagram of another semiconductor structure provided in an embodiment of the present application;

[0042] FIG11b is a structural diagram of another semiconductor structure provided in an embodiment of the present application;

[0043] FIG12a is a structural diagram of another semiconductor structure provided in an embodiment of the present application;

[0044] FIG12 b is a structural diagram of another semiconductor structure provided in an embodiment of the present application;

[0045] FIG13a is a structural diagram of another semiconductor structure provided in an embodiment of the present application;

[0046] FIG13 b is a structural diagram of another semiconductor structure provided in an embodiment of the present application;

[0047] FIG14 is a cross-sectional view of the semiconductor structure along section line CC in FIG13a;

[0048] FIG15a is a structural diagram of another semiconductor structure provided in an embodiment of the present application;

[0049] FIG15 b is a structural diagram of another semiconductor structure provided in an embodiment of the present application;

[0050] FIG16 is a flowchart of a method for preparing a semiconductor structure according to an embodiment of the present application;

[0051] FIG17 is a structural diagram of a semiconductor structure fabrication method according to an embodiment of the present application after forming a first buffer layer and a second buffer layer;

[0052] FIG18 is a structural diagram after forming a first buffer layer and a second buffer layer in another method for preparing a semiconductor structure provided by an embodiment of the present application;

[0053] FIG19 is a structural diagram of forming a channel layer in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0054] FIG20 is a structural diagram of forming a channel layer in another method for preparing a semiconductor structure provided by an embodiment of the present application;

[0055] FIG21 is a structural diagram of forming a second electrode layer in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0056] FIG22 is a structural diagram of forming a second electrode layer in another method for preparing a semiconductor structure provided in an embodiment of the present application;

[0057] FIG23 is a structural diagram of forming a second electrode layer in another method for preparing a semiconductor structure provided by an embodiment of the present application;

[0058] FIG24 is a structural diagram of forming a second electrode layer in another method for preparing a semiconductor structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0059] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0060] In the following, the terms "first," "second," etc., are used for descriptive convenience only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature specified as "first," "second," etc. may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0061] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0062] When describing some embodiments, the expressions "connected," "electrically connected," and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical contact with each other, and the term "electrically connected" may be used to indicate that two or more components are in electrical contact with each other.

[0063] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0064] In the context of this application, the meanings of “on,” “above,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes “on something” with intervening features or layers, and “above” or “over” means not only “above” or “over” something, but also includes the meaning of “above” or “over” something with no intervening features or layers (i.e., directly on something).

[0065] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0066] The embodiments of the present application provide an electronic device, which may be, for example, a mobile phone, a tablet computer (pad), a personal digital assistant (PDA), a television, a smart wearable product (e.g., a smart watch, a smart bracelet), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a rechargeable small household appliance (e.g., a soymilk maker, a robot vacuum), a drone, a radar, aerospace equipment, and a vehicle-mounted device, etc., and may also be a network device such as a base station. The embodiments of the present application do not impose any special restrictions on the specific form of the electronic device.

[0067] FIG1 is a schematic diagram of the architecture of an electronic device 001 provided illustratively in an embodiment of the present application. As shown in FIG1 , the electronic device 001 includes components such as a storage device 002 and a processor 003. Those skilled in the art will appreciate that the structure of the electronic device 001 shown in FIG1 does not limit the electronic device 001. The electronic device 001 may include more or fewer components than those shown in FIG1 , or may combine certain components shown in FIG1 , or may have a different arrangement of components than shown in FIG1 .

[0068] The storage device 002 is used to store software programs and modules. The storage device 002 mainly includes a program storage area and a data storage area. The program storage area can store an operating system, applications required for at least one function (such as a sound playback function, an image playback function, etc.); the data storage area can store data created based on the use of the electronic device 001 (such as audio data, image data, a phone book, etc.). In addition, the storage device 002 includes an external memory 021 and an internal memory 022. The data stored in the external memory 021 and the internal memory 022 can be transferred to each other. The external memory 021 can include, for example, a hard disk, a USB flash drive, a floppy disk, etc. The internal memory 022 can include, for example, a random access memory, a read-only memory, etc. The random access memory can include a dynamic random access memory (DRAM), a ferroelectric random access memory (FeRAM), a phase change memory, or a magnetic memory, etc.

[0069] Processor 003 is the control center of electronic device 001. It connects the various components of electronic device 001 using various interfaces and circuits. By running or executing software programs and / or modules stored in storage device 002 and accessing data stored in storage device 002, it performs various functions of electronic device 001 and processes data, thereby monitoring electronic device 001 as a whole. Optionally, processor 003 may include one or more processing units. For example, processor 003 may include an application processor (AP), a modem processor, a graphics processing unit (GPU), etc. The different processing units may be independent devices or integrated into one or more processors 003. For example, processor 003 may integrate an application processor and a modem processor, wherein the application processor primarily processes the operating system, user interface, and application programs, while the modem processor primarily handles wireless communications. It is understood that the modem processor may not be integrated into processor 003. The application processor 003 may be, for example, a central processing unit (CPU).

[0070] The following description uses the example of internal memory 022 including a dynamic random access memory (DRAM). The DRAM may include a circuit board and a semiconductor structure, which is electrically connected to the circuit board. To further reduce the size of the memory cells in the DRAM, a vertical fielded effect transistor (VFET) is provided within the semiconductor structure. FIG2 is a structural diagram of a vertical transistor provided in some embodiments. As shown in FIG2 , the vertical transistor may include a first electrode layer 11, a gate layer 13, and a second electrode layer 12, which are stacked in sequence along a first direction X. In some embodiments, the materials of the first electrode layer 11, the gate layer 13, and the second electrode layer 12 may include metals, such as a combination of one or more conductive materials such as Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), Al (aluminum), Cu (copper), Ru (ruthenium), Ag (silver), TiN, and TiAl. The vertical transistor also includes a channel layer 20, at least a portion of which is located between the first electrode layer 11 and the second electrode layer 12, and the channel layer 20 extends through the gate layer 13 along the first direction X.

[0071] For example, the first electrode layer 11 may include a bit line (BL), which may extend along a third direction Z; the gate layer 13 may include a word line (WL), which may extend along a second direction Y. The third direction Z and the second direction Y may both intersect with the first direction X, for example, the third direction Z and the second direction Y may both be perpendicular to the first direction X; the third direction Z may intersect with the second direction Y, for example, the third direction Z may be perpendicular to the second direction Y.

[0072] Of course, in some other embodiments, the planes where the third direction Z and the second direction Y are located may also form an acute angle with the first direction X, and the value range of the acute angle may be, for example, 70°-90°.

[0073] In an embodiment of the present application, the first electrode layer 11 can also serve as the source of the transistor, and the second electrode layer 12 can also serve as the drain of the transistor; alternatively, the first electrode layer 11 can also serve as the drain of the transistor, and the second electrode layer 12 can also serve as the source of the transistor. The semiconductor structure can also include a capacitor, which can be electrically connected to the second electrode layer 12. During operation, the word line voltage on the word line can control the on and off of the transistor, and then the data information in the capacitor can be read or written to the capacitor through the bit line.

[0074] In some embodiments, the material of the channel layer 20 includes an oxide semiconductor (OS), which is an N-type channel material with good uniformity, low preparation temperature, no need for doping, high mobility, and a wide band gap. The inventors of the present application have found that when the material of the channel layer 20 includes an oxide semiconductor, due to the presence of a gap between the first electrode layer 11 and the gate layer 13, and a gap between the second electrode layer 12 and the gate layer 13, the carrier concentration in the region where the channel layer 20 is located between the first electrode layer 11 and the gate layer 13 (i.e., the extension region at 20b in FIG2 ) and the region where the channel layer 20 is located between the second electrode layer 12 and the gate layer 13 (i.e., the extension region at 20a in FIG2 ) is low, resulting in increased resistance, thereby reducing the turn-on current of the transistor structure.

[0075] Furthermore, the material of the first electrode layer 11 or the second electrode layer 12 generally includes metal. When an oxide semiconductor contacts the first electrode layer 11 or the second electrode layer 12 , a large Schottky barrier is formed, causing degradation of the transistor on-current.

[0076] FIG3 is a structural diagram of a semiconductor structure provided in an embodiment of the present application, and FIG4 is a cross-sectional view of the semiconductor structure in FIG3 taken along section line AA. In view of this, as shown in FIG3 and FIG4 , the semiconductor structure provided in an embodiment of the present application further includes a first buffer layer 30, at least a portion of which is located between the first electrode layer 11 and the channel layer 20. The first buffer layer 30 is in contact with the channel layer 20, and the concentration of N-type ions in the first buffer layer 30 is greater than the concentration of N-type ions in the channel layer 20.

[0077] Through the above-mentioned setting, the N-type ions in the first buffer layer 30 can diffuse into the channel layer 20, so that the doping concentration of the N-type ions in the channel layer 20 near the first buffer layer 30 is increased, thereby reducing the resistance of the region of the channel layer 20 located between the first electrode layer 11 and the gate layer 13, which is beneficial to increasing the turn-on current of the transistor structure.

[0078] At the same time, the N-type ions in the first buffer layer 30 diffuse into the channel layer 20, which can also form a graded junction at the contact portion of the first buffer layer 30 and the channel layer 20, avoiding the formation of a large Schottky barrier between the first buffer layer 30 and the channel layer 20, which is beneficial to reducing the contact resistance between the first buffer layer 30 and the channel layer 20, and is beneficial to increasing the turn-on current of the transistor structure.

[0079] In some embodiments, with continued reference to FIG3 , a first isolation layer 102 is further disposed between the first electrode layer 11 and the gate layer 13. A second isolation layer 103 is further disposed on the side of the gate layer 13 facing away from the first electrode layer 11. The channel layer 20 is further disposed throughout the first isolation layer 102 and the second isolation layer 103. The materials of the first isolation layer 102 and the second isolation layer 103 may include insulating materials such as silicon oxide and silicon nitride. By providing the first isolation layer 102 and the second isolation layer 103, the first electrode layer 11 and the gate layer 13 can be electrically isolated by the first isolation layer 102, and the gate layer 13 can also be electrically isolated from other film structures by the second isolation layer 103.

[0080] Continuing with reference to FIG3 , the channel layer 20 may include a first portion 21 and a second portion 22 connected to each other, wherein the first portion 21 may be disposed around the edge of the second portion 22. In some embodiments, the first portion 21 may include a first sub-portion 201 and a second sub-portion 202, wherein the second sub-portion 202 is located between the first sub-portion 201 and the second portion 22, and the second sub-portion 202 is disposed around the edge of the second portion 22, and the first sub-portion 201 is disposed around the edge of the second sub-portion 202. The first sub-portion 201 may have an annular flat plate structure, and the second sub-portion 202 may have a generally cylindrical structure, with the first sub-portion 201 being located on a side of the second sub-portion 202 that is closer to the gate layer 13.

[0081] The second portion 22 may be located on a side of the gate layer 13 close to the first electrode layer 11. The second portion 22 may include a third sub-portion 203 and a fourth sub-portion 204. The third sub-portion 203 is located between the fourth sub-portion 204 and the first portion 21. The third sub-portion 203 may be generally cylindrical in structure, and the fourth sub-portion 204 may be a flat plate. The fourth sub-portion 204 is located on a side of the third sub-portion 203 away from the gate layer 13. The second sub-portion 202 of the first portion 21, the third sub-portion 203 of the second portion 22, and the fourth sub-portion 204 of the second portion 22 may collectively define a groove.

[0082] Continuing with FIG3 , the semiconductor structure may further include an insulating layer 15. The insulating layer 15 may be located within a groove defined by the first portion 21 and the second portion 22. For example, the insulating layer 15 may be located within a groove 113 defined by the second sub-portion 202, the third sub-portion 203, and the fourth sub-portion 204. The insulating layer 15 may be made of insulating materials such as silicon dioxide and aluminum oxide.

[0083] Continuing with reference to FIG3 , the semiconductor structure may further include a gate dielectric layer 14, which may be located between the gate layer 13 and the channel layer 20, and the gate dielectric layer 14 is further disposed around the first portion 21 and the second portion 22 of the channel layer 20. Exemplarily, the gate dielectric layer 14 may be substantially cylindrical in structure, and the gate dielectric layer 14 may be disposed around the second sub-portion 202 and the third sub-portion 203. The material of the gate dielectric layer 14 may include SiO2 (silicon dioxide), Al2O3 (aluminum oxide), HfO2 (hafnium dioxide), ZrO2 (zirconium oxide), TiO2 (titanium dioxide), Y2O3 (yttrium trioxide), Si3N4 (silicon nitride), and a combination of one or more of a high dielectric constant material. Providing the gate dielectric layer 14 is beneficial for improving the problems of gate layer loss and increased leakage current.

[0084] Based on the above structure, at least a portion of the first buffer layer 30 can be located between the second portion 22 and the first electrode layer 11, and the first buffer layer 30 can contact the second portion 22. Furthermore, at least a portion of the first buffer layer 30 can be located between the fourth sub-portion 204 and the first electrode layer 11, and the first buffer layer 30 can contact the fourth sub-portion 204. Through the above arrangement, N-type ions within the first buffer layer 30 can diffuse into the second portion 22 of the channel layer 20, thereby increasing the doping concentration of N-type ions in the fourth sub-portion 204 of the second portion 22. This results in a reduction in the resistance of the region of the channel layer 20 located between the first electrode layer 11 and the gate layer 13, which is beneficial for increasing the turn-on current of the transistor structure.

[0085] In some embodiments, the concentration of N-type ions in the first buffer layer 30 ranges from 1e 18 -1e 21 For example, the concentration of N-type ions in the first buffer layer 30 may be 1e 18 、1e 19 、1e 20 or 1e 21 Through the above-mentioned configuration, the concentration of N-type ions in the first buffer layer 30 is greater than the concentration of N-type ions in the channel layer 20, so that the N-type ions in the first buffer layer 30 can diffuse into the channel layer 20, thereby increasing the doping concentration of N-type ions in the second portion 22. This results in a decrease in the resistance of the region of the channel layer 20 located between the first electrode layer 11 and the gate layer 13, which is beneficial for increasing the turn-on current of the transistor structure. At the same time, the contact portion between the first buffer layer 30 and the channel layer 20 can also form a graded junction, avoiding the formation of a large Schottky barrier between the first buffer layer 30 and the channel layer 20, which is beneficial for increasing the turn-on current of the transistor structure.

[0086] In some embodiments, the orthographic projection of the first buffer layer 30 on the first electrode layer 11 may be located within the first electrode layer 11. Here, it can be understood that the orthographic projection of the first buffer layer 30 on the first electrode layer 11 coincides with the first electrode layer 11, or the orthographic projection of the first buffer layer 30 on the first electrode layer 11 is located within the edge of the first electrode layer 11.

[0087] As shown in Figure 3, the orthographic projection of the first buffer layer 30 on the first electrode layer 11 can overlap with the first electrode layer 11. During the preparation of the first buffer layer 30 and the first electrode layer 11, after the first electrode layer 11 and the first buffer layer 30 are formed, the first electrode layer 11 and the first buffer layer 30 can be patterned simultaneously to ensure that the pattern shapes of the first buffer layer 30 and the first electrode layer 11 are the same. This arrangement helps improve the preparation efficiency of the first buffer layer 30 and the first electrode layer 11.

[0088] Figure 5 is a structural diagram of another semiconductor structure provided by an embodiment of the present application. As shown in Figure 5, the orthographic projection of the first buffer layer 30 on the first electrode layer 11 can be located within the edge of the first electrode layer 11. In other words, the orthographic projection area of ​​the first buffer layer 30 on the first electrode layer 11 can be smaller than the area of ​​the first electrode layer 11. This arrangement helps reduce the area occupied by the first buffer layer 30, thereby reducing the material used in the first buffer layer 30.

[0089] Continuing with FIG5 , the first electrode layer 11 may have a groove 113 on a side adjacent to the channel layer 20, and the first buffer layer 30 may be located within the groove 113. For example, the groove 113 may be a substantially rectangular groove 113, and the extending direction of the rectangular groove 113 may be the same as the extending direction of the first electrode layer 11, that is, the extending direction of the rectangular groove 113 is parallel to the third direction Z. This configuration facilitates reducing the size of the semiconductor structure along the first direction X, thereby further facilitating miniaturization of the memory device.

[0090] 3 and 5 , the first buffer layer 30 may include a first sublayer 31 and a second sublayer 32 that are stacked. At least a portion of the first sublayer 31 may be located between the second sublayer 32 and the channel layer 20, and the second sublayer 32 and the channel layer 20 may respectively contact the first sublayer 31. The concentration of N-type ions in the second sublayer 32 may be greater than the concentration of N-type ions in the first sublayer 31, and the concentration of N-type ions in the first sublayer 31 may be greater than the concentration of N-type ions in the channel layer 20.

[0091] Through the above-mentioned setting, the N-type ions in the second sublayer 32 diffuse into the first sublayer 31, and the N-type ions in the first sublayer 31 diffuse into the channel layer 20, so that the concentration of N-type ions in the second sublayer 32, the first sublayer 31 and the channel layer 20 gradually decreases in the direction close to the gate layer 13, which is beneficial to further reduce the Schottky barrier between the first buffer layer 30 and the channel layer 20, forming a better ohmic contact, and further beneficial to improving the turn-on current of the semiconductor structure.

[0092] The material of the second sublayer 32 may include at least one of InSnO, F:SnO (fluorinated tin oxide), AlZnO, AlSnO, In2O3, InGaZnO, InZnO, InZnSnO, H:a-Si (hydrogenated amorphous silicon), or D:a-Si (deuterated amorphous silicon). Through the above configuration, the concentration of N-type ions in the second sublayer 32 is greater than the concentration of N-type ions in the first sublayer 31. The N-type ions in the second sublayer 32 can diffuse into the first sublayer 31, forming a graded junction at the contact portion between the first sublayer 31 and the second sublayer 32. This prevents the formation of a large Schottky barrier between the first sublayer 31 and the second sublayer 32, thereby reducing the contact resistance between the first sublayer 31 and the second sublayer 32.

[0093] Among them, the material of the first sublayer 31 may include IZO and / or IGO. Here, "and / or" can be understood as that the material of the first sublayer 31 includes one of IZO and IGO, or that the material of the first sublayer 31 includes IZO and IGO. Through the above-mentioned arrangement, the concentration of N-type ions in the first sublayer 31 is greater than the concentration of N-type ions in the channel layer 20. The N-type ions in the first sublayer 31 can diffuse into the channel layer 20, so that the contact portion of the first sublayer 31 and the channel layer 20 forms a graded junction, avoiding the formation of a large Schottky barrier between the first sublayer 31 and the channel layer 20, which is beneficial to reducing the contact resistance between the first sublayer 31 and the channel layer 20.

[0094] Since the film structure needs to be heated during the process of forming the first buffer layer 30, when the material of the first electrode layer 11 includes metal, the metal in the first electrode layer 11 is easily partially oxidized during the process of forming the first buffer layer 30, thereby increasing the contact resistance between the first buffer layer 30 and the first electrode layer 11 and reducing the turn-on current of the semiconductor structure.

[0095] Of course, in some embodiments, the first buffer layer 30 may also be a single film layer structure. For example, the first buffer layer 30 may only include the first sublayer 31 , or the first buffer layer 30 may only include the second sublayer 32 .

[0096] Figure 6 is a structural diagram of another semiconductor structure provided in an embodiment of the present application; Figure 7 is a structural diagram of another semiconductor structure provided in an embodiment of the present application. As shown in Figures 6 and 7, the semiconductor structure may further include a second buffer layer 40. The second buffer layer 40 may be located between the first buffer layer 30 and the first electrode layer 11, and the first buffer layer 30 and the first electrode layer 11 may respectively contact the second buffer layer 40.

[0097] The material of the second buffer layer 40 may include at least one of a metal and a conductive metal oxide. By disposing the second buffer layer 40 between the first buffer layer 30 and the first electrode layer 11, when the first buffer layer 30 is formed on the second buffer layer 40, the metal in the second buffer layer 40 is partially oxidized. Because the metal oxide in the second buffer layer 40 is conductive, an increase in the contact resistance between the first buffer layer 30 and the second buffer layer 40 is avoided, thereby facilitating an increase in the turn-on current of the semiconductor structure.

[0098] In some embodiments, the material of the second buffer layer 40 may include Ru (ruthenium). Of course, the material of the second buffer layer 40 may also include other metals, as long as the metal oxide thereof has conductivity, which is not specifically limited in the present embodiment.

[0099] As shown in Figure 6, in some examples, the orthographic projection of the second buffer layer 40 on the first electrode layer 11 and the orthographic projection of the first buffer layer 30 on the first electrode layer 11 can both overlap with the first electrode layer 11. As described in the above embodiment, the second buffer layer 40, the first buffer layer 30, and the first electrode layer 11 can be patterned simultaneously so that the patterns of the second buffer layer 40, the first buffer layer 30, and the first electrode layer 11 have the same shape. This arrangement helps improve the production efficiency of the second buffer layer 40, the first buffer layer 30, and the first electrode layer 11.

[0100] As shown in FIG7 , in some other examples, the orthographic projection of the second buffer layer 40 on the first electrode layer 11 may also be located within the edge of the first electrode layer 11. For example, in an embodiment where a groove 113 is provided on a side of the first electrode layer 11 close to the channel layer 20, both the second buffer layer 40 and the first buffer layer 30 may be located within the groove 113. This arrangement facilitates further reducing the size of the semiconductor structure along the first direction X, thereby further facilitating the miniaturization of memory devices.

[0101] Continuing with reference to Figures 3, 5, 6, and 7, the semiconductor structure may further include a third buffer layer 50. The third buffer layer 50 may be located between the first portion 21 and the second electrode layer 12, and the third buffer layer 50 may contact the first portion 21. The concentration of N-type ions in the third buffer layer 50 is greater than the concentration of N-type ions in the channel layer 20. Through the above configuration, the N-type ions in the third buffer layer 50 may diffuse into the first portion 21 of the channel layer 20, thereby increasing the doping concentration of N-type ions in the first portion 21 near the third buffer layer 50. This results in a reduction in the resistance of the region of the channel layer 20 located between the second electrode layer 12 and the gate layer 13, which is beneficial for further increasing the turn-on current of the transistor structure. Of course, in some embodiments, the semiconductor structure may further include the third buffer layer 50 and omit the first buffer layer 30.

[0102] In some embodiments, the concentration of N-type ions in the third buffer layer 50 ranges from 1e 18 -1e 21 For example, the concentration of N-type ions in the third buffer layer 50 may be 1e 18 、1e 19 、1e 20 or 1e 21 Through the above arrangement, the concentration of N-type ions in the third buffer layer 50 is greater than the concentration of N-type ions in the channel layer 20, so that the N-type ions in the third buffer layer 50 can diffuse into the channel layer 20, thereby increasing the doping concentration of N-type ions in the first portion 21, resulting in a decrease in the resistance of the region of the channel layer 20 located between the second electrode layer 12 and the gate layer 13, which is beneficial to increasing the turn-on current of the transistor structure.

[0103] Continuing with Figures 6 and 7, at least a portion of the third buffer layer 50 is located between the first sub-portion 201 and the second electrode layer 12, and the third buffer layer 50 may contact the first sub-portion 201. For example, the third buffer layer 50 and the second electrode layer 12 may be located on a side of the first sub-portion 201 away from the second sub-portion 202, with the edges of the orthographic projection of the first sub-portion 201 on the second electrode layer 12 and the edges of the orthographic projection of the third buffer layer 50 on the second electrode layer 12 respectively coinciding with the edges of the second electrode layer 12. During the fabrication of the semiconductor structure, after forming the first sub-portion 201, the second electrode layer 12, and the third buffer layer 50, they may be patterned simultaneously to ensure that the patterns of the first sub-portion 201, the third buffer layer 50, and the second electrode layer 12 have the same shape. This arrangement facilitates improved fabrication efficiency of the third buffer layer 50 and the second electrode layer 12.

[0104] Continuing with reference to Figures 6 and 7, in some embodiments, at least a portion of the third buffer layer 50 can be located between the first sub-portion 201 and the second electrode layer 12, and the third buffer layer 50 is in contact with the first sub-portion 201. For example, the insulating layer 15 can completely fill the groove enclosed by the channel layer 20, and a portion of the third buffer layer 50 is also located between the insulating layer 15 and the second electrode layer 12, and the surface of the third buffer layer 50 facing away from the first sub-portion 201 and the surface of the third buffer layer 50 facing away from the insulating layer 15 are located in the same plane. Through the above arrangement, N-type ions in the third buffer layer 50 can diffuse into the first sub-portion 201 of the first portion 21, thereby increasing the doping concentration of N-type ions in the first sub-portion 201 near the third buffer layer 50, resulting in a reduction in the resistance of the region of the channel layer 20 located between the second electrode layer 12 and the gate layer 13, which is beneficial for further increasing the turn-on current of the transistor structure.

[0105] At the same time, by providing the first buffer layer 30 and the third buffer layer 50 , it is beneficial to achieve electrical symmetry between the upper and lower electrodes of the semiconductor structure.

[0106] In some embodiments, the positions of the first electrode layer 11 and the second electrode layer 12 can be interchanged. Accordingly, the positions of the first buffer layer 30 and the third buffer layer 50 can be interchanged.

[0107] 8 is a structural diagram of another semiconductor structure provided in an embodiment of the present application; FIG9 is a cross-sectional view of the semiconductor structure in FIG8 along the BB section line; and FIG10 is a structural diagram of another semiconductor structure provided in an embodiment of the present application.

[0108] As shown in Figures 8 and 10, in some other embodiments, the first portion 21 may omit the first sub-portion 201. The third buffer layer 50 and the second electrode layer 12 may be located within a groove enclosed by the first portion 21 and the insulating layer 15. For ease of description, the groove enclosed by the first portion 21 and the insulating layer 15 will be referred to as the first groove 151. For example, the first groove 151 may be formed by the second sub-portion 202 of the first portion 21 and the insulating layer 15. The third buffer layer 50 covers the walls and bottom of the first groove 151, and the second electrode layer 12 is located within the groove enclosed by the third buffer layer 50. This arrangement facilitates reducing the size of the semiconductor structure along the first direction X, thereby facilitating memory device miniaturization. Furthermore, the third buffer layer 50 covering the walls and bottom of the first groove 151 also increases the contact area between the third buffer layer 50 and the channel layer 20, facilitating diffusion of N-type ions within the third buffer layer 50 into the channel layer 20.

[0109] 6 to 10 , the third buffer layer 50 may include a third sublayer 51 and a fourth sublayer 52, which are stacked. At least a portion of the third sublayer 51 is located between the fourth sublayer 52 and the channel layer 20, and the fourth sublayer 52 and the channel layer 20 are respectively in contact with the third sublayer 51. The concentration of N-type ions in the fourth sublayer 52 is greater than the concentration of N-type ions in the third sublayer 51, and the concentration of N-type ions in the third sublayer 51 is greater than the concentration of N-type ions in the channel layer 20.

[0110] Through the above-mentioned setting, the N-type ions in the fourth sublayer 52 diffuse into the third sublayer 51, and the N-type ions in the third sublayer 51 diffuse into the channel layer 20, so that the concentration of N-type ions in the third sublayer 51, the fourth sublayer 52 and the channel layer 20 gradually decreases in the direction close to the gate layer 13, which is beneficial to further reduce the Schottky barrier between the second buffer layer 40 and the channel layer 20, forming a better ohmic contact, and further beneficial to improving the turn-on current of the semiconductor structure.

[0111] The material of the fourth sublayer 52 may include at least one of InSnO, F:SnO, AlZnO, AlSnO, N+In2O3, N+InGaZnO, n+InZnO, N+InZnSnO, H:a-Si, or D:a-Si. Through the above configuration, the concentration of N-type ions in the fourth sublayer 52 is greater than the concentration of N-type ions in the third sublayer 51. The N-type ions in the fourth sublayer 52 can diffuse into the third sublayer 51, forming a graded junction at the contact portion between the fourth sublayer 52 and the third sublayer 51. This prevents the formation of a large Schottky barrier between the fourth sublayer 52 and the third sublayer 51, thereby reducing the contact resistance between the fourth sublayer 52 and the third sublayer 51.

[0112] The material of the third sublayer 51 may include IZO and / or IGO. Through the above configuration, the concentration of N-type ions in the third sublayer 51 is greater than the concentration of N-type ions in the channel layer 20. The N-type ions in the third sublayer 51 can diffuse into the channel layer 20, forming a graded junction at the contact portion between the third sublayer 51 and the channel layer 20. This prevents the formation of a large Schottky barrier between the third sublayer 51 and the channel layer 20, thereby reducing the contact resistance between the third sublayer 51 and the channel layer 20.

[0113] Of course, in some embodiments, the third buffer layer 50 may also be a single film layer structure. For example, the third buffer layer 50 may only include the third sublayer 51 , or the third buffer layer 50 may only include the fourth sublayer 52 .

[0114] 6 and 7 , in some embodiments, at least a portion of the third buffer layer 50 may be located between the first sub-portion 201 and the second electrode layer 12, and the insulating layer 15 may fill the groove defined by the channel layer 20. For example, a portion of the third sub-layer 51 may be located between the first sub-portion 201 and the second electrode layer 12, and a portion of the third sub-layer 51 may also be located between the insulating layer 15 and the second electrode layer 12, with the surface of the third sub-layer 51 facing away from the first sub-portion 201 and the surface of the third sub-layer 51 facing away from the insulating layer 15 coplanar. The fourth sub-layer 52 is located between the third sub-layer 51 and the second electrode layer 12, and the surface of the fourth sub-layer 52 facing away from the first sub-portion 201 and the surface of the fourth sub-layer 52 facing away from the insulating layer 15 coplanar.

[0115] 8 and 10 , in some other embodiments, the third sublayer 51 may cover the walls and bottom of the first groove 151, the fourth sublayer 52 may cover the walls and bottom of the groove enclosed by the third sublayer 51, and the second electrode layer 12 may be located within the groove enclosed by the fourth sublayer 52. The above configuration is advantageous in increasing the contact area between the third sublayer 51 and the channel layer 20, and the contact area between the fourth sublayer 52 and the third sublayer 51, thereby facilitating the diffusion of N-type ions in the fourth sublayer 52 into the third sublayer 51, and the diffusion of N-type ions in the third sublayer 51 into the channel layer 20.

[0116] FIG11 a is a structural diagram of another semiconductor structure provided in an embodiment of the present application; FIG11 b is a structural diagram of another semiconductor structure provided in an embodiment of the present application.

[0117] 11a and 11b , the semiconductor structure may further include a fourth buffer layer 60. The fourth buffer layer 60 may be located between the third buffer layer 50 and the second electrode layer 12, with the third buffer layer 50 and the second electrode layer 12 respectively contacting the fourth buffer layer 60. The material of the fourth buffer layer 60 includes at least one of a metal and a conductive metal oxide. As described in the above embodiment, by disposing the fourth buffer layer 60 between the third buffer layer 50 and the second electrode layer 12, when the third buffer layer 50 is formed on the fourth buffer layer 60, the metal in the fourth buffer layer 60 is partially oxidized. Since the metal oxide in the fourth buffer layer 60 is conductive, an increase in the contact resistance between the fourth buffer layer 60 and the third buffer layer 50 is avoided, thereby facilitating an increase in the turn-on current of the semiconductor structure.

[0118] Continuing with reference to Figures 11a and 11b, in an embodiment in which at least a portion of the third buffer layer 50 can be located between the first sub-portion 201 and the second electrode layer 12, the surface of the fourth buffer layer 60 facing away from the first sub-portion 201 and the surface of the fourth buffer layer 60 facing away from the insulating layer 15 are located in the same plane.

[0119] For example, the edges of the orthographic projection of the first sub-portion 201 on the second electrode layer 12, the edges of the orthographic projection of the third buffer layer 50 on the second electrode layer 12, and the edges of the orthographic projection of the fourth buffer layer 60 on the second electrode layer 12 respectively coincide with the edges of the second electrode layer 12. As described in the above embodiment, the first sub-portion 201, the fourth buffer layer 60, the third buffer layer 50, and the second electrode layer 12 can be patterned simultaneously so that the patterns of the first sub-portion 201, the fourth buffer layer 60, the third buffer layer 50, and the second electrode layer 12 have the same shape. This arrangement helps improve the production efficiency of the fourth buffer layer 60, the third buffer layer 50, and the second electrode layer 12.

[0120] Figure 12a is a structural diagram of another semiconductor structure provided in an embodiment of the present application; Figure 12b is a structural diagram of another semiconductor structure provided in an embodiment of the present application. In some embodiments, as shown in Figures 12a and 12b, in the above two embodiments, the positions of the first electrode layer 11 and the second electrode layer 12 can be interchanged. Correspondingly, the positions of the first buffer layer 30 and the third buffer layer 50 can be interchanged, wherein the positions of the second buffer layer 40 and the fourth buffer layer 60 can be interchanged. Figure 13a is a structural diagram of another semiconductor structure provided in an embodiment of the present application; Figure 13b is a structural diagram of another semiconductor structure provided in an embodiment of the present application; and Figure 14 is a cross-sectional view of the semiconductor structure in Figure 13a along the CC section line. Referring to Figures 13a, 13b, and 14, in an embodiment in which the third buffer layer 50 is located in the first groove 151, the fourth buffer layer 60 can be located within the groove enclosed by the fourth sublayer 52. This arrangement helps to increase the contact area between the fourth sublayer 52 and the fourth buffer layer 60, thereby preventing oxidation of the metal within the fourth buffer layer 60.

[0121] For example, the fourth buffer layer 60, the third buffer layer 50, and the second electrode layer 12 can all be located within a groove enclosed by the first portion 21 and the insulating layer 15. For example, the third buffer layer 50 covers the walls and bottom of the first groove 151, the fourth buffer layer 60 covers the walls and bottom of the groove enclosed by the third buffer layer 50, and the second electrode layer 12 is located within the groove enclosed by the fourth buffer layer 60. This arrangement facilitates reducing the size of the semiconductor structure along the first direction X, thereby facilitating memory device miniaturization.

[0122] In some embodiments, the material of the fourth buffer layer 60 may include at least one of Ru (ruthenium) and RuO2 (ruthenium oxide). Of course, the material of the fourth buffer layer 60 may also include other metals, as long as the metal oxide thereof is conductive, and this embodiment of the present application does not specifically limit this.

[0123] Figure 15a is a structural diagram of another semiconductor structure provided in an embodiment of the present application; Figure 15b is a structural diagram of another semiconductor structure provided in an embodiment of the present application. In some embodiments, as shown in Figures 15a and 15b, the positions of the first electrode layer 11 and the second electrode layer 12 can be interchanged. Correspondingly, the positions of the first buffer layer 30 and the third buffer layer 50 can be interchanged, and the positions of the second buffer layer 40 and the fourth buffer layer 60 can be interchanged. An embodiment of the present application also provides a method for preparing a semiconductor structure for preparing the semiconductor structure in any of the above embodiments. Figure 16 is a flow chart of the steps of a method for preparing a semiconductor structure exemplarily provided in an embodiment of the present application. In conjunction with Figure 16, the preparation method includes steps S101-S103:

[0124] S101 , forming a first electrode layer, a first buffer layer, and a gate layer stacked in sequence along a first direction.

[0125] FIG17 is a structural diagram of a method for preparing a semiconductor structure provided in an embodiment of the present application after forming a first buffer layer 30 and a second buffer layer 40 .

[0126] Figure (a) in Figure 17 is a structural diagram after providing a substrate 101. In an embodiment of the present application, as shown in Figure (a) in Figure 17, the step of forming a first electrode layer 11, a first buffer layer 30 and a gate layer 13 stacked in sequence along a first direction X may include: providing a substrate 101. The present application does not specifically limit the material of the provided substrate 101. Among them, the substrate 101 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI) and / or any other suitable material. In some examples, the substrate 101 includes silicon, for example: single crystal silicon, polycrystalline silicon.

[0127] FIG17(b) shows a structure diagram after forming the first electrode layer 11, the second buffer layer 40, and the first buffer layer 30. As shown in FIG17(b), after providing a substrate 101, a first electrode layer 11 and a first buffer layer 30 can be formed on the substrate 101 in a stacked arrangement. The first electrode layer 11 can be located between the substrate 101 and the first buffer layer 30. The first electrode layer 11 and the first buffer layer 30 can be formed by a deposition process. In some embodiments, the first buffer layer 30 can include a first sublayer 31 and a second sublayer 32, and the first sublayer 31 can be located between the second sublayer 32 and the channel layer 20.

[0128] After forming the first electrode layer 11 and the first buffer layer 30, the first electrode layer 11 and the first buffer layer 30 can be patterned simultaneously. The patterning process can include exposure, development, etching, and other processes. Through the above arrangement, the first electrode layer 11 and the first buffer layer 30 have the same shape.

[0129] In some embodiments, after forming the first electrode layer 11 and before forming the first buffer layer 30, a second buffer layer 40 may be formed. Accordingly, the step of simultaneously patterning the first electrode layer 11 and the first buffer layer 30 may further include: simultaneously patterning the first electrode layer 11, the second buffer layer 40, and the first buffer layer 30. Through the above arrangement, the shapes of the first electrode layer 11, the second buffer layer 40, and the first buffer layer 30 are the same. By arranging the second buffer layer 40 between the first buffer layer 30 and the first electrode layer 11, when the first buffer layer 30 is formed on the second buffer layer 40, the metal in the second buffer layer 40 is partially oxidized. Since the metal oxide in the second buffer layer 40 is conductive, the contact resistance between the first buffer layer 30 and the second buffer layer 40 is avoided from increasing, which is conducive to increasing the turn-on current of the semiconductor structure.

[0130] After the first electrode layer 11, the second buffer layer 40, and the first buffer layer 30 are simultaneously patterned, a first isolation layer 102, a gate layer 13, and a second isolation layer 103 are sequentially stacked on the side of the first buffer layer 30 facing away from the first electrode layer 11. The materials of the first isolation layer 102 and the second isolation layer 103 are not further described herein.

[0131] Figure 18 is a structural diagram after forming the first buffer layer 30 and the second buffer layer 40 in another method for preparing a semiconductor structure provided by an embodiment of the present application. Figure (a) in Figure 18 is a structural diagram after forming the first electrode layer 11. In some other embodiments, as shown in Figure (a) in Figure 18, the step of forming the first electrode layer 11, the first buffer layer 30 and the gate layer 13 stacked in sequence along the first direction X may include: after forming the first electrode layer 11, patterning the first electrode layer 11 to form a groove 113. As described in the above embodiment, the groove 113 can be roughly a rectangular groove 113, and the extension direction of the rectangular groove 113 can be the same as the extension direction of the first electrode layer 11.

[0132] FIG18(b) is a structural diagram after the first electrode layer 11 is formed. As shown in FIG18(b), after the groove 113 is formed, a first buffer layer 30 can be formed in the groove 113. As described in the above embodiment, the first buffer layer 30 may include a first sublayer 31 and a second sublayer 32, and the first sublayer 31 may be located between the second sublayer 32 and the channel layer 20. After the first buffer layer 30 is formed, the semiconductor structure may be planarized using a chemical mechanical planarization (CMP) process so that the surfaces of the first buffer layer 30 and the first electrode layer 11 are located in the same plane. The above arrangement is conducive to reducing the size of the semiconductor structure along the first direction X, thereby facilitating the miniaturization of the memory.

[0133] In some embodiments, after forming the first electrode layer 11 and before forming the first buffer layer 30 in the groove 113, a second buffer layer 40 may be formed. Accordingly, the second buffer layer 40 is formed in the groove 113, wherein the material of the second buffer layer 40 includes at least one of a metal and a conductive metal oxide. By providing the second buffer layer 40 between the first buffer layer 30 and the first electrode layer 11, when the first buffer layer 30 is formed on the second buffer layer 40, the metal in the second buffer layer 40 is partially oxidized. Since the metal oxide in the second buffer layer 40 is conductive, the contact resistance between the first buffer layer 30 and the second buffer layer 40 is prevented from increasing, thereby facilitating an increase in the turn-on current of the semiconductor structure.

[0134] After forming the first buffer layer 30 in the groove 113, a first isolation layer 102, a gate layer 13, and a second isolation layer 103 may be sequentially stacked on the side of the first buffer layer 30 away from the first electrode layer 11. The materials of the first isolation layer 102 and the second isolation layer 103 are not described in detail herein.

[0135] In the embodiment of the present application, after forming the second isolation layer 103 , the method for preparing the semiconductor structure further includes step S102 .

[0136] S102 , forming a channel layer, wherein the channel layer penetrates the gate layer along a first direction, wherein a first buffer layer contacts the channel layer, and a concentration of N-type ions in the first buffer layer is greater than a concentration of N-type ions in the channel layer.

[0137] Figure 19 is a structural diagram of forming a channel layer 20 in a method for preparing a semiconductor structure provided in an embodiment of the present application; Figure 20 is a structural diagram of forming a channel layer 20 in another method for preparing a semiconductor structure provided in an embodiment of the present application.

[0138] FIG19(a) shows the structure after the first channel hole 106 is formed. FIG20(a) shows the structure after the first channel hole 106 is formed. As shown in FIG19(a) and FIG20(a), in the embodiment of the present application, after the first isolation layer 102, the gate layer 13, and the second isolation layer 103 are sequentially stacked on the side of the first buffer layer 30 facing away from the first electrode layer 11, the first channel hole 106 can be formed to penetrate the second isolation layer 103 and the gate layer 13. In some embodiments, the first channel hole 106 can also penetrate a portion of the first isolation layer 102.

[0139] FIG19(b) shows the structure after the gate dielectric layer 14 and the sacrificial layer 205 are formed. FIG20(b) shows the structure after the gate dielectric layer 14 and the sacrificial layer 205 are formed. As shown in FIG19(b) and FIG20(b), after the first channel hole 106 is formed, the gate dielectric layer 14 and the sacrificial layer 205 can be formed in sequence. The gate dielectric layer 14 and the sacrificial layer 205 can cover the hole wall and the hole bottom of the first channel hole 106. The gate dielectric layer 14 and the sacrificial layer 205 are also located on the side of the second isolation layer 103 facing away from the gate layer 13. For example, a gate dielectric material can be deposited on the first channel hole 106 and the second isolation layer 103 to form the gate dielectric layer 14. After the gate dielectric layer 14 is formed, a sacrificial material can be deposited on the gate dielectric material to form the sacrificial layer 205. The material of the sacrificial layer 205 may include insulating materials such as silicon oxide and silicon nitride.

[0140] FIG19(c) illustrates the structure after the second channel hole 108 is formed. FIG20(c) illustrates the structure after the second channel hole 108 is formed. As shown in FIG19(c) and FIG20(c), after forming the sacrificial layer 205, a second channel hole 108 can be formed that penetrates the sacrificial layer 205 and the first isolation layer 102. The second channel hole 108 extends through the first buffer layer 30. For example, the second channel hole 108 can be connected to the first channel hole 106, and the second channel hole 108 is located on the side of the first channel hole 106 closer to the substrate 101. The second channel hole 108 can sequentially penetrate the sacrificial layer 205, the gate dielectric layer 14, and the first isolation layer 102 along the first direction X. In some embodiments, the second channel hole 108 can also partially penetrate the first buffer layer 30. Through the above arrangement, the sacrificial layer 205 helps protect the gate dielectric layer 14 during the formation of the second channel layer 20.

[0141] FIG19(d) shows the structure after the sacrificial layer 205 is removed. FIG20(d) shows the structure after the sacrificial layer 205 is removed. As shown in FIG19(d) and FIG20(d), after the second channel hole 108 is formed, the sacrificial layer 205 can be removed to prevent the sacrificial layer 205 from affecting subsequent fabrication processes.

[0142] FIG19(e) shows the structure after the channel layer 20 is formed. FIG20(e) shows the structure after the channel layer 20 is formed. As shown in FIG19(e) and FIG20(e), after the sacrificial layer 205 is removed, the channel layer 20 can be formed. The first portion 21 covers the hole wall and bottom of the first channel hole 106. The first portion 21 is also located on the side of the second isolation layer 103 away from the gate layer 13. The second portion 22 covers the hole wall and bottom of the second channel hole 108.

[0143] For example, channel material can be deposited within the first channel hole 106, within the second channel hole 108, and on the side of the second isolation layer 103 facing away from the gate layer 13. The channel material covering one side of the second isolation layer 103 constitutes a first sub-portion 201, and the channel material covering the hole wall and bottom of the first channel hole 106 constitutes a second sub-portion 202. The first sub-portion 201 and the second sub-portion 202 together constitute a first portion 21. The channel material covering the hole wall of the second channel hole 108 constitutes a third sub-portion 203, and the channel material covering the hole bottom of the second channel hole 108 constitutes a fourth sub-portion 204. The third sub-portion 203 and the fourth sub-portion 204 together constitute a second portion 22. The first portion 21 and the second portion 22 together constitute a channel layer 20.

[0144] In summary, in the embodiment where the first buffer layer 30 includes the first sublayer 31 and the second sublayer 32, the concentration of N-type ions in the second sublayer 32 can be greater than the concentration of N-type ions in the first sublayer 31, and the concentration of N-type ions in the first sublayer 31 can be greater than the concentration of N-type ions in the channel layer 20. Through the above arrangement, the N-type ions in the second sublayer 32 diffuse into the first sublayer 31, and the N-type ions in the first sublayer 31 diffuse into the channel layer 20, so that the concentration of N-type ions in the second sublayer 32, the first sublayer 31, and the channel layer 20 gradually decreases in the direction approaching the gate layer 13, which is beneficial for further reducing the Schottky barrier between the first buffer layer 30 and the channel layer 20, forming a better ohmic contact, and further facilitating an increase in the turn-on current of the semiconductor structure.

[0145] In the embodiment of the present application, after forming the channel layer 20 , the method for preparing the semiconductor structure may further include step S103 .

[0146] S103 , forming a second electrode layer on a side of the channel layer away from the first electrode layer.

[0147] Figure 21 is a structural diagram of forming the second electrode layer 12 in a method for preparing a semiconductor structure provided in an embodiment of the present application; Figure 22 is a structural diagram of forming the second electrode layer 12 in another method for preparing a semiconductor structure provided in an embodiment of the present application.

[0148] FIG21(a) is a structural diagram after the insulating layer 15 is formed. FIG22(a) is a structural diagram after the insulating layer 15 is formed. As shown in FIG21(a) and FIG22(a), and in combination with FIG20(e), after the channel layer 20 is formed, the first channel hole 106 and the second channel hole 108 can be filled with an insulating material to form the insulating layer 15. The insulating layer 15 and the first portion 21 enclose a first groove 151. Exemplarily, the insulating material can be filled into the second channel hole 108 and a portion of the first channel hole 106 to form the insulating layer 15. The surface of the insulating layer 15 facing away from the first electrode layer 11 and the hole wall of the first channel hole 106 together constitute the first groove 151.

[0149] FIG21(b) shows the structure after forming the third buffer layer 50, the fourth buffer layer 60, and the second electrode layer 12. FIG22(b) shows the structure after forming the third buffer layer 50, the fourth buffer layer 60, and the second electrode layer 12. As shown in FIG21(b) and FIG22(b), after forming the insulating layer 15, a third buffer layer 50 can be formed in the first groove 151. The third buffer layer 50 contacts the first portion 21, and the concentration of N-type ions in the third buffer layer 50 is greater than the concentration of N-type ions in the channel layer 20. For example, the third buffer layer 50 can cover the groove wall and groove bottom of the first groove 151. The third buffer layer 50 can also cover the side of the first sub-portion 201 facing away from the gate layer 13, so that the third buffer layer 50 can contact the first sub-portion 201 and the second sub-portion 202 of the first portion 21.

[0150] As described in the above embodiment, the third buffer layer 50 may include a third sublayer 51 and a fourth sublayer 52 that are stacked, with at least a portion of the third sublayer 51 located between the fourth sublayer 52 and the channel layer 20, and the fourth sublayer 52 and the channel layer 20 respectively contacting the third sublayer 51. The concentration of N-type ions in the fourth sublayer 52 is greater than the concentration of N-type ions in the third sublayer 51, and the concentration of N-type ions in the third sublayer 51 is greater than the concentration of N-type ions in the channel layer 20.

[0151] After forming the third buffer layer 50, a fourth buffer layer 60 may be formed within the first recess 151. The material of the fourth buffer layer 60 includes at least one of a metal and a conductive metal oxide. The fourth buffer layer 60 may be located within the first recess 151 and cover the walls and bottom of the recess defined by the third buffer layer 50. The fourth buffer layer 60 may also cover the side of the third buffer layer 50 facing away from the gate layer 13.

[0152] After the fourth buffer layer 60 is formed, the second electrode layer 12 can be formed in the first groove 151. For example, the second electrode layer 12 can be located in the first groove 151 and cover the groove wall and groove bottom enclosed by the fourth buffer layer 60. The second electrode layer 12 can also cover the side of the fourth buffer layer 60 away from the gate layer 13. The above arrangement is conducive to reducing the size of the semiconductor structure along the first direction X, thereby facilitating the miniaturization of the memory. By arranging the fourth buffer layer 60 between the third buffer layer 50 and the second electrode layer 12, when the third buffer layer 50 is formed on the fourth buffer layer 60, the metal in the fourth buffer layer 60 is partially oxidized. Since the metal oxide in the fourth buffer layer 60 is conductive, the contact resistance between the fourth buffer layer 60 and the third buffer layer 50 is avoided from increasing, thereby facilitating increasing the turn-on current of the semiconductor structure.

[0153] FIG21(c) is a structural diagram after the semiconductor structure is planarized. FIG22(c) is a structural diagram after the semiconductor structure is planarized. As shown in FIG21(c) and FIG22(c), after the second electrode layer 12 is formed, a chemical mechanical polishing process can be used to planarize the semiconductor structure to remove the second electrode layer 12, the fourth buffer layer 60, the third buffer layer 50, and the first sub-portion 201 of the first portion 21 located on the side of the second isolation layer 103 away from the gate layer 13. After the semiconductor structure is planarized, an isolation material can be further deposited on the side of the second isolation layer 103 away from the gate layer 13, wherein the isolation material can include one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride.

[0154] Figure 23 is a structural diagram of forming the second electrode layer 12 in another method for preparing a semiconductor structure provided in an embodiment of the present application; Figure 24 is a structural diagram of forming the second electrode layer 12 in another method for preparing a semiconductor structure provided in an embodiment of the present application.

[0155] FIG23(a) shows the structure after the insulating layer 15 is formed. FIG24(a) shows the structure after the insulating layer 15 is formed. As shown in FIG23(a) and FIG24(a), in conjunction with FIG20(e), in some other embodiments, after forming the channel layer 20, an insulating material may be deposited. The insulating material is deposited within the first channel hole 106 and the second channel hole 108, and the insulating material may also be deposited on one side of the second isolation layer. After depositing the insulating material, the insulating material covering one side of the second isolation layer may be removed, while the insulating material within the first channel hole 106 and the second channel hole 108 remains to form the insulating layer 15. Due to process limitations, the top surface of the insulating layer 15 may be recessed toward the first electrode layer 11. The insulating layer 15 may fill the first channel hole 106 and the second channel hole 108, and the insulating layer 15 may completely fill the first channel hole 106.

[0156] FIG23(b) shows the structure after forming the third buffer layer 50, the fourth buffer layer 60, and the second electrode layer 12. FIG24(b) shows the structure after forming the third buffer layer 50, the fourth buffer layer 60, and the second electrode layer 12. As shown in FIG23(b) and FIG24(b), after forming the insulating layer 15, the third buffer layer 50 can be formed. The third buffer layer 50 is located on the side of the first portion 21 facing away from the second isolation layer 103. The third buffer layer 50 is also located on the side of the insulating layer 15 facing away from the second portion 22. The third buffer layer 50 is in contact with the first portion 21. The concentration of N-type ions in the third buffer layer 50 is greater than the concentration of N-type ions in the channel layer 20. For example, the surface of the third buffer layer 50 facing away from the first sub-portion 201 of the first portion 21 and the surface of the third buffer layer 50 facing away from the insulating layer 15 can be located in the same plane.

[0157] As described in the above embodiment, the third buffer layer 50 may include a third sublayer 51 and a fourth sublayer 52, which are stacked together. At least a portion of the third sublayer 51 is located between the fourth sublayer 52 and the channel layer 20, and the fourth sublayer 52 and the channel layer 20 are respectively in contact with the third sublayer 51. The concentration of N-type ions in the fourth sublayer 52 is greater than the concentration of N-type ions in the third sublayer 51, and the concentration of N-type ions in the third sublayer 51 is greater than the concentration of N-type ions in the channel layer 20. Through this arrangement, the N-type ions in the fourth sublayer 52 diffuse into the third sublayer 51, and the N-type ions in the third sublayer 51 diffuse into the channel layer 20. This causes the concentrations of N-type ions in the third sublayer 51, the fourth sublayer 52, and the channel layer 20 to gradually decrease toward the gate layer 13. This further reduces the Schottky barrier between the second buffer layer 40 and the channel layer 20, forming a better ohmic contact and thereby increasing the turn-on current of the semiconductor structure.

[0158] After forming the third buffer layer 50, a fourth buffer layer 60 may be formed on a side of the third buffer layer 50 facing away from the first electrode layer 11. The material of the fourth buffer layer 60 includes at least one of a metal and a conductive metal oxide. Exemplarily, the fourth buffer layer 60 is located on a side of the first portion 21 facing away from the second isolation layer 103. The fourth buffer layer 60 is also located on a side of the insulating layer 15 facing away from the second portion 22. The surface of the fourth buffer layer 60 facing away from the first sub-portion 201 of the first portion 21 and the surface of the fourth buffer layer 60 facing away from the insulating layer 15 may be coplanar. By disposing the fourth buffer layer 60 between the third buffer layer 50 and the second electrode layer 12, the metal in the fourth buffer layer 60 is partially oxidized when the third buffer layer 50 is formed on the fourth buffer layer 60. Because the metal oxide in the fourth buffer layer 60 is conductive, an increase in the contact resistance between the fourth buffer layer 60 and the third buffer layer 50 is avoided, thereby facilitating an increase in the on-state current of the semiconductor structure.

[0159] After forming the fourth buffer layer 60, the second electrode layer 12 can be formed on a side of the third buffer layer 50 facing away from the first portion 21. Exemplarily, the second electrode layer 12 is located on a side of the first portion 21 facing away from the second isolation layer 103. The second electrode layer 12 is also located on a side of the insulating layer 15 facing away from the second portion 22. The surface of the second electrode layer 12 facing away from the first sub-portion 201 of the first portion 21 and the surface of the second electrode layer 12 facing away from the insulating layer 15 can be located in the same plane.

[0160] FIG23(c) is a structural diagram after the semiconductor structure is patterned. FIG24(c) is a structural diagram after the semiconductor structure is patterned. As shown in FIG23(c) and FIG24(c), after the second electrode layer 12 is formed, the first subsection 201 of the first portion 21, the third buffer layer 50, the fourth buffer layer 60, and the second electrode layer 12 may be patterned together. After the patterning, an isolation material may be further deposited on the side of the second isolation layer 103 facing away from the gate layer 13, wherein the isolation material may include one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0161] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention are intended to be covered by the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope of protection of the claims.

Claims

1. A semiconductor structure, characterized in that include: A first electrode layer, a gate layer, and a second electrode layer are sequentially stacked along a first direction; a channel layer, at least partially located between the first electrode layer and the second electrode layer, extending along the first direction, and penetrating the gate layer; The first buffer layer is at least partially located between the first electrode layer and the channel layer, and the first buffer layer is in contact with the channel layer. The concentration of N-type ions in the first buffer layer is greater than the concentration of N-type ions in the channel layer.

2. The semiconductor structure according to claim 1, wherein: The concentration of N-type ions in the first buffer layer ranges from 1e 18 -1e 21 .

3. The semiconductor structure according to claim 1 or 2, characterized in that: The first buffer layer includes a first sublayer and a second sublayer stacked together, at least a portion of the first sublayer is located between the second sublayer and the channel layer, and the second sublayer and the channel layer are in contact with the first sublayer respectively; The concentration of N-type ions in the second sub-layer is greater than that in the first sub-layer, and the concentration of N-type ions in the first sub-layer is greater than that in the channel layer.

4. The semiconductor structure according to claim 3, wherein: The material of the second sublayer includes at least one of InSnO, F:SnO, AlZnO, AlSnO, In2O3, InGaZnO, InZnO, InZnSnO, H:a-Si or D:a-Si.

5. The semiconductor structure according to claim 3, wherein: The material of the first sub-layer includes IZO and / or IGO.

6. The semiconductor structure according to any one of claims 1 to 5, characterized in that: The semiconductor structure further includes a second buffer layer, wherein the second buffer layer is located between the first buffer layer and the first electrode layer, and the first buffer layer and the first electrode layer are in contact with the second buffer layer respectively; The material of the second buffer layer includes at least one of metal and conductive metal oxide.

7. The semiconductor structure according to any one of claims 1 to 6, wherein: The channel layer includes a first portion and a second portion connected to each other, wherein the first portion is arranged around an edge of the second portion; the semiconductor structure further includes an insulating layer, wherein the insulating layer is located in a groove enclosed by the first portion and the second portion; At least a portion of the first buffer layer is located between the second portion and the first electrode layer, and the first buffer layer is in contact with the second portion.

8. The semiconductor structure according to claim 7, wherein: An orthographic projection of the first buffer layer on the first electrode layer is located within the first electrode layer.

9. The semiconductor structure according to claim 8, wherein: A side of the first electrode layer close to the channel layer has a groove, and the first buffer layer is located in the groove.

10. The semiconductor structure according to any one of claims 7 to 9, characterized in that: The semiconductor structure further includes a third buffer layer, which is located between the first portion and the second electrode layer and contacts the first portion. The concentration of N-type ions in the third buffer layer is greater than the concentration of N-type ions in the channel layer.

11. The semiconductor structure according to claim 10, wherein: The third buffer layer and the second electrode layer are located in a groove enclosed by the first portion and the insulating layer.

12. The semiconductor structure according to claim 10, wherein: The first portion includes a first sub-portion and a second sub-portion, the second sub-portion is located between the first sub-portion and the second portion, the second sub-portion is arranged around an edge of the second portion, the first sub-portion is arranged around an edge of the second sub-portion, one side of the first sub-portion is connected to the second sub-portion, and the other side of the first sub-portion extends away from the second sub-portion; At least a portion of the third buffer layer is located between the first sub-portion and the second electrode layer, and the third buffer layer is in contact with the first sub-portion.

13. The semiconductor structure according to any one of claims 10 to 12, characterized in that: The third buffer layer includes a third sublayer and a fourth sublayer that are stacked, at least a portion of the third sublayer is located between the fourth sublayer and the channel layer, and the fourth sublayer and the channel layer are in contact with the third sublayer respectively; The concentration of N-type ions in the fourth sublayer is greater than that in the third sublayer, and the concentration of N-type ions in the third sublayer is greater than that in the channel layer.

14. The semiconductor structure according to any one of claims 10 to 12, characterized in that: The semiconductor structure further includes a fourth buffer layer, wherein the fourth buffer layer is located between the third buffer layer and the second electrode layer, and the third buffer layer and the second electrode layer are respectively in contact with the fourth buffer layer; Wherein, the material of the fourth buffer layer includes at least one of metal and conductive metal oxide.

15. The semiconductor structure according to any one of claims 1 to 14, characterized in that The material of the channel layer includes an oxide semiconductor.

16. A method for preparing a semiconductor structure, characterized in that: include: forming a first electrode layer, a first buffer layer, and a gate layer stacked in sequence along a first direction; forming a channel layer, the channel layer penetrating the gate layer along the first direction, wherein the first buffer layer contacts the channel layer, and a concentration of N-type ions in the first buffer layer is greater than a concentration of N-type ions in the channel layer; A second electrode layer is formed on a side of the channel layer facing away from the first electrode layer.

17. The method for preparing a semiconductor structure according to claim 16, wherein: The forming of a first electrode layer, a first buffer layer, and a gate layer sequentially stacked along a first direction includes: forming a first electrode layer and a first buffer layer that are stacked; performing patterning on the first electrode layer and the first buffer layer simultaneously; A first isolation layer, a gate layer, and a second isolation layer are sequentially stacked on a side of the first buffer layer away from the first electrode layer.

18. The method for preparing a semiconductor structure according to claim 16, wherein: The forming of a first electrode layer, a first buffer layer, and a gate layer sequentially stacked along a first direction includes: performing patterning on the first electrode layer to form a groove; forming a first buffer layer in the groove; A first isolation layer, a gate layer, and a second isolation layer are sequentially stacked on a side of the first buffer layer away from the first electrode layer.

19. The method for preparing a semiconductor structure according to any one of claims 16 to 18, wherein: The forming of the channel layer comprises: forming a first channel hole penetrating the second isolation layer and the gate layer; forming a gate dielectric layer and a sacrificial layer in sequence, wherein the gate dielectric layer and the sacrificial layer cover the hole wall and the hole bottom of the first channel hole, and the gate dielectric layer and the sacrificial layer are also located on a side of the second isolation layer away from the gate layer; forming a second channel hole penetrating the first isolation layer, wherein the second channel hole penetrates the first buffer layer; removing the sacrificial layer; A channel layer is formed, the channel layer including a first portion and a second portion, the first portion covering the hole wall and the hole bottom of the first channel hole, the first portion also being located on a side of the second isolation layer away from the gate layer, and the second portion covering the hole wall and the hole bottom of the second channel hole.

20. The method for preparing a semiconductor structure according to claim 19, wherein: After forming the channel layer and before forming the second electrode layer on a side of the channel layer away from the first electrode layer, the method further includes: Filling the first trench hole and the second trench hole with an insulating material to form an insulating layer, wherein the insulating layer and the first portion enclose a first groove; forming a third buffer layer in the first groove, the third buffer layer being in contact with the first portion, wherein a concentration of N-type ions in the third buffer layer is greater than a concentration of N-type ions in the channel layer; The forming of the second electrode layer on a side of the channel layer away from the first electrode layer comprises: The second electrode layer is formed in the first groove.

21. The method for preparing a semiconductor structure according to claim 19, wherein: After forming the channel layer and before forming the second electrode layer on a side of the channel layer away from the first electrode layer, the method further includes: filling the first trench hole and the second trench hole with an insulating material to form an insulating layer; forming a third buffer layer, the third buffer layer being located on a side of the first portion facing away from the second isolation layer, the third buffer layer being also located on a side of the insulating layer facing away from the second portion, the third buffer layer being in contact with the first portion, and a concentration of N-type ions in the third buffer layer being greater than a concentration of N-type ions in the channel layer; The forming of the second electrode layer on a side of the channel layer away from the first electrode layer comprises: The second electrode layer is formed on a side of the third buffer layer facing away from the first portion.

22. An electronic device, characterized in that: The invention comprises a circuit board and the semiconductor structure according to any one of claims 1 to 15, wherein the semiconductor structure is electrically connected to the circuit board.

Images