Display substrate and preparation method therefor, and display apparatus

Abstract

A display substrate and a preparation method therefor, and a display apparatus. The display substrate comprises a driving structure layer and a light-emitting structure layer, which are disposed on a base, wherein the driving structure layer comprises a plurality of circuit repeating units, and the light-emitting structure layer comprises a plurality of first light-emitting devices; a circuit repeating unit comprises M first circuit units and one second circuit unit, each first circuit unit at least comprises a first pixel driving circuit, the first pixel driving circuit is connected to a first light-emitting device, the second circuit unit at least comprises a second pixel driving circuit, and the second pixel driving circuit is not connected to any first light-emitting device; and the driving structure layer further comprises a first insertion line, a second insertion line and a power connection line, the second insertion line is connected to a data signal line by means of the first insertion line, the power connection line is connected to a first power line, the second insertion line is disposed in a first circuit unit, and the power connection line is disposed in a second circuit unit.

Description

Display substrate and manufacturing method thereof, and display device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on March 29, 2024, with application number 202410382816.9 and invention name “Display substrate, preparation method thereof, and display device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] This article relates to but is not limited to the field of display technology, and specifically to a display substrate and a preparation method thereof, and a display device. Background Art

[0003] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field. Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] On the one hand, the present disclosure provides a display substrate, including a driving structure layer arranged on a substrate and a light-emitting structure layer arranged on a side of the driving structure layer away from the substrate; the driving structure layer includes a plurality of circuit repetition units, and the light-emitting structure layer includes a plurality of first light-emitting devices; at least one circuit repetition unit includes M first circuit units and 1 second circuit unit, M is a positive integer greater than or equal to 3, the first circuit unit includes at least a first pixel driving circuit, the first pixel driving circuit is respectively connected to a data signal line, a first power line and the first light-emitting device, the second circuit unit includes at least a second pixel driving circuit, the second pixel driving circuit is respectively connected to the data signal line and the first power line, but is not connected to the first light-emitting device; the driving structure layer also includes at least one first insertion line extending along a first direction, at least one second insertion line extending along a second direction, and at least one power connection line extending along the second direction, the first direction and the second direction intersect; the second insertion line is connected to the data signal line through the first insertion line, the power connection line is connected to the first power line, the second insertion line is arranged in the first circuit unit, and the power connection line is arranged in the second circuit unit.

[0006] In an exemplary embodiment, M is equal to 4.

[0007] In an exemplary embodiment, at least one first insertion line includes a first data connection line and a first power line arranged in sequence along the first direction, and a first break is provided between the first data connection line and the first power line; at least one second insertion line includes a second data connection line and a second power line arranged in sequence along the second direction, and a second break is provided between the second data connection line and the second power line; the second data connection line is connected to the data signal line through the first data connection line.

[0008] In an exemplary embodiment, the orthographic projection of at least one first break on the display substrate plane at least partially overlaps with the orthographic projection of the first power line on the display substrate plane, and / or the orthographic projection of at least one second break on the display substrate plane at least partially overlaps with the orthographic projection of the first power line on the display substrate plane.

[0009] In an exemplary embodiment, in at least one second circuit unit, the power connection line is connected to the first power line to form a mesh connection structure.

[0010] In an exemplary embodiment, at least one first circuit unit further includes a data connection block, through which the second data connection line is connected to the first data connection line; at least one first circuit unit further includes a dummy connection block, to which the second power line is connected; the position and shape of the data connection block in one first circuit unit are the same as the position and shape of the dummy connection block in another first circuit unit.

[0011] In an exemplary embodiment, the first pixel driving circuit and the second pixel driving circuit each include at least a storage capacitor, a first initialization transistor and a first light-emitting control transistor, the first electrode of the first initialization transistor is connected to the fifth connection electrode, the second electrode of the first initialization transistor is connected to the first plate of the storage capacitor through the first connection electrode, and the first electrode of the first light-emitting control transistor is connected to the second plate of the storage capacitor through the third connection electrode; in at least one first circuit unit, the first connection electrode, the third connection electrode and the fifth connection electrode are arranged in isolation; in at least one second circuit unit, the first connection electrode is respectively connected to the third connection electrode and the fifth connection electrode to form the power connection line.

[0012] In an exemplary embodiment, the first power line is connected to the third connection electrode.

[0013] In an exemplary embodiment, the first circuit unit and the second circuit unit both include a first initial signal line extending along the first direction; in at least one first circuit unit, the fifth connecting electrode is respectively connected to the first electrode of the first initialization transistor and the first initial signal line; in at least one second circuit unit, the fifth connecting electrode is connected to the first electrode of the first initialization transistor and is not connected to the first initial signal line.

[0014] In an exemplary embodiment, in at least one second circuit unit, the data signal line is connected to the first power line.

[0015] In an exemplary embodiment, the display substrate includes a display area, a binding area located on one side of the display area, and a frame area located on the other side of the display area, the display area includes at least a first display area and a second display area, the first display area at least partially surrounds the second display area, the first display area is configured to display images, and the second display area is configured to display images and transmit light; the driving structure layer of the first display area includes multiple circuit repeating units, and the light-emitting structure layer of the first display area includes multiple first light-emitting devices.

[0016] In an exemplary embodiment, at least one circuit repetition unit includes M first circuit units and 1 third circuit unit, and at least one third circuit unit includes at least a third pixel driving circuit; the light-emitting structure layer of the second display area includes a plurality of second light-emitting devices, and the third pixel driving circuit is connected to the second light-emitting device.

[0017] In an exemplary embodiment, the driving structure layer includes at least a first source-drain metal layer, a second source-drain metal layer arranged on a side of the first source-drain metal layer away from the substrate, and a third source-drain metal layer arranged on a side of the second source-drain metal layer away from the substrate; the power connection line and the first insertion line are arranged in the first source-drain metal layer, the first power line is arranged in the second source-drain metal layer, and the data signal line and the second insertion line are arranged in the third source-drain metal layer.

[0018] In an exemplary embodiment, the border area at least includes an upper border area located on a side of the display area away from the binding area, the upper border area includes a plurality of dummy repeating units, at least one dummy repeating unit includes M first dummy units and 1 second dummy unit, the first dummy unit includes at least a first dummy pixel circuit, the second dummy unit includes at least a second dummy pixel circuit, and neither the first dummy pixel circuit nor the second dummy pixel circuit is connected to the light-emitting device; the driving structure layer also includes a passivation layer arranged between the first source and drain metal layer and the second source and drain metal layer, in at least one first dummy unit, at least one via is provided on the passivation layer to connect the first source and drain metal layer with the second source and drain metal layer; in at least one second dummy unit, no via is provided on the passivation layer.

[0019] In an exemplary embodiment, at least one first dummy cell is provided with the second source / drain metal layer, and at least one second dummy cell is not provided with the second source / drain metal layer.

[0020] In an exemplary embodiment, at least one power connection line is connected to a bonding power trace of the bonding area, and the bonding power trace is configured to transmit a first power signal.

[0021] In an exemplary embodiment, at least one power connection line is connected to a border power trace of the border area, and the border power trace is configured to transmit a first power signal.

[0022] In an exemplary embodiment, at least one second insertion line includes a second power trace connected to a power lead in the border area or the binding area, and the power lead is configured to transmit a second power signal.

[0023] On the other hand, the present disclosure further provides a display device comprising the aforementioned display substrate.

[0024] In another aspect, the present disclosure further provides a method for preparing a display substrate, comprising:

[0025] forming a driving structure layer on a substrate, and forming a light-emitting structure layer on the driving structure layer;

[0026] The driving structure layer includes multiple circuit repetition units, and the light-emitting structure layer includes multiple first light-emitting devices; at least one circuit repetition unit includes M first circuit units and 1 second circuit unit, M is a positive integer greater than or equal to 3, the first circuit unit includes at least a first pixel driving circuit, the first pixel driving circuit is respectively connected to the data signal line, the first power line and the first light-emitting device, the second circuit unit includes at least a second pixel driving circuit, the second pixel driving circuit is respectively connected to the data signal line and the first power line, but is not connected to the first light-emitting device; the driving structure layer also includes at least one first insertion line extending along the first direction, at least one second insertion line extending along the second direction, and at least one power connection line extending along the second direction, the first direction and the second direction intersect; the second insertion line is connected to the data signal line through the first insertion line, the power connection line is connected to the first power line, the second insertion line is arranged in the first circuit unit, and the power connection line is arranged in the second circuit unit.

[0027] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0029] FIG1 is a schematic structural diagram of a display device;

[0030] FIG2 is a schematic structural diagram of a display substrate;

[0031] FIG3 is a schematic diagram of a planar structure of a first display area in a display area;

[0032] FIG4 is a schematic diagram of a cross-sectional structure of a first display area in a display region;

[0033] FIG5 is an equivalent circuit diagram of a pixel driving circuit;

[0034] FIG6 is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0035] FIG7 is a structure of a circuit repeating unit according to an embodiment of the present disclosure;

[0036] FIG8 is a structure of a light-emitting repeating unit according to an embodiment of the present disclosure;

[0037] FIG9 is a schematic diagram showing the connection between a pixel driving circuit and a light-emitting device according to an embodiment of the present disclosure;

[0038] FIG10 is a schematic structural diagram of an insertion line according to an exemplary embodiment of the present disclosure;

[0039] FIG11 is a schematic structural diagram of a first display area according to an exemplary embodiment of the present disclosure;

[0040] FIG12 is a schematic structural diagram of a first insertion line and a second insertion line according to an embodiment of the present disclosure;

[0041] FIG13 is a schematic diagram of a semiconductor layer pattern formed according to an embodiment of the present disclosure;

[0042] 14A and 14B are schematic diagrams of an embodiment of the present disclosure after forming a first conductive layer pattern;

[0043] 15A and 15B are schematic diagrams of an embodiment of the present disclosure after forming a second conductive layer pattern;

[0044] FIG16 is a schematic diagram of an embodiment of the present disclosure after forming a fourth insulating layer pattern;

[0045] 17A and 17B are schematic diagrams of an embodiment of the present disclosure after forming a third conductive layer pattern;

[0046] FIG17C is a plan view of the third conductive layer at the junction of the display area and the binding area;

[0047] FIG17D is a plan view of the third conductive layer at the junction of the display area and the upper frame area;

[0048] FIG18 is a schematic diagram of an embodiment of the present disclosure after forming patterns of a fifth insulating layer and a first planar layer;

[0049] 19A and 19B are schematic diagrams of an embodiment of the present disclosure after forming a fourth conductive layer pattern;

[0050] FIG19C is a plan view of the fourth conductive layer at the junction of the display area and the upper frame area;

[0051] FIG20 is a schematic diagram of an embodiment of the present disclosure after forming a second planar layer pattern;

[0052] 21A and 21B are schematic diagrams of an embodiment of the present disclosure after forming a fifth conductive layer pattern.

[0053] Explanation of Reference Numerals: 11—first active layer; 12—second active layer; 13—third active layer; 14—fourth active layer; 15—fifth active layer; 16—sixth active layer; 17—seventh active layer; 21—first scanning signal line; 22—second scanning signal line; 23—light-emitting signal line; 31—first electrode plate; 32—second electrode plate; 33—opening; 34—plate connecting bar; 41—first initial signal line; 42—second initial signal line; 43—first shielding electrode; 44—second shielding electrode; 51—first connecting electrode; 52—second connecting electrode; 53—third connecting electrode; 54—fourth connecting electrode; 55—fifth connecting electrode; 56—sixth connecting electrode; 61—eleventh connecting electrode; 62—twelfth connecting electrode; 63—thirteenth connecting electrode; 64—fourteenth connecting electrode; 70—power connection line; 71—first power line; 72—data signal line; 73—first data connection electrode; 74—first anode connection electrode; 75—second data connection electrode; 76—second anode connection electrode; 77—dummy electrode; 81—first data connection line; 82—second data connection line; 83—data connection bar; 84—data connection block; 91—first power trace; 92—second power trace; 93—dummy connection bar; 94—dummy connection block; 100—display area; 101—substrate; 102—driving structure layer; 103—light-emitting structure layer; 104—packaging structure layer; 200—binding area; 201—lead-out area; 202—bending area; 210—binding power trace; 300—frame area; 310—frame power trace. DETAILED DESCRIPTION

[0054] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0055] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0056] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0057] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0058] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0059] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0060] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" can be interchanged, and "source terminal" and "drain terminal" can be interchanged.

[0061] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0062] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0063] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0064] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined. They may be approximate triangles, rectangles, trapezoids, pentagons, or hexagons, and may have some minor deformations due to tolerances, such as chamfers, rounded edges, and deformation. The term "approximately" in this disclosure does not strictly define the boundaries, but allows for values ​​within the range of process and measurement errors.

[0065] FIG1 is a schematic diagram of the structure of a display device. As shown in FIG1 , the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is respectively connected to the data driver, the scan driver, and the light-emitting driver. The data driver is respectively connected to a plurality of data signal lines (D1 to Dn). The scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm). The light-emitting driver is respectively connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is respectively connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. The light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, may provide clock signals, scan start signals, etc. suitable for the specifications of the scan driver to the scan driver, and may provide clock signals, emission stop signals, etc. suitable for the specifications of the light-emitting driver to the light-emitting driver. The data driver can generate data voltages to be supplied to data signal lines D1, D2, D3, ..., and Dn using grayscale values ​​and control signals received from a timing controller. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a per-pixel basis, where n can be a natural number. The scan driver can generate scan signals to be supplied to scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, and the like from the timing controller. For example, the scan driver can sequentially supply scan signals having on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can sequentially transmit scan start signals provided in the form of on-level pulses to the next-stage circuit under the control of a clock signal, where m can be a natural number. The light driver can generate emission signals to be supplied to light signal lines E1, E2, E3, ..., and Eo by receiving clock signals, emission stop signals, and the like from the timing controller. For example, the light emitting driver may sequentially provide emission signals having off-level pulses to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured as a shift register and may generate emission signals by sequentially transmitting emission stop signals provided in the form of off-level pulses to the next stage circuit under the control of a clock signal. o may be a natural number. In an exemplary embodiment, the pixel array may be provided on a display substrate.

[0066] Smart devices and other products typically require hardware such as front-facing cameras, fingerprint sensors, or light sensors. To increase the screen-to-body ratio, display devices often utilize a hole in the display substrate to create an under-display camera (UDC). Sensors such as cameras are placed within the UDC, achieving full-screen display (FDC) technology. The UDC not only has a certain degree of transmittance but also provides display functionality.

[0067] Figure 2 is a schematic diagram of the structure of a display substrate. As shown in Figure 2, the display substrate may include a display area 100, a binding area 200 located on one side of the display area 100, and a border area 300 located on the other side of the display area 100. In an exemplary embodiment, the display area 100 may be a flat area including a plurality of sub-pixels Pxij that form a pixel array. The plurality of sub-pixels Pxij are configured to display dynamic images or still images. The display area 100 may be referred to as an active area (AA). In an exemplary embodiment, the display substrate may be a flexible substrate, and thus the display substrate may be deformable, such as being curled, bent, folded, or rolled up.

[0068] In an exemplary embodiment, the display area 100 may include at least a first display area 110 and a second display area 120. The first display area 110 may at least partially surround the second display area 120. The first display area 110 is configured to display images and may be referred to as a normal display area. The second display area 120 is configured to display images and transmit light, with the transmitted light being received by an optical device. It may be referred to as an under-screen camera display area or a light-transmitting display area. The position of the second display area 120 may correspond to the position of the optical device.

[0069] In an exemplary embodiment, the binding area 200 may include a lead area 201, a bending area 202, a driver chip area and a binding pin area arranged in sequence along a direction away from the display area, and the lead area 201 is connected to the display area 100 and includes at least a data lead. The bending area 202 is connected to the lead area 201 and may include at least a composite insulating layer provided with a groove, and the groove is configured to bend the binding area to the back of the display area. The driver chip area may include an integrated circuit (IC), which is configured to be connected to a plurality of data lead lines. The binding pin area may include a binding pad (Bonding Pad), which is configured to be bound and connected to an external flexible printed circuit (FPC).

[0070] In an exemplary embodiment, the frame area 300 may include a circuit area, a power line area, a crack dam area, and a cutting area, which are sequentially arranged in a direction away from the display area 100. The circuit area is connected to the display area 100 and may include at least a gate drive circuit, which is connected to the scanning signal line and the light-emitting signal line in the display area 100. The power line area is connected to the circuit area and may include at least a frame power lead, which extends in a direction parallel to the edge of the display area and is connected to the cathode in the display area 100. The crack dam area is connected to the power line area and may include at least a plurality of cracks provided on the composite insulating layer. The cutting area is connected to the crack dam area and may include at least a cutting groove provided on the composite insulating layer. The cutting groove is configured so that after all the film layers of the display substrate are prepared, the cutting equipment can cut along the cutting groove respectively.

[0071] In an exemplary embodiment, the lead line area in the binding area 200 and the power line area in the border area 300 can be provided with an isolation dam, and the isolation dam can extend in a direction parallel to the edge of the display area to form an annular structure surrounding the display area 100. The edge of the display area is the edge of one side of the display area binding area or the border area.

[0072] FIG3 is a schematic diagram of a planar structure of a first display area in a display region. As shown in FIG3 , the first display area may include a plurality of pixel units P arranged in a matrix, and at least one pixel unit P may include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is respectively connected to a scan signal line, a light-emitting signal line, and a data signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting unit. The light-emitting unit may include a light-emitting device. The light-emitting device is connected to the pixel driving circuit of the sub-pixel in which it is located. The light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which it is located.

[0073] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) that emits red light, the second subpixel P2 and the fourth subpixel P4 may be green subpixels (G) that emit green light, and the third subpixel P3 may be a blue subpixel (B) that emits blue light. In an exemplary embodiment, the subpixels may be rectangular, diamond, pentagonal, or hexagonal in shape, and the four subpixels may be arranged in an RGBG pattern.

[0074] In other exemplary embodiments, the pixel unit P may include three sub-pixels, and the three sub-pixels may be arranged in parallel horizontally or vertically, etc., which is not limited in the present disclosure.

[0075] Figure 4 is a schematic cross-sectional view of the first display area within a display region. As shown in Figure 4, in a plane perpendicular to the display substrate, the first display area may include a drive structure layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on a side of the drive structure layer 102 facing away from the substrate 101, and an encapsulation structure layer 104 disposed on a side of the light-emitting structure layer 103 facing away from the substrate 101. In some possible implementations, the first display area may include other film layers, such as a touch structure layer, but this disclosure does not limit this.

[0076] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The driving structure layer 102 may include a plurality of circuit units, each of which may include at least a pixel driving circuit composed of a plurality of transistors and a storage capacitor. The light-emitting structure layer 103 may include a plurality of light-emitting units, each of which may include a light-emitting device, which may include at least an anode, an organic light-emitting layer and a cathode, the anode being connected to the pixel driving circuit, the organic light-emitting layer being connected to the anode, and the cathode being connected to the organic light-emitting layer, and the organic light-emitting layer emitting light of corresponding colors under the drive of the anode and the cathode. The encapsulation structure layer 104 may include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer stacked together, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0077] Figure 5 is an equivalent circuit diagram of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. As shown in Figure 5, the pixel driving circuit may include seven transistors (first transistor T1 to seventh transistor T7) and one storage capacitor C. The pixel driving circuit is respectively connected to seven signal lines (a first scanning signal line S1, a second scanning signal line S2, an emission signal line EM, a first initial signal line INIT1, a second initial signal line INIT2, a data signal line DATA, and a first power line VDD).

[0078] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the second electrode of the first transistor, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first end of the storage capacitor C, respectively; the second node N2 is connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the second electrode of the fifth transistor T5, respectively; the third node N3 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, respectively; and the fourth node N4 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, respectively.

[0079] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first node N1 , and a second end of the storage capacitor C is connected to the first power line VDD.

[0080] In an exemplary embodiment, a gate electrode of the first transistor T1 is connected to the second scan signal line S2 , a first electrode of the first transistor T1 is connected to the first initial signal line INIT1 , and a second electrode of the first transistor is connected to the first node N1 .

[0081] In an exemplary embodiment, a gate electrode of the second transistor T2 is connected to the first scan signal line S1 , a first electrode of the second transistor T2 is connected to the first node N1 , and a second electrode of the second transistor T2 is connected to the third node N3 .

[0082] In an exemplary embodiment, a gate electrode of the third transistor T3 is connected to the first node N1 , a first electrode of the third transistor T3 is connected to the second node N2 , and a second electrode of the third transistor T3 is connected to the third node N3 .

[0083] In an exemplary embodiment, a gate electrode of the fourth transistor T4 is connected to the first scan signal line S1 , a first electrode of the fourth transistor T4 is connected to the data signal line DATA, and a second electrode of the fourth transistor T4 is connected to the second node N2 .

[0084] In an exemplary embodiment, a gate electrode of the fifth transistor T5 is connected to the light emitting signal line EM, a first electrode of the fifth transistor T5 is connected to the first power line VDD, and a second electrode of the fifth transistor T5 is connected to the second node N2.

[0085] In an exemplary embodiment, a gate electrode of the sixth transistor T6 is connected to the light emitting signal line EM, a first electrode of the sixth transistor T6 is connected to the third node N3 , and a second electrode of the sixth transistor T6 is connected to the fourth node N4 .

[0086] In an exemplary embodiment, a gate electrode of the seventh transistor T7 is connected to the first scan signal line S1 , a first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2 , and a second electrode of the seventh transistor T7 is connected to the fourth node N4 .

[0087] In an exemplary embodiment, a first electrode of the light-emitting device EL is connected to the fourth node N4, and a second electrode of the light-emitting device EL is connected to the second power supply line VSS. The light-emitting device EL may be an OLED including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or may be a QLED including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode).

[0088] In an exemplary embodiment, the first power line VDD is configured to provide a constant first power signal to the pixel driving circuit, and the second power line VSS is configured to provide a constant second power signal to the light-emitting device. The first power signal is a high-level signal, and the second power signal is a low-level signal. The first initial voltage signal and the second initial voltage signal may be constant voltage signals, which is not limited in this disclosure.

[0089] In an exemplary embodiment, the first to seventh transistors T1 to T7 in the pixel driving circuit may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first to seventh transistors T1 to T7 may include P-type transistors and N-type transistors.

[0090] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be low-temperature polysilicon thin-film transistors, or oxide thin-film transistors, or both. The active layer of the low-temperature polysilicon thin-film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display substrate to form an LTPO (Low Temperature Polycrystalline + Oxide) display substrate can leverage the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0091] With the development of display technology, consumers have increasingly higher requirements for the display effects and display quality of display products. Products such as full-screen and narrow-border products have gradually become the development trend of display products with their large screen-to-body ratio and ultra-narrow borders. Therefore, the narrowing of the border or even the borderless design has received more and more attention in the design of OLED display products. In a display substrate, since the data signal of the integrated circuit in the binding area needs to be introduced into the wider display area through the data lead in a fan-out manner, the lead area occupies a large space, resulting in a larger width of the lower border. In addition, since the gate drive circuit and power lead need to be set in the border area, and the gate drive circuit and power lead occupy a large space, the width of the left and right borders is large.

[0092] To reduce the width of the lower bezel, exemplary embodiments of the present disclosure provide a display substrate employing a fanout in panel (FIP) structure. Multiple data connection lines are arranged in the display area. One end of each of the multiple data connection lines is connected to a plurality of data signal lines in the display area. The other ends of the multiple data connection lines extend to a binding area and are connected to the integrated circuit via a plurality of lead lines in a lead-out area. Because the lead-out area does not require fan-shaped diagonal lines, the width of the lead-out area is reduced, thereby reducing the width of the lower bezel.

[0093] An exemplary embodiment of the present disclosure provides a display substrate, comprising a driving structure layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving structure layer away from the substrate; the driving structure layer comprises a plurality of circuit repetition units, and the light-emitting structure layer comprises a plurality of first light-emitting devices; at least one circuit repetition unit comprises M first circuit units and one second circuit unit, where M is a positive integer greater than or equal to 3, the first circuit unit comprises at least a first pixel driving circuit, the first pixel driving circuit being connected to a data signal line, a first power line, and the first light-emitting device, respectively; the second circuit unit comprises at least a second pixel driving circuit, the second pixel driving circuit being connected to the data signal line and the first power line, respectively, but not to the first light-emitting device; the driving structure layer further comprises at least one first inset line extending along a first direction, at least one second inset line extending along a second direction, and at least one power connection line extending along the second direction, the first direction and the second direction intersecting; the second inset line being connected to the data signal line via the first inset line, the power connection line being connected to the first power line, the second inset line being disposed in the first circuit unit, and the power connection line being disposed in the second circuit unit.

[0094] In an exemplary embodiment, M is equal to 4.

[0095] In an exemplary embodiment, at least one first insertion line includes a first data connection line and a first power line arranged in sequence along the first direction, and a first break is provided between the first data connection line and the first power line; at least one second insertion line includes a second data connection line and a second power line arranged in sequence along the second direction, and a second break is provided between the second data connection line and the second power line; the second data connection line is connected to the data signal line through the first data connection line.

[0096] In an exemplary embodiment, in at least one second circuit unit, the power connection line is connected to the first power line to form a mesh connection structure.

[0097] In an exemplary embodiment, the first pixel driving circuit and the second pixel driving circuit each include at least a storage capacitor, a first initialization transistor and a first light-emitting control transistor, the first electrode of the first initialization transistor is connected to the fifth connection electrode, the second electrode of the first initialization transistor is connected to the first plate of the storage capacitor through the first connection electrode, and the first electrode of the first light-emitting control transistor is connected to the second plate of the storage capacitor through the third connection electrode; in at least one first circuit unit, the first connection electrode, the third connection electrode and the fifth connection electrode are arranged in isolation; in at least one second circuit unit, the first connection electrode is respectively connected to the third connection electrode and the fifth connection electrode to form the power connection line.

[0098] In an exemplary embodiment, in at least one second circuit unit, the data signal line is connected to the first power line.

[0099] In an exemplary embodiment, the display substrate includes a display area, a binding area located on one side of the display area, and a frame area located on the other side of the display area, the display area includes at least a first display area and a second display area, the first display area at least partially surrounds the second display area, the first display area is configured to display images, and the second display area is configured to display images and transmit light; the driving structure layer of the first display area includes multiple circuit repeating units.

[0100] In an exemplary embodiment, the display substrate includes a display area, a binding area located on one side of the display area, and a frame area located on the other side of the display area, the display area includes at least a first display area and a second display area, the first display area at least partially surrounds the second display area, the first display area is configured to display images, and the second display area is configured to display images and transmit light; the driving structure layer of the first display area includes multiple circuit repeating units, and the light-emitting structure layer of the first display area includes multiple first light-emitting devices.

[0101] In an exemplary embodiment, at least one circuit repetition unit includes M first circuit units and 1 third circuit unit, and at least one third circuit unit includes at least a third pixel driving circuit; the light-emitting structure layer of the second display area includes a plurality of second light-emitting devices, and the third pixel driving circuit is connected to the second light-emitting device.

[0102] FIG6 is a schematic structural diagram of a display substrate of an exemplary embodiment of the present disclosure. As shown in FIG6 , in a plane parallel to the display substrate, the display substrate may include a display area 100, a binding area 200 located on one side of the display area 100, and a frame area 300 located on the other side of the display area 100. The display area 100 may include at least a first display area 110 and a second display area 120. The first display area 110 may at least partially surround the second display area 120. The first display area 110 is configured to display an image, and the second display area 120 is configured to display an image and transmit light. In a direction perpendicular to the display substrate, the display area may include at least a driving structure layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving structure layer away from the substrate.

[0103] In an exemplary embodiment, the driving structure layer of the first display area 110 may include multiple pixel driving circuits, the driving structure layer of the second display area 120 is not provided with a pixel driving circuit, the light-emitting structure layer of the first display area 110 may include multiple first light-emitting devices, the light-emitting structure layer of the second display area 120 may include multiple second light-emitting devices, and the multiple pixel driving circuits of the first display area 110 are configured to provide driving signals to the first light-emitting devices in the first display area 110 and the second light-emitting devices in the second display area 120, respectively, to drive the corresponding first light-emitting devices and the second light-emitting devices to emit light.

[0104] In an exemplary embodiment, the driving structure layer of the first display area 110 may include a plurality of circuit repeating units. A circuit repeating unit is a basic unit constituting the driving structure layer of the first display area 110. The driving structure layer of the first display area 110 is formed by repeating and continuously arranging the circuit repeating units along the first direction X and the second direction Y. The light-emitting structure layer of the first display area 110 may include a plurality of light-emitting repeating units. A light-emitting repeating unit is a basic unit constituting the light-emitting structure layer of the first display area 110. The light-emitting structure layer of the first display area 110 is formed by repeating and continuously arranging the light-emitting repeating units along the first direction X and the second direction Y.

[0105] In an exemplary embodiment, in the first display area 110, the positions of the plurality of circuit repeating units and the plurality of light-emitting repeating units may be substantially corresponding, the orthographic projection of at least one circuit repeating unit on the substrate has a first area, and the orthographic projection of at least one light-emitting repeating unit on the substrate has a second area, and the ratio of the first area to the second area may be approximately 0.95 to 1.05, that is, the area of ​​the orthographic projection of the circuit repeating unit on the substrate and the area of ​​the orthographic projection of the light-emitting repeating unit on the substrate may be substantially the same.

[0106] In an exemplary embodiment, the size of at least one circuit repeating unit in the first direction X and the size of at least one light emitting repeating unit in the first direction X may be substantially the same, and the size of at least one circuit repeating unit in the second direction Y and the size of at least one light emitting repeating unit in the second direction Y may be substantially the same.

[0107] In an exemplary embodiment, at least one circuit repetition unit may include M+1 circuit units sequentially arranged along a first direction X, each circuit unit may include at least a pixel driving circuit. At least one light-emitting repetition unit may include M first light-emitting units sequentially arranged along the first direction X, each first light-emitting unit may include at least a first light-emitting device. The area of ​​the orthogonal projection of the M+1 pixel driving circuits on the substrate may be substantially the same as the area of ​​the orthogonal projection of the M first light-emitting devices on the substrate.

[0108] In exemplary embodiments, the circuit unit referred to in this disclosure refers to a region divided according to the pixel driving circuit, and the light-emitting unit referred to in this disclosure refers to a region divided according to the light-emitting device. In exemplary embodiments, the position of the orthographic projection of the light-emitting unit on the substrate may correspond to the position of the orthographic projection of the circuit unit on the substrate, or the position of the orthographic projection of the light-emitting unit on the substrate may not correspond to the position of the orthographic projection of the circuit unit on the substrate.

[0109] In an exemplary embodiment, a plurality of circuit units sequentially arranged along a first direction X may be referred to as a unit row, and a plurality of circuit units sequentially arranged along a second direction Y may be referred to as a unit column. The plurality of unit rows and the plurality of unit columns constitute a circuit unit array arranged in an array, and the first direction X intersects the second direction Y.

[0110] In an exemplary embodiment, in at least one circuit repetition unit, the sizes of the multiple pixel driving circuits may be substantially the same. In at least one light-emitting repetition unit, the sizes of the multiple first light-emitting devices may be substantially the same. In the present disclosure, the size of the pixel driving circuit refers to the size of the orthographic projection of the pixel driving circuit on the substrate, and the size of the light-emitting device refers to the size of the orthographic projection of the light-emitting device on the substrate. When the orthographic projections of the pixel driving circuit and the light-emitting device on the substrate are rectangular, the size may include any one or more of the following: the length of the orthographic projection in the first direction X, the length of the orthographic projection in the second direction Y, and the area of ​​the orthographic projection. When the orthographic projections of the pixel driving circuit and the light-emitting device on the substrate are circular or elliptical, the size may include any one or more of the following: the radius of the orthographic projection, the major axis and minor axis of the orthographic projection, and the area of ​​the orthographic projection.

[0111] In an exemplary embodiment, in the first display area 110, the driving structure layer can be arranged in a compressed manner to set the circuit unit (pixel driving circuit), while the light-emitting structure layer is arranged in a normal (non-compressed) manner to set the first light-emitting unit (first light-emitting device). For example, in the normal manner, M circuit units can be arranged in a circuit repeating unit, and M first light-emitting units can be arranged in a light-emitting repeating unit. In the compressed manner, the number of circuit units arranged in the circuit repeating unit can be increased by adopting lateral compression, and 1 circuit unit is inserted into the area where M circuit units were previously arranged, so that M+1 circuit units can be arranged in a circuit repeating unit. Since the light-emitting structure layer adopts a normal manner, M first light-emitting devices are still arranged in the light-emitting repeating unit, and the area occupied by the M+1 circuit units is substantially the same as the area occupied by the M first light-emitting units. In an exemplary embodiment, M can be a positive integer greater than or equal to 3.

[0112] In an exemplary embodiment, for an RGBG pixel arrangement, M may be an integer multiple of 4, such as 4, 8, or 12. In the embodiment of the present disclosure, M is equal to 4, that is, the display substrate of the embodiment of the present disclosure adopts a 4-in-1 structure.

[0113] In some possible implementations, when the pixel arrangement is an RGB arrangement, M may be an integer multiple of 3, such as 3, 6, or 9.

[0114] In an exemplary embodiment, the driving structure layer of the second display area 120 may include multiple insulating layers, and the light-emitting structure layer of the second display area 120 may include multiple second light-emitting units. The second light-emitting units may include at least second light-emitting devices. That is, the second display area 120 is not provided with a pixel driving circuit, but only with light-emitting devices. Since the second display area 120 is not provided with a pixel driving circuit, the second light-emitting devices in the second display area 120 need to be connected to the pixel driving circuit in the first display area 110 via anode connection lines.

[0115] In an exemplary embodiment, the size of the second light-emitting device in the second display area 120 can be substantially the same as the size of the first light-emitting device in the first display area 110, and the arrangement of the plurality of second light-emitting devices in the second display area 120 can be substantially the same as the arrangement of the plurality of first light-emitting devices in the first display area 110.

[0116] In an exemplary embodiment, in at least one circuit repetition unit, the M+1 circuit units may include M first circuit units and one second circuit unit, or may include M first circuit units and one third circuit unit. The first circuit unit may include at least a first pixel driving circuit, the second circuit unit may include at least a second pixel driving circuit, and the third circuit unit may include at least a third pixel driving circuit. The first pixel driving circuit is configured to provide a driving signal to a first light-emitting device in the first display area 110, the second pixel driving circuit serves as a dummy pixel circuit, and the third pixel driving circuit is configured to provide a driving signal to a second light-emitting device in the second display area 120.

[0117] Figure 7 illustrates the structure of a circuit repetition unit according to an embodiment of the present disclosure. As shown in Figure 7, the driving structure layer in the first display area 110 may include multiple circuit repetition units 110A. At least one circuit repetition unit 110A may include four first circuit units and one second circuit unit sequentially arranged along a first direction X, or may include four first circuit units and one third circuit unit sequentially arranged along the first direction X. The first circuit unit may include at least a first pixel driving circuit Q1, the second circuit unit may include at least a second pixel driving circuit Q2, and the third circuit unit may include at least a first pixel driving circuit Q3.

[0118] Figure 8 illustrates the structure of a light-emitting repeating unit according to an embodiment of the present disclosure. As shown in Figure 8 , the light-emitting structure layer of the first display area 110 may include multiple light-emitting repeating units 110B, at least one of which may include four first light-emitting devices F1 arranged sequentially along a first direction X. The light-emitting structure layer of the second display area 120 may include multiple second light-emitting devices F2.

[0119] As shown in Figures 7 and 8, at least one first pixel driving circuit Q1 in the first display area 110 is connected to at least one first light-emitting unit F1 in the first display area 110, and the orthographic projection of at least one first pixel driving circuit Q1 on the substrate at least partially overlaps with the orthographic projection of at least one first light-emitting device F1 on the substrate. The first pixel driving circuit Q1 is configured to provide a driving signal to the connected first light-emitting device F1 to drive the corresponding first light-emitting device F1 to emit light. In some examples, the relationship between the multiple first pixel driving circuits Q1 and the multiple first light-emitting devices F1 can be one-to-one, that is, one first pixel driving circuit Q1 can be connected to one first light-emitting device F1 and configured to drive the connected first light-emitting device F1 to emit light; or, the relationship between the multiple first pixel driving circuits Q1 and the multiple first light-emitting devices F1 can be one-to-many, that is, one first pixel driving circuit Q1 can be connected to multiple first light-emitting devices F1 and configured to drive the connected multiple first light-emitting devices F1 to emit light; or, the relationship between the multiple first pixel driving circuits Q1 and the multiple first light-emitting devices F1 can be many-to-one, that is, multiple first pixel driving circuits Q1 can be connected to one first light-emitting device F1 and configured to drive the first light-emitting device F1 to emit light.

[0120] In an exemplary embodiment, at least one third pixel driving circuit Q3 in the first display area 110 is connected to at least one second light-emitting device F2 in the second display area 120 through an anode connecting line, and the orthographic projection of the at least one third pixel driving circuit Q3 on the substrate does not overlap with the orthographic projection of the at least one second light-emitting device F2 on the substrate. The third pixel driving circuit Q3 is configured to provide a driving signal to the connected second light-emitting device F2 to drive the corresponding second light-emitting device F2 to emit light. In some examples, the relationship between multiple third pixel driving circuits Q3 and multiple second light-emitting devices F2 can be one-to-one, that is, one third pixel driving circuit Q3 can be connected to one second light-emitting device F2 and configured to drive the connected second light-emitting device F2 to emit light; or, the relationship between multiple third pixel driving circuits Q3 and multiple second light-emitting devices F2 can be one-to-many, that is, one third pixel driving circuit Q3 can be connected to multiple second light-emitting devices F2 and configured to drive the connected multiple second light-emitting devices F2 to emit light; or, the relationship between multiple third pixel driving circuits Q3 and multiple second light-emitting devices F2 can be many-to-one, that is, multiple third pixel driving circuits Q3 can be connected to one second light-emitting device F2 and configured to drive the second light-emitting device F2 to emit light.

[0121] In an exemplary embodiment, the sizes of the first, second, and third pixel driving circuits Q1, Q2, and Q3 may be substantially the same, and the sizes of the first and second light emitting devices F1, F2 may be substantially the same.

[0122] Figure 9 is a schematic diagram illustrating the connection between a pixel driver circuit and a light-emitting device according to an embodiment of the present disclosure. As shown in Figure 9, at least one first light-emitting device F1 in the first display area 110 can be connected to at least one first pixel driver circuit Q1 in the first display area 110, and at least one second light-emitting device F2 in the second display area 120 can be connected to at least one third pixel driver circuit Q3 in the first display area 110 via an anode connection line AL.

[0123] In an exemplary embodiment, the circuit repetition unit in the first display area 110 may include four first pixel driving circuits Q1 and one third pixel driving circuit Q3 (or second pixel driving circuit Q2), the four first pixel driving circuits Q1 may be arranged sequentially along the first direction X, and the one third pixel driving circuit Q3 (or second pixel driving circuit Q2) may be arranged on one side of the four first pixel driving circuits Q1 in the first direction X.

[0124] In an exemplary embodiment, the light emitting repeating units in the first display area 110 may each include four first light emitting devices F1. The four first light emitting devices F1 may be a red light emitting device, a first green light emitting device, a blue light emitting device, and a second green light emitting device sequentially arranged along the first direction X.

[0125] In an exemplary embodiment, the second display area 120 may include a plurality of second light emitting devices F2 , which may include red, first, blue, and second green light emitting devices periodically disposed along the first direction X.

[0126] In an exemplary embodiment, the position of a circuit repetition unit in the first display area 110 may substantially correspond to the position of a light-emitting repetition unit. In the corresponding circuit repetition unit and light-emitting repetition unit, at least one first light-emitting device F1 is directly connected to at least one first pixel driving circuit Q1. The orthographic projection of at least one first light-emitting device F1 on the substrate at least partially overlaps with the orthographic projection of at least one first pixel driving circuit Q1 on the substrate. The first pixel driving circuit Q1 is configured to provide a driving signal to the connected first light-emitting device F1 to drive the corresponding first light-emitting device F1 to emit light.

[0127] In an exemplary embodiment, at least one second light-emitting device F2 in the second display area 120 is connected to at least one third pixel driving circuit Q3 in the first display area 110 through an anode connection line AL, and the orthographic projection of the at least one second light-emitting device F2 on the substrate does not overlap with the orthographic projection of the at least one third pixel driving circuit Q3 on the substrate. The third pixel driving circuit Q3 is configured to provide a driving signal to the connected second light-emitting device F2 to drive the corresponding second light-emitting device F2 to emit light.

[0128] In an exemplary embodiment, the first circuit unit may be referred to as a normal circuit unit, and the second and third circuit units may be referred to as insertion circuit units. The first pixel driving circuit in the first circuit unit provides a driving signal to the first light-emitting device in the first display area and may be referred to as a normal pixel circuit. The second pixel driving circuit in the second circuit unit is not connected to either the first or second light-emitting device and may be referred to as a dummy pixel circuit. The third pixel driving circuit in the third circuit unit provides a driving signal to the second light-emitting device in the second display area and may be referred to as an insertion pixel circuit.

[0129] In an exemplary embodiment, a plurality of first circuit units arranged sequentially along the second direction Y may be referred to as a normal unit column, a plurality of second circuit units (or a plurality of second circuit units and at least one third circuit unit) arranged sequentially along the second direction Y may be referred to as an insertion unit column, and four normal unit columns may be arranged between two adjacent insertion unit columns in the first direction X to form a 4-in-1 structure.

[0130] In an exemplary embodiment, the plurality of third circuit units may be disposed at a position close to the second display area, and the plurality of second circuit units may be disposed at a position away from the second display area, which is not limited in the present disclosure.

[0131] In an exemplary embodiment, the position of the second display area 120 in the first display area 110 is not limited, and can be located in the upper area or the lower area of ​​the first display area 110, or can be located at the edge of the first display area 110. The resolution of the first display area 110 and the second display area 120 can be the same or different, which is not limited in the present disclosure.

[0132] In an exemplary embodiment, within a plane parallel to the display substrate, the second display area 120 may have a shape that is any one or more of the following: rectangular, polygonal, circular, and elliptical. The optical device may be a fingerprint recognition device, a camera, or an optical sensor such as a 3D imaging device. When the second display area 120 is circular, the diameter of the circle may be approximately 3 mm to 5 mm. When the second display area 120 is rectangular, the side length of the rectangle may be approximately 3 mm to 5 mm, although this disclosure is not limited thereto.

[0133] As shown in Figure 6, the driving structure layer of the first display area 110 can also include multiple data signal lines 72, multiple first data connection lines 81 and multiple second data connection lines 82. The shape of the first data connection line 81 can be a straight line or a broken line extending along the first direction X, and the shape of the data signal line 72 and the second data connection line 82 can be a straight line or a broken line extending along the second direction Y.

[0134] In an exemplary embodiment, a plurality of data signal lines 72 are sequentially arranged at predetermined intervals in a first direction X. At least one data signal line 72 is connected to a plurality of pixel driving circuits in a unit column, and the data signal line 72 is configured to provide data signals to the connected pixel driving circuit. A first end of at least one first data connection line 81 is connected to a data signal line 72, and a second end is connected to one end of a second data connection line 82. The other end of the second data connection line 82 extends to the bonding area and is connected to a data lead-out line 80. This connects the data signal lines 72 in the display area to the data lead-out line 80 in the bonding area 200 via the first and second data connection lines 81 and 82, forming a FIP structure (also known as a FIAA structure). In an exemplary embodiment, the first and second data connection lines 81 and 82 are collectively referred to as data connection lines.

[0135] In an exemplary embodiment, the binding area 200 may include a lead area 201, a bend area, a driver chip area, and a binding pin area, arranged sequentially along a direction away from the display area. The lead area 201 is connected to the display area 100, and the bend area is connected to the lead area 201. The lead area 201 may be provided with a plurality of data lead lines 80, extending in a direction away from the display area. The first ends of some of the data lead lines 80 are connected to the second data connection lines 82 in the display area 100, while the first ends of other data lead lines 80 are connected to the data signal lines 72 in the display area 100. The second ends of all data lead lines 80 extend along a second direction Y, cross the bend area, and connect to the integrated circuit in the driver chip area. This allows the integrated circuit to apply data signals to the data signal lines via the data lead lines and data connection lines. Since the first and second data connection lines 81, 82 are arranged within the display area, the length of the lead area in the second direction Y can be effectively reduced, significantly reducing the width of the bottom bezel and increasing the screen-to-body ratio, thus facilitating full-screen display.

[0136] In an exemplary embodiment, the number of data connection lines in the display area may be the same as the number of data signal lines, and each data signal line is connected to a corresponding lead line via a data connection line. Alternatively, the number of data connection lines in the display area may be less than the number of data signal lines, with some of the data signal lines in the display area being connected to corresponding lead lines via data connection lines, while other data signal lines are directly connected to the lead lines. This disclosure is not limited herein.

[0137] Figure 10 is a schematic diagram of an interposer structure according to an exemplary embodiment of the present disclosure. As shown in Figure 10 , the drive structure layer of the first display area 110 may further include a plurality of first power supply lines 91 and a plurality of second power supply lines 92. The first power supply lines 91 may be in the shape of a straight line or a broken line extending along a first direction X, and the plurality of first power supply lines 91 may be arranged sequentially along a second direction Y. The second power supply lines 92 may be in the shape of a straight line or a broken line extending along the second direction Y, and the plurality of second power supply lines 92 may be arranged sequentially along the first direction X. In exemplary embodiments, the first power supply lines 91 and the second power supply lines 92 may be collectively referred to as power supply lines.

[0138] In an exemplary embodiment, the first data connection line 81 and the first power supply line 91 can be disposed on the same layer and formed simultaneously through the same patterning process. A first break K1 is provided between the first data connection line 81 and the first power supply line 91 disposed in the same cell row. The first break K1 is configured to achieve mutual insulation between the first data connection line 81 and the first power supply line 91.

[0139] In an exemplary embodiment, the second data connection line 82 and the second power supply line 92 can be disposed on the same layer and formed simultaneously through the same patterning process. A second break K2 is provided between the second data connection line 82 and the second power supply line 92 disposed in the same cell column. The second break K2 is configured to achieve mutual insulation between the second data connection line 82 and the second power supply line 92.

[0140] In an exemplary embodiment, the first data connection line 81 can be referred to as a lateral connection line (lateral FIP line), and the first power line 91 can be referred to as a lateral dummy connection line (lateral Dummy FIP line). The lateral connection line and the lateral dummy connection line are formed simultaneously using the same film layer and through the same patterning process (such as the first source and drain metal layer), and the two are disconnected. In an exemplary embodiment, the first data connection line 81 and the first power line 91 can both be referred to as first interposer lines. In some cell rows, the first interposer lines can include the first data connection line 81 and the first power line 91 arranged sequentially along the first direction X. In other cell rows, the first interposer lines can include only the first power line 91.

[0141] In an exemplary embodiment, the second data connection line 82 can be referred to as a vertical connection line (vertical FIP line), and the second power line 92 can be referred to as a vertical dummy connection line (vertical Dummy FIP line). The vertical connection line and the vertical dummy connection line are formed simultaneously using the same film layer and through the same patterning process (such as the third source and drain metal layer), and the two are disconnected. In an exemplary embodiment, the second data connection line 82 and the second power line 92 can both be referred to as second inset lines. In some cell columns, the second inset lines can include the second data connection line 82 and the second power line 92 arranged sequentially along the second direction Y. In other cell columns, the second inset lines can only include the second power line 92.

[0142] In a direction perpendicular to the display substrate, the driving structure layer of the first display area 110 may include multiple conductive layers. The data signal line 72 and the first data connection line 81 may be arranged in different conductive layers, and the first data connection line 81 and the second data connection line 82 may be arranged in different conductive layers. The first end of the first data connection line 81 is connected to the data signal line 72 through a first connection hole VK1. The second end of the first data connection line 81 extends along the first direction X or the direction opposite to the first direction X, and then connects to the first end of the second data connection line 82 through a second connection hole VK2. The second end of the second data connection line 82 extends along the second direction Y toward the binding area.

[0143] In an exemplary embodiment, since the data connection lines are provided in a portion of the display area, the driving structure layer of the first display area can be divided into a first area 110-1 and a second area 110-2 based on the presence or absence of the data connection lines. The first area 110-1 can be the area where the first and second data connection lines 81 and 82 are provided (the dark area in FIG. 10 ), and the second area 110-2 can be the area where the first and second data connection lines 81 and 82 are not provided (the area outside the dark area in FIG. 10 ). In an exemplary embodiment, the first area 110-1 can be referred to as a FIP area, and the second area 110-2 can be referred to as a non-FIP area or a SIP area.

[0144] Figure 11 is a schematic diagram of the structure of a first display area according to an exemplary embodiment of the present disclosure, illustrating the structure of 16 circuit units in two unit rows (the Mth unit row and the M+1th unit row) and eight unit columns (the Nth unit column to the N+7th unit column) in the first display area. The Nth unit column, the N+2th unit column to the N+5th unit column, and the N+7th unit column are normal unit columns, and the circuit units in these unit columns are first circuit units. The N+1th unit column and the N+6th unit column are inserted unit columns, and the circuit units in these unit columns are second circuit units.

[0145] As shown in FIG11 , within a plane parallel to the display substrate, the driving structure layer of the first display area may include multiple first circuit units and multiple second circuit units. At least one first circuit unit may include a first pixel driving circuit, and at least one second circuit unit may include a second pixel driving circuit. The first pixel driving circuit and the second pixel driving circuit may be connected to the first scan signal line 21, the second scan signal line 22, the light emitting signal line 23, the first initial signal line 41, the second initial signal line 42, the first power line 71, and the data signal line 72, respectively. The first scan signal line 21, the second scan signal line 22, and the light emitting signal line 23 are configured to provide the first scan signal, the second scan signal, and the light emitting control signal, respectively, to the first pixel driving circuit. The first initial signal line 41 and the second initial signal line 42 are configured to provide the first initial signal and the second initial signal, respectively, to the first pixel driving circuit. The first power line 71 is configured to provide the first power signal to the first pixel driving circuit, and the data signal line 72 is configured to provide the data signal to the first pixel driving circuit. The multiple signal lines connected to the first pixel driving circuit and the second pixel driving circuit may be located within the corresponding circuit units.

[0146] In an exemplary embodiment, the shapes of the first scanning signal line 21, the second scanning signal line 22, the light-emitting signal line 23, the first initial signal line 41, and the second initial signal line 42 can be straight lines or broken lines with the main parts extending along the first direction X, and the shapes of the first power line 71 and the data signal line 72 can be straight lines or broken lines with the main parts extending along the second direction Y.

[0147] In the present disclosure, "A extends along direction B" means that A may include a main portion and a secondary portion connected to the main portion, the main portion being a line, line segment, or strip, the main portion extending along direction B, and the length of the main portion extending along direction B being greater than the length of the secondary portion extending along other directions. In the following description, "A extends along direction B" means "the main portion of A extends along direction B." In an exemplary embodiment, the first direction X may be the direction of unit rows, and the second direction Y may be the direction of unit columns.

[0148] In an exemplary embodiment, the first pixel driving circuit and the second pixel driving circuit may include at least a storage capacitor and a plurality of transistors. The plurality of transistors may include a first transistor T1 as a first reset transistor, a second transistor T2 as a compensation transistor, a third transistor T3 as a drive transistor, a fourth transistor T4 as a data write transistor, a fifth transistor T5 as a first emission control transistor, a sixth transistor T6 as a second emission control transistor, and a seventh transistor T7 as a second reset transistor. The storage capacitor may include a first plate and a second plate stacked together.

[0149] In the exemplary embodiment, the gate electrode of the first transistor T1 is connected to the second scan signal line 22, the first electrode of the first transistor T1 is connected to the first initial signal line 41, and the second electrode of the first transistor T1 is respectively connected to the first electrode and the first plate of the second transistor T2 (which also serves as the gate electrode of the third transistor T3). The gate electrode of the second transistor T2 is connected to the first scan signal line 21, and the second electrode of the second transistor T2 is respectively connected to the second electrode of the third transistor T3 and the first electrode of the sixth transistor T6. The gate electrode of the fourth transistor T4 is connected to the first scan signal line 21, the first electrode of the fourth transistor T4 is connected to the data signal line 72, and the second electrode of the fourth transistor T4 is respectively connected to the first electrode of the third transistor T3 and the second electrode of the fifth transistor T5. The gate electrode of the fifth transistor T5 is connected to the light emission signal line 23, and the first electrode of the fifth transistor T5 is connected to the first power supply line 71. The gate electrode of the sixth transistor T6 is connected to the light emission signal line 23, and the second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7. A gate electrode of the seventh transistor T7 is connected to the first scanning signal line 21 , and a first electrode of the seventh transistor T7 is connected to the second initial signal line 42 .

[0150] Figure 12 is a schematic diagram of the structure of the first and second inset wires of an exemplary embodiment of the present disclosure. As shown in Figures 11 and 12, the drive structure layer of the first display area may further include at least one first inset wire and at least one second inset wire. The first inset wire may be in the shape of a straight line or a broken line extending along the first direction X, and the second inset wire may be in the shape of a straight line or a broken line extending along the second direction Y.

[0151] In an exemplary embodiment, at least one first interposer may include a first data connection line 81 and a first power supply line 91 disposed in the same cell row and sequentially arranged along the first direction X. A first break K1 is disposed between the first data connection line 81 and the first power supply line 91, and the first break K1 cuts off the first data connection line 81 and the first power supply line 91. In other cell rows, the first interposer may include only the first power supply line 91.

[0152] In an exemplary embodiment, at least one second interposer may include a second data connection line 82 and a second power supply line 92 disposed in the same cell column and sequentially arranged along the second direction Y. A second break K2 is disposed between the second data connection line 82 and the second power supply line 92, and the second break K2 cuts off the second data connection line 82 and the second power supply line 92. In other cell columns, the second interposer may include only the second power supply line 92.

[0153] In an exemplary embodiment, the second data link line 82 may be connected to the first data link line 81 through a via, and the first data link line 81 may be connected to the data signal line 72 through a via, that is, the second data link line 82 is connected to the data signal line 72 through the first data link line 81 .

[0154] In an exemplary embodiment, the driving structure layer of the first display area may further include at least one power connection line 70 . The power connection line 70 may be shaped like a broken line extending along the second direction Y. The power connection line 70 is configured to be connected to the first power line 71 .

[0155] In an exemplary embodiment, the second data connection line 82 and the second power supply line 92 can be set only in the first circuit unit, and the power connection line 70 can be set only in the second circuit unit, that is, the power connection line 70 is not set in the normal unit column (first circuit unit), and the second insertion line is not set in the insertion unit column (second circuit unit), so as to reduce the circuit difference between the first circuit unit and the second circuit unit, avoid the load difference of the data signal caused by the circuit difference, and improve the display quality.

[0156] In an exemplary embodiment, at least one circuit unit (including a first circuit unit and a second circuit unit) may include at least a first connection electrode 51, a third connection electrode 53, and a fifth connection electrode 55. The first connection electrode 51 may be connected to the second electrode of the first transistor T1 and the first plate of the storage capacitor, respectively. The third connection electrode 53 may be connected to the first electrode of the fifth transistor T5 and the second plate of the storage capacitor, respectively. The fifth connection electrode 55 may be connected to the first electrode of the first transistor T1.

[0157] In an exemplary embodiment, in at least one first circuit unit, the first connection electrode 51, the third connection electrode 53, and the fifth connection electrode 55 may be isolated, i.e., not connected. In at least one second circuit unit, the first connection electrode 51 may be connected to the third connection electrode 53 and the fifth connection electrode 55, respectively, to form a power connection line 70 extending along the second direction Y.

[0158] In an exemplary embodiment, in at least one second circuit unit, the third connection electrode 53 and the fifth connection electrode 55 are both connected to the first power supply line 91, so that the power connection line 70 forms a mesh-like connection structure with the first power supply line 91. In at least another second circuit unit, the third connection electrode 53 and the fifth connection electrode 55 are not connected to the first data connection line 81.

[0159] In an exemplary embodiment, at least one first circuit unit is further provided with a data connection bar 83 and a data connection block 84. The data connection bar 83 may be in the shape of a bar extending along the second direction Y, and the data connection block 84 may be in the shape of a block (e.g., a rectangle). A first end of the data connection bar 83 is connected to the first data connection line 81, and a second end of the data connection bar 83 is connected to the second data connection line 82. That is, the first data connection line 81 is connected to the second data connection line 82 via the data connection bar 83 and the data connection block 84.

[0160] In an exemplary embodiment, at least one first circuit unit is further provided with a dummy connection bar 93 and a dummy connection block 94. The dummy connection bar 93 may be in the shape of a bar extending along the second direction Y, and the dummy connection block 94 may be in the shape of a block (e.g., a rectangle). The first end of the dummy connection bar 93 is located on one side of the first power trace 91, and the second end of the dummy connection bar 93 is connected to the dummy connection block 94. The dummy connection block 94 is connected to the second power trace 92.

[0161] In an exemplary embodiment, the position and shape of the data connection bar 83 in one first circuit unit are the same as the position and shape of the dummy connection bar 93 in another first circuit unit, and the position and shape of the data connection block 84 in one first circuit unit are the same as the position and shape of the dummy connection block 94 in another first circuit unit.

[0162] In an exemplary embodiment, the driving structure layer may include multiple conductive layers in a direction perpendicular to the display substrate. The multiple conductive layers may include at least a first source-drain metal layer (third conductive layer), a second source-drain metal layer (fourth conductive layer) disposed on a side of the first source-drain metal layer away from the substrate, and a third source-drain metal layer (fifth conductive layer) disposed on a side of the second source-drain metal layer away from the substrate. The power connection line 70, the first data connection line 81, and the first power trace 91 may be disposed in the first source-drain metal layer, the first power line 71 may be disposed in the second source-drain metal layer, and the data signal line 72, the second data connection line 82, and the second power trace 92 may be disposed in the third source-drain metal layer.

[0163] The following is an exemplary description of the preparation process of the substrate shown in this exemplary embodiment. The "patterning process" mentioned in this disclosure includes processes such as depositing a film layer, coating a photoresist on the film layer, mask exposure, development, etching, and stripping the photoresist for metal materials, inorganic materials, or transparent conductive materials. For organic materials, it includes processes such as coating an organic material, mask exposure, and development. Deposition can be achieved by any one or more of sputtering, evaporation, and chemical vapor deposition. Coating can be achieved by any one or more of spraying, spin coating, and inkjet printing. Etching can be achieved by any one or more of dry etching and wet etching, and this disclosure does not limit this. "Thin film" refers to a thin film made by depositing, coating, or other processes on a substrate using a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are provided in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps the boundary of the orthographic projection of B.

[0164] In an exemplary embodiment, taking 16 circuit units in two unit rows (the Mth unit row and the M+1th unit row) and eight unit columns (the Nth unit column to the N+7th unit column) as an example, the preparation process of the display substrate of this embodiment may include the following operations. The Nth unit column, the N+2th unit column to the N+5th unit column, and the N+7th unit column are normal unit columns, and the circuit units in these unit columns are first circuit units. The N+1th unit column and the N+6th unit column are inserted unit columns, and the circuit units in these unit columns are second circuit units.

[0165] (11) Forming a semiconductor layer pattern. In an exemplary embodiment, forming the semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on a substrate, patterning the semiconductor film through a patterning process to form a first insulating layer disposed on the substrate, and a semiconductor layer pattern disposed on the first insulating layer, as shown in FIG. 13 .

[0166] In an exemplary embodiment, the semiconductor layer pattern of each circuit unit (including the first circuit unit and the second circuit unit) in the first display area may include at least the first active layer 11 of the first transistor T1 to the seventh active layer 17 of the seventh transistor T7, and the first active layer 11 to the seventh active layer 17 may be an integrated structure connected to each other.

[0167] In an exemplary embodiment, in the second direction Y, the first active layer 11, the second active layer 12, and the fourth active layer 14 may be located on a side of the third active layer 13 in the opposite direction of the second direction Y, and the fifth active layer 15, the sixth active layer 16, and the seventh active layer 17 may be located on a side of the third active layer 13 in the second direction Y.

[0168] In an exemplary embodiment, the third active layer 13 may have an Ω shape, the first active layer 11 may have an n shape, the second active layer 12, the fifth active layer 15, and the sixth active layer 16 may have an L shape, and the fourth active layer 14 and the seventh active layer 17 may have an I shape.

[0169] In an exemplary embodiment, each of the first to seventh active layers 11 to 17 may include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, the second region 11-2 of the first active layer and the first region 12-1 of the second active layer may be interconnected, and the second region 11-2 of the first active layer may serve as the first region 12-1 of the second active layer. The first region 13-1 of the third active layer, the second region 14-2 of the fourth active layer, and the second region 15-2 of the fifth active layer may be interconnected, and the first region 13-1 of the third active layer may serve as both the second region 14-2 of the fourth active layer and the second region 15-2 of the fifth active layer. The second region 12-2 of the second active layer, the second region 13-2 of the third active layer, and the first region 16-1 of the sixth active layer may be interconnected, and the second region 12-2 of the second active layer may serve as both the second region 13-2 of the third active layer and the first region 16-1 of the sixth active layer. The second region 16-2 of the sixth active layer and the second region 17-2 of the seventh active layer can be connected to each other, and the second region 16-2 of the sixth active layer can serve as the second region 17-2 of the seventh active layer. The first region 11-1 of the first active layer, the first region 14-1 of the fourth active layer, the first region 15-1 of the fifth active layer, and the first region 17-1 of the seventh active layer can be provided separately.

[0170] In an exemplary embodiment, the first region 17-1 of the seventh active layer in the circuit unit can be disposed in a circuit unit in the next unit row. For example, the first region 17-1 of the seventh active layer of the circuit unit in the M-1th unit row can be disposed in a circuit unit in the Mth unit row. For another example, the first region 17-1 of the seventh active layer of the circuit unit in the Mth unit row can be disposed in a circuit unit in the M+1th unit row.

[0171] In example embodiments, positions and shapes of semiconductor layers in a plurality of circuit cells in one cell row may be substantially the same, and positions and shapes of semiconductor layers in a plurality of circuit cells in one cell column may be substantially the same.

[0172] In an exemplary embodiment, in this process, the semiconductor layer in the second display area is etched away to form a first insulating layer disposed on the substrate.

[0173] In an exemplary embodiment, the semiconductor layer may be made of polycrystalline silicon (p-Si), i.e., the third to seventh transistors are LTPS transistors. In an exemplary embodiment, patterning the semiconductor film through a patterning process may include: first forming an amorphous silicon (a-Si) film on a first insulating film, performing a dehydrogenation treatment on the amorphous silicon film, and then crystallizing the dehydrogenated amorphous silicon film to form a polycrystalline silicon film. Subsequently, patterning the polycrystalline silicon film to form a semiconductor layer pattern.

[0174] (12) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on the substrate having the aforementioned pattern formed thereon, patterning the first conductive film through a patterning process to form a second insulating layer covering the semiconductor layer, and a first conductive layer pattern disposed on the second insulating layer, as shown in FIG14A and FIG14B , where FIG14B is a plan view schematic diagram of the first conductive layer in FIG14A . In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0175] In an exemplary embodiment, the first conductive layer pattern of each circuit unit (including the first circuit unit and the second circuit unit) in the first display area may include at least a first scan signal line 21, a second scan signal line 22, a light emitting signal line 23 and a first plate 31 of a storage capacitor.

[0176] In an exemplary embodiment, the shape of the first electrode plate 31 of the storage capacitor can be rectangular, and the corners of the rectangle can be provided with chamfers or grooves. The orthographic projection of the first electrode plate 31 on the substrate at least partially overlaps with the orthographic projection of the third active layer on the substrate. The first electrode plate 31 can serve as the lower plate of the storage capacitor and the gate electrode of the third transistor T3 at the same time.

[0177] In an exemplary embodiment, the first scan signal line 21 may be in the shape of a straight line or a zigzag line extending along the first direction X, and may be disposed on the side of the first electrode plate 31 opposite to the second direction Y. A gate block 21-1 is disposed on the first scan signal line 21 of each circuit unit. The gate block 21-1 may be in the shape of a bar extending along the second direction Y. The first end of the gate block 21-1 is connected to the side of the first scan signal line 21 closer to the first electrode plate 31, and the second end of the gate block 21-1 extends toward the first electrode plate 31. The region where the first scan signal line 21 and the gate block 21-1 overlap with the second active layer may serve as the gate electrode of the second transistor T2 of the dual-gate structure, and the region where the first scan signal line 21 overlaps with the fourth active layer may serve as the gate electrode of the fourth transistor T4.

[0178] In an exemplary embodiment, in at least one unit row, the first scan signal line 21 and the gate blocks 21 - 1 of the plurality of circuit units may be an integrated structure connected to each other.

[0179] In an exemplary embodiment, the second scan signal line 22 may be in the shape of a straight line or a zigzag line extending along the first direction X. It may be disposed on the side of the first scan signal line 21 away from the first electrode 31. The region where the second scan signal line 22 overlaps the first active layer in the current circuit unit may serve as the gate electrode of the first transistor T1 of the dual-gate structure in the current circuit unit, and the region where the second scan signal line 22 overlaps the seventh active layer in the previous circuit unit may serve as the gate electrode of the seventh transistor T7 in the previous circuit unit. This means that the seventh transistor T7 of the circuit unit in the M-1th unit row is controlled by the second scan signal line 22 in the Mth unit row, and the seventh transistor T7 of the circuit unit in the Mth unit row is controlled by the second scan signal line 22 in the M+1th unit row. The current circuit unit refers to the circuit unit in the current unit row, and the previous circuit unit refers to the circuit unit in the previous unit row. In terms of timing control, the second scan signal line in the next unit row is equivalent to the first scan signal line in the current unit row, and thus the seventh transistor T7 in the circuit unit in the Mth unit row is equivalent to the first scan signal line in the Mth unit row.

[0180] In an exemplary embodiment, the light emitting signal line 23 may be in the shape of a straight line or a broken line extending along the first direction X, and may be disposed on one side of the first electrode plate 31 in the second direction Y. The region where the light emitting signal line 23 overlaps with the fifth active layer may serve as the gate electrode of the fifth transistor T5, and the region where the light emitting signal line 23 overlaps with the sixth active layer may serve as the gate electrode of the sixth transistor T6.

[0181] In an exemplary embodiment, positions and shapes of the first conductive layers in a plurality of circuit cells in one cell row may be substantially the same, and positions and shapes of the first conductive layers in a plurality of circuit cells in one cell column may be substantially the same.

[0182] In an exemplary embodiment, in this process, the first conductive layer in the second display area is etched away to form a second insulating layer disposed on the first insulating layer.

[0183] (13) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on the substrate having the aforementioned pattern formed thereon, patterning the second conductive film through a patterning process to form a third insulating layer covering the first conductive layer pattern, and a second conductive layer pattern disposed on the third insulating layer, as shown in FIG15A and FIG15B , where FIG15B is a plan view schematic diagram of the second conductive layer in FIG15A . In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0184] In an exemplary embodiment, the second conductive layer pattern of each circuit unit (including the first circuit unit and the second circuit unit) in the first display area includes at least: a second plate 32 of the storage capacitor, a first initial signal line 41, a second initial signal line 42, a first shielding electrode 43 and a second shielding electrode 44.

[0185] In an exemplary embodiment, the outline of the second plate 32 of the storage capacitor can be rectangular, and the corners of the rectangle can be provided with chamfers or grooves. The orthographic projection of the second plate 32 on the substrate at least partially overlaps with the orthographic projection of the first plate 31 on the substrate. The second plate 32 can serve as the upper plate of the storage capacitor, and the first plate 31 and the second plate 32 constitute a storage capacitor.

[0186] In an exemplary embodiment, an opening 33 is provided on the second electrode plate 32. Opening 33 can be rectangular and located in the central region of the second electrode plate 32, forming a ring-shaped second electrode plate 32. Opening 33 exposes the third insulating layer covering the first electrode plate 31, and the orthographic projection of the first electrode plate 31 on the substrate includes the orthographic projection of the opening 33 on the substrate. In an exemplary embodiment, opening 33 is configured to accommodate a seventh via hole to be formed later. The seventh via hole is located within opening 33 and exposes the first electrode plate 31, allowing a first connecting electrode to be formed later to connect to the first electrode plate 31.

[0187] In an exemplary embodiment, the second electrode plate 32 may be provided with a plate connection bar 34. The plate connection bar 34 may be in the shape of a bar extending along the first direction X. The plate connection bar 34 may be provided on one side of the second electrode plate 32 in the first direction X or on a side opposite to the first direction X. The first end of the plate connection bar 34 is connected to the second electrode plate 32 in the current circuit unit, and the second end of the plate connection bar 34 is connected to the second electrode plate 32 in the adjacent circuit unit in the first direction X.

[0188] In an exemplary embodiment, the second plates 32 and plate connection bars 34 in two adjacent circuit cells in a cell row can be interconnected as a single, integrated structure. For example, the second plates 32 in the Nth cell column and the second plates 32 in the N+1th cell column are interconnected via the plate connection bars 34, forming a connected, integrated structure. Because the second plates 32 in each circuit cell are connected to a subsequently formed first power line, by forming the second plates 32 of adjacent circuit cells into a connected, integrated structure, the second plates of this integrated structure can be reused as lateral power signal lines, ensuring that multiple second plates in a cell row have the same potential, which helps improve panel uniformity, avoid display defects on the display substrate, and ensure the display quality of the display substrate.

[0189] In an exemplary embodiment, the first initial signal line 41 may be in the shape of a straight line or a zigzag line extending along the first direction X, and may be disposed between the first scan signal line 21 and the second scan signal line 22. A first initial connection block 41-1 may be disposed on the first initial signal line 41. The first initial connection block 41-1 may be in the shape of a block (e.g., a rectangle). A first end of the first initial connection block 41-1 is connected to a side of the first initial signal line 41 away from the second electrode plate 32, and a second end of the first initial connection block 41-1 extends in a direction away from the second electrode plate 32. The first initial connection block 41-1 is configured to be connected to the first region of the first active layer via a fifth connection electrode formed subsequently.

[0190] In an exemplary embodiment, in at least one cell row, the first preliminary signal line 41 and the first preliminary connection block 41 - 1 may be an integral structure connected to each other.

[0191] In an exemplary embodiment, the second initial signal line 42 may be in the shape of a straight line or a zigzag line extending along the first direction X, and may be disposed on a side of the second scan signal line 22 away from the first scan signal line 21. A second initial connection block 42-1 may be disposed on the second initial signal line 42. The second initial connection block 42-1 may be in the shape of a block (e.g., a rectangle) and connected to the second initial signal line 42. The second initial connection block 42-1 is configured to be connected to the first region of the seventh active layer via a subsequently formed sixth connection electrode.

[0192] In an exemplary embodiment, the orthographic projection of the second initial signal line 42 on the substrate at least partially overlaps with the orthographic projection of the first active layer between the two gate electrodes of the first transistor T1 on the substrate. The second initial signal line 42 can shield the node between the two gate electrodes of the first transistor T1, thereby preventing the influence of the data voltage jump on the first transistor T1, reducing the influence of the data voltage jump on the normal operation of the pixel driving circuit, and improving the display effect.

[0193] In an exemplary embodiment, in at least one cell row, the second preliminary signal line 42 and the second preliminary connection block 42 - 1 may be an integral structure connected to each other.

[0194] In an exemplary embodiment, the first shielding electrode 43 can be block-shaped (e.g., rectangular) and can be disposed on a side of the second plate 32 proximate to the first scan signal line 21. A first end of the first shielding electrode 43 is connected to a side of the second plate 32 proximate to the first scan signal line 21, and a second end of the first shielding electrode 43 extends toward the first scan signal line 21. The orthographic projection of the first shielding electrode 43 on the substrate at least partially overlaps with the orthographic projection of the second active layer between the two gate electrodes of the second transistor T2 on the substrate. In an exemplary embodiment, the first shielding electrode 43 is configured to shield the node between the two gate electrodes of the second transistor T2, thereby preventing data voltage jumps from affecting the second transistor T2, reducing the impact of data voltage jumps on the normal operation of the pixel driving circuit, and improving display quality.

[0195] In an exemplary embodiment, in at least one circuit unit, the second electrode plate 32 and the first shielding electrode 43 may be an integrated structure connected to each other.

[0196] In an exemplary embodiment, the shape of the second shielding electrode 44 may be block-shaped (such as a rectangle), and may be provided on a side of the first initial signal line 41 close to the first scanning signal line 21. The first end of the second shielding electrode 44 is connected to the side of the first initial signal line 41 close to the first scanning signal line 21, and the second end of the second shielding electrode 44 extends in a direction close to the first scanning signal line 21. In the first direction X, the second shielding electrode 44 may be located between the first region of the second active layer (also the second region of the first active layer) and the first region of the fourth active layer. In an exemplary embodiment, the second shielding electrode 44 is configured as a shielding bar between the second transistor T2 and the fourth transistor T4, isolating the influence of the data voltage jump of the fourth transistor T4 on the first electrode of the second transistor T2 (the first node of the pixel driving circuit), reducing the influence of the data voltage jump on the normal operation of the pixel driving circuit, and improving the display effect. Shielding

[0197] In an exemplary embodiment, in at least one circuit unit, the first preliminary signal line 41 and the second shielding electrode 44 may be an integral structure connected to each other.

[0198] In an exemplary embodiment, positions and shapes of the second conductive layers in a plurality of circuit cells in one cell row may be substantially the same, and positions and shapes of the second conductive layers in a plurality of circuit cells in one cell column may be substantially the same.

[0199] In an exemplary embodiment, in this process, the second conductive layer in the second display area is etched away to form a third insulating layer disposed on the second insulating layer.

[0200] (14) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate having the aforementioned pattern formed thereon, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the second conductive layer, wherein a plurality of vias are provided on the fourth insulating layer, as shown in FIG. 16 .

[0201] In an exemplary embodiment, the plurality of vias of at least one circuit unit in the first display area may include at least a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, and a tenth via V10.

[0202] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first region of the first active layer on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer within the first via hole V1 are etched away to expose the surface of the first region of the first active layer, and the first via hole V1 is configured to connect a subsequently formed fifth connecting electrode to the first region of the first active layer through the via hole.

[0203] In an exemplary embodiment, the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the second area of ​​the first active layer (also the first area of ​​the second active layer) on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the second via hole V2 are etched away to expose the surface of the second area of ​​the first active layer (also the first area of ​​the second active layer), and the second via hole V2 is configured to connect the subsequently formed first connecting electrode to the second area of ​​the first active layer (also the first area of ​​the second active layer) through the via hole.

[0204] In an exemplary embodiment, the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first region of the fourth active layer on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the third via hole V3 are etched away to expose the surface of the first region of the fourth active layer, and the third via hole V3 is configured to connect a subsequently formed second connecting electrode to the first region of the fourth active layer through the via hole.

[0205] In an exemplary embodiment, the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the first region of the fifth active layer on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the fourth via hole V4 are etched away to expose the surface of the first region of the fifth active layer, and the fourth via hole V4 is configured to connect a subsequently formed third connecting electrode to the first region of the fifth active layer through the via hole.

[0206] In an exemplary embodiment, the orthographic projection of the fifth via hole V5 on the substrate is located within the range of the orthographic projection of the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer) on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the fifth via hole V5 are etched away to expose the surface of the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer), and the fifth via hole V5 is configured to connect the subsequently formed fourth connecting electrode to the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer) through the via hole.

[0207] In an exemplary embodiment, the orthographic projection of the sixth via hole V6 on the substrate is located within the range of the orthographic projection of the first region of the seventh active layer on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the sixth via hole V6 are etched away to expose the surface of the first region of the seventh active layer, and the sixth via hole V6 is configured to connect a subsequently formed sixth connecting electrode to the first region of the seventh active layer through the via hole.

[0208] In an exemplary embodiment, the orthographic projection of the seventh via hole V7 on the substrate is located within the range of the orthographic projection of the opening 33 on the substrate, the third insulating layer and the fourth insulating layer in the seventh via hole V7 are etched away to expose the surface of the first electrode 31, and the seventh via hole V7 is configured to connect the subsequently formed first connecting electrode to the first electrode 31 through the via hole.

[0209] In an exemplary embodiment, the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the second electrode plate 32 on the substrate, the fourth insulating layer in the eighth via V8 is etched away, exposing the surface of the second electrode plate 32, and the eighth via V8 is configured to connect the subsequently formed third connecting electrode to the second electrode plate 32 through the via.

[0210] In an exemplary embodiment, the orthographic projection of the ninth via V9 on the substrate is located within the range of the orthographic projection of the first initial connection block 41-1 of the first initial signal line 41 on the substrate, the fourth insulating layer in the ninth via V9 is etched away, exposing the surface of the first initial connection block 41-1, and the ninth via V9 is configured to connect the subsequently formed fifth connection electrode to the first initial connection block 41-1 through the via.

[0211] In an exemplary embodiment, since a power connection line is formed in the second circuit unit in a subsequent process and the power connection line is connected to the first power line, the second circuit unit is not provided with a ninth via V9, that is, the fifth connection electrode of the second circuit unit formed subsequently is not connected to the first initial signal line.

[0212] In an exemplary embodiment, the orthographic projection of the tenth via V10 on the substrate is located within the range of the orthographic projection of the second initial connection block 42-1 of the second initial signal line 42 on the substrate, the fourth insulating layer in the tenth via V10 is etched away, exposing the surface of the second initial connection block 42-1, and the tenth via V10 is configured to connect the subsequently formed sixth connection electrode to the second initial connection block 42-1 through the via.

[0213] In an exemplary embodiment, in this process, the second display region forms a fourth insulating layer disposed on the third insulating layer.

[0214] (15) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the third conductive film using a patterning process to form a third conductive layer disposed on the fourth insulating layer, as shown in FIG17A and FIG17B , where FIG17B is a plan view schematic diagram of the third conductive layer in FIG17A . In an exemplary embodiment, the third conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0215] In an exemplary embodiment, the third conductive layer of each circuit unit (including the first circuit unit and the second circuit unit) in the first display area includes at least: a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54, a fifth connection electrode 55 and a sixth connection electrode 56.

[0216] In an exemplary embodiment, the first connection electrode 51 may be in the shape of a strip with a main portion extending along the second direction Y. A first end of the first connection electrode 51 is connected to the second region of the first active layer (also the first region of the second active layer) via a second via hole V2, and a second end of the first connection electrode 51 is connected to the first electrode plate 31 via a seventh via hole V7. Because the first electrode plate 31 serves as the gate electrode of the third transistor T3, the first connection electrode 51 interconnects the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first electrode plate 31 of the storage capacitor, thereby forming a first node N1 of the pixel driving circuit.

[0217] In an exemplary embodiment, the second connection electrode 52 may be block-shaped (eg, rectangular), connected to the first region of the fourth active layer through the third via hole V3, and configured to be connected to a first data connection electrode formed subsequently.

[0218] In an exemplary embodiment, the third connection electrode 53 may be in the shape of a strip extending along the second direction Y. A first end of the third connection electrode 53 is connected to the first region of the fifth active layer via a fourth via V4, and a second end of the third connection electrode 53 is connected to the second electrode plate 32 via an eighth via V8. The third connection electrode 53 is configured to be connected to a first power line to be formed later. In an exemplary embodiment, the third connection electrode 53 interconnects the first electrode of the fifth transistor T5 and the second electrode plate 32 of the storage capacitor, and the first electrode of the fifth transistor T5 and the second electrode plate 32 of the storage capacitor have the same potential.

[0219] In an exemplary embodiment, the shape of the fourth connecting electrode 54 can be block-shaped (such as rectangular), and the fourth connecting electrode 54 is connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) through the fifth via V5. The fourth connecting electrode 54 is configured to be connected to the first anode connecting electrode formed subsequently.

[0220] In an exemplary embodiment, the fifth connection electrode 55 may be in the shape of a strip extending along the first direction X. In the first circuit unit, the first end of the fifth connection electrode 55 is connected to the first region of the first active layer via the first via V1, and the second end of the fifth connection electrode 55 is connected to the first initial connection block 41-1 via the ninth via V9. Because the first initial connection block 41-1 is connected to the first initial signal line 41, the fifth connection electrode 55 enables the first initial signal line 41 to write the first initial signal to the first electrode of the first transistor T1. In the second circuit unit, the first end of the fifth connection electrode 55 is connected to the first region of the first active layer via the first via V1, and the second end of the fifth connection electrode 55 is not connected to the first initial connection block 41-1.

[0221] In an exemplary embodiment, a connecting bar 55-1 may be provided on the fifth connecting electrode 55. The connecting bar 55-1 may be in an "n" shape and may be provided on a side of the fifth connecting electrode 55 away from the second electrode plate 32. A first end of the connecting bar 55-1 is connected to a first end of the fifth connecting electrode 55, and a second end of the connecting bar 55-1 is connected to a second end of the fifth connecting electrode 55, so that the fifth connecting electrode 55 and the connecting bar 55-1 form a ring shape.

[0222] In an exemplary embodiment, the sixth connection electrode 56 may be in the shape of a strip extending along the second direction Y. A first end of the sixth connection electrode 56 is connected to the first region of the seventh active layer via a sixth via hole V6, and a second end of the sixth connection electrode 56 is connected to the second initial connection block 42-1 via a tenth via hole V10. Because the second initial connection block 42-1 is connected to the second initial signal line 42, the sixth connection electrode 56 enables the second initial signal line 42 to write the second initial signal to the first electrode of the seventh transistor T7.

[0223] In an exemplary embodiment, the third conductive layer of at least one circuit unit in the first display area may further include a first inserted line. The shape of the first inserted line may be a straight line or a broken line extending along the first direction X, and may be located between the light-emitting signal line 23 of the current unit row and the second initial signal line 42 of the next unit row.

[0224] In an exemplary embodiment, at least one first insertion line may include at least a first data connection line 81 and a first power trace 91, the first data connection line 81 may be arranged in the first area (FIP area), and the first power trace 91 may be arranged in the second area (non-FIP area or SIP area).

[0225] In an exemplary embodiment, in the second area (non-FIP area or SIP area), the first insertion line may include only the first power trace 91 .

[0226] In an exemplary embodiment, a first break K1 may be provided between the first data connection line 81 and the first power line 91 in the same cell row. The first break K1 may cut off the first data connection line 81 located in the FIP area from the first power line 91 located in the non-FIP area, so that the first data connection line 81 and the first power line 91 on both sides of the first break K1 are insulated from each other.

[0227] In an exemplary embodiment, an end of the first data connection line 81 away from the first break K1 is configured to be connected to a subsequently formed data signal line, and an end of the first data connection line 81 close to the first break K1 is configured to be connected to a subsequently formed second data connection line.

[0228] In an exemplary embodiment, in at least one first circuit unit in the first region (FIP region), a data connection bar 83 and a data connection block 84 may be provided on the first data connection line 81. The data connection bar 83 may be in the shape of a bar extending along the second direction Y, and the data connection block 84 may be in the shape of a block (e.g., a rectangle). The data connection bar 83 and the data connection block 84 may be provided on a side of the first data connection line 81 close to the first scan signal line 21. The first end of the data connection bar 83 is connected to a side of the first data connection line 81 close to the first scan signal line 21, and the second end of the data connection bar 83 extends toward the first scan signal line 21 and then connects to the data connection block 84. The data connection block 84 is configured to connect to a second data connection line formed subsequently.

[0229] In an exemplary embodiment, the first circuit unit where the data connection bar 83 and the data connection block 84 are provided may be the first circuit unit close to the first break K1 .

[0230] In an exemplary embodiment, in at least one first circuit unit, the first data connection line 81 , the data connection bar 83 , and the data connection block 84 may be an integrated structure connected to each other.

[0231] In an exemplary embodiment, at least one first circuit unit in the first display area may further include a dummy connection bar 93 and a dummy connection block 94. The dummy connection bar 93 may be in the shape of a bar extending along the second direction Y, and the dummy connection block 94 may be in the shape of a block (e.g., a rectangle). The dummy connection bar 93 and the dummy connection block 94 may be disposed on a side of the first power supply line 91 (or the first data connection line 81) close to the first scan signal line 21. The first end of the dummy connection bar 93 is located on a side of the first power supply line 91 (or the first data connection line 81) close to the first scan signal line 21. The second end of the dummy connection bar 93 extends toward the first scan signal line 21 and is connected to the dummy connection block 94. The dummy connection block 94 is configured to connect to a second power supply line that will be formed later.

[0232] In an exemplary embodiment, in at least one first circuit unit, the dummy connection bar 93 and the dummy connection block 94 may be an integral structure connected to each other.

[0233] In an exemplary embodiment, the position and shape of the dummy connection bar 93 in one first circuit unit and the data connection bar 83 in another first circuit unit can be substantially the same, and the position and shape of the dummy connection block 94 in one first circuit unit and the data connection block 84 in another first circuit unit can be substantially the same, except that the data connection bar 83 is connected to the first data connection line 81, while the dummy connection bar 93 is not connected to the first power supply line 91 (or the first data connection line 81). The present disclosure provides data connection bars and dummy connection bars, and data connection blocks and dummy connection blocks with identical morphologies and via connection structures. By designing the transition areas identically, not only can the uniformity of subsequent etching processes be improved, but different areas can also achieve the same display effect under transmitted and reflected light, achieving shadow elimination, effectively avoiding the poor appearance of the display substrate and the occurrence of off-screen watermarks (mura), and improving display quality.

[0234] In an exemplary embodiment, since the subsequently formed second data connection lines and second power supply traces are only provided in the first circuit unit and not in the second circuit unit, the dummy connection blocks and the data connection blocks may be provided only in the first circuit unit.

[0235] In an exemplary embodiment, the first region (FIP region) may include a plurality of first circuit units and a plurality of second circuit units. The third conductive layer of at least one second circuit unit in the first region may further include an eleventh connection electrode 61 and a twelfth connection electrode 62 .

[0236] In an exemplary embodiment, the eleventh connection electrode 61 may be shaped like a strip extending along the second direction Y and may be disposed between the first connection electrode 51 and the fifth connection electrode 55 , with a first end of the eleventh connection electrode 61 connected to the first connection electrode 51 and a second end of the eleventh connection electrode 61 connected to the fifth connection electrode 55 .

[0237] In an exemplary embodiment, the twelfth connection electrode 62 may be in the shape of a strip extending along the first direction X, and may be disposed between the first connection electrode 51 and the third connection electrode 53 , with a first end of the twelfth connection electrode 62 connected to the first connection electrode 51 and a second end of the twelfth connection electrode 62 connected to the third connection electrode 53 .

[0238] In an exemplary embodiment, in at least one second circuit unit of the first area (FIP area), the first connection electrode 51, the third connection electrode 53, the fifth connection electrode 55, the eleventh connection electrode 61 and the twelfth connection electrode 62 can be an integrated structure connected to each other, and a power connection line extending along the second direction Y is formed in the second circuit unit.

[0239] In an exemplary embodiment, since the third connecting electrode 53 is configured to be connected to the first power line formed subsequently, the power connection line can be reused as a vertical power signal line, forming a double-layer routing structure together with the first power line, which can effectively reduce the resistance of the first power line and reduce the voltage drop of the first power signal, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0240] In an exemplary embodiment, the second region (non-FIP region or SIP region) may include a plurality of first circuit units and a plurality of second circuit units. The third conductive layer of at least one second circuit unit in the second region may further include an eleventh connecting electrode 61, a twelfth connecting electrode 62, a thirteenth connecting electrode 63, and a fourteenth connecting electrode 64. The structures of the eleventh connecting electrode 61 and the twelfth connecting electrode 62 in the first region and the second region are substantially the same.

[0241] In an exemplary embodiment, the thirteenth connection electrode 63 may be in the shape of a strip extending along the second direction Y and may be disposed between the third connection electrode 53 and the first power supply trace 91. A first end of the thirteenth connection electrode 63 is connected to the third connection electrode 53, and a second end of the thirteenth connection electrode 63 is connected to the first power supply trace 91 of the current cell row. In an exemplary embodiment, the thirteenth connection electrode 63 implements a connection between the third connection electrode 53 and the first power supply trace 91.

[0242] In an exemplary embodiment, the fourteenth connection electrode 64 may be in the shape of a bar extending along the second direction Y and may be disposed between the connection bar 55-1 and the first power supply line 91. A first end of the fourteenth connection electrode 64 is connected to the connection bar 55-1, and a second end of the fourteenth connection electrode 64 is connected to the first power supply line 91 of the previous cell row. In an exemplary embodiment, since the connection bar 55-1 is connected to the fifth connection electrode 55, the fourteenth connection electrode 64 realizes the connection between the fifth connection electrode 55 and the first power supply line 91.

[0243] In the exemplary embodiment, because the first connection electrode 51, the third connection electrode 53, the fifth connection electrode 55, the eleventh connection electrode 61, and the twelfth connection electrode 62 in the second circuit unit are interconnected as an integrated structure, the thirteenth connection electrode 63 and the fourteenth connection electrode 64 not only interconnect the power connection line with the first power trace 91, but also interconnect multiple power connection lines in a unit column. In this way, the first power trace 91 extending along the first direction X and the power connection lines extending along the second direction Y form a meshed interconnected structure for transmitting power signals.

[0244] In this exemplary embodiment, since the first inserted line in the FIP area is the first data connection line 81, the power connection lines of the second circuit units in the FIP area are arranged at intervals. Within a unit column, the power connection lines of the second circuit units on both sides of the first data connection line 81 in the second direction Y are disconnected (i.e., not connected). Since the first inserted line in the non-FIP area is the first power trace 91, the power connection lines of the second circuit units in the non-FIP area are arranged continuously. Within a unit column, the power connection lines of the second circuit units on both sides of the first power trace 91 in the second direction Y are connected to each other via the first power trace 91.

[0245] Figure 17C is a schematic plan view of the third conductive layer at the junction of the display area and the binding area. As shown in Figure 17C , the display substrate may include a display area 100 and a binding area 200 located on one side of the display area 100 in the second direction Y. The binding area 200 may include at least a binding power trace 210. The binding power trace 210 is configured to transmit a constant first power signal and is connected to the first power line of the display area.

[0246] In an exemplary embodiment, the power connection line in the second circuit unit can extend to the binding area and connect to the binding power trace 210, so that the power connection line transmits a constant first power signal, which can effectively prevent the occurrence of process static electricity.

[0247] Figure 17D is a plan view of the third conductive layer at the junction of the display area and the upper frame area. As shown in Figure 17D, the display substrate may include a display area 100, frame areas 300 located on both sides of the display area 100 in a first direction X, and a frame area 300 located on the side opposite the display area 100 in a second direction Y. The frame area 300 located on the side opposite the display area 100 in the second direction Y may be referred to as the upper frame area. The upper frame area may include at least a frame power trace 310, which is configured to transmit a constant first power signal and is connected to the first power line of the display area.

[0248] In an exemplary embodiment, the power connection line in the second circuit unit can extend to the upper frame area and connect to the frame power line 310, so that the power connection line transmits a constant first power signal, which can effectively prevent the occurrence of process static electricity.

[0249] In an exemplary embodiment, because the first display area utilizes a compressed circuit configuration, the pixel driver circuit has a high routing density. Static electricity generated during the manufacturing process can easily accumulate, leading to damage and short circuits in the pixel driver circuit. For example, the first scan signal line, second scan signal line, and light-emitting signal line in the first conductive layer, and the first initial signal line and second initial signal line in the second conductive layer are all relatively long signal lines. Because there are no paths to connect to other signal lines, static electricity can easily accumulate on these long signal lines. When the connecting electrodes in the third conductive layer are connected to the second conductive layer and the semiconductor layer through vias, static electricity can easily be released at the point where the resistance of the channel region of the semiconductor layer changes from low resistance to high resistance, damaging the transistors. In the disclosed embodiment, power supply connection lines are formed in the second circuit unit, and the power supply connection lines are connected to the first power supply signal at the upper frame and the binding area. This allows static electricity from the longer signal lines in the first and second conductive layers to be transferred to the third conductive layer. This static electricity is then directed from the display area to the upper frame and the binding area through a meshed interconnect structure. This effectively eliminates static electricity accumulation generated during the manufacturing process, effectively preventing damage and short circuits in the pixel driver circuit transistors, and improving product quality.

[0250] In an exemplary embodiment, the first power line 91 extending along the first direction X and the power connection line extending along the second direction Y form a mesh-like mesh connection structure for transmitting the first power signal, which can not only effectively reduce the resistance of the first power line, reduce the voltage drop of the first power signal, effectively improve the uniformity of the first power signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality, but also can significantly reduce the width of the binding power line in the binding area and the border power line in the border area, greatly reducing the width of the upper and lower borders, improving the screen-to-body ratio, and facilitating the realization of full-screen display.

[0251] In an exemplary embodiment, in this process, the third conductive layer in the second display area is etched away.

[0252] (16) Forming a fifth insulating layer and a first planar layer pattern. In an exemplary embodiment, forming the fifth insulating layer and the first planar layer pattern may include: depositing a fifth insulating film on the substrate on which the aforementioned pattern is formed, then coating the first planar film, patterning the fifth insulating film and the first planar film using a patterning process to form a fifth insulating layer covering the third conductive layer pattern and a first planar layer disposed on the fifth insulating layer, wherein a plurality of vias are disposed on the fifth insulating layer and the first planar layer, as shown in FIG. 18 .

[0253] In an exemplary embodiment, the plurality of via holes in each circuit unit (including the first circuit unit and the second circuit unit) in the first display area includes at least a twenty-first via hole V21 , a twenty-second via hole V22 , and a twenty-third via hole V23 .

[0254] In an exemplary embodiment, the orthographic projection of the twenty-first via hole V21 on the substrate is located within the range of the orthographic projection of the second connecting electrode 52 on the substrate, the first flat layer and the fifth insulating layer in the twenty-first via hole V21 are removed, exposing the surface of the second connecting electrode 52, and the twenty-first via hole V21 is configured to connect the subsequently formed first data connecting electrode to the second connecting electrode 52 through the via hole.

[0255] In an exemplary embodiment, the orthographic projection of the twenty-second via hole V22 on the substrate is located within the range of the orthographic projection of the third connecting electrode 53 on the substrate, the first flat layer and the fifth insulating layer in the twenty-second via hole V22 are removed, exposing the surface of the third connecting electrode 53, and the twenty-second via hole V22 is configured to connect the subsequently formed first power line to the third connecting electrode 53 through the via hole.

[0256] In an exemplary embodiment, the orthographic projection of the twenty-third via hole V23 on the substrate is located within the range of the orthographic projection of the fourth connecting electrode 54 on the substrate, the first flat layer and the fifth insulating layer in the twenty-third via hole V23 are removed, exposing the surface of the fourth connecting electrode 54, and the twenty-third via hole V23 is configured to connect the subsequently formed first anode connecting electrode to the fourth connecting electrode 54 through the via hole.

[0257] In an exemplary embodiment, at least one first circuit unit may further include a twenty-fourth via hole V24. The orthographic projection of the twenty-fourth via hole V24 on the substrate is located within the range of the orthographic projection of the data connection block 84 on the substrate. The first planar layer and the fifth insulating layer within the twenty-fourth via hole V24 are removed, exposing the surface of the data connection block 84. The twenty-fourth via hole V24 is configured to connect a subsequently formed second data connection line to the data connection block 84 through the via hole.

[0258] In an exemplary embodiment, at least one first circuit unit may further include a twenty-fifth via V25. The orthographic projection of the twenty-fifth via V25 on the substrate is located within the range of the orthographic projection of the dummy connection block 94 on the substrate. The first planar layer and the fifth insulating layer within the twenty-fifth via V25 are removed, exposing the surface of the dummy connection block 94. The twenty-fifth via V25 is configured to connect a subsequently formed second power trace (or second data connection line) to the dummy connection block 94 through the via.

[0259] In an exemplary embodiment, the twenty-fourth via hole V24 and the twenty-fifth via hole V25 may be provided only in the first circuit unit.

[0260] In an exemplary embodiment, in this process, the second display region forms a fifth insulating layer disposed on the fourth insulating layer and a first planarization layer disposed on the fifth insulating layer.

[0261] (17) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on the first flat layer, as shown in FIG. 19A and FIG. 19B , where FIG. 19B is a planar schematic diagram of the fourth conductive layer in FIG. 19A . In an exemplary embodiment, the fourth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0262] In an exemplary embodiment, the fourth conductive layer of each circuit unit (including the first circuit unit and the second circuit unit) in the first display area includes at least a first power line 71 , a first data connection electrode 73 and a first anode connection electrode 74 .

[0263] In an exemplary embodiment, the first power line 71 may be in the shape of a straight line or a zigzag line, with the main portion extending along the second direction Y. The first power line 71 is connected to the third connection electrode 53 via the twenty-second via hole V22. Since the third connection electrode 53 is connected to the first region and the second electrode plate 32 of the fifth active layer respectively through the via hole, the first power line 71 can write the first power signal to the second electrode plate 32 of the storage capacitor and the first electrode of the fifth transistor T5 respectively.

[0264] In an exemplary embodiment, the first power line 71 may be a zigzag line with a variable width, and the orthographic projection of the first power line 71 on the substrate at least partially overlaps with the orthographic projection of the first connection electrode 51 on the substrate. Because the first connection electrode 51 serves as the first node N1 of the pixel driving circuit, the first power line 71, which has a constant potential, can shield the first node N1, thereby preventing the impact of data voltage jumps on the first node N1, improving the operating stability of the pixel driving circuit and enhancing the display effect.

[0265] In an exemplary embodiment, the orthographic projection of the first break K1 on the substrate can be located within the range of the orthographic projection of the first power line 71 on the substrate, so that the first power line 71 can block the first break K1 from above, which can effectively eliminate the film layer differences in different areas, is conducive to shadow elimination, and avoids poor appearance of the display substrate.

[0266] In an exemplary embodiment, since the second circuit unit is formed with a power connection line, the first power line is connected to the third connection electrode so that the power connection line in the second circuit unit and the first power line together form a double-layer routing structure, which can effectively reduce the resistance of the first power line and reduce the voltage drop of the first power signal, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0267] In an exemplary embodiment, the first data connection electrode 73 may be block-shaped (eg, rectangular), connected to the second connection electrode 52 through the twenty-first via hole V21, and configured to be connected to a subsequently formed data signal line.

[0268] In an exemplary embodiment, in at least one second circuit unit, a power connection block 73-1 may be provided on the first data connection electrode 73. The power connection block 73-1 may be block-shaped (e.g., rectangular) and may be provided between the first power line 71 and the first data connection electrode 73. A first end of the power connection block 73-1 is connected to the first data connection electrode 73, and a second end of the power connection block 73-1 is connected to the first power line 71. Because the second pixel driving circuit in the second circuit unit is not connected to the light-emitting device, the data signal line connected to the second pixel driving circuit does not have a data signal. By connecting the data signal line of the second circuit unit to the first power line 71 via the first data connection electrode 73 and the power connection block 73-1, the present disclosure can avoid floating the data signal line of the second circuit unit.

[0269] In an exemplary embodiment, since the third pixel driving circuit in the plurality of third circuit units close to the second display area is connected to the second light-emitting device in the second display area, the power connection block 73-1 is not provided in the third circuit unit, that is, there is no connection between the first data connection electrode 73 and the first power line 71 in the third circuit unit.

[0270] In an exemplary embodiment, the shape of the first anode connection electrode 74 can be block-shaped (such as rectangular), and the first anode connection electrode 74 is connected to the fourth connection electrode 54 through the twenty-third via V23. The first anode connection electrode 74 is configured to be connected to the second anode connection electrode formed subsequently.

[0271] In an exemplary embodiment, the fourth conductive layer of at least one first circuit unit may further include a second data connection electrode 75. The second data connection electrode 75 may be in a block shape (e.g., a rectangular shape), and the second data connection electrode 75 is connected to the data connection block 84 through the twenty-fourth via hole V24. The second data connection electrode 75 is configured to be connected to a second data connection line formed subsequently.

[0272] In an exemplary embodiment, the fourth conductive layer of at least one first circuit unit may further include a dummy electrode 77. The dummy electrode 77 may be in a block shape (e.g., rectangular), and the dummy electrode 77 is connected to the dummy connection block 94 through the twenty-fifth via V25. The dummy electrode 77 is configured to be connected to a second power supply line (or a second data connection line) formed subsequently.

[0273] Figure 19C is a plan view of the fourth conductive layer at the junction of the display area and the upper frame area. In an exemplary embodiment, the frame area 300 may include an upper frame area located on the side of the display area 100 away from the binding area and left and right frame areas located on both sides of the display area 100 in the first direction X. As shown in Figure 19C, the upper frame area in the frame area 300 may include at least a plurality of dummy repeating units, and at least one dummy repeating unit may include four first dummy units and one second dummy unit. The first dummy unit may include at least a first dummy pixel circuit, and the second dummy unit may include at least a second dummy pixel circuit. In an exemplary embodiment, the structure of the first dummy pixel circuit is substantially the same as that of the first pixel driver circuit in the display area 100, except that the first dummy pixel circuit is not connected to the light-emitting device. The structure of the second dummy pixel circuit is substantially the same as that of the second pixel driver circuit in the display area 100, and neither is connected to the light-emitting device.

[0274] In an exemplary embodiment, a plurality of first dummy units arranged in sequence along the second direction Y may be referred to as a first dummy column, a plurality of second dummy units arranged in sequence along the second direction Y may be referred to as a second dummy column, four first dummy columns may be provided between two adjacent second dummy columns in the first direction X, and the position of the first dummy column in the upper frame area corresponds to the position of the normal unit column in the display area, and the position of the second dummy column in the upper frame area corresponds to the position of the inserted unit column in the display area.

[0275] In an exemplary embodiment, the structures and connection relationships of the fourth conductive layer in the first dummy unit in the upper frame area and the first circuit unit in the display area may be substantially the same, and the first dummy unit may include at least a first power line, a first data connection electrode, and a first anode connection electrode, while in the second dummy unit in the upper frame area, neither corresponding vias are provided on the fifth insulating layer and the first flat layer, nor a fourth conductive layer structure is provided.

[0276] In an exemplary embodiment, the fifth insulating layer may be referred to as a passivation layer (PVX), and the vias provided in the fifth insulating layer may be referred to as passivation layer vias. Considering that the passivation layer vias are prone to introducing static electricity, the present disclosure eliminates the PVX vias and the fourth conductive layer in the second dummy unit, thereby effectively reducing the generation of static electricity and improving the efficiency of the power connection lines in the second circuit unit in discharging static electricity. This effectively eliminates static electricity accumulation generated during the manufacturing process, effectively avoids damage and short circuits to transistors in the pixel drive circuit, and improves product quality.

[0277] In an exemplary embodiment, in this process, the fourth conductive layer in the second display area is etched away.

[0278] (18) Forming a second planar layer pattern. In an exemplary embodiment, forming the second planar layer pattern may include: coating a second planar film on the substrate having the aforementioned pattern formed thereon, patterning the second planar film using a patterning process to form a second planar layer covering the fourth conductive layer pattern, wherein a plurality of vias are provided on the second planar layer, as shown in FIG. 20 .

[0279] In an exemplary embodiment, the plurality of via holes in each circuit unit (including the first circuit unit and the second circuit unit) in the first display area includes at least a thirty-first via hole V31 and a thirty-second via hole V32.

[0280] In an exemplary embodiment, the orthographic projection of the thirty-first via hole V31 on the substrate is located within the range of the orthographic projection of the first data connection electrode 73 on the substrate, the second flat layer in the thirty-first via hole V31 is removed, exposing the surface of the first data connection electrode 73, and the thirty-first via hole V31 is configured to connect a subsequently formed data signal line to the first data connection electrode 73 through the via hole.

[0281] In an exemplary embodiment, the orthographic projection of the thirty-second via hole V32 on the substrate is located within the range of the orthographic projection of the first anode connecting electrode 74 on the substrate, the second flat layer in the thirty-second via hole V32 is removed to expose the surface of the first anode connecting electrode 74, and the thirty-second via hole V32 is configured to connect the subsequently formed second anode connecting electrode to the first anode connecting electrode 74 through the via hole.

[0282] In an exemplary embodiment, at least one circuit unit may further include a thirty-third via hole V33. The orthographic projection of the thirty-third via hole V33 on the substrate is located within the range of the orthographic projection of the second data connection electrode 75 on the substrate. The second planar layer in the thirty-third via hole V33 is removed, exposing the surface of the second data connection electrode 75. The thirty-third via hole V33 is configured to connect a subsequently formed second data connection line 82 to the second data connection electrode 75 through the via hole.

[0283] In an exemplary embodiment, at least one circuit unit may further include a thirty-fourth via hole V34. The orthographic projection of the thirty-fourth via hole V34 on the substrate is located within the range of the orthographic projection of the dummy electrode 77 on the substrate. The second flat layer within the thirty-fourth via hole V34 is removed, exposing the surface of the dummy electrode 77. The thirty-fourth via hole V34 is configured to connect a subsequently formed second power supply line (or second data connection line) to the dummy electrode 77 through the via hole.

[0284] In an exemplary embodiment, in this process, the second display area forms a second planar layer disposed on the first planar layer.

[0285] (19) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer may include: depositing a fifth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fourth conductive film using a patterning process to form a fifth conductive layer disposed on the first flat layer, as shown in FIG. 21A and FIG. 21B , where FIG. 21B is a planar schematic diagram of the fifth conductive layer in FIG. 21A . In an exemplary embodiment, the fifth conductive layer may be referred to as a third source / drain metal (SD3) layer.

[0286] In an exemplary embodiment, the fifth conductive layer of each circuit unit (including the first circuit unit and the second circuit unit) in the first display area includes at least a data signal line 72 and a second anode connection electrode 76 .

[0287] In an exemplary embodiment, the data signal line 72 may be in the shape of a straight line or a zigzag line, with the main portion extending along the second direction Y. The data signal line 72 is connected to the first data connection electrode 73 via a thirty-first via hole V31. In the first circuit unit, since the first data connection electrode 73 is connected to the second connection electrode 52 via the via hole, and the second connection electrode 52 is connected to the first region of the fourth active layer via the via hole, the data signal line 72 can write a data signal to the first electrode of the fourth transistor T4. In the second circuit unit, since the first data connection electrode 73 is connected to the first power line 71 via the power connection block 73-1, the data signal line 72 has the potential of the first power line, effectively preventing the data signal line of the second circuit unit from floating.

[0288] In an exemplary embodiment, the second anode connection electrode 76 may be in a block shape (e.g., a rectangle). The second anode connection electrode 76 is connected to the first anode connection electrode 74 via a thirty-second via hole V32. The second anode connection electrode 76 is configured to be connected to a subsequently formed anode. Since the first anode connection electrode 74 is connected to the fourth connection electrode 54 via a via hole, and the fourth connection electrode 54 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) via a via hole, the pixel driving circuit can output a driving current to the light-emitting device.

[0289] In an exemplary embodiment, the fifth conductive layer of at least one circuit unit in the first display area may further include a second inserted line. The second inserted line may be in the shape of a straight line or a broken line extending along the second direction Y and may be located on the side opposite to the first direction X of the data signal line 72.

[0290] In an exemplary embodiment, at least one second insertion line may include at least a second data connection line 82 and a second power line 92 arranged in sequence along the second direction Y, the second data connection line 82 may be arranged in the first area (FIP area), and the second power line 92 may be arranged in the second area (non-FIP area or SIP area).

[0291] In an exemplary embodiment, in the second region (non-FIP region or SIP region), the second insertion line may include only the second power trace 92 .

[0292] In an exemplary embodiment, a second break K2 may be provided between the second data connection line 82 and the second power line 92 arranged in the same unit column. The second break K2 may cut off the second data connection line 82 located in the FIP area from the second power line 92 located in the non-FIP area, so that the second data connection line 82 and the second power line 92 on both sides of the second break K2 are insulated from each other.

[0293] In an exemplary embodiment, the end of the second data connection line 82, away from the second break K2, extends to the binding area and then connects to the data lead line. The end of the second data connection line 82, closer to the second break K2, is connected to the second data connection electrode 75 via the thirty-third via hole V33. Since the second data connection electrode 75 is connected to the data connection block 84 via the via hole, and the data connection block 84 is connected to the first data connection line 81 via the data connection bar 83, the first data connection line 81 is configured to connect to the data signal line in the display area. This achieves mutual connection between the first data connection line 81 extending along the first direction X of the main body portion and the second data connection line 82 extending along the second direction Y of the main body portion. The data lead lines in the binding area are connected to the data signal lines in the display area via the first data connection line 81 and the second data connection line 82.

[0294] In an exemplary embodiment, in at least one circuit unit, the second data link line 82 may be connected to the dummy electrode 77 through the thirty-fourth via hole V34 .

[0295] In an exemplary embodiment, the first display area (including the FIP area and the non-FIP area) may include a plurality of first circuit units and a plurality of second circuit units. The second inset line may be provided only in the first circuit unit, while the second circuit unit is not provided with the second data connection line 82 and the second power supply line 92. Because the SD1 layer of the second circuit unit is provided with a power supply connection line, there are certain differences in the circuit structures of the first circuit unit and the second circuit unit. By providing the second inset line only in the first circuit unit, the present disclosure can reduce the circuit differences between the first circuit unit and the second circuit unit, thereby avoiding the load differences of the data signal caused by the circuit differences and improving the display quality.

[0296] In an exemplary embodiment, the orthographic projection of the second data connection line 82 on the substrate at least partially overlaps with the orthographic projection of the first power line on the substrate. The first power line with a constant potential can shield the influence of the data voltage jump of the second data connection line 82 on the key nodes of the pixel driving circuit, thereby improving the working stability of the pixel driving circuit and improving the display effect.

[0297] In an exemplary embodiment, the orthographic projection of the second break K2 on the substrate can be located within the range of the orthographic projection of the first power line on the substrate, so that the first power line can pad the second break K2 from the bottom, which can effectively eliminate the film layer differences in different areas, is conducive to eliminating shadows, and avoids poor appearance of the display substrate.

[0298] In an exemplary embodiment, the second power supply line 92 can be connected to the dummy electrode 77 through the thirty-fourth via V34, so that the display area has basically the same transfer area structure, which improves the uniformity of the etching process. Different areas can achieve the same display effect under transmitted and reflected light, realizing shadow elimination, effectively avoiding the poor appearance of the display substrate and the occurrence of off-screen watermarks, and improving the display quality.

[0299] In an exemplary embodiment, the second power line 92 can be connected to the power lead that transmits the second power signal through the frame area or the binding area, thereby realizing a second power line located in the panel (VSS in Panel, referred to as SIP) structure. This can not only effectively reduce the resistance of the second power line, reduce the voltage drop of the second power signal, effectively improve the uniformity of the second power signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality, but also can significantly reduce the width of the frame power lead, greatly reduce the width of the left and right frames, and improve the screen-to-body ratio, which is conducive to achieving full-screen display.

[0300] In some possible implementations, the second power line may be connected to the first power line, or may be connected to the first initial signal line, or may be connected to the second initial signal line, which is not limited in the present disclosure.

[0301] In an exemplary embodiment, in this process, the fifth conductive layer in the second display area is etched away.

[0302] The subsequent preparation process may include forming a third flat layer, on which an anode via is provided, the anode via exposing the surface of the second anode connection electrode, and the anode via is configured to connect a subsequently formed anode to the second anode connection electrode through the via.

[0303] At this point, the driving structure layer of this embodiment is prepared on the substrate. In a plane parallel to the display substrate, the driving structure layer may include a first display area and a second display area, the first display area may at least partially surround the second display area, the first display area may include a plurality of circuit units, at least one circuit unit may include a pixel driving circuit, and a first scanning signal line, a second scanning signal line, a light-emitting signal line, a first initial signal line, a second initial signal line, a first power line and a data signal line connected to the pixel driving circuit. In a plane perpendicular to the display substrate, the driving structure layer of the first display area may include a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer, a first flat layer, a fourth conductive layer, a second flat layer, a fifth conductive layer and a third flat layer arranged in sequence on the substrate. The semiconductor layer may include at least an active layer of multiple transistors, the first conductive layer may include at least a first scanning signal line, a second scanning signal line, a light-emitting signal line and a first plate of a storage capacitor, the second conductive layer may include at least a first initial signal line, a second initial signal line and a second plate of a storage capacitor, the third conductive layer may include at least a first data connection line, a first power line and multiple connection electrodes, the fourth conductive layer may include at least a first power line, and the fifth conductive layer may include at least a data signal line, a second data connection line and a second power line.

[0304] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may include, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and one or more of textile fibers. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked on a glass carrier. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., for improving the water and oxygen resistance of the substrate. The first and second inorganic material layers are also referred to as barrier layers, and the material of the semiconductor layer may be amorphous silicon (a-Si).

[0305] In an exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer. The shielding layer, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer may be made of a metal material such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), or molybdenum (Mo), or may be made of an alloy material composed of a metal such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single layer structure or a multilayer composite structure such as Ti / Al / Ti. The first planar layer, the second planar layer, and the third planar layer may be made of an organic material such as a resin or polyimide.

[0306] In an exemplary embodiment, after the driving structure layer is prepared, a light emitting structure layer may be prepared on the driving structure layer, and an encapsulation structure layer may be prepared on the light emitting structure layer, which will not be described in detail here.

[0307] An exemplary embodiment of the present disclosure provides a display substrate, which, by inserting circuit units, FIP and SIP structural designs, not only ensures the normal operation of the under-screen camera area, but also eliminates the differences in pixel driving circuits in various areas, avoids the problem of screen-off watermarks and other defects caused by differences in pixel driving circuits, and achieves an integrated black display effect.

[0308] The embodiment of the present disclosure adopts a 4-in-1 design in the first display area, wherein the first pixel driving circuit drives the light-emitting device in the first display area, the third pixel driving circuit drives the light-emitting device in the second display area, and the second pixel driving circuit serves as a dummy pixel circuit. This not only ensures the display effects of the bright and dark states of the second display area, but also ensures that there is no obvious difference between the first display area and the second display area.

[0309] The disclosed embodiment realizes a FIP structure by setting a first data connection line and a second data connection line in the display area, and connecting the data lead line of the binding area to the data signal line through the first data connection line and the second data connection line, so that there is no need to set a fan-shaped oblique line in the lead line area, effectively reducing the length of the lead line area, greatly reducing the width of the lower frame, and improving the screen-to-body ratio, which is conducive to achieving full-screen display.

[0310] The embodiment of the present disclosure effectively reduces the circuit difference between the first circuit unit and the second circuit unit by setting the second insertion line in the first circuit unit and the power connection line in the second circuit unit, thereby avoiding the load difference of the data signal caused by the circuit difference and improving the display quality.

[0311] The embodiment of the present disclosure forms a power connection line in the second circuit unit, and the power connection line is connected to the first power signal at the upper frame and the binding area, thereby effectively eliminating the static electricity accumulation generated in the process, effectively avoiding damage and short circuit of transistors in the pixel driving circuit, and improving product quality.

[0312] The embodiment of the present disclosure can effectively reduce the generation of static electricity by eliminating the PVX vias of the second dummy unit in the upper frame area and the fourth conductive layer in the second dummy unit, effectively improve the efficiency of the power connection line in the second circuit unit in conducting static electricity, and effectively eliminate the accumulation of static electricity generated in the process.

[0313] The embodiment of the present disclosure forms a power connection line in the second circuit unit, and the power connection line and the first power line form a mesh-like connected structure for transmitting the first power signal. This can not only effectively reduce the resistance of the first power line, reduce the voltage drop of the first power signal, effectively improve the uniformity of the first power signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality, but also can greatly reduce the width of the binding power line in the binding area and the frame power line in the frame area, greatly reduce the width of the upper and lower frames, improve the screen-to-body ratio, and facilitate the realization of full-screen display.

[0314] The disclosed embodiment realizes a SIP structure by providing a second power line to transmit a second power signal. This not only effectively reduces the resistance of the second power line, reduces the voltage drop of the second power signal, effectively improves the uniformity of the second power signal in the display substrate, effectively improves the display uniformity, and improves the display quality, but also significantly reduces the width of the frame power lead, greatly reduces the width of the left and right frames, improves the screen-to-body ratio, and is conducive to achieving full-screen display.

[0315] The embodiment of the present disclosure utilizes the first power line to shield the first break on the first data connection line from above, and utilizes the first power line to support the second break on the second data connection line from below, thereby effectively eliminating the differences in film layers in different areas, facilitating shadow elimination, avoiding poor appearance of the display substrate, and improving display quality.

[0316] The embodiments of the present disclosure provide dummy connecting bars, dummy connecting blocks, and dummy electrodes so that the display area has substantially the same transfer area structure, thereby improving the uniformity of the etching process. Different areas can achieve the same display effect under transmitted and reflected light, thus achieving shadow elimination, effectively avoiding the poor appearance of the display substrate and the occurrence of screen-off watermarks, and improving the display quality.

[0317] In the embodiment of the present disclosure, by connecting the data signal line of the second circuit unit to the first power line, the floating of the data signal line in the second circuit unit can be avoided, thereby reducing the impact on the pixel driving circuit.

[0318] The preparation process of the embodiment of the present disclosure is well compatible with the existing preparation process, and the process is simple to implement, easy to implement, high in production efficiency, low in production cost, and high in yield rate.

[0319] The structure and fabrication process described above are merely exemplary. In exemplary embodiments, the corresponding structure may be modified and patterning processes may be added or removed as needed. For example, a first power supply line may be connected to a second power supply signal. Another example is that a second power supply line may be connected to a first power supply signal. This disclosure does not limit this.

[0320] In an exemplary embodiment, the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., which is not limited in the present disclosure.

[0321] The present disclosure also provides a method for preparing a display substrate to produce the display substrate provided in the above embodiment. In an exemplary embodiment, the preparation method may include:

[0322] forming a driving structure layer on a substrate, and forming a light-emitting structure layer on the driving structure layer;

[0323] The driving structure layer includes multiple circuit repetition units, and the light-emitting structure layer includes multiple first light-emitting devices; at least one circuit repetition unit includes M first circuit units and 1 second circuit unit, the first circuit unit includes at least a first pixel driving circuit, the first pixel driving circuit is respectively connected to the data signal line, the first power line and the first light-emitting device, the second circuit unit includes at least a second pixel driving circuit, the second pixel driving circuit is respectively connected to the data signal line and the first power line, but is not connected to the first light-emitting device; the driving structure layer also includes at least one first insertion line extending along the first direction, at least one second insertion line extending along the second direction, and at least one power connection line extending along the second direction, the first direction and the second direction intersect; the second insertion line is connected to the data signal line through the first insertion line, the power connection line is connected to the first power line, the second insertion line is arranged in the first circuit unit, and the power connection line is arranged in the second circuit unit.

[0324] The present disclosure further provides a display device including the aforementioned display substrate. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system, but the embodiments of the present invention are not limited thereto.

[0325] While the embodiments disclosed herein are as described above, it should be noted that the embodiments described above are merely illustrative and not restrictive. Therefore, the present disclosure is not limited to what is specifically shown and described herein. Various modifications, substitutions, or omissions may be made to the forms and details of the embodiments without departing from the scope of the present disclosure.

Claims

1. A display substrate comprising a driving structure layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving structure layer away from the substrate; the driving structure layer comprises a plurality of repeating circuit units, and the light-emitting structure layer comprises a plurality of first light-emitting devices; At least one circuit repeating unit includes M first circuit units and one second circuit unit, where M is a positive integer greater than or equal to 3, the first circuit unit includes at least a first pixel driving circuit, the first pixel driving circuit being connected to a data signal line, a first power line, and the first light-emitting device, respectively; the second circuit unit includes at least a second pixel driving circuit, the second pixel driving circuit being connected to the data signal line and the first power line, respectively, but not connected to the first light-emitting device; the driving structure layer further includes at least one first insertion line extending along a first direction, at least one second insertion line extending along a second direction, and at least one power connection line extending along the second direction, the first direction and the second direction intersecting; The second inlet line is connected to the data signal line through the first inlet line, the power connection line is connected to the first power line, the second inlet line is provided in the first circuit unit, and the power connection line is provided in the second circuit unit.

2. The display substrate according to claim 1, wherein M is equal to 4.

3. The display substrate according to claim 1, wherein At least one first insertion line includes a first data connection line and a first power line arranged in sequence along the first direction, and a first break is provided between the first data connection line and the first power line; at least one second insertion line includes a second data connection line and a second power line arranged in sequence along the second direction, and a second break is provided between the second data connection line and the second power line; the second data connection line is connected to the data signal line through the first data connection line.

4. The display substrate according to claim 3, wherein: The orthographic projection of at least one first break on the display substrate plane at least partially overlaps with the orthographic projection of the first power line on the display substrate plane, and / or the orthographic projection of at least one second break on the display substrate plane at least partially overlaps with the orthographic projection of the first power line on the display substrate plane.

5. The display substrate according to claim 3, wherein: In at least one second circuit unit, the power connection line is connected to the first power line to form a mesh connection structure. The display substrate according to claim 3 , wherein: At least one first circuit unit further includes a data connection block, through which the second data connection line is connected to the first data connection line; at least one first circuit unit further includes a dummy connection block, to which the second power line is connected; the position and shape of the data connection block in one first circuit unit are the same as the position and shape of the dummy connection block in another first circuit unit.

7. The display substrate according to claim 1, wherein: The first pixel driving circuit and the second pixel driving circuit each include at least a storage capacitor, a first initialization transistor and a first light-emitting control transistor, the first electrode of the first initialization transistor is connected to the fifth connection electrode, the second electrode of the first initialization transistor is connected to the first plate of the storage capacitor through the first connection electrode, and the first electrode of the first light-emitting control transistor is connected to the second plate of the storage capacitor through the third connection electrode; in at least one first circuit unit, the first connection electrode, the third connection electrode and the fifth connection electrode are arranged in isolation; in at least one second circuit unit, the first connection electrode is respectively connected to the third connection electrode and the fifth connection electrode to form the power connection line.

8. The display substrate according to claim 7, wherein: The first power line is connected to the third connection electrode.

9. The display substrate according to claim 7, wherein: Both the first circuit unit and the second circuit unit include a first initial signal line extending along the first direction; in at least one first circuit unit, the fifth connecting electrode is respectively connected to the first electrode of the first initialization transistor and the first initial signal line; in at least one second circuit unit, the fifth connecting electrode is connected to the first electrode of the first initialization transistor and is not connected to the first initial signal line.

10. The display substrate according to claim 1, wherein At least one second circuit unit, the data signal line is connected to the first power line.

11. The display substrate according to any one of claims 1 to 10, wherein: The display substrate includes a display area, a binding area located on one side of the display area, and a frame area located on the other side of the display area. The display area includes at least a first display area and a second display area. The first display area at least partially surrounds the second display area. The first display area is configured to display images, and the second display area is configured to display images and transmit light. The driving structure layer of the first display area includes multiple circuit repeating units, and the light-emitting structure layer of the first display area includes multiple first light-emitting devices.

12. The display substrate according to claim 11, wherein: At least one circuit repetition unit includes M first circuit units and 1 third circuit unit, and at least one third circuit unit includes at least a third pixel driving circuit; the light-emitting structure layer of the second display area includes multiple second light-emitting devices, and the third pixel driving circuit is connected to the second light-emitting device.

13. The display substrate according to claim 11, wherein: The driving structure layer includes at least a first source-drain metal layer, a second source-drain metal layer arranged on the side of the first source-drain metal layer away from the substrate, and a third source-drain metal layer arranged on the side of the second source-drain metal layer away from the substrate; the power connection line and the first insertion line are arranged in the first source-drain metal layer, the first power line is arranged in the second source-drain metal layer, and the data signal line and the second insertion line are arranged in the third source-drain metal layer.

14. The display substrate according to claim 13, wherein: The frame area at least includes an upper frame area located on a side of the display area away from the binding area, the upper frame area includes a plurality of dummy repeating units, at least one dummy repeating unit includes M first dummy units and 1 second dummy unit, the first dummy unit includes at least a first dummy pixel circuit, the second dummy unit includes at least a second dummy pixel circuit, and neither the first dummy pixel circuit nor the second dummy pixel circuit is connected to the light-emitting device; the driving structure layer further includes a passivation layer provided between the first source-drain metal layer and the second source-drain metal layer, and in at least one first dummy unit, the passivation layer is provided with at least one via connecting the first source-drain metal layer to the second source-drain metal layer; In at least one second dummy unit, no via hole is provided on the passivation layer.

15. The display substrate according to claim 14, wherein: The second source-drain metal layer is disposed in at least one first dummy unit, and the second source-drain metal layer is not disposed in at least one second dummy unit.

16. The display substrate according to claim 11, wherein At least one power connection line is connected to a binding power line of the binding area, and the binding power line is configured to transmit a first power signal.

17. The display substrate according to claim 11, wherein At least one power connection line is connected to a frame power line in the frame area, and the frame power line is configured to transmit a first power signal.

18. The display substrate according to claim 11, wherein At least one second insertion line includes a second power trace, the second power trace is connected to a power lead in the border area or the binding area, and the power lead is configured to transmit a second power signal.

19. A display device comprising the display substrate according to any one of claims 1 to 18.

20. A method for preparing a display substrate, comprising: forming a driving structure layer on a substrate, and forming a light-emitting structure layer on the driving structure layer; The driving structure layer includes a plurality of circuit repeating units, and the light emitting structure layer includes a plurality of first light emitting devices; At least one circuit repeating unit includes M first circuit units and one second circuit unit, where M is a positive integer greater than or equal to 3, the first circuit unit includes at least a first pixel driving circuit, the first pixel driving circuit being connected to a data signal line, a first power line, and the first light-emitting device, respectively; the second circuit unit includes at least a second pixel driving circuit, the second pixel driving circuit being connected to the data signal line and the first power line, respectively, but not connected to the first light-emitting device; the driving structure layer further includes at least one first insertion line extending along a first direction, at least one second insertion line extending along a second direction, and at least one power connection line extending along the second direction, the first direction and the second direction intersecting; The second inlet line is connected to the data signal line through the first inlet line, the power connection line is connected to the first power line, the second inlet line is provided in the first circuit unit, and the power connection line is provided in the second circuit unit.

Images