Semiconductor device and manufacturing method for semiconductor device

Abstract

The present invention relates to the technical field of semiconductors, and provides a semiconductor device and a manufacturing method for the semiconductor device. The semiconductor device comprises an epitaxial layer, a P-type ion implantation layer, an N-type ion implantation layer, a gate structure and a source structure. The manufacturing method comprises: forming the P-type ion implantation layer in the epitaxial layer; partially etching the P-type ion implantation layer to form a trench, a side wall area of the trench forming a cap layer structure; and then forming the N-type ion implantation layer in the P-type ion implantation layer, the N-type ion implantation layer being configured to be buried in the trench and to extend to the cap layer structure. Compared with the prior art, the present invention configures a first channel as a longitudinal conductive channel, so as to use the characteristic of high mobility of the longitudinal channel to increase turn-on current density in the case of a fixed size of unit cells, thereby achieving the purpose of improving performance. In addition, there is no need to use a trench type buried gate structure, achieving a simple process and being compatible with existing planar gate processes.

Description

Semiconductor device and method for manufacturing semiconductor device Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for preparing the semiconductor device. Background Art

[0002] Among common power device MOSFET structures, there are mainly planar and trench MOSFET structures. However, due to the increased scattering effect (Coulomb scattering / phonon scattering / surface roughness scattering) at the interface between oxide and semiconductor, the electron mobility of the inversion layer of planar silicon carbide MOSFET is lower than that of the semiconductor material. The channel mobility of currently available SiC products is generally between 15-35cm 2 V -1 S -1 , making the channel resistance account for a large proportion of the entire on-series resistance. The trench structure makes the channel direction along the crystal direction from <0001> Due to the material's characteristics, the mobility of the channel is about twice that of the planar channel. Therefore, most current research focuses on using process technology to improve mobility. However, this process is complex and difficult, making it difficult to widely promote. Technical Solutions

[0003] The objectives of the present invention include, for example, providing a semiconductor device and a method for preparing the semiconductor device, which can increase the current density during conduction and improve device performance, while having a simple process and being compatible with existing planar gate processes.

[0004] The embodiments of the present invention can be implemented as follows:

[0005] In a first aspect, the present invention provides a semiconductor device comprising:

[0006] epitaxial layer;

[0007] A P-type ion implantation layer, wherein the P-type ion implantation layer is disposed in the epitaxial layer and is locally etched to form a trench, wherein a sidewall region of the trench forms a cap layer structure;

[0008] an N-type ion implantation layer, the N-type ion implantation layer being disposed in the P-type ion implantation layer, and the N-type ion implantation layer being configured to be buried in the trench and extend to the cap layer structure;

[0009] a gate structure, the gate structure insulatingly covering the epitaxial layer, the N-type ion implantation layer, and the P-type ion implantation layer;

[0010] a source structure, the source structure being disposed on the N-type ion implantation layer;

[0011] In which, in the on state, a first channel and a second channel are formed at the contact interface between the cap layer structure and the gate structure, the first channel is located at the side wall interface of the cap layer structure, and the second channel is located at the top wall interface of the cap layer structure, the first channel is configured as a longitudinal conductive channel, and the second channel is configured as a transverse conductive channel.

[0012] In a second aspect, the present invention provides a semiconductor device, comprising:

[0013] epitaxial layer;

[0014] A P-type ion implantation layer, the P-type ion implantation layer being disposed in the epitaxial layer and locally etched to form a groove;

[0015] an N-type ion implantation layer, the N-type ion implantation layer being disposed in the P-type ion implantation layer and configured to be buried in the trench and extend to a sidewall region of the trench;

[0016] a gate structure, the gate structure insulatingly covering the epitaxial layer, the N-type ion implantation layer, and the P-type ion implantation layer;

[0017] a source structure, the source structure being disposed on the N-type ion implantation layer;

[0018] In which, in the on state, a first channel and a second channel are formed at the contact interface between the P-type ion injection layer and the gate structure, the first channel is located in the side wall area of ​​the groove, and the second channel is located at the top wall interface of the P-type ion injection layer, the first channel is configured as a longitudinal conductive channel, and the second channel is configured as a transverse conductive channel.

[0019] In a third aspect, the present invention provides a method for preparing a semiconductor device, for preparing the semiconductor device according to any one of the aforementioned embodiments, the method comprising:

[0020] growing an epitaxial layer on a substrate;

[0021] locally implanting ions into the epitaxial layer using a first mask pattern to form a P-type ion implantation layer;

[0022] Partially etching the P-type ion implantation layer using a second mask pattern to form a trench, wherein a sidewall region of the trench forms a cap layer structure;

[0023] Implanting ions into the P-type ion implantation layer in the trench to form an N-type ion implantation layer, wherein the N-type ion implantation layer is configured to be buried in the trench and extend to the cap layer structure;

[0024] forming a gate structure on the epitaxial layer, wherein the gate structure is insulated and covers the epitaxial layer, the N-type ion implantation layer, and the P-type ion implantation layer;

[0025] forming a source structure on the N-type ion implantation layer;

[0026] In which, in the on state, a first channel and a second channel are formed at the contact interface between the cap layer structure and the gate structure, the first channel is located at the side wall interface of the cap layer structure, and the second channel is located at the top wall interface of the cap layer structure, the first channel is configured as a longitudinal conductive channel, and the second channel is configured as a transverse conductive channel. Beneficial effects

[0027] A semiconductor device provided by an embodiment of the present invention forms a P-type ion implantation layer in an epitaxial layer, wherein the P-type ion implantation layer is locally etched to form a groove, and a cap layer structure is formed in the sidewall region of the groove, and then an N-type ion implantation layer is formed in the P-type ion implantation layer, and the N-type ion implantation layer is configured to be buried in the groove and extend to the cap layer structure, while the gate structure is insulated and covered on the epitaxial layer, the N-type ion implantation layer and the cap layer structure, and finally the source structure is arranged on the N-type ion implantation layer, wherein, in the on state, a first channel and a second channel are formed at the contact interface between the cap layer structure and the gate structure, the first channel is located at the sidewall interface of the cap layer structure, and the second channel is located at the top wall interface of the cap layer structure, the first channel is configured as a longitudinal conductive channel, and the second channel is configured as a transverse conductive channel, thereby enabling the conduction of the two-dimensional electron gas. Compared to existing technologies, the semiconductor device provided by the present invention configures the first channel as a vertical conductive path. This utilizes the higher mobility of the vertical channel to increase the on-state current density while maintaining a fixed cell size, thereby improving performance. Furthermore, the device eliminates the need for a trench-type buried gate structure, simplifies the process, and is compatible with existing planar gate processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0029] FIG1 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention;

[0030] Figure 2 is a partial enlarged schematic diagram of II in Figure 1;

[0031] 3 to 9 are schematic diagrams of process steps of a method for manufacturing a semiconductor device provided by an embodiment of the present invention.

[0032] Icons: 100-semiconductor device; 110-epitaxial layer; 130-P-type ion implantation layer; 131-trench; 133-cap layer structure; 135-first channel; 137-second channel; 150-N-type ion implantation layer; 170-gate structure; 171-gate oxide layer; 1711-first gate oxide segment; 1713-vertical gate oxide segment; 1715-second gate oxide segment; 173-gate electrode; 180-dielectric layer; 190-source structure; 200-substrate; 210-first mask layer; 230-second mask layer; 231-spacer. Modes for Carrying Out the Invention

[0033] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0034] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort shall fall within the scope of protection of the present invention.

[0035] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0036] In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the accompanying drawings, or is the orientation or position relationship in which the product of the invention is usually placed when in use. It is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be understood as a limitation on the present invention.

[0037] In addition, the terms "first", "second", etc., if used, are merely used to distinguish and describe, and should not be understood as indicating or implying relative importance.

[0038] As disclosed in the background technology, there are two main ways to improve device performance from the perspective of mobility in the prior art. One is to use process to improve mobility, such as depositing gate oxide and then annealing nitridation, which can improve the electron mobility of the planar channel. However, the effect of process improvement is still limited. The other is to directly adopt a trench structure, that is, to make the channel direction along the crystal direction from <0001> It becomes <11-20>. Due to the characteristics of the material, the mobility of the channel will be about twice as high as that of the planar channel. However, the trench structure requires buried gate and additional process steps, which makes the process complicated.

[0039] In order to improve the current density of a single unit cell, the embodiments of the present invention provide a novel semiconductor device and a method for manufacturing the same. It should be noted that the features of the embodiments of the present invention can be combined with each other if there is no conflict.

[0040] 1 and 2 , an embodiment of the present invention provides a semiconductor device 100 , which can increase the current density during conduction and improve device performance, while having a simple process and being compatible with existing planar gate processes.

[0041] The semiconductor device 100 provided in this embodiment includes an epitaxial layer 110, a P-type ion implantation layer 130, an N-type ion implantation layer 150, a gate structure 170, and a source structure 190. The P-type ion implantation layer 130 is disposed in the epitaxial layer 110 and is partially etched to form a trench 131. A cap layer structure 133 is formed in the sidewall region of the trench 131. The N-type ion implantation layer 150 is arranged in the P-type ion implantation layer 130, and the N-type ion implantation layer 150 is configured to be buried in the trench 131 and extend to the cap layer structure 133; the gate structure 170 is insulated and covered on the epitaxial layer 110, the N-type ion implantation layer 150 and the P-type ion implantation layer 130; the source structure 190 is arranged on the N-type ion implantation layer 150; wherein, in the on state, a first channel 135 and a second channel 137 are formed at the contact interface between the cap layer structure 133 and the gate structure 170, the first channel 135 is located at the side wall interface of the cap layer structure 133, and the second channel 137 is located at the top wall interface of the cap layer structure 133, the first channel 135 is configured as a longitudinal conductive channel, and the second channel 137 is configured as a transverse conductive channel.

[0042] It should be noted that the semiconductor device 100 in this embodiment can be a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). In this embodiment, the epitaxial layer 110 can be made of materials such as silicon carbide, silicon, and gallium nitride. Silicon carbide is used as an example for this embodiment. In this embodiment, the P-type ion implantation layer 130 can be formed by performing a localized P-type ion implantation process on the epitaxial layer 110. The material can be boron (B) or aluminum (Al), thereby generating a P-type semiconductor region. The total ion implantation dose is less than 5E13 cm⁻², the implantation depth can be 1-2 μm, and the temperature is approximately 400-700°C. Therefore, the ion implantation depth of the P-type ion implantation layer 130 is 1-2 μm, that is, the distance between the bottom side of the P-type ion implantation layer 130 and the surface of the epitaxial layer 110 can be 1-2 μm. The ion implantation depth can indicate the thickness of the cap layer structure 133. Therefore, the thickness of the cap layer structure 133 can also be 0.5-2 μm.

[0043] It is worth noting that, in the embodiment of the present invention, a P-type ion implantation layer 130 is first formed in the epitaxial layer 110, the P-type ion implantation layer 130 is partially etched to form a trench 131, and a cap layer structure 133 is formed in the sidewall region of the trench 131, and then an N-type ion implantation layer 150 is formed in the P-type ion implantation layer 130, and the N-type ion implantation layer 150 is configured to be buried in the trench 131 and extend to the cap layer structure 133, thereby completely covering the trench 131, and at the same time, the gate structure 170 is insulated and covered on the epitaxial layer 110, the N-type ion implantation layer 131, and ... The source structure 190 is disposed on the N-type ion implantation layer 150 and the cap layer structure 133. Finally, in the on-state, a first channel 135 and a second channel 137 are formed at the contact interface between the cap layer structure 133 and the gate structure 170. The first channel 135 is located at the sidewall interface of the cap layer structure 133, and the second channel 137 is located at the top wall interface of the cap layer structure 133. The first channel 135 is configured as a longitudinal conductive channel, and the second channel 137 is configured as a transverse conductive channel, thereby enabling conduction of the two-dimensional electron gas. Since the first channel 135 is configured as a longitudinal conductive channel, the higher mobility of the longitudinal channel can be utilized to increase the current density during conduction when the unit cell size is fixed, thereby achieving the purpose of improving performance. At the same time, there is no need to adopt a trench 131-type buried gate structure, the process is simple, and it is compatible with existing planar gate processes.

[0044] In some embodiments, the angle between the sidewall of the cap layer structure 133 bonded to the trench 131 and the bottom wall of the trench 131 is between 85° and 90°, which can be determined by an etching process.

[0045] In some embodiments, the sidewall of the cap layer structure 133 facing away from the first trench 135 is arc-shaped.

[0046] In some embodiments, the gate structure 170 includes a gate oxide layer 171 and a gate electrode 173, the gate oxide layer 171 covers the epitaxial layer 110, the N-type ion implantation layer 150 and the cap layer structure 133, the gate electrode 173 covers the gate oxide layer 171, and the gate oxide layer 171 is configured to insulate the gate electrode 173 from the epitaxial layer 110, the P-type ion implantation layer 130 and the N-type ion implantation layer 150, respectively. Among them, the cap layer structure 133 is a part of the P-type ion implantation layer 130, that is, the P-type ion implantation layer 130 located in the side wall area of ​​the trench 131 constitutes the cap layer structure 133, the gate oxide layer 171 can be a material such as silicon dioxide or silicon oxynitride, and the gate electrode 173 can be polycrystalline silicon. Since the cap layer structure 133 is formed, and the gate electrode 173 covers the top wall and side wall of the cap layer structure 133, the gate electrode 173 in the source area forms a cap shape. By adjusting the groove process and the injection energy, the conventional planar channel can be separated into a planar channel and a vertical channel, that is, separated into a second channel 137 and a first channel 135.

[0047] In some embodiments, the semiconductor device 100 further includes a dielectric layer 180, which covers the gate structure 170 and the N-type ion implantation layer 150. The source structure 190 is embedded in the dielectric layer 180. The dielectric layer 180 is configured to insulate the gate electrode 173 from the source structure 190 and the N-type ion implantation layer 150. Specifically, the dielectric layer 180 completely covers the gate electrode 173, thereby achieving insulation between the gate electrode 173 and the source structure 190.

[0048] In some embodiments, the gate oxide layer 171 includes a first gate oxide segment 1711, a vertical gate oxide segment 1713, and a second gate oxide segment 1715, which are sequentially connected. The first gate oxide segment 1711 is disposed on the N-type ion implantation layer 150, the second gate oxide segment 1715 is disposed on the cap structure 133 and the epitaxial layer 110, and the vertical gate oxide segment 1713 is disposed on the sidewalls of the cap structure 133. The gate electrode 173 covers the first gate oxide segment 1711, the gate oxide segment, and the second gate oxide segment 1715. The first gate oxide segment 1711 is spaced apart from the source structure 190, and a staircase structure is formed between the first gate oxide segment 1711, the vertical gate oxide segment 1713, and the second gate oxide segment 1715. When the gate electrode 173 covers the gate oxide layer 171, it forms a cap shape, thereby ensuring the formation of the first channel 135 and the second channel 137 when the gate electrode 173 is turned on.

[0049] In some embodiments, the P-type ion implantation layer 130 is embedded in the epitaxial layer 110, and the surface of the cap layer 133 bonded to the second gate oxide segment 1715 is configured to be flush with the surface of the epitaxial layer 110 bonded to the second gate oxide layer 171. Specifically, the P-type ion implantation layer 130 can be directly formed by local ion implantation of the epitaxial layer 110. Therefore, the cap layer 133 is flush with the surface of the epitaxial layer 110, thereby maintaining the second gate oxide segment 1715 in a horizontal arrangement, and thus the gate electrode 173 can remain horizontal on the second gate oxide segment 1715.

[0050] In some embodiments, the end of the N-type ion implantation layer 150 is embedded in the cap layer structure 133. Specifically, when N-type ions are implanted into the P-type ion implantation layer 130, a certain amount of lateral diffusion may occur, so that the end of the formed N-type ion implantation layer 150 can be embedded in the cap layer structure 133, thereby better defining the lower end position of the first channel 135 in the conductive state.

[0051] In some embodiments, the end of the N-type ion implantation layer 150 is flush with the sidewall of the cap layer structure 133. Specifically, when performing N-type ion implantation on the P-type ion implantation layer 130, the implantation can be performed vertically, so that the N-type ion implantation layer 150 is aligned with the sidewall of the trench 131, which can also define the lower end position of the first channel 135.

[0052] Furthermore, the semiconductor device 100 further includes a drain structure, which is disposed on a side of the epitaxial layer 110 facing away from the source structure 190. Specifically, the drain metal can be disposed on the back surface. Of course, in other preferred embodiments, the drain structure can also be disposed on the epitaxial layer 110. The specific structure thereof can refer to the existing MOSFET structure.

[0053] The embodiment of the present invention further provides a semiconductor device 100, comprising an epitaxial layer 110, a P-type ion implantation layer 130, an N-type ion implantation layer 150, a gate structure 170, and a source structure 190. The P-type ion implantation layer 130 is disposed in the epitaxial layer 110 and is partially etched to form a trench 131. The N-type ion implantation layer 150 is disposed in the P-type ion implantation layer 130 and is configured to be buried in the trench 131 and extend to the sidewall region of the trench 131. The gate structure 170 is insulated and covered on the epitaxial layer. 110, N-type ion implantation layer 150, and P-type ion implantation layer 130; source structure 190 is disposed on N-type ion implantation layer 150; wherein, in the on state, a first channel 135 and a second channel 137 are formed at the contact interface between P-type ion implantation layer 130 and gate structure 170. First channel 135 is located in the sidewall region of trench 131, and second channel 137 is located at the top wall interface of P-type ion implantation layer 130. First channel 135 is configured as a longitudinal conductive channel, and second channel 137 is configured as a lateral conductive channel. Specifically, the sidewall region of trench 131 can constitute the aforementioned cap layer structure 133, which can form a stepped structure, thereby forming first channel 135 and second channel 137.

[0054] In some embodiments, an angle between a sidewall of the trench 131 joined to the P-type ion implantation layer 130 and a bottom wall of the trench 131 is between 85° and 90°.

[0055] In some embodiments, the sidewall of the P-type ion implantation layer 130 facing away from the trench 131 is in an arc shape.

[0056] It should be noted that the total channel width Lz in the embodiment of the present invention is the sum of the width L1 of the first channel 135 and the width L2 of the second channel 137. Even if Lz in the embodiment of the present invention is equal to the width of the planar channel in the conventional planar structure, due to the influence of vertical mobility, the forward electrical performance will still be better than that of the planar structure.

[0057] An embodiment of the present invention further provides a method for manufacturing a semiconductor device 100, which is used to manufacture the aforementioned semiconductor device 100. The method comprises the following steps:

[0058] S1 : growing an epitaxial layer 110 on the substrate 200 .

[0059] Referring to Figure 3 , a conventional epitaxial growth process can be used to grow a silicon carbide epitaxial structure on a substrate 200. Substrate 200 can be either a substrate or a carrier, and can be subsequently stripped. The epitaxial layer 110 can be made of silicon carbide, silicon, or gallium nitride, with silicon carbide being used as an example.

[0060] It should be noted that after the epitaxial layer 110 is grown, the substrate 200 can be peeled off, or peeled off in a subsequent process.

[0061] S2 : Locally implanting ions into the epitaxial layer 110 using a first mask pattern to form a P-type ion implantation layer 130 .

[0062] Referring to Figure 4 , specifically, a first mask layer 210 can be formed on the epitaxial layer 110. A first patterned opening is then formed in the first mask layer 210 to form a first mask pattern. P-type ion implantation is then performed through the first patterned opening to form the P-type ion implantation layer 130. The first mask layer 210 can be silicon dioxide (SiO2). A P-Well opening is formed using the first mask layer 210, and then P-type ion implantation is performed. The material can be boron (B) or aluminum (Al), creating a P-type semiconductor region, thus forming the P-type ion implantation layer 130. The total ion implantation dose is less than 5E13 cm-2, the implantation depth can be 1-2 μm, and the temperature is approximately 400-700°C.

[0063] S3 : Partially etching the P-type ion implantation layer 130 using a second mask pattern to form a trench 131 .

[0064] 5 to 7 , specifically, a cap layer structure 133 is formed in the sidewall region of the trench 131. After forming the P-type ion implantation layer 130, a second mask layer 230 is first formed on the first mask layer 210 and the P-type ion implantation layer 130, as shown in FIG5 ; then, a portion of the second mask layer 230 is removed using a self-aligned etching process, and the remaining portion and the first mask layer 210 together form a second mask pattern, as shown in FIG6 ; finally, the P-type ion implantation layer 130 is partially etched through the second mask pattern to form a trench 131, as shown in FIG7 .

[0065] After forming the P-type ion implantation layer 130, a second mask layer 230 can be deposited on the entire surface of the epitaxial layer 110. The second mask layer 230 can be a dielectric material, such as silicon dioxide, silicon nitride, or polysilicon, with a thickness ranging from 0.1 μm to 0.5 μm. A self-aligned etching process is then used to form spacers 231. Specifically, the second mask layer 230 located on the first mask layer 210 and the P-type ion implantation layer 130 is removed with equal thickness. Since the second mask layer 230 formed between the first mask layer 210 and the P-type ion implantation layer 130 is relatively thick, this portion of the second mask layer 230 remains to form spacers 231. The width of the spacers 231 can be determined by the thickness of the second mask layer 230 and can be set according to the actual requirements of the planar channel. After forming the spacer 231 , the spacer 231 and the first mask layer 210 together form a second mask pattern. The P-type ion implantation layer 130 is etched through the second mask pattern to form a trench 131 with an etching depth of 0.1-0.5 μm.

[0066] S4 : Ions are implanted into the P-type ion implantation layer 130 in the trench 131 to form an N-type ion implantation layer 150 .

[0067] Referring to FIG. 8 , an N-type ion implantation layer 150 is configured to be embedded within trench 131 and extend to cap layer structure 133 . During the actual implantation, the second mask pattern can still be used for N-type ion implantation. The material is nitrogen (N), the total ion implantation dose is less than 5E15 cm⁻², the implantation depth is 0.3-0.7 microns, and the temperature is 400-700°C.

[0068] S5 : forming a gate structure 170 on the epitaxial layer 110 .

[0069] 9 , specifically, after removing the first mask layer 210 and the second mask layer 230, a gate structure 170 is formed. The gate structure 170 simultaneously insulates and covers the epitaxial layer 110, the N-type ion implantation layer 150, and the P-type ion implantation layer 130. When actually forming the gate structure 170, a gate oxide layer 171 with a thickness of 20-60 nm can be first formed, and then polysilicon is deposited as a gate electrode 173 with a thickness of 0.1-0.5 μm.

[0070] S6 : forming a source structure 190 on the N-type ion implantation layer 150 .

[0071] Continuing to refer to FIG. 1 , specifically, a front source metal may be deposited on the N-type ion implantation layer 150 to form a source structure 190 .

[0072] It should be noted that, in the on state, a first channel 135 and a second channel 137 are formed at the contact interface between the cap layer structure 133 and the gate structure 170. The first channel 135 is located at the side wall interface of the cap layer structure 133, and the second channel 137 is located at the top wall interface of the cap layer structure 133. The first channel 135 is configured as a longitudinal conductive channel, and the second channel 137 is configured as a transverse conductive channel.

[0073] In some embodiments, a dielectric layer 180 is further deposited, and after the substrate 200 is peeled off, a drain structure is formed on the back side of the epitaxial layer 110 . The process can refer to the existing MOSFET manufacturing process.

[0074] In summary, the semiconductor device 100 provided by the embodiment of the present invention forms a P-type ion implantation layer 130 in the epitaxial layer 110, the P-type ion implantation layer 130 is partially etched to form a groove 131, and a cap layer structure 133 is formed in the sidewall region of the groove 131, and then an N-type ion implantation layer 150 is formed in the P-type ion implantation layer 130, and the N-type ion implantation layer 150 is configured to be buried in the groove 131 and extend to the cap layer structure 133, and at the same time, the gate structure 170 is insulated and covered on the epitaxial layer 110 and the N-type ion implantation layer. 150 and the cap layer structure 133, and finally the source structure 190 is arranged on the N-type ion implantation layer 150. In the conductive state, a first channel 135 and a second channel 137 are formed at the contact interface between the cap layer structure 133 and the gate structure 170. The first channel 135 is located at the side wall interface of the cap layer structure 133, and the second channel 137 is located at the top wall interface of the cap layer structure 133. The first channel 135 is configured as a vertical conductive channel, and the second channel 137 is configured as a horizontal conductive channel, thereby enabling the conduction of the two-dimensional electron gas. Compared with the prior art, the semiconductor device 100 provided in the embodiment of the present invention configures the first channel 135 as a vertical conductive channel, which can utilize the high mobility of the vertical channel to increase the current density during conduction when the cell size is fixed, thereby achieving the purpose of performance improvement. At the same time, there is no need to adopt a trench 131-type buried gate structure, the process is simple, and it is compatible with the existing planar gate process.

[0075] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A semiconductor device, characterized in that: include: epitaxial layer (110); A P-type ion implantation layer (130), the P-type ion implantation layer (130) being arranged in the epitaxial layer (110) and locally etched to form a groove (131), with a sidewall region of the groove (131) forming a cap layer structure (133); An N-type ion implantation layer (150), the N-type ion implantation layer (150) being disposed in the P-type ion implantation layer (130), and the N-type ion implantation layer (150) being configured to be buried in the trench (131) and extending to the cap layer structure (133); a gate structure (170), the gate structure (170) insulatingly covering the epitaxial layer (110), the N-type ion implantation layer (150), and the cap layer structure (133); a source structure (190), the source structure (190) being arranged on the N-type ion implantation layer (150); Wherein, in the on state, a first channel (135) and a second channel (137) are formed at the contact interface between the cap layer structure (133) and the gate structure (170), the first channel (135) is located at the side wall interface of the cap layer structure (133), the second channel (137) is located at the top wall interface of the cap layer structure (133), the first channel (135) is configured as a longitudinal conductive channel, and the second channel (137) is configured as a transverse conductive channel.

2. The semiconductor device according to claim 1, wherein The angle between the side wall of the cap layer structure (133) joined to the groove (131) and the bottom wall of the groove (131) is between 85° and 90°.

3. The semiconductor device according to claim 1, wherein The side wall of the cap layer structure (133) facing away from the first channel (135) is in an arc shape.

4. The semiconductor device according to claim 1, wherein The gate structure (170) comprises a gate oxide layer (171) and a gate electrode (173), wherein the gate oxide layer (171) covers the epitaxial layer (110), the N-type ion implantation layer (150) and the cap layer structure (133), and the gate electrode (173) covers the gate oxide layer (171), and the gate oxide layer (171) is configured to insulate the gate electrode (173) from the epitaxial layer (110), the P-type ion implantation layer (130) and the N-type ion implantation layer (150), respectively.

5. The semiconductor device according to claim 4, wherein The semiconductor device further comprises a dielectric layer (180), the dielectric layer (180) covering the gate structure (170) and the N-type ion implantation layer (150), the source structure (190) being embedded in the dielectric layer (180), and the dielectric layer (180) being configured to insulate the gate electrode (173) from the source structure (190) and the N-type ion implantation layer (150).

6. The semiconductor device according to claim 4, wherein The gate oxide layer (171) comprises a first gate oxide segment (1711), a vertical gate oxide segment (1713) and a second gate oxide segment (1715) which are sequentially connected, the first gate oxide segment (1711) being arranged on the N-type ion implantation layer (150), the second gate oxide segment (1715) being arranged on the cap layer structure (133) and the epitaxial layer (110), the vertical gate oxide segment (1713) being arranged on the side wall of the cap layer structure (133), and the gate electrode (173) covering the first gate oxide segment (1711), the vertical gate oxide segment (1713) and the second gate oxide segment (1715).

7. The semiconductor device according to claim 6, wherein: The P-type ion implantation layer (130) is embedded in the epitaxial layer (110), and a surface of one side of the cap layer structure (133) bonded to the second gate oxide segment (1715) is configured to be flush with a surface of one side of the epitaxial layer (110) bonded to the second gate oxide segment (1715).

8. The semiconductor device according to any one of claims 1 to 7, wherein: The end of the N-type ion implantation layer (150) is embedded in the cap layer structure (133).

9. The semiconductor device according to any one of claims 1 to 7, wherein: The end of the N-type ion implantation layer (150) is flush with the side wall of the cap layer structure (133).

10. The semiconductor device according to any one of claims 1 to 7, wherein: The semiconductor device further comprises a drain structure, wherein the drain structure is arranged on a side of the epitaxial layer (110) away from the source structure (190).

11. A semiconductor device, characterized in that: include: epitaxial layer (110); A P-type ion implantation layer (130), the P-type ion implantation layer (130) being arranged in the epitaxial layer (110) and locally etched to form a groove (131); an N-type ion implantation layer (150), the N-type ion implantation layer (150) being arranged in the P-type ion implantation layer (130), and the N-type ion implantation layer (150) being configured to be buried in the trench (131) and extending to a sidewall region of the trench (131); a gate structure (170), the gate structure (170) insulatingly covering the epitaxial layer (110), the N-type ion implantation layer (150), and the P-type ion implantation layer (130); a source structure (190), the source structure (190) being arranged on the N-type ion implantation layer (150); Wherein, in the on state, a first channel (135) and a second channel (137) are formed at the contact interface between the P-type ion implantation layer (130) and the gate structure (170), the first channel (135) is located in the side wall region of the groove (131), and the second channel (137) is located at the top wall interface of the P-type ion implantation layer (130), the first channel (135) is configured as a longitudinal conductive channel, and the second channel (137) is configured as a transverse conductive channel.

12. The semiconductor device according to claim 12, wherein: The angle between the side wall of the groove (131) joined to the P-type ion implantation layer (130) and the bottom wall of the groove (131) is between 85° and 90°.

13. The semiconductor device according to claim 12, wherein: The side wall of the P-type ion implantation layer (130) facing away from the groove (131) is in an arc shape.

14. The semiconductor device according to claim 11, wherein The gate structure (170) comprises a gate oxide layer (171) and a gate electrode (173), wherein the gate oxide layer (171) covers the epitaxial layer (110), the N-type ion implantation layer (150) and the P-type ion implantation layer (130), and the gate electrode (173) covers the gate oxide layer (171), and the gate oxide layer (171) is configured to insulate the gate electrode (173) from the epitaxial layer (110), the P-type ion implantation layer (130) and the N-type ion implantation layer (150), respectively.

15. The semiconductor device according to claim 14, wherein: The semiconductor device further comprises a dielectric layer (180), the dielectric layer (180) covering the gate structure (170) and the N-type ion implantation layer (150), the source structure (190) being embedded in the dielectric layer (180), and the dielectric layer (180) being configured to insulate the gate electrode (173) from the source structure (190) and the N-type ion implantation layer (150).

16. The semiconductor device according to claim 14, wherein: The gate oxide layer (171) comprises a first gate oxide segment (1711), a vertical gate oxide segment (1713) and a second gate oxide segment (1715) which are sequentially connected, the first gate oxide segment (1711) being arranged on the N-type ion implantation layer (150), the second gate oxide segment (1715) being arranged on part of the P-type ion implantation layer (150) and the epitaxial layer (110), the vertical gate oxide segment being arranged on the sidewall of the trench (131), and the gate electrode (173) covering the first gate oxide segment (1711), the vertical gate oxide segment (1713) and the second gate oxide segment (1715).

17. The semiconductor device according to claim 11, wherein The semiconductor device further comprises a drain structure, wherein the drain structure is arranged on a side of the epitaxial layer (110) away from the source structure (190).

18. A method for preparing a semiconductor device, for preparing the semiconductor device according to claim 1, characterized in that: The method comprises: growing an epitaxial layer (110) on a substrate (200); locally implanting ions into the epitaxial layer (110) using a first mask pattern to form a P-type ion implantation layer (130); Partially etching the P-type ion implantation layer (130) using a second mask pattern to form a trench (131), wherein a sidewall region of the trench (131) forms a cap layer structure (133); Ion implantation is performed on the P-type ion implantation layer (130) in the trench (131) to form an N-type ion implantation layer (150), wherein the N-type ion implantation layer (150) is configured to be buried in the trench (131) and extend to the cap layer structure (133); forming a gate structure (170) on the epitaxial layer (110), wherein the gate structure (170) simultaneously insulates and covers the epitaxial layer (110), the N-type ion implantation layer (150), and the P-type ion implantation layer (130); forming a source structure (190) on the N-type ion implantation layer (150); Wherein, in the on state, a first channel (135) and a second channel (137) are formed at the contact interface between the cap layer structure (133) and the gate structure (170), the first channel (135) is located at the side wall interface of the cap layer structure (133), the second channel (137) is located at the top wall interface of the cap layer structure (133), the first channel (135) is configured as a longitudinal conductive channel, and the second channel (137) is configured as a transverse conductive channel.

19. The method for manufacturing a semiconductor device according to claim 18, wherein: The step of locally ion implanting the epitaxial layer (110) using a first mask pattern to form a P-type ion implantation layer (130) comprises: forming a first mask layer (210) on the epitaxial layer (110); Making a first graphic opening on the first mask layer (210) to form a first mask pattern; P-type ion implantation is performed through the first graphic opening to form a P-type ion implantation layer (130).

20. The method for manufacturing a semiconductor device according to claim 19, wherein: The step of locally etching the P-type ion implantation layer (130) to form a groove (131) using a second mask pattern comprises: forming a second mask layer (230) on the first mask layer (210) and the P-type ion implantation layer (130); removing a portion of the second mask layer (230) by using a self-aligned etching process, so that the remaining portion and the first mask layer (210) together form a second mask pattern; The P-type ion implantation layer (130) is locally etched through a second mask pattern to form a trench (131).

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