Solar cell and method for manufacturing same, and photovoltaic device

Abstract

The present invention relates to the technical field of solar cells, and provides a solar cell and a method for manufacturing same, and a photovoltaic device. By properly configuring the parallel resistances of a crystalline silicon sub-cell and a perovskite sub-cell, the cell efficiency and the hot spot resistance are balanced, so that when the solar cell is shaded and is in reverse bias, the difference in parallel resistance between the two sub-cells can reduce the reverse voltage borne by the perovskite sub-cell, weakening the impact of hot-spot effects on the perovskite sub-cell, improving the stability of the solar cell under hot-spot effects, prolonging the service life of the solar cell. When the ratio of the parallel resistance of the crystalline silicon sub-cell to the parallel resistance of the perovskite sub-cell is controlled to be 40 or above, the impact of hot spot effects on the perovskite sub-cell can be effectively mitigated and weakened while basically not affecting the power generation power of the solar cell, thereby improving the stability of the solar cell under hot spot effects.

Description

Solar cell and preparation method thereof, photovoltaic device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure claims priority to application number 202410361920X filed with the China Patent Office on March 27, 2024, entitled “A solar cell, a method for preparing the same, and a photovoltaic device,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the technical field of solar cells, and in particular to a solar cell and a preparation method thereof, and a photovoltaic device. Background Art

[0004] As the conversion efficiency of crystalline silicon cells gradually approaches its limit, in order to further improve the photoelectric conversion efficiency, a new solar cell, namely perovskite / crystalline silicon tandem cell, has been proposed.

[0005] When perovskite / crystalline silicon tandem cells operate outdoors, the cell surface will inevitably become dirty or shaded, resulting in what the industry calls a hot spot effect. A cell affected by the hot spot effect will be reverse biased and continue to generate heat, causing the temperature to rise, which can easily trigger high-temperature decomposition of the perovskite material and reduce the cell's stability. Furthermore, when a perovskite sub-cell is severely reverse biased, the halogen ions, metals, or organic cations within the perovskite sub-cell are driven to migrate to the interface through defects in the crystal. During this process, they can easily escape or react with the functional layers or electrodes in the cell, causing irreversible aging and device efficiency degradation. Summary of the Invention

[0006] The purpose of the present disclosure is to address the deficiencies in the above-mentioned prior art and provide a solar cell and a method for preparing the same, as well as a photovoltaic device. By configuring parallel resistance between crystalline silicon sub-cells and perovskite sub-cells, the influence of the hot spot effect on the stability of the perovskite sub-cells is weakened, thereby improving the stability of the solar cell under the hot spot effect.

[0007] To achieve the above objectives, the technical solutions adopted in the embodiments of the present disclosure are as follows:

[0008] In one aspect of an embodiment of the present disclosure, a solar cell is provided, comprising a crystalline silicon sub-cell and a perovskite sub-cell connected in series, wherein a ratio of a parallel resistance of the crystalline silicon sub-cell to a parallel resistance of the perovskite sub-cell is greater than 40.

[0009] Optionally, the ratio of the parallel resistance of the crystalline silicon sub-cell to the parallel resistance of the perovskite sub-cell is greater than 100.

[0010] Optionally, the solar cell is a crystalline silicon perovskite tandem cell, and the ratio of the parallel resistance of the crystalline silicon sub-cell to the parallel resistance of the perovskite sub-cell is greater than Voc-tandem*(n-1) / Vbias-max, where n is the number of cell strings in which the solar cell is located, Voc-tandem is the voltage of the crystalline silicon perovskite tandem cell, and Vbias-max is the maximum reverse bias voltage that the perovskite sub-cell can withstand.

[0011] Optionally, the parallel resistance of the crystalline silicon subcell is 200,000 ohm·cm 2 The parallel resistance of the perovskite subcell is 1,000 ohm·cm 2 above.

[0012] Optionally, the parallel resistance of the crystalline silicon subcell is 800,000 ohm·cm 2 Above, the parallel resistance of the perovskite subcell is 5,000 ohm·cm 2 above.

[0013] Optionally, the parallel resistance of the crystalline silicon subcell is 1,000,000 ohm·cm 2 Above, and / or, the parallel resistance of the perovskite subcell is 5,000 ohm·cm 2 Up to 100,000 ohm·cm 2 .

[0014] Optionally, the parallel resistance of the perovskite subcell is 5,000 ohm·cm 2 Up to 10,000 ohm·cm 2 .

[0015] Optionally, the reverse breakdown voltage of the solar cell is not less than 40V or not less than 48V, for example, greater than 60V.

[0016] Optionally, the crystalline silicon sub-cell uses a high-resistance silicon wafer with a resistivity of not less than 8 ohm-cm.

[0017] Another aspect of the present disclosure provides a method for preparing a solar cell, the method comprising:

[0018] preparing a crystalline silicon sub-cell, wherein the parallel resistance of the crystalline silicon sub-cell is not less than a first target value;

[0019] A perovskite sub-cell is formed on the crystalline silicon sub-cell, wherein the parallel resistance of the perovskite sub-cell is not less than a second target value, and a ratio of the first target value to the second target value is not less than 40.

[0020] Optionally, the ratio of the first target value to the second target value is not less than 100.

[0021] Optionally, the first target value is 200,000 ohm·cm 2 , the second target value is 1,000 ohm·cm 2

[0022] Optionally, the first target is 800,000 ohm·cm 2 , and / or, the second target value is 5,000 ohm·cm 2 .

[0023] Optionally, the parallel resistance of the perovskite subcell is in the range of 5,000 ohm·cm 2 Up to 10,000 ohm·cm 2 .

[0024] Optionally, the parallel resistance of the crystalline silicon subcell is 1,000,000 ohm·cm 2 Above, and / or, the parallel resistance of the perovskite subcell is in the range of 5,000 ohm·cm 2 Up to 100,000 ohm·cm 2 .

[0025] Optionally, the preparation process of the crystalline silicon sub-cell adopts at least one of the following to ensure that the parallel resistance of the crystalline silicon sub-cell is not less than a first target value:

[0026] If the crystalline silicon sub-cell is a heterojunction cell, a mask plate is used to block the edge area of ​​the back of the cell, and a sputtering process is used to form a transparent conductive film on the back of the cell; or, a mask plate is used to block the edge area of ​​the back of the cell, and a reactive plasma deposition process is further used to replace the sputtering process to form a transparent conductive film on the back of the cell;

[0027] If the crystalline silicon subcell is a tunneling oxide passivation contact cell, after forming the ultra-thin tunneling layer or polycrystalline silicon film, the wrap-around plating on the front surface of the cell is removed. Alternatively, the ultra-thin tunneling layer and / or polycrystalline silicon film is formed using a physical vapor deposition process to avoid wrap-around plating on the front surface of the cell. Optionally, a high-resistance silicon wafer with a resistivity of no less than 8 ohm-cm is used to prepare the crystalline silicon subcell.

[0028] Optionally, the preparation process of the perovskite sub-cell adopts at least one of the following to ensure that the parallel resistance of the perovskite sub-cell is not less than a second target value, and the ratio of the parallel resistance of the crystalline silicon sub-cell to the parallel resistance of the perovskite sub-cell is not less than 40:

[0029] Regulating the lateral conductivity of the composite layer between the crystalline silicon sub-cell and the perovskite sub-cell;

[0030] Regulating the density of the electron transport layer of the crystalline silicon subcell, and,

[0031] Regulating the crystallization growth sites at the buried perovskite interface.

[0032] Optionally, the ratio of the parallel resistance of the crystalline silicon sub-cell to the parallel resistance of the perovskite sub-cell is not less than 100.

[0033] In another aspect of the present disclosure, a photovoltaic device is provided, comprising a plurality of battery cells connected in series, wherein at least one of the plurality of battery cells is a solar cell as described above; or at least one of the plurality of battery cells is manufactured using any of the solar cell manufacturing methods described above. The photovoltaic device may include, for example, a battery string, a photovoltaic module, or the like.

[0034] The beneficial effects of the present disclosure include:

[0035] The present disclosure provides a solar cell and a preparation method thereof, and a photovoltaic device. By setting a suitable parallel resistance range for two sub-cells, the numerical difference in parallel resistance between the crystalline silicon sub-cell and the perovskite sub-cell is increased without substantially affecting the cell efficiency. In this way, when the solar cell is blocked and thus in reverse bias, the reverse voltage borne by the perovskite sub-cell is reduced by the difference in parallel resistance between the crystalline silicon sub-cell and the perovskite sub-cell, thereby weakening the influence of the hot spot effect on the perovskite sub-cell, improving the stability of the solar cell under the hot spot effect, and increasing the life of the solar cell.

[0036] When the ratio of the parallel resistance of the crystalline silicon sub-cell to the perovskite sub-cell is controlled at above 40 (for example, above 400), the impact of the hot spot effect on the perovskite sub-cell can be effectively alleviated and weakened without substantially affecting the power generation of the solar cell, thereby improving the stability of the solar cell under the hot spot effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present disclosure and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0038] FIG1 is a schematic diagram of a process for preparing a solar cell according to an embodiment of the present disclosure;

[0039] FIG2 is a simulated diagram of an IV curve of a stacked battery under different parallel resistances provided by an embodiment of the present disclosure;

[0040] FIG3 is a partial enlarged view within the dotted box in FIG2 ;

[0041] FIG4 is an actual measurement diagram of the IV curve of a wide bandgap perovskite battery provided by the present application under different parallel resistances;

[0042] FIG5 is a schematic diagram of bias voltages allocated to each sub-cell in a solar cell provided by an embodiment of the present disclosure;

[0043] FIG6 is a reverse IV curve diagram of a crystalline silicon sub-cell manufactured using high-resistance silicon wafers with different resistivities according to an embodiment of the present disclosure;

[0044] FIG7 is a partial enlarged view of the curve in FIG6;

[0045] FIG8 is a schematic diagram of the cell efficiency of crystalline silicon sub-cells manufactured using silicon wafers with different resistivities and bulk phase minority carrier lifetimes according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0046] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are only some of the embodiments of the present disclosure, but not all of them. Generally, the components of the embodiments of the present disclosure described and shown in the drawings herein can be arranged and designed in various different configurations.

[0047] Therefore, the following detailed description of the embodiments of the present disclosure provided in the accompanying drawings is not intended to limit the scope of the present disclosure as claimed, but rather merely represents selected embodiments of the present disclosure. It should be noted that, unless there is a conflict, the various features of the embodiments of the present disclosure may be combined with each other, and the combined embodiments are still within the scope of protection of the present disclosure.

[0048] In the description of the present disclosure, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the product of the application is typically placed when in use. These terms are intended solely to facilitate the description of the present disclosure and to simplify the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. Furthermore, the terms "first," "second," "third," etc., etc., are used solely to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0049] It should also be noted that, in the description of this disclosure, unless otherwise expressly specified or limited, the terms "disposed," "installed," "connected," and "connected" should be understood broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in this disclosure based on the specific circumstances.

[0050] Series and Parallel Resistors

[0051] There are three types of equivalent resistance in the equivalent circuit of a photovoltaic module. The first type is series resistance, usually denoted by Rs. This represents the resistance of the cell connections and the resistance of the cell itself within the module. This resistance primarily consists of the substrate resistance of the semiconductor material, the metal resistance and connection resistance, and the resistance generated by the connection between the metal and the semiconductor. Specifically, series resistance = wafer substrate resistance + lateral resistance + electrode resistance + contact resistance. The second type is shunt resistance, usually denoted by Rsh. This resistance is primarily due to an imperfect pn junction in the cell or impurities near the pn junction, which can cause a pn junction short circuit, particularly at the cell edges. The shunt resistance reflects the cell's leakage level. Leakage current can theoretically be attributed to the shunt resistance. The shunt resistance, Rsh, affects the open-circuit voltage of the solar cell. Reducing Rsh lowers the open-circuit voltage but has little effect on the short-circuit current. Finally, the output load resistance is present.

[0052] In order to increase the power generation capacity of solar cells, multiple battery cells are usually connected in series to form a battery string. Therefore, when some battery cells in the battery string are blocked, the so-called hot spot effect in the industry occurs, while the remaining battery cells are still under continuous light. The blocked battery cells (that is, the batteries affected by the hot spot effect) will be placed in a reverse bias state, that is, a reverse voltage will be applied to the blocked battery cells. The reverse voltage comes from the battery cells that normally receive light, and the blocked battery cells will change from a power source to a load, consuming energy.

[0053] Therefore, when the reverse breakdown voltage of the blocked battery cell is lower than the sum of the voltages generated by the battery cells that receive normal light, the blocked battery cell will generate heat, causing the temperature to rise, which may easily cause high-temperature decomposition of the perovskite material in the battery cell, reduce the stability of the battery, and reduce the power generation capacity of the battery string.

[0054] When the reverse breakdown voltage of the obscured battery cell is greater than the sum of the voltages generated by the normally illuminated battery cells, the current in the battery string approaches zero, and the power generation power of the battery string further decreases, approaching zero. When the avalanche voltage of the battery is very large, the battery will be severely reverse biased (the reverse breakdown of the battery is usually based on avalanche breakdown, and the breakdown voltage is generally high, such as above 20V for heterojunction batteries). When the perovskite sub-cell in the obscured battery cell is severely reverse biased, the halogen ions, metals or organic cations inside the perovskite sub-cell are driven by the electric field to transfer through defects in the crystal to the interface, and are easily escaped during this process, or react with the functional layer or electrode in the battery, causing irreversible aging and device efficiency degradation.

[0055] To solve the above problems, the present disclosure provides a solar cell and a preparation method thereof. For a multi-junction cell including a perovskite sub-cell and a crystalline silicon sub-cell, the parallel resistance of the crystalline silicon sub-cell and the parallel resistance of the perovskite sub-cell are configured to be in a suitable ratio, thereby increasing the numerical difference in parallel resistance between the crystalline silicon sub-cell and the perovskite sub-cell. When the solar cell is blocked and thus in reverse bias, the reverse voltage borne by the perovskite sub-cell is reduced by the difference in parallel resistance between the crystalline silicon sub-cell and the perovskite sub-cell, thereby weakening the influence of the hot spot effect on the perovskite sub-cell, improving the stability of the solar cell under the hot spot effect, and increasing the life of the solar cell.

[0056] More specifically, if the reverse breakdown voltage of the blocked solar cell is lower than the sum of the voltages generated by the remaining cells that receive normal light, the reverse voltage borne by the perovskite sub-cell is smaller, so the current flowing through is very small, and the heat generated is also very small. The temperature change at the perovskite sub-cell is not large, thus avoiding the decomposition of the perovskite material in the perovskite sub-cell at high temperature, thereby improving the stability of the solar cell.

[0057] If the reverse breakdown voltage of the blocked solar cell is greater than the sum of the voltages generated by the other cells that receive normal light, the reverse voltage borne by the perovskite sub-cell is smaller, so the reverse electric field it withstands is smaller. Therefore, the influence of the reverse electric field on the halogen ions, metal or organic cations inside the perovskite sub-cell can be reduced, the ion escape phenomenon can be reduced, and the aging and device efficiency attenuation caused by the reaction between the ions inside the perovskite sub-cell and the functional layer or electrode in the battery can be alleviated.

[0058] For ease of understanding, one aspect of the present disclosure is to provide a method for preparing a solar cell, with reference to FIG1 . The method includes:

[0059] S100: preparing crystalline silicon sub-cells, wherein the parallel resistance of the crystalline silicon sub-cells is not less than a first target value.

[0060] S200: forming a perovskite sub-cell on the crystalline silicon sub-cell, wherein the parallel resistance of the perovskite sub-cell is not less than a second target value, and a ratio of the first target value to the second target value is not less than 40.

[0061] By forming a crystalline silicon sub-cell and a perovskite sub-cell through S100 and S200, a solar cell is prepared. It should be understood that the crystalline silicon sub-cell and the perovskite sub-cell should be connected in series so that the crystalline silicon sub-cell and the perovskite sub-cell of the single-junction cell are combined in series to form a multi-junction cell. The solar cell thus formed can effectively broaden the spectral response of the cell and have a higher ultimate photoelectric conversion efficiency than a single-junction cell. Exemplarily, the solar cell described in the present disclosure is a crystalline silicon perovskite tandem cell.

[0062] The solar cell described in the present disclosure is a multi-junction cell comprising a crystalline silicon sub-cell and a perovskite sub-cell, and can be, for example, a two-terminal, three-terminal or four-terminal cell, and the present disclosure does not impose any specific restrictions thereon. For example, the solar cell can be a crystalline silicon perovskite tandem cell, which can be a two-terminal cell, that is, a composite layer (i.e., a tunneling junction) can be provided between the crystalline silicon sub-cell and the perovskite sub-cell, thereby utilizing the composite layer to connect the crystalline silicon sub-cell and the perovskite sub-cell in series. The following description will be made using a crystalline silicon perovskite tandem cell as an example.

[0063] It is understandable that the present disclosure does not limit the type of crystalline silicon sub-cells. For example, the crystalline silicon sub-cells can be heterojunction cells (HJT, Hereto-junction with Intrinsic Thin-layer) or tunnel oxide passivated contact (Tunnel Oxide Passivated Contact, topcon) cells.

[0064] During the preparation of S100, the parallel resistance of the crystalline silicon bottom cell is increased as much as possible so that its parallel resistance is larger than the parallel resistance of the traditional crystalline silicon sub-cell, that is, the parallel resistance of the crystalline silicon sub-cell is not less than the first target value. Factors affecting the parallel resistance of the crystalline silicon sub-cell include but are not limited to edge leakage (such as incomplete etching, printing leakage), impurities and micro defects in the matrix, and partial short circuit of the PN junction (such as the diffusion junction is too shallow, the graining pyramid particles are too large). The parallel resistance of the crystalline silicon sub-cell can be increased as much as possible by optimizing the corresponding process. The first target value can be, for example, 200,000 ohm·cm 2 or above (e.g., 800,000 ohm·cm 2 or above), so that when the ratio of the parallel resistance of the crystalline silicon sub-cell to the parallel resistance of the perovskite sub-cell is greater than 40, the parallel resistance of the perovskite sub-cell will not be so small as to affect the efficiency of the perovskite sub-cell.

[0065] During the preparation process of S200, the parallel resistance of the perovskite sub-cell can be adjusted to reduce its parallel resistance compared to the parallel resistance of the conventional perovskite sub-cell, but the parallel resistance of the perovskite sub-cell cannot be less than the second target value. In S200, the parallel resistance of the perovskite sub-cell needs to be controlled within a relatively small range that does not affect the efficiency, such as 1,000 ohm·cm 2 above, for example, preferably 5,000 ohm·cm 2 ~10,000 ohm·cm 2 , or for example 5,000 ohm·cm 2 ~800,000ohm·cm 2 .

[0066] 2 and 3, it can be seen that when the parallel resistance of the perovskite sub-cell is 5,000 ohm·cm 2 Up to 20,000 ohm·cm 2 When the voltage is within the range of 100V, the IV curves of the perovskite sub-cells almost overlap (indicated by the arrows in Figure 3), and the efficiency is not much different. Therefore, the parallel resistance of the perovskite sub-cell is not less than 5,000 ohm·cm 2 (The second target value is 5,000 ohm·cm 2 ), the efficiency of the perovskite sub-cell can be guaranteed to be basically unaffected.

[0067] Referring to Figures 2 and 4 and Table 1 below, it can be seen that the parallel resistance of the perovskite cell is 1,000 ohm·cm 2 The fill factor FF is greater than 81.5%, and can be further improved through optimization, 1,000ohm·cm 2 The parallel resistance has a smaller impact on FF. The parallel resistance of the perovskite subcell is 5,000 ohm·cm 2 Up to 20,000 ohm·cm 2 When the IV curves of the perovskite sub-cells are almost the same, the efficiency is not much different. Therefore, the parallel resistance of the perovskite sub-cell is preferably not less than 5,000 ohm·cm 2 (For example, the second target value may be 5,000 ohm·cm 2 ), the efficiency of the perovskite sub-cell can be guaranteed to be basically unaffected.

[0068] Table 1

[0069] Through S100 and S200, the crystalline silicon sub-cell and the perovskite sub-cell can be set to a suitable parallel resistance range, and the numerical difference in parallel resistance between the crystalline silicon sub-cell and the perovskite sub-cell can be effectively increased. Therefore, when the solar cell is blocked and is in reverse bias, the difference in parallel resistance between the crystalline silicon sub-cell and the perovskite sub-cell can be used to increase the proportion of reverse voltage borne by the crystalline silicon sub-cell and reduce the proportion of reverse voltage borne by the perovskite sub-cell, thereby weakening the adverse effects of the hot spot effect on the perovskite sub-cell, improving the stability of the solar cell under the hot spot effect, and increasing the life of the solar cell.

[0070] It should be understood that crystalline silicon cells and perovskite cells have parallel resistance (also known as bypass resistance). In crystalline silicon cells, the smaller parallel resistance is mainly caused by process defects, such as pinhole shorts caused by local defects in high-temperature diffusion, local overlap of the front and back films at the edge of the cell, or local shorts caused by the metallization process. Such local process defects can cause current shunting, and in severe cases, the fill factor of the cell is significantly reduced, resulting in low cell efficiency. Therefore, in order to improve the conversion efficiency of solar cells, it is generally desirable to increase the parallel resistance of both crystalline silicon and perovskite sub-cells.

[0071] However, in the disclosed solution, for the perovskite sub-cell, the parallel resistance of the perovskite sub-cell is adjusted to a suitable range instead of blindly increasing it. Therefore, the disclosed solution adjusts the parallel resistance of the perovskite sub-cell in the opposite direction to the conventional method of increasing the parallel resistance of the perovskite sub-cell, and controls the parallel resistance of the perovskite sub-cell within a relatively small range without affecting the efficiency, such as 5,000 ohm·cm 2 Up to 100,000 ohm·cm 2 At the same time, the parallel resistance of the crystalline silicon sub-cell is increased as much as possible to increase the difference in parallel resistance between the two, thereby effectively alleviating and weakening the impact of the hot spot effect on the perovskite sub-cell, improving the stability of the solar cell under the hot spot effect, and increasing the life of the solar cell.

[0072] Furthermore, the design concept of the present disclosure for qualified inspection or screening of battery production lines is also different from the prior art, in which the parallel resistance of crystalline silicon batteries is set to a minimum qualified value (generally 20,000 ohm·cm 2 ) is used to screen cells that meet specifications on the production line and does not significantly increase the parallel resistance. For perovskite cells, there are currently no specific restrictions on parallel resistance, and the general goal is to maximize the parallel resistance.

[0073] However, in the disclosed solution, for the crystalline silicon sub-cell, on the one hand, the parallel resistance of the crystalline silicon sub-cell is improved as much as possible from the process, and on the other hand, the parallel resistance qualification standard in the qualified inspection item of the crystalline silicon sub-cell is increased to the first target value, such as 200,000 ohm·cm 2 Above, for example 800,000 ohm·cm 2 Alternatively, a secondary screening is designed based on the original qualified test to select crystalline silicon cells with parallel resistance greater than or equal to the first target value. Other crystalline silicon cells with parallel resistance greater than the conventional qualified value (such as 20,000 ohm·cm 2 ) However, a crystalline silicon subcell with a resistance less than the first target value can be used as a single-junction cell. In specific implementations, the first target value can be set based on actual conditions while optimizing and increasing the parallel resistance of the crystalline silicon subcells as much as possible. This application does not impose specific limitations on this.

[0074] In the disclosed solution, for the perovskite sub-cell, the parallel resistance of the perovskite sub-cell is controlled to be no less than the second target value (1,000 ohm·cm 2 Or above, such as 5000ohm / cm 2 ), and the ratio of the parallel resistance of the crystalline silicon sub-cell to the parallel resistance of the perovskite sub-cell is not less than 40. In a specific implementation, the screening criteria can be set based on the ratio and the first target value without significantly affecting the output power of the perovskite sub-cell, and this application does not impose any specific restrictions on this.

[0075] By controlling the parallel resistance of the crystalline silicon subcell and the perovskite subcell, and thereby rationally controlling the ratio of the reverse voltage to which the perovskite subcell is subjected, the impact of the hot spot effect on the perovskite subcell can be effectively mitigated and weakened without substantially affecting the power generation of the solar cell, thereby improving the stability of the solar cell under the hot spot effect. For example, the ratio of the parallel resistance of the crystalline silicon subcell to the parallel resistance of the perovskite subcell can be set to be greater than 40 (e.g., greater than 100). For example, this ratio can also be set to values ​​such as 80, 100, 150, 200, or 300. When the ratio of the parallel resistance of the crystalline silicon subcell to the perovskite subcell is controlled within this range, a better balance can be achieved between the power generation of the perovskite subcell and the adverse effects of the hot spot effect on the perovskite subcell, thereby improving the stability of the solar cell under the hot spot effect and extending the life of the solar cell.

[0076] In some embodiments, the ratio of the parallel resistance of the crystalline silicon sub-cell to the parallel resistance of the perovskite sub-cell is greater than 100.

[0077] In other embodiments, the ratio of the parallel resistance of the crystalline silicon sub-cell to the parallel resistance of the perovskite sub-cell is greater than 150, and further, the ratio of the parallel resistances is greater than 200.

[0078] Considering that a photovoltaic module usually includes a battery string, and each battery string can be composed of multiple solar cells connected in series, the specific design of the photovoltaic module needs to be considered when setting the ratio of the parallel resistance of the crystalline silicon sub-cell to the perovskite sub-cell. For example, the actual number of solar cells in the battery string within the module should be considered to determine the maximum reverse bias voltage that a certain cell can withstand. In this way, the ratio of the parallel resistance of the crystalline silicon sub-cell to the perovskite sub-cell of the solar cell can be made greater than [(n-1)*V oc-tandem / V bias-max ]-1, n is the number of cells in the cell string where the solar cell is located, V oc-tandem is the voltage of the crystalline silicon perovskite stacked battery, V bias-max is the maximum reverse bias voltage that the perovskite sub-cell can withstand.

[0079] If the maximum reverse voltage that the perovskite sub-cell can withstand is calculated to be 0.3V (cations and halogen ions can migrate at only 0.3V), the ratio of the parallel resistance of the crystalline silicon sub-cell to the parallel resistance of the perovskite sub-cell must be greater than 10 / 3*(n-1)*V oc-tandem -1. V oc-tandem The general value is 2V. Considering the process factors, V bias-max The maximum reverse voltage V that the perovskite sub-cell can withstand is bias-max It can be controlled below 0.2V, so the ratio of the parallel resistance of the crystalline silicon sub-cell to the titanium ore sub-cell should preferably be no less than [(n-1)*V oc-tandem / 0.2], which is about 10(n-1), which is safer. Of course, the maximum reverse voltage V bias-max The value can also be changed according to actual conditions.

[0080] Typically, V oc-tandem The general value is 2V. Considering factors such as process, it can be slightly changed up or down based on 2V. oc-tandem Calculate the qualified value of .

[0081] Taking the current 210 half-cell design for a medium-sized photovoltaic module, with 22 cells in a string, the open-circuit voltage of a stacked solar cell is a maximum reverse bias of 21 × 2V = 42V. If a 1% reverse electric field is applied to the perovskite subcell, the voltage is 0.42V. Cations and halides require only 0.3V for migration. When the ratio of the parallel resistance of the crystalline silicon subcell to the perovskite subcell is controlled at 150, the maximum reverse bias is 21 × 2V = 42V. If a 1 / 150 reverse electric field is applied to the perovskite subcell, the voltage is 42V * 1 / 150 = 0.28. Furthermore, allowing for some margin, the reverse voltage to which the perovskite subcell can be subjected can be controlled to 0.2V. Therefore, in this example, the ratio of the parallel resistance of the crystalline silicon subcell to the perovskite subcell can be controlled to above 200.

[0082] In practice, the larger the parallel resistance ratio, the more difficult it is to achieve. The above calculations consider the extreme case. Therefore, for a 210 half-cell design, the parallel resistance ratio of the crystalline silicon sub-cell to the perovskite sub-cell can be controlled to be above 100, preferably above 150, and most preferably above 200. In specific implementations, adaptive adjustments can be made based on the actual number of cell strings, the actual open-circuit voltage of the stacked cell, the maximum bias voltage, and the probability of occurrence.

[0083] Furthermore, the open-circuit voltage of a cell actually decreases with increasing temperature and increases with decreasing temperature. The following calculations consider the effect of temperature on open-circuit voltage. Furthermore, there is no unified standard for module panel design for perovskite-silicon tandem cells, nor is there a unified industry standard for the number of cells in a string. For this calculation, the number of cells in the string is temporarily referenced in Table 2, which shows the most likely string designs for tandem cells.

[0084] Table 2

[0085] The operating temperature range of photovoltaic cells is usually between -40℃ and 85℃, and the standard operating temperature is 25℃. The voltage temperature coefficient of crystalline silicon cells is 0.24%. Considering that the operating temperature of crystalline silicon cells can drop by up to 65℃, the maximum increase in the open circuit voltage of crystalline silicon cells is 760mv*65*0.24%=118mv. The temperature coefficient of the open circuit voltage of perovskite cells is even lower, about one-tenth of the temperature coefficient of the open circuit voltage of crystalline silicon cells. The specific value is related to the perovskite system. Considering some safety margin, the temperature coefficient of the perovskite crystalline silicon tandem cell can also be calculated as 0.24%. The maximum increase in the open circuit voltage of the tandem cell is: 2v*65*0.24%=0.312v, that is, considering the temperature effect, the maximum open circuit voltage of the tandem cell is: 2v+0.312=2.312V. The actual output voltage of the tandem cell is V oc-tandem Will be less than 2.312V.

[0086] When n=6, it is inferred that the ratio of the parallel resistance of the crystalline silicon sub-cell to the parallel resistance of the perovskite sub-cell is greater than V oc-tandem *(n-1) / V bias-max =2.312*(6-1) / 0.3=38.53. Taking into account the case of reserving some margin, the ratio of the parallel resistance of the crystalline silicon sub-cell to the parallel resistance of the perovskite sub-cell is greater than 40. At this time, the maximum reverse bias voltage that the perovskite sub-cell can withstand is: 2.312*(6-1)*1 / 40=0.289, which is less than 0.3V. For example, the parallel resistance of the crystalline silicon sub-cell is controlled at 200,000 ohm·cm 2 and above, the parallel resistance of the perovskite subcell is 5,000 ohm·cm 2 about.

[0087] When n=12, it is inferred that the ratio of the parallel resistance of the crystalline silicon sub-cell to the parallel resistance of the perovskite sub-cell is greater than V oc-tandem *(n-1) / V bias-max =2.312*(12-1) / 0.3=84.8. Considering that more margin is reserved, the ratio of the parallel resistance of the crystalline silicon sub-cell to the parallel resistance of the perovskite sub-cell can be controlled to be greater than 100. At this time, the maximum reverse bias voltage that the perovskite sub-cell can withstand is: 2.312*(12-1)*1 / 100=0.254, which is less than 0.3V. For example, the parallel resistance of the crystalline silicon sub-cell is controlled at 200,000 ohm·cm 2 and above, the parallel resistance of the perovskite subcell is 2,000 ohm·cm 2 about.

[0088] For the G210 half cell, n=23, and it can be inferred that the ratio of the parallel resistance of the crystalline silicon subcell to the parallel resistance of the perovskite subcell is greater than V oc-tandem *(n-1) / V bias-max =2.312*(23-1) / 0.3=169.54, which is about 170. Considering that more margin is reserved, the ratio of the parallel resistance of the crystalline silicon sub-cell to the parallel resistance of the perovskite sub-cell can be controlled to be greater than 200. For example, the parallel resistance of the crystalline silicon sub-cell is controlled at 200,000 ohm·cm 2 and above, the parallel resistance of the perovskite subcell is 1,000 ohm·cm 2 about.

[0089] For the G210 half-cell, if we only consider the effect of temperature on the crystalline silicon sub-cell and ignore the effect on the perovskite cell (which is relatively small), Voc-tandem =2V+118mv=2.118V, based on this, the ratio of the parallel resistance of the crystalline silicon sub-cell to the parallel resistance of the perovskite sub-cell is greater than V oc-tandem *(n-1) / V bias-max =2.118*(23-1) / 0.3=155.32, which is approximately 155. According to this calculation result, the ratio of the parallel resistance of the crystalline silicon sub-cell to the perovskite sub-cell can be controlled to be above 150.

[0090] It should be understood that when the format or series-parallel layout of the photovoltaic modules changes, the above formula can be used to make adaptive adjustments.

[0091] In some embodiments, the first target value is 200,000 ohm·cm 2 or above, for example, 300,000 ohm·cm 2 or above, 800,000 ohm·cm 2 or above, 900,000 ohm·cm 2 or above, 1000,000 ohm·cm 2 or above. The parallel resistance of the perovskite sub-cell is greater than or equal to a second target value and satisfies the ratio of the parallel resistances of the crystalline silicon sub-cell to the perovskite sub-cell. The second target value prevents the parallel resistance of the perovskite sub-cell from being reduced to a level that affects the cell efficiency or causes a non-negligible reduction in efficiency. The second target value can be specifically determined through experimentation. When the parallel resistance of the perovskite sub-cell is greater than the second target value, the efficiency reduction of the perovskite sub-cell due to the reduction in its parallel resistance standard is negligible.

[0092] After testing, the parallel resistance of the crystalline silicon perovskite tandem cell and the perovskite sub-cell was 1,000 ohm·cm 2 or more (e.g. 5,000 ohm·cm 2 The change in battery efficiency due to the change in parallel resistance can be ignored, that is, the second target value can be 1,000 ohm·cm 2 , 2,000ohm·cm 2 、5,000ohm·cm 2 or greater than 5,000 ohm·cm 2 Specifically, the parallel resistance of the perovskite subcell can be 5,000 ohm·cm 2 、6,000ohm·cm 2 , 7,000ohm·cm 2 Etc., this embodiment does not impose any specific limitation on the second target value.

[0093] In some embodiments, the parallel resistance of the perovskite subcell can be in the range of 5,000 ohm·cm 2 Up to 20,000 ohm·cm 2 , or 5,000 ohm·cm 2 Up to 10,000 ohm·cm 2 , for example 5,000 ohm·cm 2 、10,000ohm·cm 2 、15,000ohm·cm 2 etc.; correspondingly, the parallel resistance of the crystalline silicon sub-cell can be determined according to the parallel resistance of the perovskite sub-cell so as to satisfy the ratio relationship between the two, and this embodiment does not impose any specific restrictions on it.

[0094] Specifically: Please refer to Figures 2 and 3, which show that the parallel resistance of the perovskite sub-cell is 1,000 ohm·cm 2 、5,000ohm·cm 2 、10,000ohm·cm 2 、15,000ohm·cm 2 、30,000ohm·cm 2 、50,000ohm·cm 2 When the current and voltage generated by the corresponding perovskite sub-cell are 5,000 ohm·cm, it can be seen from Figures 2, 3 (indicated by the arrows in Figure 3) and 4 that when the parallel resistance of the perovskite sub-cell is 5,000 ohm·cm 2 Up to 20,000 ohm·cm 2 When the resistance of the perovskite sub-cell is within the range of 100000 ohm·cm, the IV curves of the perovskite sub-cells are almost the same, and the efficiency difference is not much. The parallel resistance of the crystalline silicon sub-cell can reach 200,000 ohm·cm on the current production line. 2 After screening and optimization of crystalline silicon sub-cells, the resistance is expected to be 200,000-400,000ohm·cm 2 Therefore, the parallel resistance of the perovskite subcell can be controlled at 5,000 ohm·cm 2 Up to 10,000 ohm·cm 2 .

[0095] In some embodiments, a crystalline silicon perovskite tandem cell is provided, wherein the parallel resistance of the crystalline silicon subcell is 1,000,000 ohm·cm 2 , the parallel resistance of the perovskite subcell is 10,000 ohm·cm 2 , the bias voltages allocated between the two are shown in Figure 5.

[0096] In other embodiments, the parallel resistance of the crystalline silicon subcell is 1,000,000 ohm·cm 2, the parallel resistance of the perovskite subcell is 5,000 ohm·cm 2 Through the simulation results, it can be found that the crystalline silicon sub-cell and the perovskite sub-cell bear a reverse bias voltage in proportion to their respective parallel resistances. Since the parallel resistance of the perovskite sub-cell is small, it only bears less than 1% of the bias voltage. Therefore, the stability of the perovskite sub-cell in the hot spot state can be greatly enhanced.

[0097] In actual production, a test sorting can be set up on the production line, that is, the parallel resistance of the crystalline silicon sub-cell is greater than or equal to the qualified value, which means that the test is qualified. The qualified value can be, for example, 20,000 ohm·cm 2 If the parallel resistance of the crystalline silicon sub-cell is greater than a first target value (greater than a qualified value, such as 200,000 or 800,000), it can be used as the bottom cell of the stacked cell.

[0098] The parallel resistance of the perovskite sub-cell is equal to or greater than the second target value. Therefore, the solar cell that meets the qualification line can be selected by screening, and then the upper limit of the parallel resistance of the crystalline silicon sub-cell is determined according to the ratio of the parallel resistance of the crystalline silicon sub-cell to the parallel resistance of the perovskite sub-cell. This ratio is determined based on the number of battery cells in series at the component application end. The preparation process of the perovskite sub-cell is adjusted to meet the requirements of the present disclosure for the parallel resistance of the perovskite sub-cell. A stacked battery with an appropriate value of the parallel resistance ratio of the crystalline silicon sub-cell to the perovskite sub-cell is obtained through online qualification testing or screening, and the battery is subjected to reverse bias avalanche voltage testing on the production line. For example, a battery with a smaller parallel resistance ratio and a smaller avalanche voltage can be used in small-sized components with a smaller number of series-connected cells, and will not affect stability. A battery with a higher parallel resistance ratio and a higher avalanche voltage can be used in large-plate components.

[0099] Of course, the present disclosure does not impose any specific restrictions on the method of increasing the parallel resistance of the crystalline silicon sub-cell. For example, the transparent conductive oxide film (TCO) coating process on the back of the crystalline silicon sub-cell can be adjusted, such as using reactive ion deposition (RPD process) to control the edge film overflow phenomenon of the TCO process, or optimizing the carrier based on traditional physical vapor deposition (PVD process), increasing the shielding area of ​​the edge of the carrier, and controlling the local short-circuit channel at the edge.

[0100] For example, in one method, if the crystalline silicon sub-cell is a heterojunction cell, a mask plate is used to block the edge area of ​​the back of the cell, and a sputtering process is used to form a transparent conductive film on the back of the cell; or, a mask plate is used to block the edge area of ​​the back of the cell, and a reactive plasma deposition process is further used to replace the sputtering process to form a transparent conductive film on the back of the cell;

[0101] When the crystalline silicon subcell is a heterojunction cell and the silicon wafer is n-type, the plasma-enhanced chemical vapor deposition process is to form an intrinsic layer on the front surface of the n-type silicon wafer, an intrinsic layer on the back surface of the n-type silicon wafer, an n-type doped layer on the intrinsic layer on the front surface of the n-type silicon wafer, and a p-type doped layer on the intrinsic layer on the back surface of the n-type silicon wafer. Alternatively, the intrinsic layer and n-type doped layer can be first formed on the front surface of the n-type silicon wafer, and then the intrinsic layer and p-type doped layer can be formed on the back surface of the n-type silicon wafer. A transparent conductive film (TCO) is deposited entirely on the n-type doped layer on the front surface, and when forming the TCO on the p-type doped layer on the back surface, a mask can be used to block the edge area on the back of the p-type doped layer. Then, a sputtering process is used to form the TCO on the p-type doped layer. This can reduce edge leakage current, and the more edge blocking, the better the effect.

[0102] For example, in another method, the difference from the previous method is that reactive plasma deposition can be used instead of magnetron sputtering (it is still necessary to block the edge area on the back of the p-type doped layer through a mask plate), because reactive plasma deposition has better directionality. Under the same edge blocking conditions, the leakage current of reactive plasma deposition is smaller.

[0103] For example, in one method: if the crystalline silicon sub-cell is a tunneling oxide passivation contact (TOPCon) cell, after forming an ultra-thin tunneling layer or a polycrystalline silicon film, the wrap-around plating generated on the front surface of the cell is removed, or the ultra-thin tunneling layer and / or polycrystalline silicon film is prepared by a physical vapor deposition process to avoid wrap-around plating on the front surface of the cell.

[0104] When the crystalline silicon sub-cell is a tunneling oxide passivation contact cell, and if the silicon wafer is N-type, a p-type emitter and a passivation layer need to be formed in sequence on the upper surface of the N-type silicon wafer, and an ultra-thin tunneling layer and a polysilicon film (silicon oxide / poly layer process) need to be formed on the lower surface of the N-type silicon wafer. After the ultra-thin tunneling layer or polysilicon film is formed (generally PECVD or LPCVD), the wrap-around plating generated on the front surface of the cell is completely removed to reduce leakage current at the edge. Of course, the physical vapor deposition process can also be used to prepare the ultra-thin tunneling layer and / or polysilicon film in the crystalline silicon sub-cell, because the physical vapor deposition process does not produce wrap-around plating, which can effectively reduce leakage current at the edge.

[0105] For example, in one embodiment, during the formation of the composite layer, a portion of the film layer is located on the side of the crystalline silicon sub-cell. Therefore, the composite layer located on the side of the crystalline silicon sub-cell can be removed by an edge engraving process to achieve the above purpose.

[0106] This embodiment does not specifically limit how to increase the parallel resistance of the crystalline silicon sub-cell. The manufacturing process of the crystalline silicon sub-cell can adopt any one or more of the above methods, so that the parallel resistance of the crystalline silicon sub-cell is not less than the first target value.

[0107] Optionally, the present disclosure may also adopt at least one of the following in the preparation process of the perovskite sub-cell so that the parallel resistance of the perovskite sub-cell is not less than a second target value, and the ratio of the parallel resistance of the crystalline silicon sub-cell to the parallel resistance of the perovskite sub-cell is not less than 40: regulating the lateral conductivity of the composite layer located between the crystalline silicon sub-cell and the perovskite sub-cell; regulating the density of the electron transport layer of the crystalline silicon sub-cell, and regulating the crystallization growth site of the perovskite buried interface.

[0108] One of the ways is to increase the parallel resistance of the crystalline silicon sub-cell by reducing the lateral conductivity of the composite layer.

[0109] For example: in the process of preparing the composite layer located between the crystalline silicon sub-cell and the perovskite sub-cell, the thickness of the composite layer is thinned; for example: when preparing the TCO composite layer, the oxygen ventilation volume is increased to reduce the carrier concentration and thus reduce the conductivity; for example: a doped nanocrystalline silicon oxide thin film layer is used instead of TCO as the composite layer to reduce the lateral conductivity of the composite layer.

[0110] Another way is to adjust the parallel resistance by regulating the density of the electron transport layer. The denser the electron transport layer, the greater the parallel resistance of the perovskite sub-cell. Conversely, the looser the electron transport layer, the smaller the parallel resistance of the perovskite sub-cell. For example, in the process of preparing perovskite sub-cells, before forming a tin oxide thin film layer (electron transport layer) by an in-situ deposition process, a small molecule or low molecular weight polymer material with hydroxyl groups is deposited on the surface of the cell to provide a dense site for TDMASn attachment, thereby increasing the density of the tin oxide thin film layer. For another example, in the process of preparing perovskite sub-cells, the thickness of the tin oxide thin film layer formed by the atomic layer deposition process is increased, so that the parallel resistance of the perovskite sub-cell can be effectively increased. For another example, due to insufficient purge in the atomic layer deposition process, the process can be considered as an ALD (atomic layer deposition) / CVD (chemical vapor deposition) mode. By increasing the purge time between the ALD precursor pulses, the density of the tin oxide film can be adjusted.

[0111] Another approach can achieve this by manipulating the crystallization growth sites at the buried perovskite interface. Specifically, for example, the wettability of the buried perovskite interface can be controlled to ensure that the perovskite deposition process is void-free. A high-boiling-point solvent-free perovskite solvent system can be used to ensure that during annealing, the perovskite film does not overflow with high-boiling-point solvents, damaging the film structure and causing voids. All of these approaches can improve the quality of the perovskite film and the parallel resistance of the perovskite subcell.

[0112] The above is mainly aimed at increasing the parallel resistance of the titanium ion sub-battery. If necessary, the parallel resistance of the titanium ion sub-battery can also be reduced by reverse adjustment.

[0113] In summary, by adjusting the parallel resistance ratio of the crystalline silicon sub-cell to the perovskite sub-cell, the parallel resistance of the crystalline silicon sub-cell can be made much larger than the parallel resistance of the perovskite sub-cell (more than 40 times, preferably more than 100 times). In this way, when the solar cell is reverse biased, the bias voltage allocated to the crystalline silicon sub-cell is also relatively large, protecting the perovskite sub-cell that is more sensitive to the reverse bias voltage and more easily damaged, thereby improving the hot spot resistance of the entire stacked cell (or multi-junction cell).

[0114] Furthermore, to further enhance the crystalline silicon subcell's ability to withstand reverse voltage, high-resistance silicon wafers can be used when preparing the crystalline silicon subcells in S100 to enhance their ability to withstand reverse voltage and match their resistance ratio with the stacked cell. The greater the silicon wafer resistance of the crystalline silicon subcell, the greater the reverse breakdown voltage of the cell, and the greater the cell's ability to withstand reverse voltage.

[0115] Specifically: a high-resistance silicon wafer with a resistivity of not less than 8 ohm·cm is used to prepare a crystalline silicon sub-cell.

[0116] For example, in a 72-panel module, the voltage of a single string of solar cells can be as high as 48V. In the worst case, if one of the battery cells is blocked, this battery cell will be subjected to a reverse bias of approximately 46V. If this battery cell is set to not be reversely broken down, high-resistance silicon wafers will need to be used to prepare crystalline silicon sub-cells.

[0117] Please refer to Figures 6 and 7, which show the reverse IV curves of the corresponding devices at silicon wafer resistances of 1-5 ohm·cm, 8-10 ohm·cm, 80-100 ohm·cm, and 1 k-2 kohm·cm. It can be seen that the 0.5 ohm·cm silicon wafer has the greatest tolerance for its minority carrier lifetime (silicon wafer quality). When the resistivity is higher than 8 ohm·cm, it has relatively no effect on the efficiency of the tandem cell. Therefore, it is preferred to use high-resistance silicon wafers with a resistivity of 8 ohm·cm or higher to prepare crystalline silicon sub-cells, so that the reverse breakdown voltage of the solar cell can be greater than 40V or greater than 48V, for example 60V.

[0118] It should be noted that, according to FIG. 6 and FIG. 7 , it can be seen that the reverse breakdown voltage of the solar cell can be greater than 48V.

[0119] The inventors discovered that using high-resistance silicon wafers sacrifices some cell efficiency for module stability. Assuming the same minority carrier lifetime, Figure 8 shows the relationship between cell efficiency, silicon wafer resistivity, and bulk minority carrier lifetime. While using high-resistance silicon wafers can reduce efficiency by ~0.3 to 0.5%, in practice, high-resistance silicon wafers generally have a longer minority carrier lifetime, effectively compensating for or even neutralizing the loss in cell efficiency.

[0120] On the other hand, an embodiment of the present disclosure provides a solar cell, comprising a crystalline silicon sub-cell and a perovskite sub-cell arranged in series, wherein the ratio of the parallel resistance of the crystalline silicon sub-cell to the parallel resistance of the perovskite sub-cell is greater than 100. Therefore, the influence of the hot spot effect on the perovskite sub-cell can be effectively alleviated and weakened without substantially affecting the power generation capacity of the solar cell, thereby improving the stability of the solar cell under the hot spot effect.

[0121] Optionally, the solar cell is a crystalline silicon perovskite tandem cell, and the ratio of the parallel resistance of the crystalline silicon sub-cell to the parallel resistance of the perovskite sub-cell is greater than V oc-tandem *(n-1) / V bias-max , n is the number of solar cell strings, V oc-tandem is the voltage of the crystalline silicon perovskite tandem battery, V bias-max is the maximum reverse bias voltage that the perovskite subcell can withstand.

[0122] In some embodiments, the solar cell disclosed herein is a crystalline silicon perovskite tandem cell, and the ratio of the parallel resistance of the crystalline silicon subcell to the parallel resistance of the perovskite subcell is greater than 10 / 3*(n-1)*V oc-tandem , n is the number of solar cell strings, V oc-tandem is the voltage of a crystalline silicon perovskite stacked cell.

[0123] Assuming that the battery string contains n stacked batteries, when it is blocked and a hot spot effect occurs, the maximum reverse bias voltage that one of the batteries may withstand is (n-1)V. oc-tandem , V oc-tandem is the voltage of a crystalline silicon perovskite stacked cell, which is generally about 2 volts. Based on this, the maximum reverse voltage that the perovskite sub-cell can withstand is controlled at Vbias-max (the maximum reverse voltage that the perovskite sub-cell can withstand). The ratio of the parallel resistance of the crystalline silicon sub-cell to the perovskite sub-cell must be greater than [(n-1)*V oc-tandem / V bias-max ]-1.

[0124] If the maximum reverse voltage that the perovskite sub-cell can withstand is calculated to be 0.3V (cations and halogen ions can migrate at only 0.3V), then the ratio of the parallel resistance of the crystalline silicon sub-cell to the parallel resistance of the perovskite sub-cell must be greater than [10 / 3*(n-1)*V bias-max ]-1.

[0125] If the process factors will cause V bias-max The maximum reverse voltage V that the perovskite sub-cell can withstand is bias-max It is best to control it below 0.2V, so the ratio of the parallel resistance of the crystalline silicon sub-cell to the titanium ore sub-cell should preferably be no less than [(n-1)*V oc-tandem / 0.2], which is about 10(n-1), and is more secure.

[0126] Typically, V oc-tandem The typical value is 2V. Considering process factors and other factors, small fluctuations can be made within this range. Specific calculations can be based on the qualified V value set on the production line.

[0127] For example, in the current 210 half-cell design of a medium-sized photovoltaic module, with 22 cells in a string, according to the above calculation, the ratio of the parallel resistance of the crystalline silicon sub-cell to the perovskite sub-cell should be at least greater than 40, preferably greater than 100, or at least greater than 140, preferably greater than 210. In actual implementation, the ratio of the parallel resistance of the crystalline silicon sub-cell to the perovskite sub-cell is generally controlled to be greater than 150 (for example, greater than 200).

[0128] In some embodiments, the parallel resistance of the crystalline silicon subcell is 200,000 ohm·cm 2 .

[0129] In some embodiments, the parallel resistance of the crystalline silicon subcell is 1,000,000 ohm·cm 2 .

[0130] In some embodiments, the parallel resistance of the perovskite subcell is 5,000 ohm·cm 2 Up to 100,000 ohm·cm 2 .

[0131] In some embodiments, the parallel resistance of the perovskite subcell is between 5,000 and 8,000 ohm·cm 2 Above, the parallel resistance of the crystalline silicon sub-cell is 200,000 ohm·cm 2 Above, or 800,000 ohm·cm 2 above.

[0132] In some embodiments, the parallel resistance of the crystalline silicon subcell is 1,000,000 ohm·cm 2 Above, the parallel resistance of the perovskite subcell is 5,000 ohm·cm 2 Up to 20,000 ohm·cm 2 .

[0133] In some embodiments, the parallel resistance of the crystalline silicon subcell is 800,000 ohm·cm 2 Above, the parallel resistance of the perovskite subcell is 5,000 ohm·cm 2 Above, and the ratio of the two parallel resistances is greater than 150.

[0134] In some embodiments, at least one of the following conditions is met: the parallel resistance of the crystalline silicon subcell is 1,000,000 ohm·cm 2 Above, and / or, the parallel resistance of the perovskite subcell is 5,000 ohm·cm 2 Up to 20,000 ohm·cm 2 .

[0135] In some embodiments, at least one of the following conditions is met: the parallel resistance of the crystalline silicon subcell is 20,000 ohm·cm 2 Above, the parallel resistance of the perovskite subcell is 5,000 ohm·cm 2 Up to 10,000 ohm·cm 2 .

[0136] In some embodiments, the reverse breakdown voltage of the solar cell is not less than 40V.

[0137] In some embodiments, the reverse breakdown voltage of the solar cell is no less than 48V, for example, greater than 60V. For example, the reverse breakdown voltage of the crystalline silicon subcell can be increased by selecting a high-resistance wafer. This ensures that the stacked cell can withstand a reverse bias exceeding 40V (e.g., 48V or more) in the cell string of the module. This means that when reverse biased, the cell current is minimal, generating only minimal heat. For example, this can be achieved by using a high-resistance silicon wafer with a resistivity of no less than 8 ohm·cm.

[0138] Assuming the same minority carrier lifetime, using high-resistance silicon wafers will reduce efficiency by ~0.3% to 0.5%. However, in reality, because high-resistance silicon wafers generally have a longer minority carrier lifetime, using high-resistance silicon wafers has relatively little impact on the efficiency of tandem cells. Simulations have shown that when the resistivity is above 8 ohm·cm, the efficiency of tandem cells is barely affected.

[0139] The crystalline silicon sub-cell and perovskite sub-cell of the solar cell in the embodiment of this aspect can adopt the aforementioned crystalline silicon sub-cell and perovskite sub-cell, and therefore have the same or corresponding technical effects, which will not be described in detail here.

[0140] According to another aspect of the embodiments of the present disclosure, a photovoltaic module is provided, comprising a plurality of battery cells connected in series, wherein at least one of the plurality of battery cells is manufactured using any of the above-mentioned solar cell manufacturing methods.

[0141] According to another aspect of the embodiments of the present disclosure, a photovoltaic assembly is provided, comprising a plurality of battery cells connected in series, wherein at least one of the plurality of battery cells is any one of the aforementioned solar cells.

[0142] According to another aspect of the embodiments of the present disclosure, a photovoltaic device is provided, comprising any one of the photovoltaic modules described above.

[0143] In some embodiments, the photovoltaic device may also be a lighting device, an energy storage device, etc., and the embodiments of the present disclosure include but are not limited to the above. For example, the photovoltaic device may be a solar water heater, a solar street light, a solar photovoltaic generator, etc.

[0144] The disclosed solution is applicable to multi-junction cells comprising crystalline silicon subcells and perovskite subcells, particularly crystalline silicon perovskite tandem cells. Furthermore, it is also applicable to two-terminal, three-terminal, and four-terminal multi-junction cells. The crystalline silicon subcells disclosed herein may, for example, be heterojunction cells or topcon cells.

[0145] The foregoing description is merely a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Those skilled in the art will readily appreciate that various modifications and variations are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present disclosure shall be included within the scope of protection of the present disclosure. Industrial Applicability

[0146] The solar cell and preparation method provided by the present disclosure are for a multi-junction cell including a perovskite sub-cell and a crystalline silicon sub-cell. By configuring the parallel resistance of the crystalline silicon sub-cell and the parallel resistance of the perovskite sub-cell to be in a suitable ratio, the numerical difference in parallel resistance between the crystalline silicon sub-cell and the perovskite sub-cell is increased. When the solar cell is blocked and thus in reverse bias, the reverse voltage borne by the perovskite sub-cell is reduced by the difference in parallel resistance between the crystalline silicon sub-cell and the perovskite sub-cell, the influence of the hot spot effect on the perovskite sub-cell is weakened, the stability of the solar cell under the hot spot effect is improved, and the life of the solar cell is increased.

Claims

1. A solar cell comprising a crystalline silicon subcell and a perovskite subcell connected in series, characterized in that: The ratio of the parallel resistance of the crystalline silicon sub-cell to the parallel resistance of the perovskite sub-cell is greater than 40.

2. The solar cell according to claim 1, wherein The ratio of the parallel resistance of the crystalline silicon sub-cell to the parallel resistance of the perovskite sub-cell is greater than 100.

3. The solar cell according to claim 1, wherein The solar cell is a crystalline silicon perovskite stacked cell, and the ratio of the parallel resistance of the crystalline silicon sub-cell to the parallel resistance of the perovskite sub-cell is greater than V oc-tandem *(n-1) / V bias-max , n is the number of cells in the cell string where the solar cell is located, V oc-tandem is the voltage of the crystalline silicon perovskite stacked battery, V bias-max is the maximum reverse bias voltage that the perovskite sub-cell can withstand.

4. The solar cell according to any one of claims 1 to 3, wherein The parallel resistance of the crystalline silicon subcell is 200,000 ohm·cm 2 The parallel resistance of the perovskite subcell is 1,000 ohm·cm 2 above.

5. The solar cell according to any one of claims 1 to 3, wherein The parallel resistance of the crystalline silicon subcell is 800,000 ohm·cm 2 The parallel resistance of the perovskite subcell is 5,000 ohm·cm 2 above.

6. The method for preparing a solar cell according to claim 4 or 5, wherein: The parallel resistance of the perovskite subcell is 5,000 ohm·cm 2 Up to 10,000 ohm·cm 2 .

7. The method for preparing a solar cell according to claim 5, wherein: The parallel resistance of the crystalline silicon subcell is 1,000,000 ohm·cm 2 Above, and / or, the parallel resistance of the perovskite sub-cell is 5,000 ohm·cm 2 Up to 100,000 ohm·cm 2 .

8. The solar cell according to any one of claims 1 to 7, wherein The reverse breakdown voltage of the solar cell is not less than 40V.

9. The solar cell according to claim 8, wherein The reverse breakdown voltage of the solar cell is not less than 48V.

10. The solar cell according to any one of claims 1 to 9, wherein The crystalline silicon sub-cell adopts a high-resistance silicon wafer with a resistivity of not less than 8 ohm·cm.

11. A method for preparing a solar cell, characterized in that: The method comprises: preparing a crystalline silicon sub-cell, wherein the parallel resistance of the crystalline silicon sub-cell is not less than a first target value; A perovskite sub-cell is formed on the crystalline silicon sub-cell, wherein the parallel resistance of the perovskite sub-cell is not less than a second target value, and the ratio of the parallel resistance of the crystalline silicon sub-cell to the parallel resistance of the perovskite sub-cell is not less than 40.

12. The method for preparing a solar cell according to claim 11, wherein: The ratio of the parallel resistance of the crystalline silicon sub-cell to the parallel resistance of the perovskite sub-cell is not less than 100.

13. The method for preparing a solar cell according to claim 11 or 12, wherein: The first target value is 200,000 ohm·cm 2 , the second target value is 1,000 ohm·cm 2 .

14. The method for preparing a solar cell according to claim 11 or 12, wherein: The first target value is 800,000 ohm·cm 2 , and / or, the second target value is 5,000 ohm·cm 2 .

15. The method for preparing a solar cell according to claim 13 or 14, wherein: The parallel resistance of the perovskite subcell is in the range of 5,000 ohm·cm 2 Up to 10,000 ohm·cm 2 .

16. The method for preparing a solar cell according to claim 13 or 14, wherein: The parallel resistance of the crystalline silicon subcell is 1,000,000 ohm·cm 2 Above, and / or, the parallel resistance of the perovskite sub-cell is in the range of 5,000 ohm·cm 2 Up to 100,000 ohm·cm 2 .

17. The method for preparing a solar cell according to any one of claims 11 to 16, wherein: The preparation process of the crystalline silicon sub-cell adopts at least one of the following to ensure that the parallel resistance of the crystalline silicon sub-cell is not less than a first target value: If the crystalline silicon sub-cell is a heterojunction cell, a mask plate is used to block the edge area of ​​the back of the cell, and a sputtering process is used to form a transparent conductive film on the back of the cell; or, a mask plate is used to block the edge area of ​​the back of the cell, and a reactive plasma deposition process is further used to replace the sputtering process to form a transparent conductive film on the back of the cell; If the crystalline silicon sub-cell is a tunneling oxide layer passivation contact cell, after forming an ultra-thin tunneling layer or polycrystalline silicon film, the wrap-around plating generated on the front surface of the cell is removed, or the ultra-thin tunneling layer and / or polycrystalline silicon film is prepared by a physical vapor deposition process to avoid wrap-around plating on the front surface of the cell.

18. The method for preparing a solar cell according to any one of claims 11 to 17, wherein: The preparation process of the crystalline silicon sub-cell adopts a high-resistance silicon wafer with a resistivity of not less than 8 ohm·cm.

19. The method for preparing a solar cell according to any one of claims 11 to 18, wherein: The preparation process of the perovskite sub-cell adopts at least one of the following to ensure that the parallel resistance of the perovskite sub-cell is not less than a second target value, and the ratio of the parallel resistance of the crystalline silicon sub-cell to the parallel resistance of the perovskite sub-cell is not less than 40 or 100: Regulating the lateral conductivity of the composite layer between the crystalline silicon sub-cell and the perovskite sub-cell; Regulating the density of the electron transport layer of the crystalline silicon subcell, and, Regulating the crystallization growth sites at the buried perovskite interface.

20. A photovoltaic device, characterized in that: The invention comprises a plurality of battery cells connected in series, wherein at least one of the plurality of battery cells is a solar cell according to any one of claims 1 to 10, or at least one battery cell is prepared by the solar cell preparation method according to any one of claims 11 to 19.

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