Driver circuit and method for temporary storage of a gate charge in a capacitor

Abstract

A driver circuit (TR) comprises a driver output stage (TE) which has a gate potential (GP). The driver circuit (TR) has a switchable capacitor (SK) via which the gate potential (GP) is connected to a reference potential (M) of the driver circuit (TR). The invention furthermore relates to a method for the temporary storage of gate charge.

Description

[0001] Description

[0002] Driver circuit and method for temporarily storing gate charge in a capacitor

[0003] Electric vehicles have an inverter and an electric machine driven by the inverter. Pulse-width-modulated control signals are known to be used to control the electric machine, turning switches in the inverter on and off. The duty cycle of the control signal (PWM signal) determines the desired current acting on the electric machine. Inverters are known to use switches (semiconductor switches) that are either fully closed or fully open. These switches are not typically controlled in linear mode, which would result in a voltage drop across the switch with a simultaneous current flow, thus resulting in high power dissipation.In other words, for efficiency reasons and because of unwanted heat generation, it is well known that the electronic switches of a drive inverter should not be in linear operation for longer than necessary, in which a voltage drops across the switches while they carry a current. Therefore, the greatest possible edge steepness is desirable, if feasible.

[0004] Silicon-based IGBTs, for example, can be used to implement such an inverter, while SiC-based or GaN-based FETs, for example, enable higher edge steepness. However, the use of these transistors also generates (albeit lower) power dissipation. These transistors are so-called wide-bandgap semiconductors, which allows for high edge steepness (due to increased electron mobility). At the same time, semiconductors for fast switching require a minimum control voltage or gate voltage for efficient (fast) execution of the switching processes, so frequent switching also leads to significant losses due to the changing control voltage at the gate of the FET.Current driver circuits therefore generate undesirable power dissipation when driving the gate, so that it is an object of the invention to reduce the power dissipation in the driver circuit caused by switching in a simple and reliable manner.

[0005] This problem is solved by the subject matter of the independent claims. Further properties, features, embodiments, and advantages are revealed by the dependent claims, the description, and the figures.

[0006] It is proposed to connect a capacitor to the gate of a power semiconductor for a defined time, preferably during each switching operation (switching on and off, triggered by a PWM signal). The switching on takes place a defined period of time after the switching operation. In particular, the capacitor is only switched on for a predefined period of time. The connection carried out for switching on provides that the capacitor is connected to the gate shortly after switching on. When switched on, the gate voltage is (still) lower than the capacitor voltage, whereby charge is transferred from the capacitor to the gate. When switched on, part of the charge stored in the capacitor is thus transferred directly to the gate. This charge then no longer needs to be drawn from a supply or operating voltage source. The capacitor discharges to a specific value (voltage value).When the device is turned off, the capacitor is reconnected to the gate at defined times. Specifically, after the turn-off process, the capacitor is connected to the gate for a specific period of time.

[0007] Before connection, the gate (still) has a voltage that is higher than the voltage of the capacitor (which was partially discharged during the previous switch-on process). Accordingly, the charge supplied by the supply or operating voltage source, which must flow between a driver signal source and the gate to carry out the switching process, can also be reduced. Part of the gate charge can thus be stored on the capacitor (when the gate is switched off) or removed from it (when the gate is switched on) to support the switching process. The length of time the capacitor is connected to the gate during switch-on can be the same as the length of time the capacitor is connected to the gate during switch-off. In other embodiments, different lengths of time can be provided for switch-on and switch-off.This is performed repeatedly; after the switch-off, the next switch-on command follows, and the described cycle starts again. This allows some of the gate charge to be recovered and does not need to be taken from the operating voltage or the relevant source.

[0008] This approach can be implemented using a driver circuit. The driver circuit has a driver output stage with a gate potential. The gate potential can be applied to a power transistor. For this purpose, the driver output stage can also have a reference potential that can be connected to the power transistor. This allows the voltage between the gate potential and the reference potential to be applied to the power transistor as a control voltage for driving it. The reference potential is preferably a source potential or a ground potential, so that the control voltage is applied to the power transistor as a gate-source voltage. The reference potential can also differ from the source potential or ground potential by a potential difference, whereby the potential difference can be constant or adjustable in magnitude, but preferably does not have different polarities itself or for the switchable capacitor.

[0009] The driver circuit further includes a switchable capacitor. The gate potential is connected to the reference potential of the driver circuit via the switchable capacitor. The switchable capacitor thus has one end that is permanently connected to the reference potential of the driver circuit, just as the source potential is permanently connected to the reference potential. In particular, the switchable capacitor has one end that is permanently connected to the reference potential of the driver circuit, just as the source potential is permanently connected to the reference potential. Therefore, only one switchable element of the capacitor needs to be activated to achieve the desired effect.

[0010] The reference potential is connected directly (i.e., without a resistance element) to the gate potential via the switchable capacitor (as a series connection element). This enables a high current flow. The switchable capacitor is formed by a series connection of a switch and a capacitor. The switch can be connected to the reference potential via the capacitor. The switch can also be connected to the gate potential via the capacitor. Preferably, the switch is connected to the reference potential (directly), and the capacitor connects the switch (or the reference potential via the switch) to the gate potential. As a result, the switching signal of the switch can have a direct reference to the reference potential. The switch of the switchable capacitor is preferably a semiconductor switch, in particular a transistor, such as a MOSFET.

[0011] Furthermore, the switchable capacitor can be connected to the gate potential via a resistor. The switchable capacitor can also be connected directly to the gate potential and connected to the reference potential via a resistor. The switchable capacitor can also have a current-limiting resistor connected in series within the switchable capacitor. The switchable capacitor can itself have a current-limiting resistor, or a connection to a potential (to the reference potential or the gate potential) can have a current-limiting resistor. The current-limiting resistor is connected in series (with the aforementioned components). This results in a limited current. A series connection of the switchable capacitor and a resistor (for current limiting) can connect the reference potential to the gate potential.

[0012] The reference potential to which the switchable capacitor is (directly or permanently) connected can be the ground potential, the source potential, or the potential of a (constant) voltage source via which the switchable capacitor is connected to the ground or source potential. In particular, the gate potential can be connected via the switchable capacitor to a negative potential of a negative voltage source or to a positive potential of a positive voltage source, which can be part of a driver output stage of the driver circuit. The reference potential can be connected to the gate potential via the switchable capacitor and via a voltage source (in this order or vice versa). If the reference potential is, for example, ground, the gate potential can be connected to the gate potential via the switchable capacitor and via a voltage source (in this order or vice versa).

[0013] The switchable capacitor is connected to the reference potential in particular directly, with a potential offset (i.e., via a voltage source), and / or via a passive circuit (e.g., a resistor or a resistor circuit and / or a capacitor, perhaps connected in series). The switchable capacitor of the driver circuit is connected to the reference potential in particular in a polarity-maintaining manner, i.e., one end of the switchable capacitor that faces the reference potential when switched on is also facing the reference potential when switched off. In other words, the connection between the switchable capacitor and the reference potential is not capable of reversing the polarity of the switchable capacitor with respect to the gate potential.

[0014] The driver circuit may comprise a controller (control device). This controller is connected to the switchable capacitor or its switch in a driving manner. The controller is configured to set the switchable capacitor into an active state with a delay relative to the time of a switching edge of the driver circuit. The delay with which the switchable capacitor is set to the active (conductive) state may correspond to a predetermined time period, for example, between 0.1 and 1 ns or less than 2 ns. Other embodiments provide that the time period is no more than 5 ns, 20 ns, 100 ns, or no more than 1 ps, 5 ps, or 20 ps. The delay is preferably no longer than one PWM period or ON period or OFF period, which begins with the switching edge.

[0015] The delay is preferably constant, for example permanently implemented in the driver circuit. The delay can be predetermined. The controller can be implemented as a control device, for example as a control circuit or logic circuit, as a microprocessor with software code running on it (which at least partially implements the described procedure), or as a combination thereof. The controller is preferably set up to end the active state of the switchable capacitor after a predetermined ON duration. In this way, the amount of charge transferred between gate and capacitor is also controlled or limited. In particular, the voltage swing of the capacitor is limited during the switching on of the capacitor or during the ON duration. The controller can be set up so that the duration for which the capacitor charges the gate and the duration for which the gate charges the capacitor (corresponding to the ON duration or(depending on the active state) is no more than 2%, 1%, or 0.7% of the duration of a PWM period of a pulse pattern signal. The pulse pattern signal is the control signal of the power transistor.

[0016] A power circuit can be provided that has a power transistor and a driver circuit as described here. The power transistor has a gate (which has the gate potential). The power transistor also has a source; the gate-source voltage is applied between the gate and source of the power transistor. The power circuit also includes the driver circuit described here, the gate potential of which is connected to the gate of the power transistor. The reference potential of the driver circuit is connected to the source of the power transistor. The power transistor is preferably a power MOSFET or a power IGBT. The power transistor is designed in particular for voltages > 60 V, in particular of at least 400 V or at least 800 V, optionally for a blocking voltage of at least 1200 V.The power transistor is preferably designed for a rated current of at least 10 A, at least 50 A or at least 100 A.

[0017] The procedure described here can also be implemented by a method. The circuits described here are preferably designed to carry out the method. A method for temporarily storing charge of a gate of a power transistor is described. After a turn-on edge of the power transistor, a capacitor charges the gate. This is provided by designing the capacitor as a switchable capacitor (as described here) and activating the capacitor, for example, by an ON state of the switch of the capacitor. After a turn-off edge of the power transistor, the gate charges the capacitor, i.e., the gate is discharged to the capacitor. This step is also preferably carried out by activating the switchable capacitor. The charging processes result in desired changes in the gate potential, which in particular increase the switching speed, i.e.,Increase the edge steepness of the power transistor's on / off switching. This is achieved by designing the capacitor as a switchable capacitor (as described here) and activating it, for example, by an ON state of the capacitor's switch.

[0018] In particular, within the scope of the method, it is provided that the duration for which the capacitor charges the gate and the duration for which the gate charges the capacitor (i.e., the durations of the active state of the switchable capacitor) amount to only a small fraction of a PWM period of a pulse pattern signal with which the power transistor is driven. In particular, the duration for which the capacitor charges the gate and the duration for which the gate charges the capacitor amount to no more than 2%, 1%, or 0.7% of the duration of a PWM period of a pulse pattern signal with which the power transistor is driven.

[0019] In addition, the voltage swing of the voltage dropped across the capacitor element of the switchable capacitor is preferably only a fraction of the voltage swing at the transistor gate (the swing between a turn-on level and a turn-off level of the gate). The capacitor thus stores only a fraction of the charge applied to and removed from the gate. The magnitude of the voltage swing generated by charging the capacitor is, in particular, no more than 40%, 30%, or 25% of the voltage swing between a turn-on level and a turn-off level of the gate.

[0020] The charging (of the gate) or the start of charging after a turn-on edge is delayed by a predetermined time period compared to the turn-on edge. The charging (of the capacitor) after a turn-off edge is delayed by a predetermined time period compared to the turn-off edge. The delay is dimensioned such that the level of the gate is still at least 80%, at least 90%, or at least 95% of the level that was present at the gate immediately before the edge. The level of the gate relates to the reference potential and can therefore be regarded as a voltage relative to the reference potential. The time period by which the charging (or its start) is delayed compared to the respective preceding edge is in particular no more than 4%, 2%, 1%, or 0.7% of the duration of a PWM period of a pulse pattern signal with which the power transistor is controlled.

[0021] Figure 1 serves to explain exemplary embodiments of a driver circuit.

[0022] Figure 2 serves to explain the operation of exemplary driver circuits as well as to explain exemplary embodiments of the procedure described here.

[0023] Figure 1 shows a driver circuit TR with a bipolar power supply comprising a first voltage source V1 and a second voltage source V2. The voltage of the voltage source V2 is adapted to a desired OFF level of a gate G of a power transistor T, approximately -3 volts to -5 volts (e.g., 4 volts) relative to ground M. The voltage of the voltage source V1 is adapted to a desired ON level of a gate G of a power transistor T, approximately 10 volts to 15 volts (e.g., 12 volts) relative to ground M. The voltages of the voltage sources can also be greater (in magnitude) than the desired gate voltage to support the switching process.

[0024] The connection point, which results from the serial connection of the two voltage sources V1, V2, is connected to a reference potential M (ground). The voltage sources V1, V2 are part of a driver output stage TE. The driver output stage TE also has two switches S1, S2, with switch S1 connected downstream of the first, positive voltage source V1 and switch S2 connected downstream of the second, negative voltage source V2. The voltage outputs of the voltage sources V1, V2 are thus switchable. The switches S1, S2 are connected to a gate potential GP via respective resistors R1, R2. The gate potential GP is part of an output of the driver circuit TR or the driver output stage TE. If switch S1 is closed (and S2 is open), the gate potential GP receives the positive potential of the voltage source V1. If switch S2 is closed (and S1 is open), the gate potential GP receives the negative potential of the voltage source V2.

[0025] A power transistor T is connected downstream of the driver circuit TR and in particular of the driver output stage TE or the output A. Its gate terminal G is connected to the gate potential GP of the driver circuit TR. The drain D and source S of the power transistor T are connected to positive and negative potentials H-, H+, respectively, not directly, however, but via a load (not shown) that can be switched by the switching state of the power transistor T. The gate G or its potential defines the switching state of the power transistor T. Thus, the level of the gate potential GP of the driver circuit TR (relative to the reference potential M, which is also part of the output A) is crucial for the switching state of the power transistor. The control signal for the power transistor is emitted by the voltage between the potentials GP and M, with GP changing during control as shown.

[0026] To support the switching process and to avoid some of the power loss in the driver output stage TE, a switchable capacitor SK is provided. As shown, the switchable capacitor SK comprises a series circuit consisting of a capacitor C and a switching element S3. The switching element S3, which can also be referred to as switch S3, is assigned to the switchable capacitor SK or connected in series with it. The switching element S3 is in particular a MOSFET or another transistor. The reference potential is connected to the capacitor C via the switch S3. The end of the capacitor C opposite the switch S3 is connected to the driver output stage TE or to its gate potential GP. The switchable capacitor SK is thus connected to the output A of the driver circuit TR or the driver output stage.When switch S3 is closed, the capacitor C of the switchable capacitor SK is connected in parallel to the reference potential and the gate potential GP. The gate potential and the reference potential (ground) are therefore present at both ends of the capacitor C. The voltage between these potentials is then applied to the capacitor. The voltage across the capacitor is then applied to these potentials GP, M. The voltage between the reference potential M and the gate potential GP is then applied across the capacitor C. Not shown are parasitic series and parallel resistances of the capacitor C, which are preferably taken into account when examining the charging processes described below in detail (especially the parasitic series resistance which limits the current flow to / from the capacitor). Fig. 1 shows that the switchable capacitor SK is connected to the gate potential GP on the one hand and to the reference potential M on the other.However, the switchable capacitor can also be connected between the gate potential GP and a potential that is offset in potential from the reference potential M, for example with the negative potential of the voltage source V2 or with the positive potential of the voltage source V1. These two potentials are offset from the reference potential M (ground) due to the voltage sources. In principle, however, the switchable capacitor SK connects the gate potential GP to a potential (directly or indirectly) that is fixed relative to the potential to which the gate potential or its voltage refers. Only the connection of the switchable capacitor SK to reference potential M is shown; for clarity, other possible connections are not shown.Basically, the switchable capacitor SK is connected between the gate potential GP and a galvanically connected potential (with or without potential offset by a voltage source).

[0027] There is also a signal source for a pulse pattern or a pulse width modulation signal (cf. reference symbol PWM), by means of which the switches S1 and S2 are controlled. A controller ST is, as symbolically shown, connected to the switches S1, S2 and S3. The controller ST forms the signal source for a pulse width modulation signal (“PWM signal”), by means of which the switches S1, S2 are controlled or according to which a gate control voltage is generated at the output A. The controller ST can be regarded as the signal source for the pulse pattern PWM (pulse width modulated control signal) shown in Figure 2. The controller ST is set up to control the switches S1 and S2 alternately (or both in the OFF state). This results in a voltage at the gate potential GP compared to the reference potential M with a first level (switch-on level, positive level) when switch S1 is closed, corresponding to the positive voltage of the voltage source V1.A second level (switch-off level, negative level) results when switch S2 is closed, whereby the resulting second level corresponds to the negative potential of the second voltage source.

[0028] As mentioned, the speed of the switching process is crucial for the power loss at transistor T, whereby the switching processes also generate switching losses in the driver circuit TR due to the alternating voltages at the gate potential GP and at gate G. When changing between the two aforementioned levels, gate G is charged or discharged, depending on the direction of the switching edge, whereby each time charge must be removed from the gate at high speed or charge must be applied to the gate. To support this and thereby reduce the current that has to be supplied by the voltage sources V1, V2 for the charge transfer processes, the switchable capacitor SK is provided. This releases charge to gate G via the gate potential GP or via the output A in order to charge the gate with the capacitor in addition to the voltage source V1. When switch S2 is closed and voltage source V2 is therefore active, the gate is discharged.In this case, capacitor C supports the discharge process by absorbing charge. This results in a supporting current flow between the switchable capacitor SK and the gate potential GP, which supports the level change by the driver output stage TE.

[0029] The current flowing from the switchable capacitor SK to the gate potential GP of the output A has the same current flow direction as the current flowing simultaneously from the first voltage source V1 to the output A or to its gate potential GP. The same applies to the voltage source V2, which draws charge from the gate G (when S2 is closed), with the switchable side SK providing support here by generating an additional current flow in the same direction (away from the gate G or, respectively, the output). The controller ST also controls the switch S3, in particular with a delay to the control of the switches S1 and S2. The controller ST controls the switch S3 or, in general, the controllable capacitor SK using the capacitor control signal KS. The controller ST switches the switch S3 on when the switch S1 is switched on, but only for a short time of the duration of the ON state of the switch S1.The same applies to switch S2, whereby switch S3 is turned on when switch S2 is activated, but for a shorter period of time than the duration of the ON state of switch S2.

[0030] Figure 2 serves to explain in more detail the timing of the control process implemented by the controller ST (as a device). The upper timing diagram shows the pulse wave modulation signal PWM, according to which the switches S1 and S2 of Figure 1 are switched. When the pulse width modulation signal PWM is at a low level (low level - OFF level of transistor T), switch S2 is closed and switch S1 is open. When the pulse width modulation signal PWM is at a high level (high level - ON level of transistor T), switch S1 is closed and switch S2 is open. A switch-on edge PF 1 results when switch S1 is turned on. When switching to a closed switch S2, a switch-on edge PF 2 results.

[0031] The lower timing diagram shows the sequence of the capacitor switching signal KS in comparison to the sequence of the pulse width modulation signal PWM (PWM signal for short). Both timing diagrams in Figure 2 refer to a time profile t running to the right. It can be seen that there is a switching edge F1 (switch-on edge) of the capacitor switching signal KS, which occurs after the switch-on edge PF1 of the PWM signal. The switch-on edge F1 of the signal KS is delayed by the time period tD after the switch-on edge PF1. It can also be seen that the switch-off edge F2 of the capacitor switching signal KS occurs significantly before the switch-off edge PF2 of the PWM signal. The switch-on duration of the capacitor switching signal KS is shown as tON and is significantly shorter than the duration of the positive level between the edges PF1, PF2 of the PWM signal. During the delay tD the gate is not fully charged.Rather, there is a switch-on phase in which the gate only has a fraction of the voltage that exists at the end of the switch-on phase (just before the edge PF 2). If the capacitor C is now switched on for the duration tON between the edges F1 (switch-on edge) and F2 (subsequent switch-off edge) of the capacitor switching signal JS, the higher voltage of the capacitor SK (compared to the gate) can contribute to charging the gate. This results in the desired support of the switch-on process. The capacitor K has a voltage from a previous process during the duration tON that is higher than the voltage intended at gate G at this time, which up to this point is only a fraction of the final voltage (at the end of the ON phase of the PWM signal). This is why the supporting current flow from capacitor C to gate G occurs.

[0032] Figure 2 further shows that the same process is repeated after the turn-off edge PF2. If the PWM signal has a turn-off edge PF2, the capacitor is switched on after this switching edge PF2 for the duration tON' between the turn-on edge F1' and the turn-off edge F2' of the capacitor switching signal KS. Since the turn-on duration tON' is at the beginning of the corresponding period of the PWM signal, the gate G is only discharged to a fraction of its capacity shortly after the turn-off edge PF2 of the PWM signal. Switching on the capacitor C or SK then serves to support this, with the capacitor C or SK taking up the charge in this case. Since the capacitor is only switched on for a relatively short time, it neither reaches the high level nor the low level of the PWM signal. Rather, the voltage swing of the capacitor (between F1, F2 and the subsequent level orbetween FT, F2' and the subsequent level) represents only a fraction of the gate voltage swing, as shown in the upper PWM signal. Figure 2 shows that the temporary switching of the switchable capacitor ZK is repeated directly or shortly after the switching edges of the PWM signal, or is performed for all switching edges, although this can also be performed for only a portion of the switching edges. There may be operating ranges in which it is advantageous not to switch the capacitor on continuously.

[0033] The controller ST shown in Figure 1 is equipped to carry out the method described here, the switching operations of which are shown by way of example in Figure 2. The controller ST is in particular a control circuit, such as a logic circuit, or is at least partially implemented as software code that runs on a processor. The software code is configured to carry out the method described here when run on a processor. For this purpose, the processor can have a virtual or physical output interface for outputting the signal and, if applicable, the PWM signal. The controller can be configured to generate only the KS signal, while another control device generates the PWM signal. The controller can receive a PWM signal from this control device in order to generate the KS signal (with a time delay and with a shorter on duration) in accordance with the switching edges of the PWM signal. The delay tD is optional.Preferably, tON is less than 10%, 5%, or 1% of the ON time of the PWM signal. This depends on the size of the capacitor C and the gate capacitance acting on the gate G.

Claims

Patent claims 1 . Driver circuit (TR) with a driver output stage (TE) having a gate potential (GP), wherein the driver circuit (TR) further comprises a switchable capacitor (SK) via which the gate potential (GP) is connected to a reference potential (M) of the driver circuit (TR).

2. Driver circuit (TR) according to claim 1, wherein the switchable capacitor (SK) connects the reference potential (M) directly to the gate potential (GP) or the reference potential (M) is connected to the gate potential (GP) via the switchable capacitor (SK) and via a voltage source (V2), or a series circuit of the switchable capacitor (SK) and a resistor connects the reference potential (M) to the gate potential (GP).

3. Driver circuit (TR) according to claim 1 or 2, wherein the switchable capacitor (SK) is formed by a series circuit of a switch (S3) and a capacitor (C).

4. Driver circuit (TR) according to claim 1, 2 or 3, which further comprises a controller (ST) which is drivingly connected to the switchable capacitor (SK) and which is arranged to put the switchable capacitor (SK) into an active state (F1) with a delay (tD) compared to the time of a switching edge (PF1, PF2) of the driver circuit (TR).

5. Driver circuit (TR) according to claim 4, wherein the delay (tD) with which the switchable capacitor (SK) is set to the active state corresponds to a predetermined time period, or the delay (tD) ends when a predetermined level of the gate potential (GP) is reached.

6. Driver circuit (TR) according to claim 4 or 5, wherein the controller (ST) is arranged to terminate (F2) the active state of the switchable capacitor (SK) after a predetermined ON duration (tON).

7. Power circuit with a power transistor (T) having a gate (G), wherein the power circuit has a driver circuit (TR) according to one of the preceding claims, whose gate potential (GP) is connected to the gate (G) of the power transistor (T).

8. Method for temporarily storing charge of a gate (G) of a power transistor (T), wherein after a turn-on edge (PF1) of the power transistor (T) a capacitor (C) is switched on (F1) and charges the gate (G) and wherein further after a turn-off edge (PF2) of the power transistor (T) the capacitor (C) is switched on (F2), whereby the gate (G) charges the capacitor (C).

9. The method according to claim 8, wherein the duration (tON) for which the capacitor (C) charges the gate (G) and the duration (tON') for which the gate (G) charges the capacitor is not more than 2%, 1%, or 0.7% of the duration of a PWM period of a pulse pattern signal with which the power transistor is driven.

10. The method according to claim 8 or 9, wherein the amount of the voltage swing generated by the recharging at the capacitor is not more than 40%, 30% or 25% of the voltage swing existing between a turn-on level and a turn-off level of the gate (G).

11. Method according to one of claims 8, 9 or 10, wherein the recharging after a turn-on edge (PF1) of the power transistor is delayed by a predetermined time period (tD) relative to the turn-on edge (PF1) and the recharging after a turn-off edge (PF2) is delayed by a predetermined time period (tD') relative to the turn-off edge (PF2).

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