Apparatus and method

Abstract

An analogue front-end apparatus for analogue to digital conversion of analogue readout signals, the apparatus comprising a converter; a first capacitor; and a second capacitor; wherein the apparatus is configured to control each capacitor to operate in an integration mode which comprises operating the capacitor to store a charge associated with the analogue signal to be converted, and a conversion mode which comprises connecting the capacitor to the converter for a digital conversion indicative of a voltage of said capacitor; and wherein the apparatus is configured to control one of the capacitors to operate in its integration mode while controlling the other capacitor to operate in its conversion mode.

Description

[0001] Apparatus and Method

[0002] Technical Field

[0003] The present disclosure relates to the field of analogue front-end apparatuses, as well as methods of using such apparatuses and sensors comprising such apparatuses. For example, the present disclosure may relate to capacitive sensors and capacitive sensing methods, such as capacitive biometric skin contact sensors and methods, which utilise such analogue frontend apparatuses and methods.

[0004] Background

[0005] Capacitive biometric skin contact sensors are designed to detect the ridges and valleys in the skin of a user contacting the sensor. For this, capacitance is detected to obtain an indication of how far away the skin is from each of a plurality of different capacitive sensing electrodes of the sensor. By obtaining such information for an area of a user’s fingerprint, the user may be identified based on the unique distribution of ridges and valleys in their fingerprint.

[0006] The present disclosure provides improved apparatuses and methods for performing analogue to digital conversion of analogue read-out signals, such as for read-out signals from capacitive sensing electrodes of the type of capacitive sensors mentioned above.

[0007] Summary

[0008] The present invention is defined by the appended independent claims. Optional features are set out in the dependent claims. Aspects of the present disclosure may be provided in conjunction with each other, and features of one aspect may be applied to other aspects.

[0009] In an aspect, there is provided an analogue front-end apparatus for analogue to digital conversion of analogue read-out signals, the apparatus comprising: a converter; a first capacitor; and a second capacitor. The apparatus is configured to control each capacitor to operate in: (i) an integration mode which comprises operating the capacitor to store a charge associated with the analogue signal to be converted, and (ii) a conversion mode which comprises connecting the capacitor to the converter for a digital conversion indicative of a voltage of said capacitor. The apparatus is configured to control one of the capacitors to operate in its integration mode while controlling the other capacitor to operate in its conversion mode. Embodiments may provide a pipelined analogue front-end apparatus. This may facilitate increased throughput and / or higher efficiency for the apparatus. In turn, individual integration times for each read-out signal may be higher (and thus with higher sensitivity digitisation) while still achieving a high throughput of read-out signals being digitised.

[0010] Each capacitor may be selectively connectable to a read-out connection line. For example, each capacitor, e.g. a first plate of the capacitor, may be connected to the read-out connection line via a respective read-out switch. The read-out switch may be activated to connect the capacitor to the read-out connection line. The apparatus may be configured to control the connection of the capacitor to the read-out connection line to control whether or not the capacitor receives a read-out signal to be integrated. To perform an analogue signal integration with a capacitor, the apparatus is configured to connect that capacitor (e.g. its first plate) to the read-out connection line.

[0011] Each capacitor may be selectively connectable to an input of the converter. For example, each capacitor, e.g. a first plate of the capacitor, may be connected to the converter input via a respective converter switch. The converter switch may be activated to connect the capacitor to the input of the converter. The apparatus may be configured to control the connection of the capacitor to the converter input to control whether or not an integrated signal received on that capacitor is converted using the converter. To perform an analogue signal conversion with a capacitor, the apparatus is configured to connect that capacitor (e.g. its first plate) to the converter input.

[0012] Each capacitor may be selectively connectable to a first reference voltage source, such as an electrical ground. For example, each capacitor, e.g. a second plate of the capacitor, may be connected to the first reference voltage source (e.g. ground) via a respective ground switch. The ground switch may be activated to connect the capacitor to the first reference voltage source (e.g. to ground). The apparatus may be configured to control the connection of the capacitor (e.g. the second plate) to the first reference voltage source (e.g. ground) to occur when said capacitor (e.g. the first plate) is connected to the read-out connection line. To perform signal integration with that capacitor, the apparatus may connect the first plate to the read-out connection line (e.g. to receive a read-out signal) and connect the second plate to the first reference voltage source (e.g. ground).

[0013] Each capacitor may be selectively connectable to a second reference voltage source, such as a supply voltage. For example, each capacitor, e.g. a second plate of the capacitor, may be connected to the second reference voltage source (e.g. supply voltage) via a respective supply switch. The supply switch may be activated to connect the capacitor to the second reference voltage source (e.g. to the supply voltage). The apparatus may be configured to control the connection of the capacitor (e.g. the second plate) to the second reference voltage source (e.g. the supply voltage) to occur when said capacitor (e.g. the first plate) is connected to the converter input. To perform signal conversion with that capacitor, the apparatus may connect the first plate to the converter input (e.g. to provide the integrated signal thereto) and connect the second plate to the second reference voltage source (e.g. to the supply voltage).

[0014] The converter may comprise a comparator. To operate a capacitor in its conversion mode, the apparatus may be configured to use the comparator to compare a voltage of said capacitor against a controlled voltage. Comparing the voltage of said capacitor against a controlled voltage may comprise applying a ramp voltage to the comparator as the controlled voltage. The converter may be configured to perform the conversion based on an obtained indication of when the ramp voltage corresponds to the capacitor voltage, e.g. when the ramp voltage equals the capacitor voltage. The converter may be configured to perform the conversion by determining an amount of time taken for the ramp voltage to ramp from an initial voltage to a voltage at which it corresponds to the capacitor voltage.

[0015] The apparatus may be configured to pre-charge each capacitor. Pre-charging a capacitor may comprise setting (e.g. restoring) said capacitor to a known voltage, e.g. so that the voltage across that capacitor is at a known value. Controlling a capacitor to operate in its conversion mode may comprise restoring the capacitor to a selected voltage after the capacitor voltage has been applied to the converter for conversion thereof. Resetting the capacitor to the selected voltage may comprise pre-charging the capacitor to the selected voltage.

[0016] Resetting the capacitor to the selected voltage may comprise connecting each plate of the capacitor to a respective source of reference voltage. The two sources of reference voltage may be different. For example, one source of reference voltage may be a voltage at the output of the comparator. For example, the other source of reference voltage may be the supply voltage source. To pre-charge a capacitor, the apparatus may be configured to selectively connect one (e.g. the first) plate of the capacitor to the output of the comparator. To pre-charge the capacitor, the apparatus may be configured to selectively connect one (e.g. the second) plate of the capacitor to a supply voltage source. The capacitor may be pre-charged to a level set by the difference in voltage between the comparator output voltage (as at the first plate) and the supply voltage (as at the second plate). The apparatus may comprise a third capacitor. The apparatus may be configured to control the third capacitor to operate in an integration mode. The apparatus may be configured to control the third capacitor to operate in its integration mode in parallel with operation of the first and / or second capacitors in their respective integration modes. The apparatus may be configured to connect the third capacitor in parallel with the first capacitor when the first capacitor is operating in its integration mode. The apparatus may be configured to connect the third capacitor in parallel with the second capacitor when the second capacitor is operating in its integration mode. The apparatus may be configured to vary the capacitance of the third capacitor. The apparatus may be configured to pre-charge the third capacitor prior to controlling that third capacitor to perform a subsequent integration operation. Pre-charging the third capacitor may comprise connecting each plate of the capacitor to a respective source of reference voltage. The two sources may be different, e.g. one of the sources of reference voltage may comprise an output of the converter.

[0017] The apparatus may be configured to perform analogue signal integration using one of the capacitors while performing analogue signal conversion using the other of the capacitors. The apparatus may be configured to toggle use of each capacitor from its integration mode into its conversion mode for conversion of a voltage of said capacitor arising from the integration performed by said capacitor. Each capacitor may be selectively connectable to a read-out line connection or an input of the converter. When operating a capacitor in its integration mode, the apparatus may be configured to connect one plate of said capacitor to receive the analogue signal and the other plate of said capacitor to ground. When operating a capacitor in its conversion mode, the apparatus may be configured to connect one plate of said capacitor to an input of the converter and the other plate of said capacitor to a source of reference voltage.

[0018] The apparatus may be configured to control operation of the capacitors to perform: (i) a first cycle which comprises operating the first capacitor is in its integration mode and operating the second capacitor in its conversion mode, and (ii) a second cycle subsequent to the first cycle, wherein the second cycle comprises operating the first capacitor in its conversion mode and operating the second capacitor in its integration mode. The apparatus may be configured to control operation of the capacitors to perform a third cycle subsequent to the second cycle, wherein the third cycle comprises operating the first capacitor is in its integration mode and operating the second capacitor in its conversion mode. The apparatus may be configured to control operation of the converter to transmit data indicative of the conversion performed in the second cycle during the third cycle of operation to a controller of the apparatus. Aspects of the present disclosure may comprise a capacitive sensor, such as a capacitive biometric skin contact sensor, comprising any analogue front-end apparatus disclosed herein.

[0019] In an aspect, there is provided a capacitive sensor comprising: an active-matrix array of sensor pixels; and any analogue front-end apparatus disclosed herein. Each sensor pixel is connected to a read-out line of the active-matrix array, and wherein at least one of the readout lines of the array is connected to the analogue front-end apparatus. The sensor may be a capacitive biometric skin contact sensor.

[0020] In an aspect, there is provided a method of controlling operation of an analogue front-end apparatus to perform an analogue to digital conversion of an analogue read-out signal, the method comprising: operating the apparatus in a first cycle, wherein operation in the first cycle comprises operating a first capacitor in an integration mode in which the first capacitor is connected to a read-out connection line to receive a first analogue read-out signal to be converted; and operating the apparatus in a second cycle, wherein operation in the second cycle comprises: operating a second capacitor in an integration mode in which the second capacitor is connected to the read-out connection line to receive a second analogue read-out signal to be converted; and operating the first capacitor in a conversion mode in which the first capacitor is connected to a converter to perform a conversion of the first read-out signal as stored on the first capacitor.

[0021] Aspects of the present disclosure may comprise one or more computer program products comprising computer program instructions configured to program a controller to control operation of an apparatus to implement any of the methods disclosed herein.

[0022] Figures

[0023] Some examples of the present disclosure will now be described, by way of example only, with reference to the figures, in which:

[0024] Fig. 1a is a schematic diagram illustrating functionality of an analogue front-end.

[0025] Fig. 1b is a timing diagram illustrating example operation of the analogue front-end of Fig. 1a.

[0026] Fig. 2 is a schematic diagram depicting an analogue front-end.

[0027] Fig. 3 is a schematic diagram depicting an analogue front-end.

[0028] Fig. 4 is a schematic diagram illustrating a capacitive touch sensor comprising an array of pixels. In the drawings like reference numerals are used to indicate like elements.

[0029] Specific Description

[0030] The present disclosure relates to an analogue front-end apparatus. The analogue front-end apparatus is configured to perform analogue to digital conversion of analogue read-out signals. In particular, the apparatus may find particular utility for processing read-out signals from a capacitive sensor, such as a capacitive biometric skin contact sensor. The apparatus is designed to receive a first read-out signal to be digitised, e.g. a current value, and to store that signal as a charge on a first capacitor. Then, a second read-out signal to be digitised is received and stored on a second capacitor. While this second signal is being received and stored, the stored charge from the first capacitor is connected to a converter which determines a voltage associated with that first read-out signal. The second read-out signal may then subsequently be provided to the converter, while the first capacitor is charged up with a new read-out signal to be digitised.

[0031] In other words, the analogue front-end apparatus is able to multitask. That is, the analogue front-end apparatus may perform multiple different operations simultaneously, e.g. it may pipeline operation. In particular, during a time period in which the apparatus is operating to perform an integration process for one read-out signal, the apparatus may also be performing a conversion process for another read-out signal. In turn, this may increase throughput of the analogue front end apparatus, thereby increasing the speed of digitisation.

[0032] An example analogue front-end apparatus will first be described with reference to Fig. 1a.

[0033] Fig. 1a shows a schematic diagram of an analogue front-end apparatus 100. Fig. 1a is a simplified diagram intended to depict example functionality for the apparatus 100. The apparatus 100 includes two capacitors: a first capacitor 10 and a second capacitor 20. The first capacitor 10 has a first plate 11 and a second plate 12. The second capacitor 20 has a first plate 21 and a second plate 22.

[0034] Each capacitor may be selectively connected to different components of the apparatus 100. The dashed lines in Fig. 1a illustrate the possible connectivity. The first plate of each capacitor may be connected to: receive a read-out signal (‘Read-out’ in Fig. 1a), the input of a converter (‘Converter input’ in Fig. 1a), or a first pre-charging voltage source (‘Pre-charge T in Fig. 1a). Each first plate may only be connected to one of these components at a time. The second plate of each capacitor may be connected to: a second pre-charging voltage source (‘Precharge 2’ in Fig. 1a), a common conversion voltage source (‘Conversion common’ in Fig. 1a) or a common integration voltage source (‘Integration common’ in Fig. 2a). Each second plate may only be connected to one of these components at a time.

[0035] Connecting to each of Pre-charge 1 , Pre-charge 2, Conversion common and Integration common comprises a connection to a reference voltage source. Each of these reference voltage sources may be separate (e.g. at different voltages). Connecting to Read-out may comprise connecting to a read-out line from the sensor, and connecting to the Converter input comprises connecting to an input of a converter for converting the analogue signal provided thereto into a digital representation thereof.

[0036] The purpose of Figs. 1a and 1 b is to illustrate the general function to be provided by the analogue front-end apparatus 100. More detailed apparatuses will be described below in relation to Figs. 2 and 3.

[0037] The apparatus 100 is configured to receive read-out signals and to convert these into digital signals. Each received read-out signal is first stored on one of the capacitors of the apparatus 100. That stored signal is then subsequently provided to a converter for conversion thereof. The present inventors have identified that by using multiple capacitors in the front-end apparatus 100 it is possible to increase the time efficiency for operation of the apparatus 100. In particular, through the provision of two or more such capacitors, one of the capacitors of the apparatus 100 may be operated in an integration mode (e.g. about to receive a read-out signal, currently receiving a read-out signal, or storing an already received read-out signal), while another capacitor is converting an already stored read-out signal (and vice-versa).

[0038] For a capacitor to be used to receive a read-out signal, the apparatus 100 is configured to connect the first plate of that capacitor to a read-out line. For a capacitor to be used to convert a stored read-out signal, the first plate of that capacitor is connected to the input of the converter. The apparatus 100 is configured to enable one of the capacitors to be connected to receive a read-out signal (e.g. connected to a read-out line) while the other capacitor is differently connected, such as being connected to convert a stored read-out signal (e.g. connected to the converter input). Likewise, the apparatus 100 is configured to enable one of the capacitors to be connected to the converter input while the other capacitor is connected differently, e.g. connected to receive a read-out signal.

[0039] As mentioned above, the apparatus 100 may be configured to selectively connect the first plate of a capacitor to a read-out line connection or to a converter input to receive a read-out signal or to convert a read-out signal, respectively. Additionally, the apparatus 100 may be configured to selectively connect the second plate of a capacitor to a number of other components, such as different reference voltage sources. The apparatus 100 may be configured to connect the second plate of the capacitor to a particular component which is chosen based on to what the first plate of that capacitor is connected. As mentioned in more detail below, when the first plate is connected to receive the read-out signal, the second plate may be connected to the common integration voltage source. Likewise, when the first plate is connected to the converter input, the second plate may be connected to the common conversion voltage source. To facilitate improved sensitivity and reliability for digitisation of read-out signals, the apparatus 100 may also be configured to selectively connect each first plate to a first pre-charging voltage source, and / or to connect the second plate to a second pre-charging voltage source. These three different possible connections for the first and second plates are shown in Fig. 1a.

[0040] To integrate a read-out signal, the apparatus 100 is configured to connect the first plate of one of the capacitors to receive said read-out signal (e.g. to connect the first plate to a read-out line). The apparatus 100 may also be configured to connect the second plate of that capacitor to the common integration voltage source. The common integration voltage source may be an electrical ground. The apparatus 100 may be configured to concurrently connect the first plate to receive the read-out signal and the second plate to the common integration voltage source. Once an integration time period has elapsed, the apparatus 100 may disconnect the first plate from the read-out connection and the second plate from the common integration voltage connection. At which point, the capacitor may be floating. That capacitor will be charged to a voltage which is indicative of at least one property (e.g. a magnitude of a read-out current) of the received read-out signal.

[0041] To convert a stored read-out signal, the first plate of the capacitor is connected to an input of a converter. The apparatus 100 may also be configured to connect the second plate of that capacitor to the common conversion voltage source. The apparatus 100 may be configured to concurrently connect the first plate to the converter input and the second plate to the common conversion voltage source. The common conversion voltage source may be a reference voltage, such as ground or a chosen voltage. The converter may then perform a conversion based on determining a magnitude of the voltage of that read-out signal as provided by the connection to the first plate of the capacitor. This voltage magnitude may provide an indication of the property of the received read-out signal (e.g. of a magnitude of a received read-out current). In turn, this may provide an indication of a sensed parameter, where a sensor is configured to output a read-out signal having a property (e.g. magnitude of current) which is indicative of the parameter being sensed). Once the conversion process is finished, the apparatus 100 may disconnect the two plates from their respective connections. A voltage across the capacitor may then be at a value which is at least partly dependent on the previous read-out signal that capacitor received.

[0042] After conversion of a read-out signal which was stored on one of the capacitors, the apparatus 100 may pre-charge that capacitor before it is used again to store (and then convert) a new read-out signal. Pre-charging may fix the capacitor to a known voltage prior to receiving the next read-out signal, thereby increasing the sensitivity and / or reliability of any future conversion processes which use that capacitor.

[0043] To pre-charge a capacitor, both plates may be connected to respective voltage sources. For instance, the first plate may be connected to the first pre-charging voltage source and the second plate may be connected to the second pre-charging voltage source. The capacitor may therefore be pre-charged according to those two pre-charging voltages (e.g. the voltage across the pre-charged capacitor may correspond to the difference in voltage of the precharge voltage sources). The apparatus 100 may be configured to concurrently connect the first plate to the first pre-charging voltage source and the second plate to the second precharging voltage source. Once a pre-charge time period has elapsed, the apparatus 100 may disconnect the first plate from the first pre-charging voltage source and the second plate from the second pre-charging voltage source. At which point, the capacitor may be floating. The capacitor will be pre-charged to a known voltage. As such, when that capacitor is subsequently used for receiving a read-out signal, the initial voltage of that capacitor will be known (due to the pre-charge) and so any changes to the resulting voltage of that capacitor can be attributed to the read-out signal (thus increasing sensitivity and reliability for any conversions).

[0044] The apparatus 100 may be configured to control the connections for the first and second plates of each capacitor to control the modes of operation of being performed by that apparatus 100 (e.g. between pre-charge, integration and conversion). The apparatus 100 may be configured to control one of the capacitors to be operating in one mode of operation, while another capacitor is operated in another mode of operation. This may streamline the digitisation of received read-out signals.

[0045] One example method of operating the apparatus 100 shown in Fig. 1a will now be described with reference to the timing diagram shown in Fig. 1 b. The timing diagram of Fig. 1 b shows the connections for the first and second capacitors of the apparatus 100 of Fig. 1a. As shown in Fig. 1a, each first plate may be connected to either read-out, converter input or pre-charge 1 , and each second plate may be connected to either pre-charge 2, conversion common or integration common. These three options for each first plate and three options for each second plate are shown in Fig. 1b for both the first capacitor 10 and the second capacitor 20. Each line in Fig. 1b denotes whether or not its respective connection is active. Where the line is high, that connection is active (e.g. that component is connected to the relevant capacitor plate), and where the line is low, that connection is not active (e.g. that component is not connected to the relevant capacitor plate).

[0046] As mentioned above in relation to Fig. 1a, the different connections for first and second plates may be controlled to operate in pairs. That is, for each capacitor, the read-out and integration common connections may be activated (and disactivated) concurrently. Similarly, the converter input and conversion common connections may activated (and disactivated) concurrently). Likewise, the pre-charge 1 and pre-charge 2 connections may be activated (and disactivated) concurrently. This is shown throughout the timing diagram of Fig. 1 b. As explained in more detail below in relation to Figs. 2 and 3, by controlling the connections in this paired manner, the operation of relevant switches for controlling these connections may be simplified.

[0047] Starting with the first capacitor 10 (the top half of Fig. 1 b), the first action is a pre-charge. For this, pre-charge 1 and 2 connections are activated (i.e. the first and second plates are connected to their respective pre-charge voltage sources). As such, the first capacitor 10 is pre-charged to a selected voltage. The pre-charge connections are then disactivated. This leaves the first capacitor 10 disconnected (e.g. floating) and charged at a selected pre-charge voltage.

[0048] The second action with the first capacitor 10 is an integration. For this, read-out and integration common connections are activated (i.e. the first plate 11 is connected to the read-out connection and the second plate 12 is connected to the integration common connection). The first plate 11 of the first capacitor 10 thus receives the read-out signal, and this acts to charge the first capacitor 10 to a different voltage to the initial pre-charge voltage. Once an integration time period has elapsed, the read-out and integration common connections are disactivated. This leaves the first capacitor 10 disconnected (e.g. floating) and charged at a voltage indicative of a magnitude of the received read-out current.

[0049] The third action with the first capacitor 10 is a conversion. For this, the converter input and conversion common connections are activated (i.e. the first plate 11 is connected to the converter input and the second plate 12 is connected to the conversion common connection). The first plate 11 of the first capacitor 10 thus connects to the converter, and this enables the converter to perform a digital conversion indicative of the voltage across that capacitor. Once the conversion process has finished, the converter input and conversion common connections are disactivated. This leaves the first capacitor 10 disconnected (e.g. floating) and charged at a voltage which will be at least partly dependent upon the read-out signal which was previously received by that capacitor.

[0050] At this point, the cycle of operation for the first capacitor 10 may repeat. That is, as the conversion is finished, the next step may be for a pre-charge, followed by an integration and then a further conversion.

[0051] A particular advantage of the analogue front-end apparatus 100 of the present disclosure is that the operation of the first capacitor 10 may be toggled with operation of the second capacitor 20 to increase the digitisation throughput. This behaviour is apparent with reference to the timing diagram for operation of the second capacitor 20. As shown in Fig. 1 b, operation timings for the second capacitor 20 are out of sync with those for the first capacitor 10. That is, the two capacitors will be performing different modes of operation at different times.

[0052] In Fig. 1 b, the first operation shown for the second capacitor 20 is a conversion. The conversion operation for the second capacitor 20 at least partially overlaps (temporally) with the integration operation for the first capacitor 10. For example, and as shown in Fig. 1 b, the conversion process for the second capacitor 20 may commence shortly after the integration process for the first capacitor 10 has commenced. For at least some time, the first capacitor 10 is in its integration mode and the second capacitor 20 is in its conversion mode. The apparatus 100 is therefore performing simultaneous integration and conversion.

[0053] The conversion process for the second capacitor 20 finishes (shortly) after the integration process for the first capacitor 10 finishes. Before the first capacitor 10 is operated in its conversion mode, the second capacitor 20 is operated to perform a pre-charge. The second capacitor 20 is pre-charged before any conversion of the first capacitor 10 commences. Notably, the second capacitor 20 will be disconnected from both pre-charge connections before the first capacitor 10 is connected to the converter input and conversion common. For example, there may be a moment in time at which the first capacitor 10 is charged based on a read-out signal and the second capacitor 20 is charged based on the pre-charge. Both capacitors may be simultaneously floating at this point. As shown in Fig. 1 b, the next step (for either capacitor) is for the second capacitor 20 to be operated in its integration mode. Shortly after this second capacitor integration commences, the first capacitor conversion may also commence. This time round, it is the first capacitor conversion which finishes shortly after the second capacitor integration. The first capacitor 10 is then pre-charged before the second capacitor is operated in a conversion. This process may occur repeatedly, thus enabling the apparatus 100 to provide increased digitisation throughput, e.g. as compared to only being able to handle one read-out signal at a time.

[0054] A more detailed example analogue front-end apparatus 100 will now be described with reference to Fig. 2. In particular, it will be described how the apparatus 100 of Fig. 2 may enable the functionality described above in relation to Figs. 1a and 1b to be performed.

[0055] In the following example, the analogue front-end apparatus 100 will be described when used for processing read-out signals from a sensor. The sensor may be a capacitive sensor, such as a capacitive biometric skin contact sensor. Such a sensor may be formed of an activematrix array of sensor pixels. Fig. 4 shows a plan view of such a sensor 1000 comprising an array of sensor pixels 1100. A capacitive sensing electrode 1110 of each sensor pixel 1100 is also shown. For simplicity, other components of the sensor 1000 (such as gate drive lines or read-out lines) including those in each sensor pixel 1100 are not shown in Fig. 4 but may nonetheless be present.

[0056] The sensor 1000 contains a plurality of rows of sensor pixels 1100 and a plurality of columns of sensor pixels 1100. Each sensor pixel 1100 may provide its own sensing area on the sensor 1000 (i.e. each sensor pixel 1100 may be configured to provide sensing for a subset of the total area of the sensor 1000). The capacitive sensing electrode 1110 of each sensor pixel 1100 may take up a majority of the area of its sensor pixel 1100 (when viewed in plan). By increasing the area covered by a capacitive sensing electrode 1110, a greater amount of charge may be stored on that electrode 1110. The area covered by each individual electrode 1110 may also be limited so that the spatial resolution of the capacitive sensor may be sufficiently high to provide biometric sensing (e.g. for identifying contours of a user’s skin).

[0057] The sensor array may contain a plurality of gate drive lines and a plurality of read-out lines. Each sensor pixel 1100 is connected to both a gate drive line and a read-out line. For example, each row of sensor pixels 1100 may be connected to a gate drive line for that row, and each column of sensor pixels 1100 may be connected to a read-out line forthat column. By applying a gate drive signal to a gate drive line, all sensor pixels 1100 connected to that gate drive line (e.g. in that row) will be activated. Each activated sensor pixel 1100 will output a read-out signal in the form of a read-out current, where that current is indicative of the proximity of a conductive object to a capacitive sensing electrode 1110 of that sensor pixel 1100. The apparatus 100 is configured to obtain a digital indication of that read-out current, and thus a digital indication of the proximity to the capacitive sensing electrode of the conductive object.

[0058] An example sensor array of this type is disclosed in the Applicant’s patent GB2585420, which is herein incorporated by reference. The front-end apparatuses 100 of the present disclosure may be used for digital conversion of read-out signals from such a sensor array. In particular, the present disclosure includes capacitive biometric skin contact sensors of the type shown in Figure 3 of GB2585420, and in which those sensors are connected to a front-end apparatus 100 of the present disclosure.

[0059] An example analogue front-end apparatus 100 is shown in Fig. 2.

[0060] The apparatus 100 includes a first capacitor 10, a second capacitor 20 and a converter. The first capacitor 10 has a first plate 11 and a second plate 12. The second capacitor 20 has a first plate 21 and a second plate 22. The converter comprises a comparator 50 and logic 60. The comparator 50 has two inputs and an output. One input is an inverting input, and the other input is a non-inverting output. A comparator switch 52 is shown in Fig. 2. The comparator switch 52 is connected between the output and the inverting input. The non-inverting input of the comparator 50 is connected to a controlled voltage source. The controlled voltage source may comprise a ramp voltage generator (shown as VramPin Fig. 2). An output of the comparator 50 is connected to the logic 60.

[0061] The apparatus 100 includes a plurality of conductive lines and a plurality of switches. The conductive lines of the apparatus 100 include a read-out connection line 1 , a converter connection line 2, a ground line 3, and a supply line 4. The switches of the apparatus 100 comprise a plurality of switches for the first capacitor 10 and a plurality of switches for the second capacitor 20. For the first capacitor 10, the switches include a first read-out switch 111 , a first converter switch 112, a first ground switch 121 , and a first supply switch 122. For the second capacitor 20, the switches include a second read-out switch 211 , a second converter switch 212, a second ground switch 221 , and a second supply switch 222.

[0062] The first and second capacitors 10, 20 are each connectable to each of the read-out connection line 1 , the converter connection line 2, the ground line 3, and the supply line 4. A first plate 11 of the first capacitor 10 is connectable to the read-out connection line 1 and the converter connection line 2. The first plate 11 of the first capacitor 10 is connected to the read-out connection line 1 via a first read-out switch 111. The first plate 11 of the first capacitor 10 is connected to the converter connection line 2 via a first converter switch 112.

[0063] A second plate 12 of the first capacitor 10 is connectable to the ground line 3 and the supply line 4. The second plate 12 of the first capacitor 10 is connected to the ground line via the first ground switch 121. The second plate 12 of the first capacitor 10 is connected to the supply line 4 via the first supply switch 122.

[0064] A first plate 21 of the second capacitor 20 is connectable to both the read-out connection line 1 and the converter connection line 2. The first plate 21 of the second capacitor 20 is connected to the read-out connection line 1 via a second read-out switch 211. The first plate 21 of the second capacitor 20 is connected to the converter connection line 2 via a second converter switch 212.

[0065] A second plate 22 of the second capacitor 20 is connected to the ground line 3 and the supply line 4. The second plate 22 of the second capacitor 20 is connected to the ground line via the second ground switch 221. The second plate 22 of the second capacitor 20 is connected to the supply line 4 via the second supply switch 222.

[0066] In other words, the first and second plates of each capacitor are each connected to their two lines via a respective switch for each line.

[0067] As described in more detail below, this arrangement of lines and switches enables apparatus 100 to provide the connective functionality described above with reference to Fig. 1a.

[0068] The read-out connection line 1 may provide the ‘Read-out’ connection shown in Fig. 1a. The read-out connection line 1 is connected for receiving analogue read-out signals to be converted into digital signals. For example, the read-out connection line 1 may be connected to one or more read-out lines of a sensor array, such as a capacitive sensor array of the type described above.

[0069] The converter connection line 2 may provide both the ‘Converter input’ and ‘Pre-charge T connections shown in Fig. 1a. The converter connection line 2 is connectable to an input of the converter and a voltage source. The converter connection line 2 is connected to an input the comparator 50 (the inverting input in Fig. 2). The converter connection line 2 is also connected to the output of the comparator 50 via the comparator switch 52. The connection to the input of the comparator 50 (when switch 52 is not electrically conductive) may provide the ‘Converter input’ functionality of Fig. 1a. The connection to the output of the comparator 50 (when switch 52 is electrically conductive) may provide the ‘Pre-charge T functionality of Fig. 1a. In other words, the output voltage of the comparator 50 may provide the first precharging voltage source.

[0070] The ground line 3 may provide the ‘Integration common’ connection shown in Fig. 1a. The ground line 3 is connected to a source of a reference voltage. As shown in Fig. 2, the ground line 3 may be connected to electrical ground (e.g. to a zero Volts reference).

[0071] The supply line 4 may provide both the ‘Pre-charge 2’ and ‘Conversion common’ connections shown in Fig. 1a. The supply line 4 is also connected to one or more sources of reference voltage (only one shown in Fig. 2). From hereon in, this source of reference voltage will be referred to as the supply voltage source. This may be a separate voltage source to the electrical ground. This same voltage source may supply a selected voltage for both precharging and conversion common functionality.

[0072] Each of the switches is configured to provide a selective electrical conduction path. That is, each switch is controllable to operate in either an electrically conductive state or an electrically non-conductive state. The apparatus 100 is configured to selectively operate each switch to provide selective electrical connections between different components of the apparatus 100.

[0073] As disclosed herein, a switch being ‘active’ or ‘activated’ refers to that switch being in its electrically conductive state, and a switch being ‘inactive’ or ‘disactivated’ refers to that switch being in its electrically non-conductive state.

[0074] The apparatus 100 may be configured to activate and disactivate the switches in pairs. For example, for each capacitor, the apparatus 100 may be configured to activate / disactivate the read-out and ground switches together (e.g. so that they operate concurrently). Likewise, for each capacitor, the apparatus 100 may be configured to activate / disactivate the converter and supply switches together (e.g. so that they operate concurrently).

[0075] Read-out and integration

[0076] The read-out connection line 1 is arranged to receive a read-out signal to be converted. The read-out signal may be a signal in the form of a current. Each of the first and second capacitor is selectively connectable to the read-out connection line 1 . That is, each of the first and second capacitor is connected to the read-out connection line 1 via a respective read-out switch (first read-out switch 111 and second read-out switch 211 , respectively). Said read-out switches are controllable to selectively connect or disconnect the first and second capacitors to the read-out connection line 1.

[0077] Each of the first and second capacitors is operable in an integration mode. To operate each capacitor in the integration mode, said capacitor is connected to the read-out connection line 1 . For this, the read-out switch for that capacitor is controlled to operate in its electrically conductive state (i.e. that read-out switch is activated). This activation of the read-out switch electrically connects said capacitor to the read-out connection line 1. The apparatus is configured to inhibit the first and second capacitors both being in their integration mode at the same time. The apparatus 100 is configured to control operation of the first and second capacitors such that only one (or none) of the capacitors will be in its integration mode at any one time. For example, the apparatus 100 is configured to control activation of the read-out switches so that only one or neither of the read-out switches will be in its electrically conductive state at one time. In other words, the apparatus 100 may be configured to only ever have one (or none) of the first read-out switch 111 and the second read-out switch 211 in its electrically conductive state at any one time.

[0078] The apparatus 100 is configured so that, when controlling a capacitor to operate in the integration mode, the first plate of that capacitor is connected to the read-out connection line 1 for receiving a read-out signal therefrom. In other words, the apparatus 100 is configured to control a capacitor to operate in its integration mode such that the capacitor will be charged to a voltage which is indicative of the read-out current received from the read-out line. For example, the charge stored will be at least partially indicative of a magnitude of the read-out current that was received (as well as the integration time period for which that read-out signal was applied). As will be appreciated in the context of the present disclosure, the exact value for the charge stored (and the resulting capacitor voltage) may vary depending on other parameters such as the capacitance of the capacitor, and any other electrical connections (e.g. to which the second plate for example may be connected).

[0079] The apparatus 100 may be configured to connect the second plate of a capacitor to a source of reference voltage while the first plate of that capacitor is connected to the read-out connection line 1. That is, when operating a capacitor in an integration mode, the apparatus 100 may be configured to connect the first plate to the read-out connection line 1 and the second plate to a source of reference voltage. As shown in Fig. 2 and discussed in more detail below, that source of reference voltage may comprise an electrical ground. This connectivity may be provided by connecting the second plate to the ground line 3.

[0080] Each of the first and second capacitors is selectively connectable to the electrical ground (e.g. via the ground line 3). That is, the second plate of each of the first and second capacitor is connected to the electrical ground (i.e. to the ground line 3) via a respective ground switch (first ground switch 121 and second ground switch 221 , respectively). The apparatus 100 may be configured to selectively connect each of the first and second capacitors (their second plate) to the electrical ground while said capacitor is operating in its integration mode. To connect the capacitor (e.g. its second plate) to ground, the ground switch for that capacitor is activated, thereby to electrically connect said capacitor to the ground line 3 (and thus to ground).

[0081] The apparatus 100 is configured to connect one plate (i.e. the second plate) of a capacitor to the electrical ground while the other plate (i.e. the first plate) of that capacitor is receiving a read-out signal.

[0082] The apparatus 100 is configured to control grounding of the second plate to occur while a read-out signal is applied to the first plate of that capacitor. That is, the apparatus 100 is configured to control the ground switch for said capacitor to be in a conducting state while the read-out switch for said capacitor is also in its conducting state. The apparatus 100 may be configured to inhibit integration occurring with a capacitor while the plate of that capacitor which is not connected to receive the read-out signal is not connected to the electrical ground.

[0083] Converter input

[0084] The converter connection line 2 is arranged to connect capacitors to the comparator 50. That is, each capacitor may be connected to the comparator 50 via the converter connection line 2 (when the converter switch for said capacitor is activated and the comparator switch is disactivated). In other words, the converter connection line 2 is configured to apply a voltage from one of the capacitors to the non-inverting input of the comparator 50.

[0085] Each of the first and second capacitors is selectively connectable to the converter connection line 2. That is, each of the first and second capacitor is connected to the converter connection line 2 via a respective converter switch (first converter switch 112 and second converter switch 212, respectively). Said converter switches are controllable to selectively connect or disconnect the first and second capacitors to the converter connection line 2. Each of the first and second capacitors is operable in a conversion mode. To operate a capacitor in the conversion mode, said capacitor is connected to the converter connection line 2. For this, the converter switch for that capacitor is controlled to operate in its electrically conductive state (i.e. the converter switch is activated). The apparatus 100 is configured to inhibit both the first and second capacitors being in their conversion mode at the same time (e.g. only one or neither of the converter switches will be activated at one time). The apparatus 100 is configured so that, when controlling a capacitor to operate in the conversion mode, that capacitor is connected to the converter input. In particular, the apparatus 100 is configured so that, when in conversion mode, the first plate of that capacitor is connection to the (inverting) input of the comparator 50 (e.g. the converter switch is activated and the comparator switch 52 is disactivated).

[0086] When operating in the conversion mode, the capacitor is connected so that a voltage applied to the comparator 50 will be at least partially indicative of the read-out current which said capacitor received from the read-out connection line 1. In other words, the apparatus 100 is configured to control each capacitor to operate in its conversion mode such that the capacitor will apply a voltage to the comparator 50 which is indicative of the read-out current said capacitor received from the read-out line.

[0087] The apparatus 100 may be configured to connect the second plate of a capacitor to a source of reference voltage while the first plate of that capacitor is connected to the converter input. That is, when operating a capacitor in a conversion mode, the apparatus 100 may be configured to connect the first plate to the input of the converter (via converter connection line 2) and the second plate to a source of reference voltage. As shown in Fig. 2, that source of reference voltage is the supply voltage source. The supply voltage source is connected to the supply line 4. The supply voltage source may also provide a source of reference voltage for pre-charging (also discussed below). This connectivity of the second plate to the supply voltage source may be provided by connecting the second plate to the supply line 4.

[0088] Each of the first and second capacitors is selectively connectable to the supply voltage source (e.g. via the supply line 4). That is, the second plate of each of the first and second capacitor is connected to the supply voltage source via a respective supply switch (first supply switch 122 and second supply switch 222, respectively). The apparatus 100 may be configured to selectively connect each of the first and second capacitors (their second plate) to the supply voltage source while said capacitor is operating in its conversion mode. To connect the capacitor (e.g. its second plate) to the supply voltage source, the supply switch for that capacitor is activated, thereby to electrically connect said capacitor to the supply line 3 (and thus to the supply voltage source).

[0089] The apparatus 100 is configured to connect one plate (i.e. the second plate) of a capacitor to the supply voltage source while the other plate (i.e. the first plate) of that capacitor is connected to the converter input.

[0090] The apparatus 100 is configured to control connection of the second plate to the supply voltage source to occur while the first plate of that capacitor is connected to the converter input. That is, the apparatus 100 is configured to control the supply switch for said capacitor to be in a conducting state while the converter switch for said capacitor is also in its conducting state. The apparatus 100 may be configured to inhibit conversion occurring with a capacitor while the plate of that capacitor which is not connected to the converter is not connected to the supply voltage source.

[0091] For each capacitor, the apparatus 100 is configured to control operation so that said capacitor is only ever connected to one (or neither) of the read-out connection line 1 and the converter connection line 2. That is, the apparatus 100 is configured so that, for each capacitor, only one (or neither) of the read-out switch and the converter switch is in its electrically conductive state. In other words, a capacitor may not simultaneously perform integration and conversion operations. Rather, each capacitor will only ever be one of: integrating, converting or neither.

[0092] Through the provision of two (or more) such capacitors, the apparatus 100 as a whole may be configured to provide simultaneous operations, e.g. where conversion and integration occur simultaneously with different capacitors.

[0093] In other words, the apparatus 100 may be configured to control one capacitor to operate in an integration mode (in which the capacitor stores a charge associated with the analogue readout signal to be converted), while controlling the other capacitor to operate in a conversion mode (in which the capacitor is connected to the converter for a digital conversion indicative of a voltage of said capacitor). The apparatus 100 may be configured to inhibit both capacitors operating simultaneously in the same mode. Instead, the apparatus 100 may be configured to control operation of the capacitors so that they operate in opposing modes.

[0094] The apparatus 100 is configured to control operation so that there is no temporal overlap in modes for the two capacitors (e.g. so that only one capacitor will be operating in the integration mode, and only one capacitor will be operating in the conversion mode). The apparatus 100 may overlap timing of these modes, such there is at least partial overlap between one capacitor operating in an integration mode and one capacitor operating in a conversion mode. For example, the apparatus 100 may be configured to operate so that there is a window of time during which both integration by one capacitor and conversion by another capacitor is occurring simultaneously. The timing of the modes may be controlled such that the integration mode of one capacitor occurs simultaneously with the conversion mode of the other capacitor.

[0095] The apparatus 100 is configured to toggle operation of each capacitor between the integration and conversion modes. That is, the apparatus 100 is configured to switch operation between these modes (e.g. so that one capacitor is operated first in one of the modes, before then being switched into the other mode). The apparatus 100 is configured to perform this process repeatedly, e.g. so that each capacitor iteratively operates in its integration mode and then subsequently in its conversion mode.

[0096] The apparatus 100 may be configured to temporally interleave the operation of the first capacitor 10 with the operation of the second capacitor 20. In other words, the apparatus 100 may be configured to perform one operation with one of the capacitors while performing the other operation with the other of the capacitors. That is, the apparatus 100 may be configured to perform analogue signal integration using one of the capacitors while performing analogue signal conversion using the other of the capacitors. The apparatus 100 may be configured to toggle operation of the first and second capacitors, so that the capacitors then switch which operation they are performing. The apparatus 100 may be configured to enable simultaneous integration and conversion to be performed (i.e. with one capacitor providing the integration and the other capacitor providing the conversion). The integration and conversion processes may not be entirely aligned (e.g. they may not start and finish at exactly the same time), but there may be at least some overlap in time when both processes are underway (e.g. occurring) simultaneously.

[0097] The apparatus 100 may be configured to operate cyclically. In a first cycle, one of the capacitors may be operated in its integration mode, and the other capacitor may be operated in its conversion mode. In a second cycle, the capacitor which had previously been operated in its integration mode may be switched into operating in its conversion mode, and the other capacitor may be switched from its conversion mode into its integration mode. This switching may occur for each subsequent cycle. Each cycle may therefore include one integration operation and one conversion operation. Each cycle may last longer than the amount of time for which a capacitor is integrating (e.g. the cycle time may be longer than the integration time). Similarly, each cycle may last longer than the amount of time for which a capacitor voltage is applied to the comparator 50. The apparatus 100 may be configured to perform additional actions during each cycle (as described in more detail below).

[0098] As mentioned above, for operating one of the capacitors in its integration mode, the apparatus 100 is configured to connect the first plate of that capacitor so that it may be charged by an incoming analogue read-out signal (e.g. which may be a read-out current indicative of a proximity of a conductive object to be sensed to a capacitive sensing electrode of a sensor pixel of the array). For operating one of the capacitors in its conversion mode, the first plate of that capacitor is connected to an input of the converter, namely an inverting input of the comparator 50. In this sense, the apparatus 100 is configured to apply a voltage to the input of the converter, where that voltage is indicative of the analogue read-out current which was received when operating in the integration mode. That voltage being the voltage associated with the charge stored on the capacitor.

[0099] Digital conversion

[0100] The converter is configured to perform an analogue to digital conversion based on the input signal applied to it from the relevant capacitor (i.e. the capacitor which is in its conversion mode). For this, the comparator 50 is arranged to receive two input signals. The first input signal is a voltage of the capacitor which is operating in its conversion mode (hereinafter ‘the converting capacitor’). The second input signal is a voltage being applied from the controlled voltage source. The comparator 50 is configured to compare the two input voltages. The comparator 50 is configured to provide an output signal indicative of the comparison of the two input voltages.

[0101] The controlled voltage source is configured to apply a ramp voltage to the comparator 50. The ramp voltage will increase in magnitude over time from an initial voltage. In this example, the ramp voltage may be an increasing voltage. For example, the ramp may start at the initial voltage (which could be e.g. 0 volts), and this voltage is increased over time. The voltage ramp may increase linearly over time. However, it could increase in a stepwise manner (e.g. in discrete jumps), or the ramp may increase in a non-linear fashion. In this example, the voltage will be taken to increase linearly over time. It will be appreciated though that the particular ramp should not be considered limiting, and if the logic 60 is aware of the ramping profile (e.g. how the voltage will change overtime), then it can determine voltage of that ramp as a function of time whichever way that voltage is ramped. The comparator 50 is configured to compare the input voltage from the converting capacitor to the ramp voltage. The comparator 50 is configured to output a signal to indicate when the two input voltages are equal. The ramp voltage may start from its initial voltage and continue to increase in voltage over time. At some point in time, this ramp voltage will have ramped up to be at the same voltage as the converting capacitor voltage. The comparator 50 is configured to output a signal indicative of this event occurring. The voltage ramp profile (e.g. initial voltage and / or ramp rate) may be selected to utilise a greater amount of the converter bandwidth. For example, the voltage profile may be selected to try to ensure that the two voltages are equal at a point in time close to the maximum allotted conversion time (e.g. to maximise sensitivity).

[0102] The logic 60 is configured to obtain an indication of how long the ramp voltage was ramping for before that voltage equalled the converting capacitor voltage. For example, the logic 60 may comprise timeclock functionality. The logic 60 may be configured to determine, based on an output signal from the comparator 50, the time at which the ramp voltage equalled the converting capacitor voltage. For example, the logic 60 may be configured to store an indication of the time at which the output signal from the comparator 50 indicated that the two voltages were equal.

[0103] The controlled voltage source may be configured to apply a ramp voltage which starts at an initial voltage, and which increases in voltage over time according to a known voltage ramping profile. For example, the ramp voltage may start at zero volts and increase linearly towards a maximum voltage. For each subsequent conversion cycle, the controlled voltage source may be configured to start its voltage ramp at a set time. Additionally, or alternatively, the controlled voltage source (or the comparator 50) may be configured to output a signal (e.g. a clocking signal) to indicate that the voltage ramp has started. As such, the apparatus 100 may be configured to obtain an indication of the time at which the voltage ramp started and the time at which the voltage ramp had a voltage equal to the converting capacitor voltage. The apparatus 100 may therefore be configured to determine an amount of time for which the ramp voltage was ramping before the two voltages were equal. Based on this amount of time, and the ramp voltage profile for the ramp voltage, the apparatus 100 may be configured to determine a value of the ramp voltage when that ramp voltage equalled the converting capacitor voltage. The apparatus 100 may therefore be configured to determine the converting capacitor voltage.

[0104] This determination may be performed by a controller of the apparatus 100 (not shown in the figs). As will be appreciated in the context of the present disclosure, a sensor array (e.g. a capacitive biometric skin contact sensor of the type mentioned above) may have a large number of read-out channels, and so there may also be a large number of such analogue front-end apparatuses 100 as part of that sensor array. The controller of the apparatus 100 may be configured to receive such signals from all of the different apparatuses 100. The controller may be configured to process data from all of the different apparatuses 100 in the same place (e.g. with the same processing functionality).

[0105] As mentioned above, the logic 60 may be configured to obtain an indication of a time at which the two input voltages were equal. This indication may be in the form of a timestamp. The timestamp may indicate a time at which the two voltages were equal (e.g. a time of day, or an elapsed time etc.). Additionally, or alternatively, the logic 60 may be configured to determine the time taken for the ramp voltage to ramp from its initial voltage to the voltage equal to the converting capacitor voltage. For example, the logic 60 may comprise a counter. The logic 60 may determine a number of clock cycles which elapsed based on that counter. This may provide the indication of time at which voltages were equal. The logic 60 may be configured to store this indication of time in internal memory of the logic 60 itself. This may be a temporary storage. The apparatus 100 may be configured to subsequently transmit such an indication from the internal memory of the logic 60. For example, the apparatus 100 may be configured to transmit the stored data from the internal memory of the logic 60 to a controller of the apparatus 100. The controller may then process that data, as well as data from numerous other such apparatuses 100, e.g. so as to obtain proximity data for an object interacting with the sensor.

[0106] The apparatus 100 may be configured to transmit data from the internal data store of the logic 60 (e.g. to the controller) according to a timing schedule. That is, rather than transmitting that data as soon as it is ready, the apparatus 100 may transmit that data periodically. This may facilitate streamlined communication into the controller. For example, data from the internal data store of the logic 60 may be transmitted once per cycle. That is, the apparatus 100 may be configured so that, in the first cycle the capacitor is operated in an integration mode, in the second cycle that capacitor (and the converter) is operated in a conversion mode, and then in a third cycle the data from that second cycle conversion stored in the internal logic 60 may be transmitted. In other words, the apparatus 100 may be configured to perform a three-cycle process, such that by the end of the third cycle, a controller has an obtained indication of a read-out signal received in the first cycle. As such, at any one point in time, the apparatus 100 may be performing three (or more) different operations (e.g. analogue signal integration, analogue to digital conversion, and / or data transmission). As described in more detail below, the apparatus may also perform pre-charging as well (although this is generally referred to herein as being part of the conversion mode which occurs after conversion has finished but before a capacitor is ready for integration again).

[0107] Based on the conversion of the integrated analogue read-out signal, the apparatus 100 is configured to determine an indication of at least one property of that analogue read-out signal, such as a magnitude of a current of that received signal. In turn, a proximity of a conductive object to capacitive sensing electrode(s) associated with that signal may be inferred.

[0108] Pre-charging

[0109] To facilitate increased accuracy and / or reliability of this integration and conversion process, the apparatus 100 may be configured to selectively pre-charge each capacitor. For this, prior to a capacitor being operated in an integration mode (i.e. to receive an analogue read-out signal to be integrated), that capacitor may be ‘reset’ to a known value by pre-charging.

[0110] To pre-charge a capacitor, that capacitor is connected so that the capacitor is restored to a particular voltage. That is, the capacitor will be connected so that the resulting voltage across that capacitor is at a selected (and known) value. In the following description, the capacitor is pre-charged by connecting each plate to a respective source of reference voltage. However, it will be appreciated that the capacitor could be restored to a known value by connecting both plates to the same voltage source and / or by shorting the capacitor.

[0111] To pre-charge a capacitor, the first plate may be connected to one source of reference voltage while the second may be connected to another source of reference voltage. One source of reference voltage (e.g. for the first plate) may be a voltage of the comparator output. Another source of reference voltage (e.g. for the second plate) may be the supply voltage source. While other sources of reference voltage could be used, this arrangement may efficiently utilise existing components of the apparatus 100.

[0112] The apparatus 100 may be configured to perform pre-charging of a capacitor prior to integration being performed by that capacitor. The apparatus 100 is configured to perform the pre-charge after the capacitor conversion has elapsed (e.g. after the two comparator voltages have equalled and the comparator has issued an output signal). The apparatus 100 may be configured to perform this pre-charge to then restore the capacitor to a known initial starting value before a subsequent integration process may occur. Thus, any change to that capacitor voltage due to the integration process will itself be indicative of a property of the received readout signal which was integrated. Herein, for simplicity, the pre-charge process is referred to as forming part of the conversion mode of operation although it will be appreciated that the act of pre-charging is not per se. an act of conversion.

[0113] Pre-charging a capacitor may comprise activation of the converter switch and the supply switch for that capacitor, as well as activation of the comparator switch 52. For pre-charging the first plate, the converter switch and the comparator switch 52 are activated, thereby to electrically connect the first plate of the capacitor to the voltage at the output of the comparator. This process may also act to restore the inverting input of the comparator to the same voltage level (e.g. prior to that inverting input subsequently being connected to a capacitor plate for conversion). For pre-charging the second plate, the supply switch is activated, thereby to electrically connect the second plate to the supply voltage source. The pre-charge may thus charge the capacitor so that the voltage across that capacitor is equivalent to the difference in voltage between the comparator output voltage and the supply voltage.

[0114] The apparatus 100 may be configured to activate (and disactivate) the converter and supply switches concurrently (as well as the comparator switch 52) for pre-charging. The apparatus 100 may be configured to control pre-charging of a capacitor to occur after that capacitor has performed a conversion and before a subsequent integration is performed with that capacitor. The apparatus may be configured to disactivate the converter and supply switches after conversion with a capacitor before subsequently re-activating those switches (as well as comparator switch 52) for pre-charging that capacitor.

[0115] Pairs of switches

[0116] The apparatus may be configured to control activation and deactivation of switches in pairs. As shown in Fig. 2, the switches on the left of a capacitor may be activated and deactivated together. Likewise, the switches on the right of a capacitor may be activated and deactivated together. For example, these switches may be activated by applying a control voltage thereto (e.g. the switches may comprise transistors), and the control voltage may be applied to both switches in the pair at the same time. Specifically, in Fig. 2, there are four pairs of switches: (i) the first read-out switch 111 and the first ground switch 121 , (ii) the first converter switch 112 and the first supply switch 122, (iii) the second read-out switch 211 and the second ground switch 221 , and (iv) the second converter switch 212 and the second supply switch 222. Each pair of switches may be activated and disactivated together (e.g. simultaneously).

[0117] For example, to operate a capacitor in an integration mode, the first pair of switches for that capacitor (read-out and ground) may be activated (and then deactivated once integration is complete). To operate a capacitor in a conversion mode, the second pair of switches for that capacitor (converter and supply) may be activated (and then deactivated once conversion is complete). To pre-charge a capacitor, the second pair of switches for that capacitor may be activated, as well as the comparator switch 52 (and the deactivated once pre-charge is over).

[0118] Operation of the apparatus

[0119] As described above, the apparatus 100 is configured to perform several different functions as part of a process for converting an analogue read-out signal into digital data. One example of operating the apparatus 100 of Fig. 2 to perform this conversion will now be described. For simplicity, the operation of the apparatus 100 will initially be described with reference only to the first capacitor 10, but it will be appreciated that while this the first capacitor 10 is operating as described below, a corresponding operation of the second capacitor 20 will also be occurring.

[0120] For consistency, this method of operation of the apparatus 100 of Fig. 2 will follow the same timing pattern as that shown in the timing diagram of Fig. 1 b.

[0121] For the first capacitor 10, the first process is a pre-charge. For example, although not shown, this first capacitor 10 may have just completed a conversion process and it is being readied for a subsequent integration.

[0122] To perform this pre-charge of the first capacitor 10, the second pair of switches (first converter switch 112 and first supply switch 122) are activated, while the first pair of switches (first readout switch 111 and first ground 121) remain inactive (not conductive). Also, the comparator switch 52 is activated. The first plate 11 of the first capacitor 10 is connected to the comparator output (and thus charged to the comparator output voltage) and the second plate 12 of the first capacitor 10 is connected to the supply voltage source (and thus charged to the supply voltage). After a pre-charging period of time has elapsed, the three switches are disactivated. The first capacitor 10 has then been pre-charged and is ready for a subsequent integration.

[0123] The apparatus 100 is then toggled into an integration mode. To perform this integration with the first capacitor 10, the first pair of switches (first read-out switch 111 and first ground 121) are activated, while the second pair of switches (first converter switch 112 and first supply switch 122) remain not active (not conductive). The first plate 11 of the first capacitor 10 is connected to the read-out connection line 1 (and thus receives a read-out signal to be integrated) and the second plate 12 of the first capacitor 10 is connected to the ground line 3 (and thus to the electrical ground).

[0124] With the first capacitor 10 now being operated in its integration mode, the analogue read-out signal will be applied to the first plate 11 of the first capacitor 10. The read-out signal is applied to the first capacitor 10 for a selected time period (the integration time). This integration time may be less than the line time for the sensor (e.g. less than the amount of time for which a gate drive signal is applied to a gate line of the sensor). Over this integration time, the first capacitor 10 is charged to an amount based on the magnitude of the read-out current and the amount of time for which the read-out current was applied to the first plate 11 of the first capacitor 10. The first capacitor 10 will therefore be at a voltage which is indicative of the charge stored and thus a magnitude of the received read-out current. Once the integration time period has passed, the integration operation for the first capacitor 10 will be complete. The first pair of switches are then disactivated. The second pair of switches may also remain disactivated for a period of time before they are then activated for conversion.

[0125] As mentioned above, the description of this operation so far has only been with reference to the first capacitor 10 and there has been no mention of the second capacitor 20. However, while this described integration of the first capacitor 10 has been happening, the second capacitor 20 may also have been operating. As shown in Fig. 1b, the second capacitor 20 may be converting for at least some of the time while the first capacitor 10 is integrating. As such, operation of the first capacitor 10, such as the timings for opening and closing of switches, may be at least partially dependent on how the second capacitor 20 is being operated.

[0126] After the integration has been completed for the first capacitor 10, that first capacitor 10 may be ready for conversion. However, there may be a delay introduced to switching that first capacitor 10 into its conversion mode as a result of the corresponding operation of the second capacitor 20. For example, all four switches for the first capacitor 10 may remain disactivated for a period of time (e.g. leaving the first capacitor 10 floating). As the comparator output is used for pre-charging, the first capacitor 10 may remain floating until after the second capacitor 20 has been pre-charged (e.g. as only then will the converter be available to perform a conversion operation for the first capacitor 10).

[0127] Once the apparatus 100 is ready to perform conversion for the first capacitor 10, e.g. once the converter is available again, the first capacitor 10 will be toggled into its conversion mode. To perform this conversion with the first capacitor 10, the second pair of switches (first converter switch 112 and first supply switch 122) are activated, while the first pair of switches (first readout switch 111 and first ground 121) remain not active (not conductive). The first plate 11 of the first capacitor 10 is connected to the converter connection line 2 (and thus to the input of the converter, e.g. inverting input of the comparator 50) and the second plate 12 of the first capacitor 10 is connected to the supply line 4 (and thus to the supply voltage source). The voltage at the input of the converter (e.g. at the inverting input of the comparator 50) will therefore be at least partially indicative of a magnitude of the read-out current received by the first capacitor 10 during its integration operation.

[0128] To perform the conversion, the ramp voltage is also applied to the converter, i.e. to the noninverting input of the comparator 50. At an initial time period, the ramp voltage will start at its initial voltage level and commence its voltage ramp. This ramp voltage may increase linearly, e.g. to higher voltages. Initially, the first capacitor voltage will be greater than the initial voltage of the voltage ramp. As time passes and the ramp voltage increases, the ramp voltage will get closer to the first capacitor voltage until the ramp voltage equals the first capacitor voltage. At which point, the comparator 50 outputs a signal indicating that its two inputs are the same. The logic 60 detects this output signal and stores an indication of this timing data in its internal data store. For instance, the logic 60 may store a timestamp or any form of indication of the amount of time it took the voltage ramp to reach the voltage from the first capacitor 10. Additionally, or alternatively, the logic 60 may be configured to determine the first capacitor voltage itself. For example, the logic 60 may be able to determine based on the amount of ramping time taken before the comparator output signal was detected (and e.g. stored data indicative of the ramp profile) what the first capacitor voltage is.

[0129] That stored data in the logic 60 may then be transmitted to a controller (not shown in the Figs.), e.g. during the next cycle of operation for that apparatus 100 (e.g. while the first capacitor 10 returns to operating in its integration mode). The controller of the apparatus 100 may determine based on the received data, the first capacitor voltage. For example, the controller may determine a digital value based on a counter reading (e.g. a number of elapsed clock cycles between the ramp voltage commencing and the ramp voltage equalling the first capacitor voltage). For example, this digital value may provide an indication of a first capacitor voltage and / or a magnitude of the read-out current which was integrated. Based on this first capacitor voltage (and e.g. stored data indicative of the integration time period and first capacitor capacitance), it may be determined what a magnitude of the read-out current was. From this, an indication of the corresponding capacitance at the relevant capacitive sensing electrode may be determined, and as such an indication of the proximity to that capacitive sensing electrode of an object to be sensed. By obtaining this data for an array of capacitive sensing electrodes, an ‘image’ of the object interacting with that sensor array may be obtained. This image may contain an indication of ridges and valleys in the skin of a user interacting with the sensor (e.g. portions of skin which are closer or further away from the sensor). This data may then be used for biometric authentication.

[0130] Consequently, this operation of the analogue front-end apparatus 100 may enable an analogue to digital conversion of read-out signals, e.g. for use in performing biometric authentication.

[0131] A particular advantage of the apparatus 100 shown in Fig. 2 is that this operation of the apparatus 100 (e.g. integrate, convert, and transmit data) may be occurring for more than one read-out signal at a time. Again, this pipelining operation can be seen with reference to the timing diagram of Fig. 1 b. As shown, the second capacitor 20 may be operated to integrate when the first capacitor 10 is converting, and to convert while the first capacitor 10 is integrating.

[0132] For instance, the first operation shown for the second capacitor 20 in Fig. 1 b is a conversion. This may start shortly after the first capacitor 10 has started its integration operation (and while the first capacitor 10 is still integrating). To start conversion with the second capacitor 20, the second pair of switches for that capacitor (converter and supply) are activated, while the first pair of switches (read-out and ground) remain inactive. Thus, there may be a moment in time where the first capacitor 10 has its first pair of switches activated and second pair inactive, while the second capacitor 20 has its first pair of switches inactive and the second pair activated. At which point in time, the first capacitor 10 will be integrating while the second capacitor 20 is converting. The first capacitor 10 may stop integrating before the second capacitor 20 stops converting.

[0133] Once both capacitors have stopped these processes, the first capacitor 10 will be storing its integrated signal, while the second capacitor 20 will have just finished converting. Before converting the integrated signal on the first capacitor 10, the second capacitor 20 will be precharged. For this, the second pair of switches for the second capacitor 20 and the comparator switch 52 are activated. The second capacitor 20 is then pre-charged. During pre-charge, data in the logic 60 may be transmitted to a controller (not shown) of the apparatus 100. Once the pre-charge time period has passed, these three switches are disactivated. At which point, the second capacitor 20 is ready for integration and the first capacitor 10 is ready for conversion.

[0134] The modes of the two capacitors may then be toggled. As such, the first capacitor 10 will be controlled to enter a conversion mode (i.e. its second pair of switches will be activated) and the second capacitor 20 will be controlled to enter an integration mode (i.e. its first pair of switches will be activated). As shown in Fig. 1 b, the toggling of the first capacitor 10 (i.e. into its conversion mode) may occur after the toggling of the second capacitor 20 (i.e. into its integration mode). This process may keep occurring with each capacitor continually transitioning between integration and conversion operations.

[0135] This toggling operation of the two capacitors may occur in tandem. That is, one capacitor may be operating according to a first cycle, e.g. for performing integration, while the other capacitor may be operating according to a second cycle, e.g. for performing conversion. The role of the two capacitors will keep switching. During one cycle of operation of the apparatus 100, one integration will be performed (using one of the capacitors) and one conversion will be performed (using the other). Also, as mentioned above, the data transmission (from the logic 60 to the controller) may occur in a subsequent cycle. As such, in addition to one integration and one conversion being performed per cycle, one data transmission may also be performed each cycle. This data transmission may be performed at the same time during each cycle as the pre-charge is performed (for the capacitor which has just converted).

[0136] Thus, the apparatus 100 may provide more time efficient analogue to digital conversion by enabling multiple separate functions to be performed simultaneously. The apparatus 100 may be able to provide a quick overall digitisation time without compromising on the integration or conversion time for each read-out signal. In turn, this apparatus 100 may therefore provide improved analogue to digital conversion of read-out signals, such as those output from a capacitive biometric sensor.

[0137] Another example of an analogue front-end apparatus 100 will now be described with reference to Fig. 3.

[0138] The apparatus 100 of Fig. 3 is similar to that of Fig. 2, and contains all of the features of Fig. 2. For the sake of brevity, these features will not be described again in relation to Fig. 3. Instead, the description of Fig. 3 will only focus on the additional components which have not already been described in relation to Fig. 2.

[0139] In addition to the components shown in Fig. 2, the apparatus 100 of Fig. 3 includes a third capacitor 30, additional switches, a current source 72 and a ground transistor 70. The third capacitor 30 has a first plate 31 and a second plate 32. For the third capacitor 30, there is a third read-out switch 311 , a third converter switch 312, a third ground switch 321 , and a third supply switch 322. The ground transistor 70 has a ground transistor switch 71 . The third capacitor 30 is connected in a similar manner to the first and second capacitors. The third capacitor 30 is connected in parallel with the first and second capacitors. The switches for the third capacitor 30 also provide the same variable connections as the corresponding switches for the first and second capacitors. Namely, the first plate 31 of the third capacitor 30 is connected to the read-out connection line 1 via the third read-out switch 311 and to the converter connection line 2 via the third converter switch 312. Likewise, the second plate 32 of the third capacitor 30 is connected to the supply line 4 via the third supply switch 322 and to the ground line 3 via the third ground switch 321. As described in more detail below, the third capacitor 30 may be of variable capacitance. For example, the third capacitor 30 may have a variable plate size for each plate, e.g. each plate may be selectively connected, e.g. electrically and / or mechanically, to additional plate area.

[0140] The comparator switch 52 is connected between one of the inputs and the output of the comparator 50. As shown, the comparator switch 52 is provided in a conduction line between the inverting input of the comparator 50 and the output of the comparator 50. The comparator switch 52 may provide a comparator reset switch, e.g. for shorting input and output of the comparator 50.

[0141] The ground transistor 70 has a control terminal and a conductive path. For example, the ground transistor 70 may be provided as a part of an integrated circuit (e.g. as part of the readout input circuit). The control terminal may be a gate region of the transistor, and the conductive path may connect source and drain regions of the transistor. The control terminal of the ground transistor 70 is connected to the read-out connection line 1. The conductive path of the ground transistor 70 may connect the ground line 3 to the electrical ground, e.g. the ground transistor 70 may separate the ground line 3 from the electrical ground. For example, when the conductive path of the transistor is open (e.g. there is sufficient gate-source voltage), current may flow through the conductive path of the transistor from the ground line 3 to the electrical ground.

[0142] The ground transistor switch 71 is connected between the read-out connection line 1 and the ground line 3. In other words, the ground transistor switch 71 is connected across the gate and drain regions of the ground transistor 70 (e.g. to provide a ground transistor reset switch). The current source 72 is connected to the ground line 3. Both the current source 72 and the ground line 3 are connected to the conduction path of the ground transistor 70 (and also selectively connected to the capacitors).

[0143] As with the first and second capacitors 10, 20, the third capacitor 30 is connectable to each of the read-out connection line 1 , the converter connection line 2, the ground line 3, and the supply line 4. A first plate 31 of the third capacitor 30 is connectable to the read-out connection line 1 and the converter connection line 2. The first plate 31 of the third capacitor 30 is connected to the read-out connection line 1 via a third read-out switch 311 . The first plate 31 of the third capacitor 30 is connected to the converter connection line 2 via a third converter switch 312. A second plate 32 of the third capacitor 30 is connectable to the ground line 3 and the supply line 4. The second plate 32 of the third capacitor 30 is connected to the ground line via the third ground switch 321 . The second plate 32 of the third capacitor 30 is connected to the supply line 4 via the third supply switch 322.

[0144] The third capacitor 30 is configured to facilitate with integration operations performed by the first and second capacitors. The apparatus 100 may be configured to control the third capacitor 30 to perform integration operations in parallel with integration operations performed by the first and / or second capacitors. In other words, the third capacitor 30 is arranged to receive read-out signals when the first and / or second capacitors receive read-out signals. The apparatus 100 may be configured so that the third capacitor 30 is used for integration operations, but not conversion operations. The apparatus 100 may be configured to precharge the third capacitor 30.

[0145] The apparatus 100 may be configured to use the third capacitor 30 for some or all integration operations. That is, for some or all of the integration operations, the apparatus 100 may be configured to use the third capacitor 30 in parallel with the one of the first and second capacitors which is performing an integration operation. The apparatus 100 may be configured to provide the read-out signal to be integrated to the capacitor being operated in its integration mode (i.e. one of the first or second capacitor) and the third capacitor 30, e.g. so that third capacitor integration is performed in parallel with first and / or second capacitor integration.

[0146] Controlling the third capacitor 30 to operate in an integration mode is performed in a similar manner to how the first and second capacitors are each controlled to operate in an integration mode. That is, to operate the third capacitor 30 in the integration mode, the third capacitor 30 is connected to receive the read-out signal to be integrated. For this, the read-out switch 311 for the third capacitor 30 is activated to connect the first plate 31 of the third capacitor 30 to the read-out connection line 1 (and thus to receive the read-out signal therefrom). Likewise, the second plate 32 of the third capacitor 30 is grounded. For this, the ground switch 321 is activated to connect the second plate 32 to the ground connection line 3 (and thus to ground).

[0147] The apparatus 100 is configured to use the third capacitor 30 for integration operations but not conversion operations. The apparatus 30 is configured to use the third capacitor in parallel with the first and / or second capacitors, e.g. so that the third capacitor will act to facilitate more charge storage as compared to just using one of the first and second capacitor alone.

[0148] As with the first and second capacitors, the apparatus 100 may be configured to pre-charge the third capacitor 30 prior to a subsequent integration operation being performed with that capacitor. Pre-charging the third capacitor 30 is performed in a similar manner to how the first and second capacitors are each pre-charged. That is, to pre-charge the third capacitor 30, each plate of the third capacitor is connected to a respective source of reference voltage. For this, the converter switch 312 for the third capacitor 30 is activated to connect the first plate 31 of the third capacitor 30 to the converter connection line 2. The comparator switch 52 is also activated, thereby to connect the first plate 31 to the voltage at the output of the comparator 50. Likewise, the ground switch 321 is activated to connect the second plate 32 to the supply line 3 (and thus to the supply voltage source). The apparatus 100 is configured to pre-charge the third capacitor 30 so that the voltage across that capacitor 30 corresponds to the difference in voltage between the comparator output voltage and the supply voltage.

[0149] As with the first and second capacitors, the switches for the third capacitor may act in pairs. That is, the third read-out switch 311 and the third ground switch 321 may be operated together. Likewise, the third converter switch 312 and the third supply switch 322 may be operated together.

[0150] The integration and pre-charge operations for the third capacitor 30 may always be performed in parallel with the corresponding operations for the first and / or second capacitor. The switches for the third capacitor 30 may be controlled concurrently with the corresponding switches for the other of the capacitors. For example, when operating one of the first and second capacitors in an integration mode with the third capacitor 30 integrating parallel, the apparatus 100 may activate / disactivate the first pair of switches for both capacitors accordingly. Likewise, when performing parallel pre-charges, the apparatus 100 may control the second pair of switches for both capacitors accordingly. This may simplify control implementation.

[0151] The apparatus 100 may be configured to control whether or not it uses the third capacitor 30 for an integration operation in parallel with the first or second capacitor. For example, the apparatus 100 may be configured to selectively connect (or not) the third capacitor 30 to the read-out connection line 1 each time one of the first or second capacitors is being connected to the read-out connection line 1 for an integration operation. Unlike the first and second capacitor, the apparatus 100 may not operate the third capacitor 30 in a conversion mode. That is, the apparatus 100 may be arranged to connect both the third capacitor 30 and one of the first and second capacitors to the read-out connection line 1 for receiving a read-out signal (e.g. in parallel), but to only connect the one of the first and second capacitors to the converter for conversion of the signal it has integrated.

[0152] In operation, the third capacitor 30 may be selectively used to perform integration and precharge operations in parallel with the first and / or second capacitors. For the following example, the third capacitor 30 is to be used in combination with both capacitors (e.g. for all integrations).

[0153] For this, the third capacitor 30 may initially be connected in the same manner as the first capacitor 10. Both the first and third capacitors are pre-charged, as described above. That is, for both capacitors, their second pair of switches are activated (as is the comparator switch 52), before being disactivated once pre-charge is complete. Both capacitors are then used for an integration operation. For this, their first pair of switches are activated, before being disactivated once the integration time period has elapsed. Both capacitors will have been charged based on the integration of the received read-out signal.

[0154] At this point in time, the operation of the third capacitor 30 switches from being in parallel with the corresponding operation of the first capacitor 10 to being in parallel with the corresponding operation of the second capacitor 20. The second and third capacitors are then pre-charged. For this, the second pair of switches is activated for each capacitor, and then discharged once pre-charge is complete. The second and third capacitors then integrate together, with their first pair of switches being activated then disactivated accordingly. This process may continue with the third capacitor 30 swapping so that it is operated interchangeably in parallel with each of the first and second capacitors.

[0155] The apparatus 100 may be configured to also take into account whether or not the third capacitor 30 was used when determining the indication of the stored voltage (and thus received read-out signal). For example, the voltage response of the first / second capacitor may be different if the third capacitor 30 is used or not, and the apparatus 100 may be configured to take this into account when determining read-out currents.

[0156] The third capacitor 30 may comprise a variable capacitor. For example, the third capacitor 30 may comprise a variable area for the plates. The apparatus 100 may be configured to control the capacitance of the third capacitor 30. For instance, the apparatus 100 may be operable to switch a capacitance of the third capacitor 30 between a plurality of different capacitance values. The apparatus 100 may control a capacitance to be provided by the third capacitor 30 based on an expected read-out current value. For example, in the event that it is expected that the read-out signal may have a current above a threshold value, the apparatus 100 may use the third capacitor 30 (but it may not if the expected current is below the threshold value). Similarly, the apparatus 100 may be configured to vary a capacitance of the third capacitor 30 based on an expected current value, e.g. so that the higher the expected current, the greater the capacitance of the third capacitor 30. For example, when operating a capacitive sensor, the read-out current may be higher if multiple read-out currents have been combined and / or if the read-out current will be representative of a larger area of capacitive sensing electrode.

[0157] In the apparatus 100 of Fig. 3, the connection to the electrical ground is via the ground transistor 70. The ground transistor 70 is arranged to provide a selectively controllable conductive path from the ground line 3 to the electrical ground. In response to the control terminal voltage exceeding a threshold value, the transistor will be electrically conductive, thereby to connect the ground line 3 to the electrical ground. The control terminal is connected to receive read-out signals (i.e. it is connected to the read-out connection line 1). The transistor may be selected so that the read-out signals will activate the transistor, thereby to render its conductive path electrically conductive. In other words, the apparatus 100 is arranged to selectively connect the ground line 3 (e.g. the second plate of the relevant capacitor(s)) to electrical earth in response to a read-out signal being received (at the read-out connection line 1).

[0158] The ground transistor switch 71 is arranged to facilitate a reset of the ground transistor 70. That is, the ground transistor switch 71 is configured to selectively connect the control terminal to the conductive path of the transistor (e.g. to connect gate and drain regions of the transistor). The apparatus 100 is configured to retain the ground transistor switch 71 in its disactivated (e.g. non electrically conductive) state while read-out signals are being received, e.g. while any of the capacitors are operating in their integration mode. The apparatus 100 may be configured to activate the switch during periods when no integration is occurring. For example, in every time gap between adjacent integration operations, the ground transistor switch 71 may be activated, or it may only be activated in some of those (e.g. for performing a ground transistor switch reset).

[0159] The current source 72 may be a controllable current source. That is, the current source 72 may be operable to provide a selected current value (e.g. which it can vary). The apparatus 100 may be configured to select a value for the bias current provided. For instance, by increasing the bias current, the sensor performance may be improved, but this may increase power consumption. The apparatus 100 may be configured to control operation of the bias current to implement a desired performance level-power consumption trade off for the sensor. The current source 72 is arranged to vary the current flow between the second plates of the capacitors, the current source 72 itself and the electrical ground (via the conductive path of the ground transistor 70).

[0160] In operation, a read-out signal is received (via the read-out connection line 1). While that signal is being received, the read-out connection line 1 will be at an elevated voltage level. This elevated voltage is connected to the control terminal of the ground transistor 70. This voltage causes the ground transistor 70 to become electrically conductive. At the same time, the ground transistor switch 71 is in its disactivated state, and at least one of the capacitors will have its ground switch in an activated state. As such, there may be an electrical connection between the second plate of that capacitor(s) and the electrical ground (e.g. via the conductive path of the ground transistor 70). This connection may enable current flow between the second plate(s) and the electrical ground. For example, this may enable a corresponding current flow in response to the first plate of that capacitor(s) receiving the read-out signal. The bias current source 72 may also operate at this time to influence this current flow.

[0161] Once the integration process has been completed, the relevant ground switch(es) will be disactivated. The control terminal voltage of the ground transistor 70 will also be lower. The ground transistor switch 71 is then activated. This activation may cause a shorting of the ground transistor 70 (e.g. a gate-drain shorting) for resetting that ground transistor 70. The ground transistor switch 71 is then disactivated before the next read-out signal is received.

[0162] Aspects of the present disclosure may include capacitive sensors which utilise the analogue front-end apparatuses 100 disclosed herein. The capacitive sensors may be capacitive touch sensors, such as capacitive biometric skin contact sensors. However, it will be appreciated in the context of the present disclosure that the front-end apparatuses disclosed herein may find utility for other sensors, such as optical, e.g. x-ray, sensors.

[0163] Capacitive sensors to be used in combination with the present disclosure may comprise an array of sensor pixels, wherein each sensor pixel comprises a capacitive sensing electrode. The capacitive sensor may comprise an active-matrix array of sensor pixels. For this, each sensor pixel may be connected to a gate line to activate said pixel. Each sensor pixel may also be connected to a read-out line to output a read-out signal to that read-out line. The readout signal from a sensor pixel may be in the form of a current. A magnitude of that current may provide an indication of the capacitance of the capacitive sensing electrode (as coupled with the conductive object to be sensed), and thus of the proximity of the conductive object to be sensed to that electrode. Such capacitive sensors of the present disclosure may utilise analogue front-end apparatuses 100 as disclosed herein for conversion of those read-out signals.

[0164] For instance, each read-out line of the sensor array may be connectable to an analogue frontend apparatus 100 as disclosed herein. The sensor array may comprise large number of different read-out lines. The sensor may also include a plurality of such analogue front-end apparatuses 100. For example, the sensor may include a plurality of multiplexers, wherein each multiplexer is configured to selectively connect one of a plurality (e.g. two, four, etc.) of read-out lines to an analogue front-end apparatus 100 for those read-out lines. For instance, each multiplexer may be configured to provide a selective connection between one of its plurality of read-out lines and the read-out connection line 1 of the analogue front-end apparatus 100 for that multiplexer. Alternatively, there may be one front-end apparatus 100 for each read-out line. In which case, the read-out connection line 1 may be formed from the same component (e.g. the same electrical conductor) as the read-out line itself.

[0165] In other words, the sensor may be configured to control application of read-out signals from read-out lines of the sensor array to the read-out connection line 1 of an analogue front-end apparatus 100 which will perform analogue to digital conversion of those read-out signals.

[0166] The apparatus 100 may be configured so that none of the capacitor voltages cross zero. As will be appreciated the capacitor voltage may be the voltage across the capacitor. For example, after pre-charging a capacitor, the voltage across that capacitor may correspond to the difference between the comparator output voltage (as connected to the first plate) and the voltage of the supply voltage source. The apparatus 100 may be configured to inhibit the voltage across this capacitor ever crossing zero. For example, the apparatus 100 may be configured to control operation so that the more positive plate of the capacitor will always remain more positive than the other plate. For example, the apparatus 100 may be operated to maintain one of the plates of each capacitor at a more positive value than the other, e.g. by ensuring the pre-charge will not be overcome by the subsequent integration process. For example, it may be the second plates which are at the higher voltage. For example, the comparator output voltage may be selected to be less (e.g. substantially less) than the voltage of the supply voltage source.

[0167] It will be appreciated in the context of the present disclosure that the apparatuses described herein should not be considered limiting. For instance, the structure and function of the different components of the apparatus 100 has been described above, as well as the operation of those of features. However, structural and / or functional features of the apparatus 100 need not be provided in combination with each other and / or in combination with the methods described herein. For example, an arrangement of switches has been described above for implementing the functionality of enabling simultaneous operation of one capacitor in its conversion mode and the other in its integration mode. However, other arrangements may be provided to implement this selective connection functionality. For example, the different components could be connected to different plates of the capacitors, the comparator 50 may have its inputs the other way round, the ramp voltage may decrease in voltage (rather than increasing) etc.

[0168] As described herein, a pre-charge process may be performed to reset each capacitor to a defined level. While particular sources of reference voltage have been described for performing these operations, these should not be considered limiting. For example, the apparatus may comprise additional sources of reference voltages which can be used by the different components of the apparatus, or different existing sources may be used.

[0169] As described herein, the apparatus 100 may operate in cycles. Each capacitor of the apparatus 100 may operate in one of two ‘modes’. The first mode comprises an integration operation. The second mode comprises a conversion operation. For each cycle, one capacitor may operate in its integration mode, and the other may operate in its conversion mode. Apparatuses and methods described herein may advantageously enable speeding up of the conversion process by enabling each cycle of operation to include both receiving of one signal and conversion of another signal. It is to be appreciated in the context of the present disclosure that this advantageous effect may be achieved without perfect temporal overlap between operating one capacitor in one mode and the other capacitor in the other mode. For example, operation of each capacitor in its integration mode may comprise some time spent performing the integration, as well as additional time in which no integration is being performed by that capacitor. Likewise, operation of each capacitor in its conversion mode may comprise performing the conversion, as well as additional time in which no integration is being performed by that capacitor. Both modes (integration and conversion) may start and finish at the same time. There may be some temporal overlap in each cycle when one capacitor is integrating and the other is converting.

[0170] Other operations may occur during each cycle. For example, one or more additional operations to integration may occur during operation in the integration mode. Likewise, one or more additional operations to conversion may occur during operation in the conversion mode. That is, the integration and conversion modes do not consist entirely of integration / conversion operations. For example, resetting of each capacitor may occur in one of the modes. For example, in the conversion mode after the comparison has been performed, the apparatus 100 may be operated to perform the reset (e.g. to pre-charge the relevant capacitor(s)). The reset may be performed at the same time as integration is occurring or it may be performed at a time when there is no integration occurring (e.g. when the other capacitor has either already performed its integration or is about to perform its integration). A reset operation may be performed for the ground transistor 70 at a time when there is no integration occurring. This could be in either mode of operation. It will be appreciated that integration and conversion modes may occur simultaneously for the first and second capacitors even if the integration / conversion operations with the capacitors themselves are not occurring simultaneously. This arrangement may still enable speeding up of conversion. For example, one capacitor may be operated to perform integration (e.g. connected to the read-out connection line 1) at the same time as the other capacitor is performing its reset (e.g. connecting the plates to reference voltage points). Additionally, or alternatively, one capacitor may be operated to integrate at the same time as the other is operated to convert.

[0171] It will be appreciated from the discussion above that the examples shown in the figures are merely exemplary, and include features which may be generalised, removed or replaced as described herein and as set out in the claims. With reference to the drawings in general, it will be appreciated that schematic functional block diagrams are used to indicate functionality of systems and apparatus described herein. In addition the processing functionality may also be provided by devices which are supported by an electronic device. It will be appreciated however that the functionality need not be divided in this way, and should not be taken to imply any particular structure of hardware other than that described and claimed below. The function of one or more of the elements shown in the drawings may be further subdivided, and / or distributed throughout apparatus of the disclosure. In some examples the function of one or more elements shown in the drawings may be integrated into a single functional unit. For example, although reference has been made to the third capacitor 30 only being used for integration, it is to be appreciated that the third capacitor 30 could be operated in a conversion mode by controlling operation of the switches in the same manner as for the first and second capacitors. Similarly, there may be more than two capacitors for integrating and conversion.

[0172] As will be appreciated by the skilled reader in the context of the present disclosure, each of the examples described herein may be implemented in a variety of different ways. Any feature of any aspects of the disclosure may be combined with any of the other aspects of the disclosure. For example, method aspects may be combined with apparatus aspects, and features described with reference to the operation of particular elements of apparatus may be provided in methods which do not use those particular types of apparatus. In addition, each of the features of each of the examples is intended to be separable from the features which it is described in combination with, unless it is expressly stated that some other feature is essential to its operation. Each of these separable features may of course be combined with any of the other features of the examples in which it is described, or with any of the other features or combination of features of any of the other examples described herein. Furthermore, equivalents and modifications not described above may also be employed without departing from the invention.

[0173] Certain features of the methods described herein may be implemented in hardware, and one or more functions of the apparatus may be implemented in method steps. It will also be appreciated in the context of the present disclosure that the methods described herein need not be performed in the order in which they are described, nor necessarily in the order in which they are depicted in the drawings. Accordingly, aspects of the disclosure which are described with reference to products or apparatus are also intended to be implemented as methods and vice versa. The methods described herein may be implemented in computer programs, or in hardware or in any combination thereof. Computer programs include software, middleware, firmware, and any combination thereof. Such programs may be provided as signals or network messages and may be recorded on computer readable media such as tangible computer readable media which may store the computer programs in non-transitory form. Hardware includes computers, handheld devices, programmable processors, general purpose processors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), and arrays of logic gates.

[0174] Other examples and variations of the disclosure will be apparent to the skilled addressee in the context of the present disclosure.

Claims

Claims1 . An analogue front-end apparatus for analogue to digital conversion of analogue readout signals, the apparatus comprising: a converter; a first capacitor; and a second capacitor; wherein the apparatus is configured to control each capacitor to operate in: (i) an integration mode which comprises operating the capacitor to store a charge associated with the analogue signal to be converted, and (ii) a conversion mode which comprises connecting the capacitor to the converter for a digital conversion indicative of a voltage of said capacitor; and wherein the apparatus is configured to control one of the capacitors to operate in its integration mode while controlling the other capacitor to operate in its conversion mode.

2. The apparatus of claim 1 , wherein the converter comprises a comparator, and wherein, when operating a capacitor in its conversion mode, the apparatus is configured to use the comparator to compare a voltage of said capacitor against a controlled voltage.

3. The apparatus of claim 2, wherein the comparing the voltage of said capacitor against a controlled voltage comprises applying a ramp voltage to the comparator as the controlled voltage.

4. The apparatus of claim 3, wherein the converter is configured to perform the conversion based on an obtained indication of when the ramp voltage corresponds to the capacitor voltage, optionally when the ramp voltage equals the capacitor voltage.

5. The apparatus of claim 3 or 4, wherein the converter is configured to perform the conversion by determining an amount of time taken for the ramp voltage to ramp from an initial voltage to a voltage at which it corresponds to the capacitor voltage.

6. The apparatus of any preceding claim, wherein the apparatus is configured to precharge each capacitor, optionally to restore said capacitor to a known voltage.

7. The apparatus of any preceding claim, wherein controlling at least one of the capacitors to operate in its conversion mode comprises restoring the capacitor to a selected voltage after the capacitor voltage has been applied to the converter for conversion thereof.

8. The apparatus of claim 7, wherein resetting the capacitor to the selected voltage comprises pre-charging the capacitor to the selected voltage.

9. The apparatus of claim 7 or 8, wherein resetting the capacitor to the selected voltage comprises connecting each plate of the capacitor to a respective source of reference voltage, optionally wherein the two sources are different, optionally wherein one of the sources of reference voltage comprises an output of the converter.

10. The apparatus of any preceding claim, further comprising a third capacitor, and wherein the apparatus is configured to control the third capacitor to operate in an integration mode.

11. The apparatus of claim 10, wherein the apparatus is configured to control the third capacitor to operate in its integration mode in parallel with operation of the first and / or second capacitors in their respective integration modes.

12. The apparatus of claim 11 , wherein at least one of: the apparatus is configured to connect the third capacitor in parallel with the first capacitor when the first capacitor is operating in its integration mode; and the apparatus is configured to connect the third capacitor in parallel with the second capacitor when the second capacitor is operating in its integration mode.

13. The apparatus of any of claims 10 to 12, wherein the apparatus is configured to vary the capacitance of the third capacitor.

14. The apparatus of any of claims 10 to 13, wherein the apparatus is configured to precharge the third capacitor prior to controlling that third capacitor to perform a subsequent integration operation.

15. The apparatus of claim 14, wherein pre-charging the third capacitor comprises connecting each plate of the capacitor to a respective source of reference voltage, optionally wherein the two sources are different, optionally wherein one of the sources of reference voltage comprises an output of the converter.

16. The apparatus of any preceding claim, wherein the apparatus is configured to perform analogue signal integration using one of the capacitors while performing analogue signalconversion using the other of the capacitors.

17. The apparatus of any preceding claim, wherein the apparatus is configured to toggle use of each capacitor from its integration mode into its conversion mode for conversion of a voltage of said capacitor arising from the integration performed by said capacitor.

18. The apparatus of any preceding claim, wherein each capacitor is selectively connectable to a read-out line connection or an input of the converter.

19. The apparatus of any preceding claim, wherein, at least one of: when operating a capacitor in its integration mode, the apparatus is configured to connect one plate of said capacitor to receive the analogue signal and the other plate of said capacitor to ground; and when operating a capacitor in its conversion mode, the apparatus is configured to connect one plate of said capacitor to an input of the converter and the other plate of said capacitor to a source of reference voltage.

20. The apparatus of any preceding claim, wherein the apparatus is configured to control operation of the capacitors to perform: (i) a first cycle which comprises operating the first capacitor is in its integration mode and operating the second capacitor in its conversion mode, and (ii) a second cycle subsequent to the first cycle, wherein the second cycle comprises operating the first capacitor in its conversion mode and operating the second capacitor in its integration mode.21 . The apparatus of claim 20, wherein the apparatus is configured to control operation of the capacitors to perform a third cycle subsequent to the second cycle, wherein the third cycle comprises operating the first capacitor is in its integration mode and operating the second capacitor in its conversion mode; and wherein the apparatus is configured to control operation of the converter to transmit data indicative of the conversion performed in the second cycle during the third cycle of operation to a controller of the apparatus.

22. A capacitive sensor comprising: an active-matrix array of sensor pixels; and the analogue front-end apparatus of any preceding claim; wherein each sensor pixel is connected to a read-out line of the active-matrix array, and wherein at least one of the read-out lines of the array is connected to the analogue front-end apparatus.

23. The sensor of claim 22, wherein the sensor is a capacitive biometric skin contact sensor.

24. A method of controlling operation of an analogue front-end apparatus to perform an analogue to digital conversion of an analogue read-out signal, the method comprising: operating the apparatus in a first cycle, wherein operation in the first cycle comprises operating a first capacitor in an integration mode in which the first capacitor is connected to a read-out connection line to receive a first analogue read-out signal to be converted; and operating the apparatus in a second cycle, wherein operation in the second cycle comprises: operating a second capacitor in an integration mode in which the second capacitor is connected to the read-out connection line to receive a second analogue read-out signal to be converted; and operating the first capacitor in a conversion mode in which the first capacitor is connected to a converter to perform a conversion of the first read-out signal as stored on the first capacitor.

25. A computer program product comprising computer program instructions configured to program a controller to control operation of an apparatus to implement the method of claim

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