Storage element, storage device, and electronic device

Abstract

Provided is a storage element exhibiting high operation speed. The storage element has first to fourth conductive layers, first and second insulation layers, and a semiconductor layer. The second conductive layer has a region that overlaps the first conductive layer via a first interlayer film therebetween. The third conductive layer has a region that overlaps the second conductive layer via a second interlayer film therebetween. In addition, each of the first interlayer film, the second conductive layer, the second interlayer film, and the third conductive layer has, in the region of mutual overlap, a first opening of which the bottom part is the upper surface of the first conductive layer. The first insulation layer is located on side surfaces of the first interlayer film, the second conductive layer, the second interlayer film, and the third conductive layer. The semiconductor layer has a region that is in contact with the upper surface of the third conductive layer, the upper surface of the first insulation layer, and the upper surface of the first conductive layer. The second insulation layer has a region that is in contact with the upper surface of the third conductive layer and the upper surface of the semiconductor layer. The fourth conductive layer has a region that overlaps with the third conductive layer and the first opening and that is in contact with the upper surface of the second insulation layer. In addition, the second insulation layer includes a material that can exhibit ferroelectricity.

Description

Memory element, memory device, and electronic device

[0001] One embodiment of the present invention relates to a memory element, a memory device, and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification relates to an object, an operating method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, specific examples of the technical field of one embodiment of the present invention disclosed in this specification include semiconductor devices, display devices (including liquid crystal display devices), light-emitting devices, power storage devices, imaging devices, memory devices, processing devices, signal processing devices, sensors, arithmetic devices (including processors), electronic devices, systems, driving methods thereof, manufacturing methods thereof, and inspection methods thereof.

[0003] In recent years, with the increase in the amount of data handled, there has been a demand for memory devices with larger storage capacities. In order to increase the storage capacity per unit area, it is effective to have a configuration in which multiple memory cells are stacked above a drive circuit (Patent Document 1). By stacking the memory cells, the storage capacity per unit area can be increased according to the number of stacked memory cells.

[0004] Furthermore, as a means for further reducing the circuit area, a memory cell using a ferroelectric field effect transistor (FeFET) as a memory element has been disclosed (Patent Document 2). The FeFET is a type of field effect transistor (FET) that uses a ferroelectric insulating material for the gate insulating film, and is a transistor that can retain data by utilizing the hysteresis characteristics of the remanent polarization of the ferroelectric insulating material. Unlike dynamic random access memories (DRAMs) and the like, memory cells using FeFETs do not require a capacitive element, and therefore can increase the memory capacity per unit area.

[0005] International Publication No. WO 2022 / 238798 International Publication No. WO 2023 / 089449

[0006] The FeFET structure disclosed in Patent Document 2 has a region between the gate electrode and the back gate electrode where a metal oxide including a channel formation region is formed, and a region where the metal oxide is not formed. Covering the side and top surfaces of the metal oxide with the gate electrode is expected to improve the field-effect mobility of the FeFET and increase the on-current, but in the region where the metal oxide is not formed between the gate electrode and the back gate electrode, parasitic capacitance may increase between the gate electrode and the back gate electrode. If the parasitic capacitance between the gate electrode and the back gate electrode increases, the supply of charge to the wiring connected to the gate electrode or the back gate electrode slows, lengthening the time required to change the voltage of the wiring. In particular, since the potentials of the gate electrode and the back gate electrode must be appropriately changed during data write and read operations of the FeFET, a large parasitic capacitance between the gate electrode and the back gate electrode may slow the write or read speed (collectively referred to as the operating speed in this specification) of the FeFET. For this reason, it is preferable to configure the FeFET to reduce this parasitic capacitance.

[0007] Furthermore, with the advancement of miniaturization and integration, the structure of FeFETs is also becoming smaller. In this case, the region where dielectric polarization occurs in the gate insulating film, including the insulating layer that may have ferroelectricity, becomes smaller, and the amount of dielectric polarization may become smaller. When the amount of dielectric polarization becomes smaller, the threshold voltage distribution of data in the memory element also becomes smaller, and there is a risk that erroneous data may be read during a read operation from the memory element.

[0008] An object of one embodiment of the present invention is to provide a memory element with high operating speed. Another object of one embodiment of the present invention is to provide a memory element with small parasitic capacitance. Another object of one embodiment of the present invention is to provide a memory element with a reduced occupation area. Another object of one embodiment of the present invention is to provide a memory element from which data can be accurately read. Another object of one embodiment of the present invention is to provide a memory device including the above-described memory element. Another object of one embodiment of the present invention is to provide an electronic device including the above-described memory device. Another object of one embodiment of the present invention is to provide a novel memory element, a novel memory device, or a novel electronic device.

[0009] Note that the problem of one embodiment of the present invention is not limited to the above problem. The above problem does not preclude the existence of other problems. Note that the other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the above problem and other problems. Therefore, one embodiment of the present invention does not necessarily solve all of the above problem and other problems.

[0010] One aspect of the present invention is a memory element having a fourth conductive layer having a region extending in a direction perpendicular or substantially perpendicular to a substrate and functioning as a gate, and a second conductive layer having a region extending in a direction parallel or substantially parallel to the substrate and functioning as a back gate. The memory element also has a first insulating layer, a second insulating layer, and a semiconductor layer between the gate and the back gate, each of which has a region extending in a direction perpendicular or substantially perpendicular to the substrate. The first insulating layer contacts the back gate, the second insulating layer contacts the gate, and the semiconductor layer is located between the first insulating layer and the second insulating layer. The second insulating layer contains a material that can exhibit ferroelectricity. Each of the source and drain has a region extending in a direction parallel or substantially parallel to the substrate, and the back gate electrode is located between the source and drain.

[0011] A typical example of a configuration according to one embodiment of the present invention will be described below.

[0012] (1) One aspect of the present invention is a memory element including a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a first insulating layer, a second insulating layer, and a semiconductor layer. A first interlayer film is located on the first conductive layer, and a second interlayer film is located on the first interlayer film. The second conductive layer is sandwiched between the first interlayer film and the second interlayer film and has a region overlapping the first conductive layer. The first interlayer film, the second conductive layer, and the second interlayer film have a first opening reaching the first conductive layer. The first insulating layer has regions in contact with the first interlayer film, the second conductive layer, and the second interlayer film in the first opening. The third conductive layer has a region overlapping the first insulating layer and a region overlapping the second interlayer film. The third conductive layer and the first insulating layer have a second opening reaching an upper surface of the first conductive layer. A third interlayer film is positioned on the third conductive layer, and the third interlayer film has a third opening reaching the third conductive layer. The third opening has a region that includes an overlap with the second opening in a plan view. The semiconductor layer has a region in contact with the first conductive layer, the first insulating layer, and the third conductive layer in the second opening, and also has a region in contact with the third conductive layer and the third interlayer film in the third opening. The second insulating layer has a region in contact with the semiconductor layer in the second opening and the third opening. The fourth conductive layer has a region facing the semiconductor layer with the second insulating layer interposed therebetween in the second opening and the third opening. The second insulating layer includes a material that may have ferroelectricity.

[0013] (2) Alternatively, in one aspect of the present invention, in the above (1), a fifth conductive layer may be included. In particular, a fourth interlayer film is preferably located on the upper surfaces of the second insulating layer and the fourth conductive layer. Furthermore, the fourth interlayer film preferably has a fourth opening reaching the fourth conductive layer.

[0014] In addition, the fifth conductive layer preferably has a region in contact with the upper surface of the fourth conductive layer and a side surface of the fourth interlayer film in the fourth opening, and also has a region in contact with the upper surface of the fourth interlayer film.

[0015] (3) Alternatively, in one aspect of the present invention, in the above (2), the first conductive layer and the third conductive layer may be positioned to overlap each other and extend in the first direction, and the second conductive layer and the sixth conductive layer may be positioned to overlap each other and extend in the second direction. In particular, it is preferable that the angle between the first direction and the second direction in a plan view is greater than 0 degrees and is equal to or less than 90 degrees.

[0016] (4) Alternatively, in one embodiment of the present invention, in any one of the above (1) to (3), the material that can have ferroelectricity may have an oxide containing one or both of hafnium and zirconium.

[0017] (5) Alternatively, in one embodiment of the present invention, in any one of the above (1) to (3), the semiconductor layer may include one or more elements selected from indium, zinc, and an element M in a channel formation region.

[0018] The element M is one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, magnesium, and antimony.

[0019] (6) Another aspect of the present invention is a memory device including a memory cell array including the memory element according to any one of (1) to (3), and a circuit layer. The memory cell array is located above the circuit layer. The circuit layer includes a first driver circuit, a second driver circuit, a third driver circuit, and a fourth driver circuit.

[0020] The first driving circuit has a function of transmitting a data signal corresponding to the data to the fourth conductive layer when writing data to the memory element, and a function of transmitting a selection signal for selecting the memory element to the fourth conductive layer when reading data from the memory element. The second driving circuit has a function of transmitting a signal with the logic of the data signal inverted to each of the first conductive layer and the third conductive layer when writing data to the memory element, and a function of precharging one of the first conductive layer and the third conductive layer with a first potential and applying a second potential to the other of the first conductive layer and the third conductive layer when reading data from the memory element. The third driving circuit has a function of transmitting a selection signal for selecting the memory element to the second conductive layer when reading data from the memory element. The fourth driving circuit has a function of reading the potential of one of the first conductive layer and the third conductive layer as data to be read from the memory element.

[0021] (7) Another embodiment of the present invention is an electronic device including the storage device according to (6) and a housing.

[0022] Furthermore, the above-described configuration (1) allows a stacked structure of a semiconductor layer, a second insulating layer containing a material that may have ferroelectricity, and a fourth conductive layer to be formed in the third opening, thereby forming a gate capacitance. In particular, increasing the height of the third opening, i.e., the thickness of the third interlayer film, allows the area of ​​the stacked structure to be increased, thereby increasing the electrode area of ​​the gate capacitance in the third opening. Increasing the electrode area of ​​the gate capacitance increases the amount of dielectric polarization in the second insulating layer when a voltage is applied to the stacked structure. This allows the threshold voltage distribution of data in the memory element to be widened, enabling accurate reading of logic "0" and "1." In this specification, the electrode area of ​​the gate capacitance refers to the area of ​​the region of a pair of opposing electrodes of the gate capacitance, or the area where a dielectric is formed in the region sandwiched between the pair of electrodes.

[0023] Furthermore, the above-described configuration (1) allows for the formation of, in order from the inside of the first opening, a fourth conductive layer serving as a gate electrode, a second insulating layer containing a material that may exhibit ferroelectricity, a semiconductor layer, and a first insulating layer, each of which has a vertical component. Furthermore, by providing a second conductive layer serving as a back gate electrode having a horizontal component on the side of the first opening, a region is formed in which the fourth conductive layer, the second insulating layer, the semiconductor layer, and the first insulating layer are surrounded by the second conductive layer. This configuration reduces the parasitic capacitance between the gate electrode (fourth conductive layer) and the back gate electrode (second conductive layer). This also increases the operating speed of the memory element.

[0024] Furthermore, with the above-described configuration (1), the back gate electrode (second conductive layer) is located vertically between the first conductive layer, which is one of the source electrode and the drain electrode, and the third conductive layer, which is the other of the source electrode and the drain electrode. In other words, the first conductive layer, the second conductive layer, and the third conductive layer are formed in this order from the bottom, so that the occupied area can be reduced in planar view compared to a planar transistor.

[0025] Furthermore, the above-described configuration (3) forms, from bottom to top, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer. Furthermore, since the first conductive layer and the third conductive layer are positioned to extend in a first direction, and the second conductive layer and the fourth conductive layer are positioned to extend in a second direction, the overlapping area between the first conductive layer and the third conductive layer and the second conductive layer is small in plan view, and the overlapping area between the second conductive layer and the fourth conductive layer and the third conductive layer is small. This reduces the parasitic capacitance between the first conductive layer and the third conductive layer and the parasitic capacitance between the second conductive layer and the fourth conductive layer. Furthermore, reducing each parasitic capacitance can increase the operating speed of the memory element.

[0026] According to one embodiment of the present invention, a memory element with high operating speed can be provided. According to one embodiment of the present invention, a memory element with small parasitic capacitance can be provided. According to one embodiment of the present invention, a memory element with a reduced occupation area can be provided. According to one embodiment of the present invention, a memory element from which data can be accurately read can be provided. According to one embodiment of the present invention, a memory device including the above-described memory element can be provided. According to one embodiment of the present invention, an electronic device including the above-described memory device can be provided. According to one embodiment of the present invention, a novel memory element, a novel memory device, or a novel electronic device can be provided.

[0027] Note that the effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. Note that the other effects are effects not mentioned in this section, which will be described below. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, etc., and can be extracted as appropriate from these descriptions. Note that one embodiment of the present invention has at least one of the effects listed above and other effects. Therefore, one embodiment of the present invention may not have the effects listed above.

[0028] FIG. 1A is a plan view showing an example of the configuration of a memory element, and FIGS. 1B and 1C are cross-sectional views showing an example of the configuration of a memory element. FIG. 2 is a perspective view showing an example of the configuration of a memory element, including a cross section. FIG. 3 is a block diagram showing an example of the configuration of a memory device. FIG. 4A is a circuit diagram showing an example of the operation of a memory element, FIG. 4B is a schematic diagram showing characteristics of the gate-source voltage and source-drain current in the memory element, and FIG. 4C is a cross-sectional view showing an example of the operation of the memory element. FIG. 5A is a circuit diagram showing an example of the operation of a memory element, FIG. 5B is a schematic diagram showing characteristics of the gate-source voltage and source-drain current in the memory element, and FIG. 5C is a cross-sectional view showing an example of the operation of the memory element. FIG. 6A is a circuit diagram showing an example of the operation of a memory element, FIG. 6B is a schematic diagram showing characteristics of the gate-source voltage and source-drain current in the memory element, and FIG. 6C is a timing chart showing an example of the operation of the memory element. FIG. 7A is a circuit diagram showing an example of operation of a memory element, FIG. 7B is a schematic diagram showing characteristics of a gate-source voltage and a source-drain current in the memory element, and FIG. 7C is a timing chart showing an example of operation of the memory element. FIG. 8A is a circuit diagram showing an example of operation of a memory element, and FIG. 8B is a schematic diagram showing characteristics of a gate-source voltage and a source-drain current in the memory element. FIG. 9A is a schematic plan view showing an example of a method for manufacturing a memory element, and FIGS. 9B and 9C are schematic cross-sectional views showing an example of the method for manufacturing a memory element. FIG. 10A is a schematic plan view showing an example of a method for manufacturing a memory element, and FIGS. 10B and 10C are schematic cross-sectional views showing an example of the method for manufacturing a memory element. FIG. 11A is a schematic plan view showing an example of a method for manufacturing a memory element, and FIGS. 11B and 11C are schematic cross-sectional views showing an example of the method for manufacturing a memory element. Fig. 12A is a schematic plan view showing an example of a method for manufacturing a memory element, and Figs. 12B and 12C are schematic cross-sectional views showing an example of the method for manufacturing a memory element. Fig. 13A is a schematic plan view showing an example of a method for manufacturing a memory element, and Figs. 13B and 13C are schematic cross-sectional views showing an example of the method for manufacturing a memory element. Fig. 14A is a schematic plan view showing an example of a method for manufacturing a memory element, and Figs. 14B and 14C are schematic cross-sectional views showing an example of the method for manufacturing a memory element.FIG. 15A is a schematic plan view showing an example of a method for manufacturing a memory element, and FIGS. 15B and 15C are schematic cross-sectional views showing an example of the method for manufacturing a memory element. FIG. 16A is a schematic plan view showing an example of a method for manufacturing a memory element, and FIGS. 16B and 16C are schematic cross-sectional views showing an example of the method for manufacturing a memory element. FIG. 17A is a schematic plan view showing an example of a method for manufacturing a memory element, and FIGS. 17B and 17C are schematic cross-sectional views showing an example of the method for manufacturing a memory element. FIG. 18A is a schematic plan view showing an example of a method for manufacturing a memory element, and FIGS. 18B and 18C are schematic cross-sectional views showing an example of the method for manufacturing a memory element. FIG. 19A is a schematic plan view showing an example of a method for manufacturing a memory element, and FIGS. 19B and 19C are schematic cross-sectional views showing an example of the method for manufacturing a memory element. FIG. 20A is a schematic plan view showing an example of a method for manufacturing a memory element, and FIGS. 20B and 20C are schematic cross-sectional views showing an example of the method for manufacturing a memory element. FIG. 21A is a schematic plan view showing an example of a method for manufacturing a memory element, and FIGS. 21B and 21C are schematic cross-sectional views showing an example of the method for manufacturing a memory element. FIG. 22A is a schematic plan view showing an example of a method for manufacturing a memory element, and FIGS. 22B and 22C are schematic cross-sectional views showing an example of the method for manufacturing a memory element. FIG. 23A is a schematic plan view showing an example of a method for manufacturing a memory element, and FIGS. 23B and 23C are schematic cross-sectional views showing an example of the method for manufacturing a memory element. FIG. 24A is a schematic plan view showing an example of a method for manufacturing a memory element, and FIGS. 24B and 24C are schematic cross-sectional views showing an example of the method for manufacturing a memory element.

[0043] Fig. 25A is a schematic plan view showing an example of a method for manufacturing a memory element, and Figs. 25B and 25C are schematic cross-sectional views showing an example of the method for manufacturing a memory element. Fig. 26A is a schematic plan view showing an example of a method for manufacturing a memory element, and Figs. 26B and 26C are schematic cross-sectional views showing an example of the method for manufacturing a memory element. Fig. 27A is a schematic plan view showing an example of a method for manufacturing a memory element, and Figs. 27B and 27C are schematic cross-sectional views showing an example of the method for manufacturing a memory element. Fig. 28A is a schematic plan view showing an example of a method for manufacturing a memory element, and Figs. 28B and 28C are schematic cross-sectional views showing an example of the method for manufacturing a memory element.FIG. 29A is a schematic plan view showing an example of a method for manufacturing a memory element, and FIGS. 29B and 29C are schematic cross-sectional views showing an example of the method for manufacturing a memory element. FIG. 30A is a schematic plan view showing an example of a method for manufacturing a memory element, and FIGS. 30B and 30C are schematic cross-sectional views showing an example of the method for manufacturing a memory element. FIG. 31A is a schematic plan view showing an example of a method for manufacturing a memory element, and FIGS. 31B and 31C are schematic cross-sectional views showing an example of the method for manufacturing a memory element. FIG. 32A is a schematic plan view showing an example of a method for manufacturing a memory element, and FIGS. 32B and 32C are schematic cross-sectional views showing an example of the method for manufacturing a memory element. FIG. 33 is a schematic cross-sectional view showing an example of a memory element. FIG. 34 is a schematic cross-sectional view showing an example of a memory element. FIG. 35A is a schematic plan view showing an example of a method for manufacturing a memory element, and FIGS. 35B and 35C are schematic cross-sectional views showing an example of the method for manufacturing a memory element.

[0073] Figure 36A is a schematic plan view showing an example of a method for manufacturing a memory element, and Figures 36B and 36C are schematic cross-sectional views showing an example of the method for manufacturing a memory element. Figure 37A is a schematic plan view showing an example of a method for manufacturing a memory element, and Figures 37B and 37C are schematic cross-sectional views showing an example of the method for manufacturing a memory element. Figure 38A is a schematic plan view showing an example of a method for manufacturing a memory element, and Figures 38B and 38C are schematic cross-sectional views showing an example of the method for manufacturing a memory element. Figure 39A is a schematic plan view showing an example of a method for manufacturing a memory element, and Figures 39B and 39C are schematic cross-sectional views showing an example of the method for manufacturing a memory element. Figure 40A is a schematic plan view showing an example of a method for manufacturing a memory element, and Figures 40B and 40C are schematic cross-sectional views showing an example of the method for manufacturing a memory element.

[0093] Figure 41A is a schematic plan view showing an example of a method for manufacturing a memory element, and Figures 41B and 41C are schematic cross-sectional views showing an example of a method for manufacturing a memory element. Figure 42A is a schematic plan view showing an example of a method for manufacturing a memory element, and Figures 42B and 42C are schematic cross-sectional views showing an example of a method for manufacturing a memory element. Figure 43A is a schematic perspective view showing an example of the configuration of a memory device, and Figure 43B is a block diagram showing an example of the configuration of a memory device. Figure 44 is a schematic cross-sectional view showing an example of the configuration of a memory device. Figure 45 is a schematic plan view showing an example of a memory cell array. Figure 46 is a schematic plan view showing an example of a memory cell array.FIG. 47 is a perspective schematic diagram showing an example of a memory cell array. FIG. 48 is a perspective schematic diagram showing an example of a plurality of memory layers. FIGS. 49A and 49B are diagrams showing an example of an electronic component. FIGS. 50A and 50B are diagrams showing an example of electronic equipment, and FIGS. 50C to 50E are diagrams showing an example of a mainframe computer. FIG. 51 is a diagram showing an example of space equipment. FIG. 52 is a diagram showing an example of a storage system applicable to a data center. FIGS. 53A1 to 53A7 and 53B1 to 53B6 are circuit diagrams for explaining electrical connections.

[0029] (Additional Notes Related to the Present Specification) In the present specification, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (for example, a transistor, a diode, and a photodiode), or a device having such a circuit. Furthermore, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. An example of a semiconductor device is an integrated circuit. Another example of a semiconductor device is a chip equipped with an integrated circuit. Another example of a semiconductor device is an electronic component in which a chip is housed in a package. Furthermore, for example, a memory device, a display device, a light-emitting device, a computing device, a lighting device, and an electronic device may themselves be a semiconductor device, or may include a semiconductor device.

[0030] In this specification, "connection" includes "electrical connection."

[0031] When the term "electrical connection" is used to define the connection relationship between circuit elements as an object, it includes, for example, "direct connection" and "indirect connection." For example, "A and B are directly connected" refers to a connection between A and B without the intervention of a circuit element (e.g., a transistor or a switch; wiring is not considered a circuit element). On the other hand, for example, "A and B are indirectly connected" refers to a connection between A and B via one or more circuit elements. Note that A, B, and C, which will be described later, represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0032] Here, when "A and B are indirectly connected," it refers to the following connection relationship, for example. That is, assuming that a circuit is operating, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, such a circuit can be defined as an entity, and "A and B are indirectly connected." Note that even if there is a time when electrical signal transmission or potential interaction does not occur between A and B, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, it can be defined as "A and B are indirectly connected." Note that "A and B are indirectly connected" is a definition of the connection relationship between circuit elements as an entity. Therefore, for example, even when a power supply voltage is not supplied to a circuit and the circuit is not operating, the circuit can be defined as an entity, and "A and B are indirectly connected" (however, for example, this is limited to the case where electrical signal transmission or potential interaction occurs between A and B during the operation of the circuit when a power supply voltage is supplied to the circuit and the circuit is operating).

[0033] Specific examples of "indirect connection" are shown below. First, an example of "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors, as shown in FIGS. 53A1 and 53A2. Another example of "A and B are indirectly connected" is when A and B are connected via one or more switches. When "A and B are indirectly connected," assuming that the circuit is operating, it is assumed that there is at least one time when a transistor between A and B is in an on state, a conductive state, or a state in which a current can flow. Note that "A and B are indirectly connected" also includes cases in which there is a time when a transistor between A and B is in an off state or a non-conductive state. When "A and B are indirectly connected," if multiple transistors are connected between A and B, it is assumed that there is at least one time when each of the multiple transistors between A and B is in an on state, a conductive state, or a state in which a current can flow, assuming that the circuit is operating. In other words, when "A and B are indirectly connected," it is not necessary for all of the multiple transistors to be in an on state, a conductive state, or a state in which current can flow simultaneously. Therefore, when "A and B are indirectly connected," it also includes cases in which the multiple transistors between A and B are in an off state or a non-conductive state at the same time or at different times. As another example, as shown in FIG. 53A3, when A and C are connected via the source and drain of transistor TrP and B and C are connected via the source and drain of transistor TrQ, it can be defined as "A and C are indirectly connected," "B and C are indirectly connected," or "A and B are indirectly connected." However, as will be described later, when a constant potential V is supplied to C from a power supply, GND, or the like, it can be said that "A and C are indirectly connected" or "B and C are indirectly connected," but it cannot be said that "A and B are indirectly connected."

[0034] While we have provided examples of cases where an "indirect connection" can and cannot be established, we will now present another example of a case where an "indirect connection" cannot be established. Even if an electrical signal exchange or potential interaction occurs between A and B during the operation of the circuit, there are exceptional cases where it cannot be said that "A and B are indirectly connected." An example of such an exceptional case is when A and B are connected via an insulator. In other words, when A and B are connected via an insulator, it cannot be said that "A and B are indirectly connected." A specific example of a case where A and B are connected via an insulator is when a capacitive element is connected between A and B, as shown in FIG. 53A4. Another example of a case where A and B are connected via an insulator is when a transistor gate insulating film or the like is interposed between A and B, as shown in FIG. 53A5. In this case, it cannot be said that "A (the gate of the transistor) and B (the source or drain of the transistor) are indirectly connected."

[0035] Another example of a case where it cannot be said that "A and B are indirectly connected" is when there is no timing at which an electrical signal is exchanged or potential interaction occurs between A and B. An example of this is when, as shown in Figures 53A6 and 53A7, multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between the transistors from a power supply, GND, or the like. In this case, it cannot be said that "A and B are indirectly connected," but it is possible to say that "A and V are indirectly connected" or "B and V are indirectly connected." In addition, in Figure 53A3, if A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, and a constant potential V is supplied to C from a power supply or GND, etc., the relationship will be the same as in Figures 53A6 and 53A7, so it cannot be said that "A and B are indirectly connected," but it can be said that "A and C are indirectly connected," or "B and C are indirectly connected."

[0036] Although an example of "indirect connection" has been given above, as an example, the definition of "indirect connection" is included in the definition of "electrical connection," so if "A and B are indirectly connected," it can also be said that "A and B are electrically connected."

[0037] Next, specific examples of "direct connection" are shown. Examples of "A and B are directly connected" include cases where A and B are connected without any circuit elements between them, as shown in FIGS. 53B1, 53B2, and 53B3. When A and B are connected to a power supply that supplies a constant potential V or to GND without any circuit elements between them, as shown in FIGS. 53B4 and 53B5, it can be said that "A and B are directly connected," "A and V are directly connected," or "B and V are directly connected." It can also be said that "A and B are directly connected," when A (or B) is connected to a constant potential V via the source and drain of a transistor, as shown in FIG. 53B6. Because A and V or B and V are connected via the source and drain of a transistor, they cannot be said to be directly connected, but rather that "A and V are indirectly connected" or "B and V are indirectly connected."

[0038] Although an example of "direct connection" has been given above, as an example, the definition of "direct connection" is included in the definition of "electrical connection," so when "A and B are directly connected," it can also be said that "A and B are electrically connected."

[0039] Note that even when independent components are shown connected to each other in a circuit diagram, one component may have the functions of multiple components. For example, if part of a wiring also functions as an electrode, one conductive film has both the function of a wiring and the function of an electrode. Therefore, in this specification, the term "connection" also includes such a case where one conductive film has the functions of multiple components.

[0040] Furthermore, in this specification, a "resistance element" can be, for example, a circuit element having a resistance value higher than 0Ω, or a wiring having a resistance value higher than 0Ω. Therefore, in this specification, a "resistance element" includes a wiring having a resistance value, a transistor in which a current flows between the source and drain, a diode, or a coil. Furthermore, the term "resistance element" can sometimes be replaced with the terms "resistance," "load," or "region having a resistance value." Conversely, the terms "resistance," "load," or "region having a resistance value" can sometimes be replaced with the term "resistance element." The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. Furthermore, for example, a resistance value can be replaced with a resistance value of 1 Ω or more and 1×10 ９ It may be set to Ω or less.

[0041] Furthermore, in this specification, a "capacitive element" can refer to, for example, a circuit element having a capacitance value higher than 0 F, a wiring region having a capacitance value higher than 0 F, or the gate capacitance of a transistor. The terms "capacitive element" and "gate capacitance" can sometimes be replaced with the term "capacitance." Conversely, the term "capacitance" can sometimes be replaced with the term "capacitive element" or "gate capacitance." A "capacitive element" (including a "capacitive element" with three or more terminals) includes an insulator and a pair of conductors sandwiching the insulator. Therefore, the term "pair of conductors" in a "capacitive element" can be replaced with "pair of electrodes," "pair of conductive regions," "pair of regions," or "pair of terminals." The terms "one of the pair of terminals" and "the other of the pair of terminals" may be referred to as a first terminal and a second terminal, respectively. The capacitance value can be, for example, 0.05 fF or more and 10 pF or less. It may also be, for example, 1 pF or more and 10 μF or less.

[0042] In this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals serves as a source and the other as a drain depending on the conductivity type (n-channel or p-channel) of the transistor and the level of potential applied to the three terminals of the transistor. Therefore, in this specification, the terms "source" and "drain" are sometimes interchangeable. In addition, in this specification, when describing the connection relationship of a transistor, the terms "one of the source or the drain" and "the other of the source or the drain" are sometimes interchangeable. In addition, "one of the source or the drain" may be interchangeable with "first terminal" or "first electrode," and "the other of the source or the drain" may be interchangeable with "second terminal" or "second electrode." Note that, depending on the structure of the transistor, a backgate may be included in addition to the three terminals described above. In this specification, one of the gate or the backgate of the transistor may be referred to as a first gate, and the other of the gate or the backgate of the transistor may be referred to as a second gate. Furthermore, the terms "gate" and "back gate" may be interchangeable for the same transistor. When a transistor has three or more gates, the respective gates may be referred to as a first gate, a second gate, a third gate, etc. in this specification.

[0043] For example, in this specification, a transistor having a multi-gate structure with two or more gate electrodes can be used as an example of a transistor. In a multi-gate structure, the channel formation regions are connected in series, resulting in a structure in which multiple transistors are connected in series. Therefore, the multi-gate structure can reduce the off-state current and improve the breakdown voltage (reliability) of the transistor. Alternatively, when operating in the saturation region, the multi-gate structure can provide voltage-current characteristics with a flat slope, such that the current between the drain and source does not change significantly even when the voltage between the drain and source changes. By utilizing voltage-current characteristics with a flat slope, an ideal current source circuit or an active load with a very high resistance value can be realized. As a result, a differential circuit or a current mirror circuit with excellent characteristics can be realized.

[0044] Furthermore, even when a single circuit element is shown on a circuit diagram, the circuit element may include multiple circuit elements. For example, when a circuit diagram shows one resistor element, this includes two or more resistor elements connected in series. For example, when a circuit diagram shows one capacitor element, this includes two or more capacitor elements connected in parallel. For example, when a circuit diagram shows one transistor, this includes two or more transistors connected in series, with the gates of the transistors connected to each other. Similarly, when a circuit diagram shows one switch, this includes two or more transistors connected in series or in parallel, with the gates of the transistors connected to each other.

[0045] In this specification, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, or an impurity region depending on the circuit configuration and device structure. A terminal, a wiring, or the like can also be referred to as a node.

[0046] Furthermore, in this specification, the term "selector" may refer to, for example, a circuit having multiple input terminals and one output terminal, selecting one of the multiple input terminals, and establishing a conductive state between the selected input terminal and the one output terminal. In other words, the term "selector" may refer to a circuit that selects one of the input signals input to each of the multiple input terminals and outputs the selected input signal to the output terminal. Alternatively, the term "selector" may refer to, for example, a circuit having multiple output terminals and one input terminal, selecting one of the multiple output terminals, and establishing a conductive state between the selected output terminal and the one input terminal. In other words, the term "selector" may refer to a circuit that selects one of the multiple output terminals and outputs the input signal input to the input terminal to the selected output terminal. In other words, the term "selector" may refer to a multiplexer or a demultiplexer. In particular, when inputting or outputting an analog potential or an analog current, the selector may refer to an analog multiplexer or an analog demultiplexer.

[0047] Furthermore, in this specification, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also changes.

[0048] Furthermore, in this specification, the terms "high-level potential" and "low-level potential" do not refer to specific potentials. For example, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials provided by both wirings do not have to be equal to each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials provided by both wirings do not have to be equal to each other.

[0049] Furthermore, "current" refers to the phenomenon of charge transfer (electrical conduction). For example, the statement "electrical conduction of a positively charged body is occurring" can be rephrased as "electrical conduction of a negatively charged body is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) associated with the movement of carriers. Examples of carriers here include electrons, holes, anions, cations, and complex ions, and the carriers differ depending on the system through which the current flows (e.g., semiconductor, metal, electrolyte, and vacuum). Furthermore, the "direction of current" in wiring, etc., refers to the direction in which positively charged carriers move and is expressed as a positive current amount. In other words, the direction in which negatively charged carriers move is opposite to the direction of current and is expressed as a negative current amount. Therefore, in this specification, unless otherwise specified regarding the positive / negative sign of the current (or the direction of current), the statement "current flows from element A to element B" can be rephrased as "current flows from element B to element A." Furthermore, the statement "current is input to element A" can be rephrased as "current is output from element A."

[0050] Furthermore, in this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. Furthermore, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0051] Furthermore, in this specification, terms indicating position, such as "above" and "below," may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each configuration is depicted. Therefore, the terms are not limited to those described in the specification, etc., and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing 180 degrees.

[0052] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B. Similarly, the expression "electrode B above insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B. Similarly, the expression "electrode B below insulating layer A" does not require that electrode B be formed in direct contact below insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0053] Furthermore, in this specification, terms such as "row" and "column" may be used to describe components arranged in a matrix and their positional relationships. Furthermore, the positional relationships between components change as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those used in the specification, and may be rephrased appropriately depending on the situation. For example, the expression "row direction" may be rephrased as "column direction" by rotating the orientation of the drawing by 90 degrees.

[0054] Furthermore, in this specification, the terms "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" can be changed to the term "conductive film". Or, for example, the term "insulating film" can be changed to the term "insulating layer". Furthermore, depending on the situation, the terms "film" and "layer" can be replaced with other terms without using them. For example, the terms "conductive layer" or "conductive film" can be changed to the term "conductor". Or, for example, the terms "insulating layer" or "insulating film" can be changed to the term "insulator".

[0055] Furthermore, the terms "electrode," "wiring," and "terminal" used herein do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" or "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where one or more selected from "electrode," "wiring," and "terminal" are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, the terms "electrode," "wiring," and "terminal" may be replaced with the term "region" in some cases.

[0056] Furthermore, in this specification, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." For example, the term "wiring" may be changed to the term "power line." Vice versa, terms such as "signal line" or "power line" may be changed to the term "wiring." A term such as "power line" may be changed to the term "signal line." Vice versa, a term such as "signal line" may be changed to the term "power line." Furthermore, a term "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Vice versa, the term "signal" may be changed to the term "potential."

[0057] In addition, timing charts may be used in this specification to describe an operation method of a semiconductor device. The timing charts used in the description in this specification illustrate ideal operation examples, and the periods, magnitudes, and timings of signals (e.g., potentials or currents) described in the timing charts are not limited unless otherwise specified. The magnitudes and timings of signals (e.g., potentials or currents) input to each wiring (including a node) in the timing charts described in this specification may be changed depending on the situation. For example, even if two periods are shown at equal intervals in a timing chart, the lengths of the two periods may be different. For example, even if one period is shown as long and the other as short, the lengths of the two periods may be equal, or one period may be short and the other may be long. For example, to clearly illustrate the timing chart, two or more overlapping signals may be intentionally shifted.

[0058] In this specification, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OSs), and the like. For example, when a metal oxide is contained in a channel formation region of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, when a metal oxide can form a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, an OS transistor can be referred to as a transistor including a metal oxide or an oxide semiconductor.

[0059] In this specification, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0060] In this specification, the term "impurities" in a semiconductor refers to, for example, elements other than the main component constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. The presence of impurities may cause one or more of the following: an increase in the defect level density of the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main component, particularly, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen.

[0061] In this specification, a switch refers to a device that can be in a conductive state (on state) or a non-conductive state (off state) and has the function of controlling whether or not a current flows. Alternatively, a switch refers to a device that has the function of selecting and switching a path through which a current flows. Therefore, a switch may have two or more terminals through which a current flows, in addition to a control terminal. As an example, an electrical switch, a mechanical switch, or the like can be used. In other words, the switch is not limited to a specific type as long as it has the function of controlling a current.

[0062] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, and diode-connected transistors), or logic circuits combining these. When a transistor is used as a switch, the "conductive state" of the transistor refers to, for example, a state in which the source electrode and drain electrode of the transistor can be considered to be electrically short-circuited, or a state in which current can flow between the source electrode and drain electrode. The "non-conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically disconnected. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0063] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology. This switch has a mechanically movable electrode, and the movement of the electrode controls conduction and non-conduction.

[0064] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0065] In this specification, the configurations shown in each embodiment can be combined with the configurations shown in other embodiments as appropriate to form one aspect of the present invention. When multiple configuration examples are shown in one embodiment, the configuration examples can be combined with each other as appropriate.

[0066] In addition, the content (part or all of the content) described in one embodiment can be applied, combined, or replaced with at least one of another content (part or all of the content) described in that embodiment and another content (part or all of the content) described in one or more other embodiments.

[0067] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0068] Furthermore, a figure (part or all) described in one embodiment can be combined with another part of that figure, another figure (part or all) described in that embodiment, and at least one figure (part or all) described in one or more other embodiments to form even more figures.

[0069] The embodiments described in this specification are described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that various changes in form and details can be made without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments. Note that in the configuration of the invention of the embodiments, the same reference numerals are used in different drawings for the same parts or parts having similar functions, and repeated description thereof may be omitted. Also, in perspective views and the like, the description of some components may be omitted to ensure clarity of the drawings.

[0070] In this specification, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "[n]", "[m, n]" may be added to the reference numeral. Furthermore, when an identification symbol such as "_1", "[n]", "[m, n]" is added to the reference numeral in the drawings or the like, the identification symbol may not be added if it is not necessary to distinguish between them in this specification.

[0071] In addition, in the drawings of this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences, etc. may be included.

[0072] Embodiment 1 In this embodiment, a memory element of one embodiment of the present invention will be described.

[0073] <Configuration Example of Memory Element> Figures 1A to 1C and 2 show a configuration example of a transistor MN included in the memory element. Figure 1A shows a schematic plan view of the transistor MN. Figure 1B is a schematic cross-sectional view corresponding to the portion of dashed dotted line A1-A2 shown in Figure 1A. Figure 1C is a schematic cross-sectional view corresponding to the portion of dashed dotted line A3-A4 shown in Figure 1A.

[0074] 1A to 1C, the direction of the dashed dotted line A1-A2 is the X direction, and the direction of the dashed dotted line A3-A4 is the Y direction. The direction perpendicular or approximately perpendicular to the X and Y directions is the Z direction. The X and Y directions can be perpendicular or approximately perpendicular to each other. The definitions of the X, Y, and Z directions may be the same or different in subsequent drawings. In describing the schematic plan views in FIG. 1A and other drawings, the left side may be referred to as the −X direction, the right side as the +X direction, the lower side as the −Y direction, and the upper side as the +Y direction. In describing the schematic cross-sectional views in FIG. 1B and other drawings, the left side may be referred to as the −X direction, the right side as the +X direction, the lower side as the −Z direction, and the upper side as the +Z direction. In describing the schematic cross-sectional views in FIG. 1C and other drawings, the left side may be referred to as the −Y direction, the right side as the +Y direction, the lower side as the −Z direction, and the upper side as the +Z direction.

[0075] 2 is a perspective view showing an example of the configuration of a transistor MN, and in particular, shows a part of a cross-sectional view corresponding to each of FIGS. 1B and 1C.

[0076] 1A to 1C and 2 , for example, a conductive layer functioning as a source and a conductive layer functioning as a drain are located at different heights, with an insulating layer functioning as an interlayer film interposed therebetween, and the conductive layer flows in the height direction in a semiconductor layer located inside an opening provided in the interlayer film. In other words, the channel length direction can be said to have a component in the height direction (vertical direction or Z direction). Therefore, the transistor MN can also be called a VFET (Vertical Field Effect Transistor), vertical transistor, vertical channel transistor, vertical channel transistor, etc. Furthermore, because the channel length direction of the transistor MN has a component along the side of the opening, it is easier to make it shorter than the channel length of, for example, a planar transistor.

[0077] Furthermore, in a vertical channel transistor, a conductive layer that functions as a source and a conductive layer that functions as a drain are located at different heights, so that the vertical channel transistor can occupy a smaller area in planar view than a planar transistor.

[0078] The transistor MN has a conductive layer that functions as a back gate on a part of a side surface of the opening. By applying a potential to the back gate, the threshold voltage of the transistor MN can be varied depending on the potential. For example, if the transistor MN is an n-channel transistor, the threshold voltage of the transistor MN can be shifted in the negative direction by increasing the potential of the back gate, and the threshold voltage of the transistor MN can be shifted in the positive direction by decreasing the potential of the back gate.

[0079] The transistor MN also has a first gate insulating film and a second gate insulating film. In particular, the first gate insulating film is located between a conductive layer that functions as the gate of the transistor MN and a channel formation region included in the semiconductor layer, and the second gate insulating film is located between a conductive layer that functions as the back gate of the transistor MN and the channel formation region. In other words, the first gate insulating film functions as a gate insulating film for the gate of the transistor MN, and the second gate insulating film functions as a gate insulating film for the back gate of the transistor MN.

[0080] Furthermore, the first gate insulating film contains a material that can have ferroelectricity. This allows the first gate insulating film to have a property that, when an electric field is applied from the outside of the first gate insulating film, dielectric polarization occurs inside the first gate insulating film, and the polarization remains even when the electric field is reduced to zero. Since the first gate insulating film contains a material that can have ferroelectricity, the transistor MN can be an FeFET (Ferroelectric Field Effect Transistor) with a vertical channel transistor structure. Ferroelectric materials will be described in embodiment 2.

[0081] 1A to 1C, the transistor MN has, as an example, a conductive layer ME1 that functions as one of a source or a drain, a conductive layer ME3 that functions as the other of the source or the drain, a conductive layer ME4 that functions as a gate, a conductive layer ME2 that functions as a back gate, a semiconductor layer SC1 that includes a channel formation region, an insulating layer GF1 that functions as a first gate insulating film, and an insulating layer BGI1 that functions as a second gate insulating film.

[0082] The transistor MN is located above an insulating layer IS1. The insulating layer IS1 functions, for example, as a base film for providing the transistor MN. The insulating layer IS1 preferably includes an insulating material with a low dielectric constant. By using an insulating material with a low dielectric constant as the interlayer film, it is possible to reduce, for example, the parasitic capacitance that occurs between the wiring provided below the insulating layer IS1 and the conductive layer ME3.

[0083] A conductive layer ME1 is located above the insulating layer IS1. The conductive layer ME1 has, as an example, a region that functions as either the source or the drain of the transistor MN. The conductive layer ME1 also has a region that functions as wiring for applying an electrical signal (e.g., potential or current) to either the source or the drain of the transistor MN. As an example, in FIGS. 1A to 1C , the region of the conductive layer ME1 that functions as wiring extends along the X direction. It is difficult to clearly distinguish between the region of the conductive layer ME1 that functions as either the source or the drain of the transistor MN and the region that functions as wiring, and they may share the same region.

[0084] Above the insulating layer IS1 and the conductive layer ME1, an insulating layer BI1, an insulating layer IS2, and an insulating layer BI2 are stacked in this order.

[0085] Specifically, the insulating layer BI1 has regions in contact with the upper surface and side surfaces of the conductive layer ME1 and the upper surface of the insulating layer IS1. In particular, as shown in Figures 1B and 1C, it is preferable that the ends of the conductive layer ME1 be covered by the insulating layer BI1.

[0086] For example, the insulating layer BI1 functions as an insulating film that separates the conductive layer ME1 and the insulating layer IS2. Specifically, the insulating layer BI1 functions as a barrier insulating film that suppresses the diffusion of impurities from the insulating layer IS2 to the conductive layer ME1. Examples of impurities include oxygen, which reduces the conductivity of the conductive layer ME1 through oxidation.

[0087] As described above, by covering the end portion of the conductive layer ME1 with the insulating layer BI1, it is possible to effectively suppress the diffusion of oxygen into the conductive layer ME1.

[0088] As an example, the insulating layer IS2 functions as an interlayer film separating the conductive layer ME1 from the conductive layer ME2 described below. The insulating layer IS2 may also function as a planarizing film that covers the uneven shape of the conductive layer ME1. The insulating layer IS2 preferably includes an insulating material with a low dielectric constant. By using an insulating material with a low dielectric constant as an interlayer film, the parasitic capacitance generated between wirings can be reduced. Therefore, for example, a material that can be used for the insulating layer IS1 can be used for the insulating layer IS2.

[0089] As an example, the insulating layer BI2 functions as an insulating film that separates the insulating layer IS2 and the conductive layer ME2, similar to the insulating layer BI1. Specifically, the insulating layer BI2 functions as a barrier insulating film that suppresses the diffusion of impurities from the insulating layer IS2 to the conductive layer ME2. As with the insulating layer BI1, the impurities here include, for example, oxygen.

[0090] The conductive layer ME2 is located on the insulating layer BI2 in a region overlapping a portion of the conductive layer ME1. The conductive layer ME2 has, as an example, a region that functions as wiring for supplying an electrical signal to the back gate of the transistor MN. Therefore, in FIGS. 1A to 1C , as an example, the region of the conductive layer ME2 that functions as wiring extends along the Y direction. It is difficult to clearly distinguish between the region of the conductive layer ME2 that functions as the back gate of the transistor MN and the region that functions as wiring, and they may share the same region.

[0091] An insulating layer BI3 and an insulating layer IS3 are stacked in this order above the insulating layer BI2 and the conductive layer ME2.

[0092] Specifically, the insulating layer BI3 has regions in contact with the upper surface and side surfaces of the conductive layer ME2 and the upper surface of the insulating layer BI2. In particular, as shown in Figures 1B and 1C, it is preferable that the ends of the conductive layer ME2 be covered with the insulating layer BI3.

[0093] As an example, the insulating layer BI3 functions as an insulating film separating the conductive layer ME2 and the insulating layer IS3, similar to the insulating layers BI1 and BI2. Specifically, the insulating layer BI3 functions as a barrier insulating film that suppresses the diffusion of impurities from the insulating layer IS3 to the conductive layer ME2. As in the insulating layers BI1 and BI2, examples of impurities include oxygen, which reduces the conductivity of the conductive layer ME2 through oxidation.

[0094] As described above, by covering the end portion of the conductive layer ME2 with the insulating layer BI3, it is possible to suppress the diffusion of oxygen into the conductive layer ME2, and to prevent the conductivity of the conductive layer ME2 from decreasing due to oxidation.

[0095] As an example, the insulating layer IS3 functions as an interlayer film separating the conductive layer ME2 from a conductive layer ME3 described below. The insulating layer IS3 may also function as a planarizing film that covers the uneven shape of the conductive layer ME2, for example. The insulating layer IS3 preferably includes an insulating material with a low dielectric constant. By using an insulating material with a low dielectric constant as an interlayer film, the parasitic capacitance generated between wirings can be reduced. Therefore, for example, a material that can be used for the insulating layer IS1 or the insulating layer IS2 can be used for the insulating layer IS3.

[0096] 1B and 1C, the insulating layer IS2, the conductive layer ME2, and the insulating layer IS3 are stacked in this order in the +Z direction, so that the conductive layer ME2 is sandwiched between the insulating layer IS2 and the insulating layer IS3. Similarly, the insulating layer BI2, the conductive layer ME2, and the insulating layer BI3 are stacked in this order, so that the conductive layer ME2 is sandwiched between the insulating layer BI2 and the insulating layer BI3.

[0097] Furthermore, the laminate of insulating layer BI1, insulating layer IS2, insulating layer BI2, conductive layer ME2, insulating layer BI3, and insulating layer IS3 has an opening KK1 that reaches conductive layer ME1. Specifically, forming opening KK1 in the laminate exposes conductive layer ME1. Furthermore, as shown in FIGS. 1B, 1C, and 2, forming opening KK1 may form a recess in conductive layer ME1. Therefore, opening KK1 may also include a recess formed in conductive layer ME1.

[0098] Furthermore, by forming opening KK1, side surfaces are formed on each of insulating layer BI1, insulating layer IS2, insulating layer BI2, conductive layer ME2, insulating layer BI3, and insulating layer IS3. Hereinafter, the side surfaces of opening KK1 will be described as including the side surfaces of insulating layer BI1, insulating layer IS2, insulating layer BI2, conductive layer ME2, insulating layer BI3, and insulating layer IS3.

[0099] Next, an insulating layer BGI1 is provided on the side of the opening KK1, in other words, on the side of each of the insulating layer BI1, the insulating layer IS2, the insulating layer BI2, the conductive layer ME2, and the insulating layer BI3. Also, in FIGS. 1B and 1C, the insulating layer BGI1 is provided so as to fill a portion of the opening KK1 formed in the conductive layer ME1 (e.g., the side of the opening KK1, a portion of the recess in the conductive layer ME1). Note that, when forming the opening KK1, a recess may not be formed in the conductive layer ME1. Alternatively, when forming the opening KK1, the opening KK1 may not reach the conductive layer ME1 but may reach the insulating layer BI1. In such cases, the insulating layer BGI1 is provided so as to contact the top surface of the insulating layer BI1.

[0100] 1B and 1C, the insulating layer BGI1 can be said to have regions in contact with the side surfaces of the edge layer BI1, the insulating layer IS2, the insulating layer BI2, the conductive layer ME2, and the insulating layer BI3. In other words, the semiconductor layer SC1 can be said to have regions in contact with the edge layer BI1, the insulating layer IS2, the insulating layer BI2, the conductive layer ME2, and the insulating layer BI3 in the opening KK1.

[0101] As shown in FIGS. 1B and 1C, an insulating layer BI4 and a conductive layer ME3 are stacked in this order in the +Z direction in the region overlapping the insulating layer IS3 and the insulating layer BGI1.

[0102] As an example, the insulating layer BI4 functions as an insulating film that separates the insulating layer IS3 from the conductive layer ME3 described later, similar to the insulating layers BI1 to BI3. Specifically, the insulating layer BI4 functions as a barrier insulating film that suppresses the diffusion of impurities from the insulating layer IS3 to the conductive layer ME3. As in the insulating layers BI1 to BI3, the impurities here include, for example, oxygen.

[0103] The conductive layer ME3 is located on the insulating layer BI4 so as to include an area overlapping with the conductive layer ME1 and the conductive layer ME2. As an example, the conductive layer ME3 has an area that functions as wiring for supplying an electrical signal to the other of the source or drain of the transistor MN. As an example, in FIGS. 1A to 1C and 2, the area of ​​the conductive layer ME1 that functions as wiring extends along the X direction. Note that, in the conductive layer ME3, it is difficult to clearly distinguish between the area that functions as the other of the source or drain of the transistor MN and the area that functions as wiring, and they may share the same area.

[0104] Furthermore, the laminate of the insulating layer BGI1, the insulating layer BI4, and the conductive layer ME3 has an opening KK2 that reaches the conductive layer ME1. Specifically, the conductive layer ME1 is exposed by forming the opening KK2 in the laminate. Furthermore, as shown in FIGS. 1B and 1C, the formation of the opening KK2 may result in a recess that is deeper than the opening KK1 being formed in the corresponding region of the conductive layer ME1. Therefore, the opening KK2 may also include the recess formed in the conductive layer ME1.

[0105] Furthermore, by forming the opening KK2, side surfaces are formed on each of the insulating layer BGI1, the insulating layer BI4, and the conductive layer ME3. Hereinafter, the side surfaces of the opening KK2 will be described as including the side surfaces of the insulating layer BGI1, the insulating layer BI4, and the conductive layer ME3.

[0106] The opening KK2 can be formed by removing the insulating layer BI4 and the conductive layer ME3 embedded in the opening KK1 by etching or the like. In other words, the opening KK2 can also be said to be an opening that reaches the conductive layer ME1. Therefore, the opening KK2 includes a region that is shared with the opening KK1.

[0107] As shown in FIGS. 1B and 1C, an insulating layer BI5 and an insulating layer IS4 are stacked in this order on the upper surface of the insulating layer BI4 and the upper surface of the conductive layer ME3.

[0108] Specifically, the insulating layer BI5 has regions in contact with the upper and side surfaces of the conductive layer ME3 and the upper surface of the insulating layer BI4. In particular, as shown in Figures 1B and 1C, the conductive layer ME3 is preferably covered with the insulating layer BI5. Furthermore, it is more preferable that the end portions of the conductive layer ME3 are covered with the insulating layer BI5.

[0109] As an example, the insulating layer BI5 functions as an insulating film separating the insulating layer IS4 and the conductive layer ME5, similar to the insulating layers BI1 to BI4. Specifically, the insulating layer BI5 functions as a barrier insulating film that suppresses the diffusion of impurities from the insulating layer IS4 to the conductive layer ME5. As in the insulating layers BI1 to BI4, the impurities here include, for example, oxygen.

[0110] As described above, by covering the conductive layer ME3 with the insulating layer BI5, it is possible to suppress the diffusion of oxygen into the conductive layer ME3, and to prevent the conductivity of the conductive layer ME3 from decreasing due to oxidation.

[0111] As an example, the insulating layer IS4 functions as an interlayer film separating the conductive layer ME4 described later and the conductive layer ME5 described later. The insulating layer IS4 may also function as a planarizing film that covers the uneven shape caused by the conductive layer ME3, for example. The insulating layer IS4 preferably includes an insulating material with a low dielectric constant. By using an insulating material with a low dielectric constant as an interlayer film, the parasitic capacitance generated between wirings can be reduced. Therefore, the insulating layer IS4 can be made of a material that can be used for any one of the insulating layers IS1 to IS3, for example.

[0112] Furthermore, the laminate of the insulating layer BI5 and the insulating layer IS4 has an opening KK3 that reaches the conductive layer ME3. The opening KK3 has an area that includes overlap with the opening KK2. In other words, the laminate can be said to have the opening KK3 in the area where the conductive layers ME1, ME2, and ME3 overlap. Forming the opening KK3 in the laminate also exposes a portion of the conductive layer ME3. In other words, the opening KK3 can also be said to be an opening that reaches the conductive layer ME3. The formation of the opening KK3 may result in the formation of a recess in the conductive layer ME1 that is deeper than the openings KK1 and KK2. The formation of the opening KK3 may result in the formation of a deeper recess in the conductive layer ME1 at the opening KK2. The formation of the opening KK3 may also result in the formation of a recess in a partial area of ​​the conductive layer ME3.

[0113] Furthermore, by forming the opening KK3, side surfaces are formed on each of the insulating layer BI5 and the insulating layer IS3. Hereinafter, the side surfaces of the opening KK3 will be described as including the side surfaces of the insulating layer BI5 and the insulating layer IS3.

[0114] In the opening KK2, a semiconductor layer SC1 is provided in the recess of the conductive layer ME1. In addition, in the opening KK2, the semiconductor layer SC1 is also provided on the side surfaces of the insulating layer BGI1, the insulating layer BI4, and the conductive layer ME3. In other words, the semiconductor layer SC1 is formed on the bottom and side surfaces of the opening KK2.

[0115] In addition, in the opening KK3, the semiconductor layer SC1 is also provided on the upper surface of the conductive layer ME3. In addition, in the opening KK3, the semiconductor layer SC1 is also provided on each side surface of the insulating layer BI5 and the insulating layer IS4. In other words, the semiconductor layer SC1 is formed on the bottom and side surfaces of the opening KK3.

[0116] Outside the opening KK3, a semiconductor layer SC1 is also provided on the upper surface of the insulating layer IS4.

[0117] To summarize the above, it can be said that the semiconductor layer SC1 has a region in contact with the upper surface (e.g., recess) of the conductive layer ME1, the side surface of the insulating layer BGI1, the side surface of the insulating layer BI4, the side surface and upper surface of the conductive layer ME3, the side surface of the insulating layer BI5, and the side surface and upper surface of the insulating layer IS4. In other words, it can be said that the semiconductor layer SC1 has a region in contact with the conductive layer ME1, the insulating layer BGI1, the insulating layer BI4, and the conductive layer ME3 in the opening KK2, a region in contact with the conductive layer ME3, the insulating layer BI5, and the insulating layer IS4 in the opening KK3, and a region in contact with the insulating layer IS4 outside the openings KK2 and KK3.

[0118] Note that the semiconductor layer SC1 preferably contains, for example, a metal oxide that functions as an oxide semiconductor. That is, the transistor MN is preferably an OS transistor. Metal oxides that function as oxide semiconductors will be described in detail in Embodiments 2 and 3.

[0119] An insulating layer GF1 is provided on the upper surface of the insulating layer IS4 and on the upper and side surfaces of the semiconductor layer SC1.

[0120] The insulating layer GF1 has regions that contact the upper surface and side surfaces of the semiconductor layer SC1 and the upper surface of the insulating layer IS4. In particular, as shown in Figures 1B and 1C, it is preferable that the end portions of the semiconductor layer SC1 be covered by the insulating layer GF1. By covering the end portions of the semiconductor layer SC1 with the insulating layer GF1, the conductive film that will become the conductive layer ME4 (described later) and the semiconductor layer SC1 do not come into direct contact with each other, thereby preventing a short circuit between the conductive layer ME4 and the semiconductor layer SC1.

[0121] As described above, the insulating layer GF1 contains a material that may have ferroelectricity. Therefore, dielectric polarization occurs inside the insulating layer GF1 due to the electric field from the conductive layer ME4 located on top of the insulating layer GF1. Furthermore, even if the electric field is reduced to zero, the dielectric polarization inside the insulating layer GF1 remains.

[0122] A conductive layer ME4 is provided on the upper surface of the insulating layer GF1. Specifically, the conductive layer ME4 is positioned so as to include a region on the upper surface of the insulating layer GF1 that overlaps with the semiconductor layer SC1. Therefore, the conductive layer ME4 includes regions where the conductive layers ME1, ME2, and ME3 overlap one another. Furthermore, it can be said that the conductive layer ME4 has regions inside each of the openings KK2 and KK3, or outside the openings KK2 and KK3, that face the semiconductor layer SC1 with the insulating layer GF1 interposed therebetween.

[0123] Furthermore, a gate capacitance of the transistor MN is formed in a region where the semiconductor layer SC1, the insulating layer GF1, and the conductive layer ME4 overlap each other (a region where the semiconductor layer SC1 and the conductive layer ME4 face each other via the insulating layer GF1). In particular, by increasing the thickness of the insulating layer IS4, the area of ​​the region where the semiconductor layer SC1, the insulating layer GF1, and the conductive layer ME4 overlap each other in the opening KK3 can be increased. This region functions as a gate capacitance, with the semiconductor layer SC1 and the conductive layer ME4 of the transistor MN acting as a pair of electrodes, so increasing the area of ​​this region can increase the electrode area of ​​the gate capacitance. As will be described in detail later, by using a material that can have ferroelectricity for the insulating layer GF1, polarization generated by applying a predetermined voltage between the semiconductor layer SC1 and the conductive layer ME4 can be retained in the insulating layer GF1 as remanent polarization. In particular, by increasing the electrode area of ​​the gate capacitance, the remanent polarization can also be increased, thereby widening the threshold voltage distribution of data in the memory element and enabling accurate reading of logic "0" and "1."

[0124] The electrode area of ​​the gate capacitance is determined by the shape and size of the openings KK2 and KK3. For example, the length L ＤＰ is the depth of the opening KK3, or can be said to be the combined film thickness of the insulating layer BI5 and the insulating layer IS4. Note that, when a recess is formed in a part of the conductive layer ME3 by forming the opening KK3, L ＤＰ may be longer than the combined thickness of the insulating layer BI5 and the insulating layer IS4. ＤＰThe longer L is, the larger the area where the semiconductor layer SC1, the insulating layer GF1, and the conductive layer ME4 overlap each other, and therefore the electrode area value of the gate capacitance can be increased. ＤＰ is preferably 0.010 μm or more and 0.30 μm or less, more preferably 0.050 μm or more and 0.30 μm or less, even more preferably 0.10 μm or more and 0.30 μm or less, still more preferably 0.15 μm or more and 0.30 μm or less, and even more preferably 0.20 μm or more and 0.30 μm or less. In addition, one of the insulating layers BI5 and IS4 may be 0 nm (one of the insulating layers BI5 and IS4 may not be formed).

[0125] If the parasitic capacitance between the conductive layer ME3 and the conductive layer ME4 increases, the operating speed of the transistor MN may decrease. ＤＰ is preferably 0.010 μm or more and 0.30 μm or less, and more preferably 0.030 μm or more and 0.060 μm or less.

[0126] Also, for example, the length L shown in FIG. ＷＤ is the width of the opening KK3 along the dashed line A1-A2. In particular, when the opening KK3 is cylindrical, L ＷＤ can be the diameter of the circle that forms the base. In this case, L ＷＤ The longer the distance, the larger the area where the semiconductor layer SC1, the insulating layer GF1, and the conductive layer ME4 overlap each other, and therefore the electrode area of ​​the gate capacitance can be increased.

[0127] Also, for example, the length L shown in FIG. ＳＣ is the width of the semiconductor layer SC1 formed on the dashed dotted line A3-A4. In particular, when the semiconductor layer SC1 has a circular shape in a plan view, L ＳＣ Furthermore, when the opening KK3 is cylindrical, L ＳＣ L ＷＤ In other words, it is preferable that the area of ​​the region of the semiconductor layer SC1 in contact with the upper surface of the insulating layer IS4 is large.

[0128] Also, for example, the length L shown in FIG. ＭＥ is the width of the conductive layer ME4 formed on the dashed dotted line A3-A4. In particular, when the conductive layer ME4 is formed in a circular shape in a plan view, L ＭＥ Furthermore, when the semiconductor layer SC1 has a circular shape, L ＭＥ Is L ＳＣ Although it is shown shorter than L ＭＥ Is L ＳＣ Preferably, L is equal to or approximately equal to ＭＥ Is L ＳＣ This makes it possible to increase the area of ​​the region on the insulating layer IS4 where the semiconductor layer SC1, the insulating layer GF1, and the conductive layer ME4 overlap each other, thereby increasing the electrode area of ​​the gate capacitance of the transistor MN.

[0129] Also, for example, the length L shown in FIG. ＲＭ is the width of the opening KK2 along the dashed line A1-A2. In particular, when the opening KK2 is cylindrical, L ＲＭ When the gate capacitance of the transistor MN4 and the parasitic capacitance between the conductive layer ME3 and the conductive layer ME4 are taken into consideration, L ＲＭ L ＷＤ shorter than L ＷＤ It is preferable to set the value close to L ＷＤ -L ＲＭ It is preferable that L is a small value and is greater than 0. ＷＤ -L ＲＭ is more preferably 0. For example, it is more preferably greater than 0.10 μm and not greater than 0.20 μm, more preferably greater than 0.050 μm and not greater than 0.10 μm, more preferably greater than 0.020 μm and not greater than 0.050 μm, more preferably greater than 0.010 μm and not greater than 0.020 μm, and more preferably 0 μm or greater and not greater than 0.010 μm.

[0130] For example, the angle θ shown in FIG. 1B is the taper angle between the insulating layer BI5 and the insulating layer IS4 due to the formation of the opening KK3. By reducing θ, the contact area between the insulating layer BI5 and the insulating layer IS4 and the semiconductor layer SC1 increases, and the area of ​​the region where the semiconductor layer SC1, the insulating layer GF1, and the conductive layer ME4 overlap also increases. This allows the electrode area of ​​the gate capacitance to be increased. For example, θ is preferably 70 degrees or more and 90 degrees or less, more preferably 65 degrees or more and 90 degrees or less, even more preferably 65 degrees or more and 85 degrees or less, even more preferably 60 degrees or more and 80 degrees or less, even more preferably 55 degrees or more and 80 degrees or less, preferably 50 degrees or more and 80 degrees or less, and preferably 45 degrees or more and 80 degrees or less.

[0131] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface. Alternatively, it refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the film surface underlying the structure. The angle between an inclined side surface and the substrate surface or the film surface is referred to as a taper angle. In this specification and the like, a side surface that is at 90 degrees with respect to the substrate surface is also referred to as an inclination. In this specification, a tapered shape having a taper angle greater than 0 degrees and equal to or less than 90 degrees is referred to as a forward tapered shape, and a tapered shape having a taper angle greater than 90 degrees and less than 180 degrees is referred to as a reverse tapered shape.

[0132] Furthermore, since the region of the semiconductor layer SC1 in contact with the insulating layer IS4 functions as one of a pair of electrodes of the gate capacitance, it is preferable that this region have high conductivity. By increasing the conductivity of this region, it is possible to speed up the accumulation of charge in this region, thereby increasing the operating speed of the memory element and increasing the amount of polarization in the insulating layer GF1 when dielectric polarization occurs. Note that a method for increasing the conductivity of this region will be described in detail in embodiment 2.

[0133] The conductive layer ME4 is provided so as to fill the openings KK2 and ME3. Therefore, the insulating layer BGI1, the semiconductor layer SC1, the insulating layer GF1, and the conductive layer ME4 are stacked in this order from the side surface of the opening KK1 toward the inside. The semiconductor layer SC1, the insulating layer GF1, and the conductive layer ME4 are stacked in this order from the side surface of the opening KK3 toward the inside.

[0134] Furthermore, in the plan view of FIG. 1A , the conductive layer ME4 may be provided inside the region of the semiconductor layer SC1. In other words, in the cross-sectional views of FIGS. 1B and 1C , the end of the conductive layer ME4 may be provided inside the end of the semiconductor layer SC1. In FIGS. 1A to 1C , by forming the conductive layer ME4 only in the region above the semiconductor layer SC1, the transistor MN can be configured so that the conductive layer ME4 is not provided in the step of the insulating layer GF1 caused by the semiconductor layer SC1. Because the step region of the insulating layer GF1 may have a thinner film thickness than other regions of the insulating layer GF1, the conductive layer ME4 and the semiconductor layer SC1 may come into contact (short-circuit) with each other in the step region of the insulating layer GF1. By configuring the transistor MN so that the conductive layer ME4 is not provided in the step of the insulating layer GF1, the conductive layer ME4 and the semiconductor layer SC1 can be prevented from coming into contact (short-circuit) with each other, thereby increasing the yield of the transistor MN.

[0135] An insulating layer IS5 is formed above the insulating layer GF1 and the conductive layer ME4.

[0136] For example, the insulating layer IS5, together with the insulating layer IS4 and the insulating layer GF1, functions as an interlayer film separating the conductive layer ME3 from the conductive layer ME5 described below. Therefore, the insulating layer IS5 preferably has an insulating material with a low dielectric constant. By using an insulating material with a low dielectric constant as an interlayer film, the parasitic capacitance generated between wirings can be reduced. Furthermore, the insulating layer IS5 may function as, for example, a planarizing film that covers the uneven shapes caused by one or both of the insulating layer GF1 and the conductive layer ME4. From the above, the insulating layer IS5 can use, for example, a material or configuration that can be applied to any one of the insulating layers IS1 to IS4.

[0137] Furthermore, the insulating layer IS5 has an opening KK4 that reaches the conductive layer ME4 in a region overlapping with the conductive layer ME4 or in a part of that region. Although the opening KK4 is provided inside the conductive layer ME4 in the plan view of FIG. 1A , the opening KK4 may be provided outside the conductive layer ME4 so as to surround it. Furthermore, the formation of the opening KK4 may result in a recess being formed in the upper surface of the conductive layer ME4 at the opening KK4.

[0138] In the opening KK4, a conductive layer ME5 is provided on the upper surface of the conductive layer ME4 and on the side surface of the insulating layer IS5. Also, as shown in Figures 1B and 1C, the conductive layer ME5 is formed so as to be embedded in the opening KK4. Therefore, the conductive layer ME5 has a region in contact with the conductive layer ME4.

[0139] A conductive layer ME5 is also provided on the upper surface of the insulating layer IS5 outside the opening KK4. The conductive layer ME5 has, as an example, a region that functions as wiring for supplying an electrical signal to the gate of the transistor MN. As an example, the region of the conductive layer ME5 that functions as wiring extends along the Y direction in FIGS. 1A to 1C.

[0140] An insulating layer BI6 is provided on the upper surface of the conductive layer ME5 and the upper surface of the insulating layer IS6. In particular, as shown in Figures 1B and 1C, it is preferable that the end portion of the conductive layer ME5 be covered with the insulating layer BI6.

[0141] As an example, the insulating layer BI6 functions as an insulating film separating the conductive layer ME5 and the insulating layer IS5, similar to the insulating layers BI1 to BI5. Specifically, the insulating layer BI6 functions as a barrier insulating film that suppresses the diffusion of impurities from the insulating layer IS6 to the conductive layer ME5, which will be described later. Examples of impurities here include oxygen, which reduces the conductivity of the conductive layer ME5 through oxidation, similar to the insulating layers BI1 to BI5.

[0142] As described above, by covering the end portion of the conductive layer ME5 with the insulating layer BI6, it is possible to suppress the diffusion of oxygen into the conductive layer ME5, and to prevent the conductivity of the conductive layer ME5 from decreasing due to oxidation.

[0143] An insulating layer IS6 is provided above the insulating layer BI5.

[0144] For example, the insulating layer IS6 functions as a protective film for the transistor MN. Furthermore, when wiring, circuit elements, etc. are provided above the transistor MN, the insulating layer IS6 functions as an interlayer film. Therefore, the insulating layer IS5 preferably has an insulating material with a low dielectric constant. By using an insulating material with a low dielectric constant as an interlayer film, the parasitic capacitance generated between wirings can be reduced. Therefore, the insulating layer IS5 can be made of a material or configuration that can be applied to any one of the insulating layers IS1 to IS4, for example. Furthermore, the insulating layer IS6 may function as a planarizing film that covers the uneven shape caused by the conductive layer ME5, for example.

[0145] As described above, the configuration of transistor MN includes, inside opening KK1 or opening KK2, a conductive layer ME4 (gate electrode of transistor MN) having a component perpendicular or approximately perpendicular to a substrate (not shown), and, on the side of opening KK1, a conductive layer ME2 (back gate electrode of transistor MN) having a component parallel or approximately parallel to the substrate. This reduces the area of ​​the region where conductive layer ME2 and conductive layer ME4 overlap, thereby reducing the parasitic capacitance between conductive layer ME2 and conductive layer ME4.

[0146] 1A to 1C , the conductive layers ME1 (either the source or drain of the transistor MN), ME2, ME3 (the other of the source or drain of the transistor MN), and ME5 are formed in this order from bottom to top. By extending the conductive layers ME1 and ME3 in the X direction and the conductive layers ME2 and ME5 in the Y direction, the parasitic capacitance between the conductive layers ME1 and ME2, the parasitic capacitance between the conductive layers ME2 and ME3, and the parasitic capacitance between the conductive layers ME3 and ME5 can be reduced. Furthermore, since the distance in the Z direction between the conductive layers ME1 and ME3 is increased, the parasitic capacitance between the conductive layers ME1 and ME3 can be reduced. Furthermore, since the distance in the Z direction between the conductive layers ME2 and ME5 is increased, the parasitic capacitance between the conductive layers ME2 and ME5 can be reduced.

[0147] Furthermore, as described above, by reducing the parasitic capacitance of the transistor MN and its periphery, the operating speed of the memory element can be increased.

[0148] <Configuration Example of Memory Device> Next, a configuration example of a memory device including a memory element of one embodiment of the present invention will be described.

[0149] 3 illustrates an example of a circuit configuration of a memory device including a memory element according to one embodiment of the present invention. The memory device MDV includes a memory cell array MCA, a driver circuit BD, a driver circuit SD, a driver circuit WD, and a driver circuit BGD.

[0150] The memory cell array MCA has a plurality of memory elements MC, and the memory elements MC are arranged in a matrix in the memory cell array MCA. Note that in this specification, the memory elements can be referred to as memory cells.

[0151] The memory element MC includes, as an example, the transistor MN described above. A first terminal of the transistor MN is connected to the wiring BL, a second terminal of the transistor MN is connected to the wiring SL, a gate of the transistor MN is connected to the wiring WL, and a back gate of the transistor MN is connected to the wiring BGL.

[0152] 1A to 1C has the function of the wiring WL in Fig. 3. Therefore, the potential applied to the wiring WL is also applied to the conductive layer ME4. For this reason, in this specification and drawings, the conductive layer ME4 may also be described as part of the wiring WL for convenience.

[0153] 1A to 1C functions as the wiring BL in Fig. 3, and the other of the conductive layer ME1 and the conductive layer ME3 functions as the wiring SL in Fig. 3. The conductive layer ME2 shown in Fig. 1A to 1C functions as the wiring BGL.

[0154] The driver circuit SD is connected to the wiring BL and the wiring SL. The driver circuit WD is connected to the wiring WL. The driver circuit BGD is connected to the wiring BGL. The driver circuit BD is connected to the wiring BL.

[0155] As an example, the drive circuit WD has a function as a first write data line driver circuit that transmits a data signal to the wiring WL when writing data to the memory element MC, and a function as a read word line driver circuit that transmits a selection signal to the wiring WL to select the memory element MC when reading data from the memory element MC.

[0156] Therefore, the wiring WL functions as a first write data line (sometimes called a write bit line) and a read word line.

[0157] For example, the driver circuit SD functions as a second write data line driver circuit that transmits signals with inverted logic of the data signal to the wiring BL and the wiring SL when writing data to the memory element MC. For example, the driver circuit SD also functions to precharge the wiring BL to a predetermined potential and to apply a fixed potential to the wiring SL when reading data from the memory element MC. Note that the fixed potential is preferably lower than the potential precharged to the wiring BL.

[0158] For example, the driver circuit BD has a function of amplifying a potential applied to the wiring BL according to data read from the memory element MC and outputting the amplified potential. In other words, the driver circuit BD functions as a read data line driver circuit for the memory element MC.

[0159] Therefore, the wiring BL functions as a second write data line and a read word line, and the wiring SL functions as a third write data line and a source line.

[0160] For example, the driver circuit BGD has a function of applying different potentials to the wiring BGL when writing data to the memory element MC and when reading data from the memory element MC.

[0161] For example, the potential applied to the wiring BGL when reading data from the memory element MC is preferably higher than the potential applied to the wiring BGL when writing data to the memory element MC. Specifically, the threshold voltage of the transistor MN when reading data from the memory element MC is preferably shifted to the negative side relative to the threshold voltage of the transistor MN when writing data to the memory element MC. As will be described in detail later, by shifting the threshold voltage of the transistor MN when reading data from the memory element MC to the negative side, the read potential applied from the driver circuit WD to the gate of the transistor MN via the wiring WL can be lowered. Lowering the read potential can prevent data from being erroneously rewritten with other data when reading data from the memory element MC.

[0162] <Example of Operation of Storage Device> Here, an example of the write operation and read operation of the storage device MDV shown in FIG. 3 will be described.

[0163] First, as an example, the operation of writing data "1" to the memory element MC will be described with reference to FIGS. 4A to 4C.

[0164] 4A is a circuit diagram of the memory element MC and its peripheral wiring from FIG. 3, and the potential level of the wiring is also indicated. FIG. 4B is a schematic diagram showing the characteristics of the gate-source voltage (VGS) and drain current (ID) of the transistor MN. The vertical axis of the schematic diagram in FIG. 4B is a linear scale. FIG. 4C is an enlarged cross-sectional view of the transistor MN in FIG. 1A.

[0165] In FIG. 4C, the conductive layer ME1 is shown as the wiring BL and the conductive layer ME3 is shown as the wiring SL, but the same explanation applies if the conductive layer ME1 is shown as the wiring SL and the conductive layer ME3 is shown as the wiring BL.

[0166] For example, when data “1” is written to the memory element MC, a high-level potential (V Ｈｉｇｈ 4A ) is applied to the wiring BL and the wiring SL, and a low-level potential (V Ｌｏｗ 4C ), positive charges SDK are unevenly distributed at and near the interface of conductive layer ME4 in contact with insulating layer GF1, and negative charges FDK are unevenly distributed at and near the interface of semiconductor layer SC1 in contact with insulating layer GF1. The positive charges SDK contained in conductive layer ME4 and the negative charges FDK contained in semiconductor layer SC1 generate an electric field E1 in the direction from conductive layer ME4 to conductive layer ME3 via insulating layer GF1, and an electric field E2 in the direction from conductive layer ME4 to conductive layer ME1 via insulating layer GF1. As a result, dielectric polarization occurs in the insulating layer GF1, which contains a material that may have ferroelectricity, in a direction opposite to the electric fields E1 and E2. Moreover, above the conductive layer ME3, an electric field E31 is generated in the direction from the conductive layer ME4 to the semiconductor layer SC1 via the insulating layer GF1, and above the conductive layer ME1 and below the conductive layer ME3, an electric field E32 is generated in the direction from the conductive layer ME4 to the semiconductor layer SC1 via the insulating layer GF1. As a result, a dielectric polarization opposite to the electric field E31 is generated in the insulating layer BGI1 above the conductive layer ME3, and a dielectric polarization opposite to the electric field E32 is generated in the insulating layer BGI1 above the conductive layer ME1 and below the conductive layer ME3.

[0167] Thereafter, even if the application of potentials from the wiring WL, the wiring BL, and the wiring SL is stopped, the dielectric polarization generated in the insulating layer GF1 is maintained, thereby making it possible to write data “1” into the memory element MC.

[0168] When data "1" is written to memory element MC, the gate-source voltage (VGS) and drain current (ID) characteristics D1 of transistor MN are as shown by the solid line in Fig. 4B. Due to dielectric polarization occurring in the material contained in insulating layer GF1 that may have ferroelectricity, an electric field is maintained in the direction from conductive layer ME4 to conductive layer ME3, an electric field in the direction from conductive layer ME4 to semiconductor layer SC1, and an electric field in the direction from conductive layer ME4 to conductive layer ME1, so that transistor MN is approximately normally on.

[0169] Note that normally-on means that a current flows between the source and drain when the gate-source voltage of the transistor is 0V.

[0170] When writing data "1" to the memory element MC, the drive circuit BGD may apply a low-level potential to the wiring BGL that is lower than the high-level potential applied to the conductive layer ME2. This makes it possible to strengthen the electric field applied to the insulating layer GF1 between the conductive layers ME2 and ME4, making it easier to generate dielectric polarization within the insulating layer GF1.

[0171] Next, as an example, a write operation of data "0" to the memory element MC will be described with reference to FIGS. 5A to 5C.

[0172] Fig. 5A is a circuit diagram of the memory element MC and its peripheral wiring from Fig. 3, similar to Fig. 4A, and also shows the potential of the wiring in the circuit diagram. Fig. 5B is a schematic diagram showing the characteristics of the gate-source voltage (VGS) and drain current (ID) of the transistor MN, similar to Fig. 4B. Fig. 5C is an enlarged cross-sectional view of the transistor MN shown in Fig. 1A, similar to Fig. 4C.

[0173] In FIG. 5C, the conductive layer ME1 is shown as the wiring BL and the conductive layer ME3 is shown as the wiring SL, but the same explanation applies if the conductive layer ME1 is shown as the wiring SL and the conductive layer ME3 is shown as the wiring BL.

[0174] For example, when data “0” is written to the memory element MC, a low-level potential (V Ｌｏｗ 5A ) is applied to the wiring BL and the wiring SL, and a high-level potential (V Ｈｉｇｈ 5C ), negative charges FDK are unevenly distributed at and near the interface of conductive layer ME4 in contact with insulating layer GF1, and positive charges SDK are unevenly distributed at and near the interface of semiconductor layer SC1 in contact with insulating layer GF1. The negative charges FDK contained in conductive layer ME4 and the positive charges SDK contained in semiconductor layer SC1 generate an electric field E1 in the direction from conductive layer ME3 to conductive layer ME4 via insulating layer GF1, and an electric field E2 in the direction from conductive layer ME1 to conductive layer ME4 via insulating layer GF1. As a result, dielectric polarization occurs in the insulating layer GF1, which contains a material that may have ferroelectricity, in a direction opposite to the electric fields E1 and E2. Moreover, above the conductive layer ME3, an electric field E31 is generated in the direction from the semiconductor layer SC1 to the conductive layer ME4 via the insulating layer GF1, and above the conductive layer ME1 and below the conductive layer ME3, an electric field E32 is generated in the direction from the semiconductor layer SC1 to the conductive layer ME4 via the insulating layer GF1. As a result, a dielectric polarization opposite to the electric field E31 is generated in the insulating layer BGI1 above the conductive layer ME3, and a dielectric polarization opposite to the electric field E32 is generated in the insulating layer BGI1 above the conductive layer ME1 and below the conductive layer ME3.

[0175] After that, even if the application of potentials from the wiring WL, the wiring BL, and the wiring SL is stopped, the dielectric polarization generated in the material that may have ferroelectricity and is included in the insulating layer GF1 is maintained, thereby making it possible to write data “0” to the memory element MC.

[0176] When data "0" is written to memory element MC, the gate-source voltage (VGS) and drain current (ID) characteristics D0 of transistor MN are as shown by the solid line in Fig. 5B. Due to dielectric polarization occurring in the material contained in insulating layer GF1 that may have ferroelectricity, an electric field is maintained in the direction from conductive layer ME3 to conductive layer ME4, an electric field in the direction from semiconductor layer SC1 to conductive layer ME4, and an electric field in the direction from conductive layer ME1 to conductive layer ME4, so that transistor MN is normally off.

[0177] Note that the normally-off state refers to a state in which the amount of current flowing between the source and drain is extremely small when the gate-source voltage of the transistor is 0 V. For example, when a semiconductor layer of a transistor contains an oxide semiconductor, the amount of current flowing between the source and drain when the transistor is normally off is 1×10 per 1 μm of channel width at room temperature (e.g., 25° C.). −２０ A or less, 1 x 10 at 85°C −１８ A or less, or 1 x 10 at 125°C −１６ It will be A or below.

[0178] When writing data "0" to the memory element MC, the drive circuit BGD may apply a high-level potential to the wiring BGL that is higher than the low-level potential applied to the conductive layer ME2. This makes it possible to strengthen the electric field applied to the insulating layer GF1 between the conductive layers ME2 and ME4, and to make it easier to generate dielectric polarization within the insulating layer GF1.

[0179] As described above, by writing data “0” or “1” to the memory element MC, the characteristics of the gate-source voltage (VGS) and drain current (ID) of the transistor MN are determined according to the data “0” or “1”.

[0180] Although it has been described above that the transistor MN is normally on when a logic "1" is written to the memory element MC, it may be normally off depending on the situation. For example, if a transistor with a low threshold voltage is used as the transistor MN, it may be normally off when a logic "1" is written to the memory element MC.

[0181] Next, as an example, a data read operation from the memory element MC will be described with reference to FIGS. 6A to 6C.

[0182] Fig. 6A is a circuit diagram of the memory element MC and its peripheral wiring from Fig. 3, similar to Figs. 4A and 5A, and the potential of the wiring in the circuit diagram is also indicated. Fig. 6B is a schematic diagram showing the characteristics of the gate-source voltage (VGS) and drain current (ID) of the transistor MN, similar to Figs. 4B and 5B. Fig. 6C is a timing chart showing an example of a read operation in the memory element MC.

[0183] 6C shows changes in the potentials of the wirings WL, BL, SL, and BGL during and around the periods T1 to T3. Note that the wiring BGL is set to a fixed potential of V ＣＮ The potential V ＣＮ is set to a potential that does not affect the read operation of the memory element MC.

[0184] For example, when data is read from the memory element MC, a low-level potential (V Ｌｏｗ Next, in the period T1, a high-level potential (V Ｈｉｇｈ After that, in a period T2, a read potential (V Ｒｅａｄ It is stated that V Ｒｅａｄ is V Ｌｏｗ Higher than V Ｈｉｇｈ (a potential lower than that of the

[0185] During the period T3, the amount of current flowing between the source and drain of the transistor MN is determined by the data ("0" or "1") written in the memory element MC. For example, the gate-source voltage of the transistor MN at this time is V Ｒｅａｄ -V Ｌｏｗ6B, when the data written to the memory element MC is "1" (when the transistor MN has the characteristic D1), a current of ID1 flows between the source and drain of the transistor MN. When the data written to the memory element MC is "0" (when the transistor MN has the characteristic D0), almost no current flows between the source and drain of the transistor MN.

[0186] When the data written to the memory element MC is "1", a current of ID1 flows between the source and drain of the transistor MN according to the characteristic D1 shown in FIG. 6B. As a result, when the potential of the wiring BL is V Ｈｉｇｈ From V １ 6C, the change in the potential of the wiring BL after the period T2 when the data written to the memory element MC is "1" is indicated by a solid line.

[0187] When the data written to the memory element MC is “0”, the characteristic D0 shown in FIG. 6B indicates that almost no current flows between the source and drain of the transistor MN. Therefore, the potential of the wiring BL is V Ｈｉｇｈ 6C, the change in the potential of the wiring BL after the period T2 when the data written to the memory element MC is "0" is indicated by a thick dashed line.

[0188] Depending on the characteristic D0, a current smaller than ID1 may flow. For example, when the characteristic D0 is the characteristic D0A shown in FIG. 6B, the gate-source voltage of the transistor MN is V Ｒｅａｄ -V Ｌｏｗ As a result, a current of ID0A flows through the transistor MN. At this time, the potential of the wiring BL is V Ｈｉｇｈ From V ０ The potential V ０ is the potential V １ 6C, the change in the potential of the wiring BL in the case of the characteristic D0A after the period T2 is indicated by a dashed line.

[0189] A potential V for reading is applied to the wiring WL. ＲＥＡＤAfter applying the potential (V Ｈｉｇｈ , V １ or V ０ ) is amplified by the driving circuit BD, whereby the data written in the memory element MC can be read out.

[0190] For this reason, it is preferable that the driver circuit BD be provided with a sense amplifier for amplifying the potential of the wiring BL.

[0191] Incidentally, the read potential V applied to the wiring WL ＲＥＡＤ However, in the operation of the circuit that writes "1" to the memory element MC in FIG. 4A, V applied to the wiring WL Ｈｉｇｈ If the value is close to "0", when data is read from the memory element MC, the data may be rewritten to "1".

[0192] In this case, V ＣＮ V as a potential higher than ＣＮＨ It is preferable to shift the characteristic D0 and the characteristic D1 of the transistor MN to the negative side by applying V. This is equivalent to shifting the threshold voltage of each of the characteristic D0 and the characteristic D1 of the transistor MN to the negative side. By shifting each of the characteristic D0 and the characteristic D1 of the transistor MN to the negative side, the potential required for reading to be applied to the wiring WL can be increased to V. ＲＥＡＤ As a result, the potential for reading and the V applied to the wiring WL, which have been described in the operation of the circuit for writing "1" to the memory element MC in FIG. Ｈｉｇｈ Since the potential difference between the positive and negative potentials is large, when data is read from the memory element MC, the data can be prevented from being rewritten to "1".

[0193] The above-mentioned specific operation will be described below with reference to FIGS. 7A to 7C.

[0194] Fig. 7A is a circuit diagram similar to Fig. 6A, showing the memory element MC and its peripheral wiring from Fig. 3, and the potential level of the wiring is also indicated. Fig. 7B is a schematic diagram similar to Fig. 6B, showing the characteristics of the gate-source voltage (VGS) and drain current (ID) of the transistor MN. Fig. 7C is a timing chart similar to Fig. 6C, showing an example of a read operation in the memory element MC.

[0195] The timing chart of Fig. 7C is a modified example of the timing chart of Fig. 6C, so for the contents of the timing chart of Fig. 7C that are similar to those of the timing chart of Fig. 6C, the description of the timing chart of Fig. 6C can be referred to.

[0196] When data is read from the memory element MC, first, V ＣＮ V as a potential higher than ＣＮＨ As a result, the characteristic D1 of the transistor MN shifts to the negative side and becomes a characteristic D1sh, as shown in FIG. 7B. Also, the characteristic D0 of the transistor MN shifts to the negative side and becomes a characteristic D0sh, as shown in FIG.

[0197] In addition, before the period T1, a low-level potential (V Ｌｏｗ Next, in the period T1, a high-level potential (V Ｈｉｇｈ After that, in a period T2, a potential for reading is applied to the wiring WL. Ｒｅａｄ potential V Ｒｅａｄｓｈ Also, the potential V Ｒｅａｄｓｈ is a potential at which the source-drain current of the transistor MN becomes ID1 in the characteristic D1sh. In other words, by shifting the characteristic D1 to the negative side to the characteristic D1sh, the amount of source-drain current in the transistor MN becomes ID1, so that the required gate-source voltage is V Ｒｅａｄ -V Ｌｏｗ From V Ｒｅａｄｓｈ -V Ｌｏｗ decreases to.

[0198] During the period T3, the amount of current flowing between the source and drain of the transistor MN is determined by the data ("0" or "1") written in the memory element MC. For example, the gate-source voltage of the transistor MN at this time is V Ｒｅａｄｓｈ -V Ｌｏｗ 7B, when the data written to the memory element MC is "1" (when the transistor MN has the characteristic D1sh), a current of ID1 flows between the source and drain of the transistor MN. When the data written to the memory element MC is "0" (when the transistor MN has the characteristic D0sh), almost no current flows between the source and drain of the transistor MN.

[0199] When the data written to the memory element MC is "1", a current of ID1 flows between the source and drain of the transistor MN in accordance with the characteristic D1sh shown in FIG. 7B. As a result, in FIG. 7C, the potential of the wiring BL is V Ｈｉｇｈ From V １ 7C, the change in the potential of the wiring WL after the period T2 when the data written to the memory element MC is "1" is indicated by a solid line.

[0200] When the data written to the memory element MC is “0”, the characteristic D0sh shown in FIG. 7B indicates that almost no current flows between the source and drain of the transistor MN. Therefore, the potential of the wiring BL is V Ｈｉｇｈ 7C, the change in the potential of the wiring BL after the period T2 when the data written to the memory element MC is "0" is indicated by a thick dashed line.

[0201] 7B, the characteristic D0 of the transistor MN is the same as the characteristic D0A of FIG. 6B, when the gate-source voltage of the transistor MN is V Ｒｅａｄ -V Ｌｏｗ 6C, the amount of source-drain current may be ID0A (not shown). Ｈｉｇｈ From V ０7C, the change in the potential of the wiring BL in the case of the above characteristics after the period T2 is indicated by a dashed line.

[0202] A potential V for reading is applied to the wiring WL. ＲＥＡＤ After applying the potential (V Ｈｉｇｈ , V １ or V ０ ) is amplified by the driving circuit BD, whereby the data written in the memory element MC can be read out.

[0203] The wiring BGL may function as a selection signal line for selecting a memory element MC to be read from, that is, the driver circuit BGD in FIG.

[0204] For example, consider a configuration in which memory elements MC[1] and MC[2] are arranged in the same column, as shown in FIG. 8A. Each of the memory elements MC[1] and MC[2] includes a transistor MN[1] and a transistor MN[2], which are FeFETs. The gate of the transistor MN[1] is connected to a wiring WL[1] corresponding to the wiring WL in FIG. 7A. The back gate of the transistor MN[1] is connected to a wiring BGL[1] corresponding to the wiring BGL in FIG. 7A. The gate of the transistor MN[2] is connected to a wiring WL[2] corresponding to the wiring WL in FIG. 7A. The back gate of the transistor MN[2] is connected to a wiring BGL[2] corresponding to the wiring BGL in FIG. 7A. The first terminals of the transistors MN[1] and MN[2] are connected to a wiring BL. The second terminals of the transistors MN[1] and MN[2] are connected to a wiring SL.

[0205] The gate-source voltage and source-drain current characteristics of the transistors MN[1] and MN[2] are represented by the characteristic D1 shown in FIG. 8B. At this time, the wirings BGL[1] and BGL[2] are connected to a potential V ＣＮ is assumed to be given.

[0206] Here, when only the memory element MC[1] is read, for example, a fixed potential V Ｌｏｗ is applied to the wiring BL, and a potential V Ｈｉｇｈ is precharged (operation in the period T1 in FIG. 7C). After that, the potential of the wiring BGL[1] is set to V ＣＮ From V ＣＮＨ and the potential of the wiring BGL[2] is changed to V ＣＮ From V ＣＮＬ It is changed to V ＣＮＬ is V ＣＮ As a result, the characteristic D1 of the transistor MN[1] shifts to the negative characteristic D1sh, and the characteristic D1 of the transistor MN[2] shifts to the positive characteristic D1shp.

[0207] The wiring WL[1] and the wiring WL[2] are each connected to a potential V Ｒｅａｄｓｈ At this time, as shown in FIG. 8B, the gate-source voltages of the transistors MN[1] and MN[2] are V Ｒｅａｄｓｈ -V Ｌｏｗ Furthermore, since the threshold voltage of the characteristic D1sh is lower than that of the characteristic D1, a current of ID1 flows between the source and drain of the transistor MN[1]. On the other hand, since the threshold voltage of the characteristic D1shp is higher than that of the characteristic D1, no current flows between the source and drain of the transistor MN[2]. Through the above operation, the memory element MC[1] can be selected from the memory elements MC[1] and MC[2], and the data read from the memory element MC[1] can be transmitted to the wiring BL.

[0208] 1A to 1C, which is included in the memory element MC, it is possible to reduce the parasitic capacitance between the gate electrode and the back gate electrode, the parasitic capacitance between the conductive layers ME1 and ME3 extending in the X direction, and the parasitic capacitance between the conductive layers ME2 and ME5 extending in the Y direction, etc. This makes it possible to increase the speed of the above-mentioned operation of the memory element MC.

[0209] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0210] Embodiment 2 In this embodiment, a manufacturing method of the transistor MN included in the memory element MC described in the above embodiment will be described. Note that an example of this manufacturing method will be described with reference to FIGS.

[0211] <Fabrication Method Example 1> In Figures 9A to 32C, (A) in each figure is a schematic plan view. Also, (B) in each figure is a schematic cross-sectional view corresponding to the portion of the dashed-dotted line A1-A2 shown in each (A). Also, (C) in each figure is a schematic cross-sectional view corresponding to the portion of the dashed-dotted line A3-A4 shown in each (A). Note that in the schematic plan view (A) in each figure, some elements are omitted for clarity. Also, Figures 33 and 34 are enlarged schematic cross-sectional views of the transistor MN shown in Figure 1B.

[0212] In the following, each of the insulating material for forming the insulating layer, the conductive material for forming the conductive layer, and the semiconductor material for forming the semiconductor layer can be formed by appropriately using a film formation method such as a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, or an atomic layer deposition (ALD) method.

[0213] First, a substrate (not shown) is prepared, and an insulating layer IS1 and a conductive film ME1v are formed in this order on the substrate (see FIGS. 9A to 9C).

[0214] The substrate can be, for example, a semiconductor substrate (e.g., a single-crystal substrate made of silicon or germanium). In addition to single-crystal substrates, other substrates that can be used include, for example, an SOI (Silicon-On-Insulator) substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate having stainless steel foil, a tungsten substrate, a substrate having tungsten foil, a flexible substrate, a laminated film, paper containing a fibrous material, or a base film. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, and soda-lime glass. Examples of flexible substrates, laminated films, and base films include plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Another example is a synthetic resin such as an acrylic resin. Other examples include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride. Other examples include polyamide, polyimide, aramid, epoxy resin, inorganic vapor deposition film, and paper. When the manufacturing method includes a heat treatment, it is preferable to select a substrate with high heat resistance. Alternatively, a circuit element may be provided on one of these substrates. Examples of the circuit element include a capacitance element, a resistance element, a switching element, a light-emitting element, and a memory element.

[0215] For example, the insulating layer IS1 functions as a base film for forming the transistor MN thereon, and also functions as an interlayer film that separates a circuit or the like from the memory element MC above the insulating layer IS1 when a circuit or the like is located below the insulating layer IS1.

[0216] The insulating layer IS1 can be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride. Other materials that can be used for the insulating layer IS1 include, for example, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, or silicon oxide with vacancies. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, or silicon oxide with vacancies are particularly preferred because they can easily form regions containing oxygen that are released by heating. Alternatively, the insulating layer IS1 can be made of, for example, a resin. The material used for the insulating layer IS1 can be an appropriate combination of the insulating materials described above. The insulating layer IS1 can be a single layer or a stacked structure obtained by sequentially depositing two or more layers of insulating materials.

[0217] In this specification and elsewhere, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0218] Furthermore, it is preferable to use an insulating material with a low relative dielectric constant for the insulating layer IS1. By using an insulating material with a low relative dielectric constant as an interlayer film, it is possible to reduce the parasitic capacitance that occurs between wirings. Specifically, for example, the relative dielectric constant of the insulating layer IS1 is preferably less than 4, and more preferably less than 3. Examples of insulating materials with a low relative dielectric constant include silicon oxide, silicon oxynitride, and silicon nitride oxide.

[0219] As described above, the insulating layer IS1 may be a single layer, or may have a laminated structure obtained by sequentially depositing two or more layers of insulating material. When the insulating layer IS1 has two or more layers of insulating material, at least one of the layers may be a barrier insulating film. Note that the barrier insulating film may be made of the same material as the insulating layers BI1 to BI6 shown in FIGS. 1A to 1C. Note that materials that can be used for any one of the insulating layers BI1 to BI6 will be described later.

[0220] For the barrier insulating film, in order to prevent oxidation of the conductive layer ME1 to be formed later, it is preferable to use, as an example, an insulating material that has a function of suppressing the diffusion of oxygen (for example, one or both of oxygen atoms and oxygen molecules) (the oxygen is less likely to permeate). In addition, in order to prevent the diffusion of impurities from below the barrier insulating film to the transistor MN above the barrier insulating film, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (for example, N ２ O, NO or NO ２ It is preferable to use an insulating material that has a function of suppressing the diffusion of impurities such as copper atoms (that is, an insulating material through which the impurities are less likely to penetrate).

[0221] As a barrier insulating film having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen, for example, an insulator containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum can be used, in a single layer or a stacked layer. Specifically, examples of insulators having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Furthermore, examples of insulators having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen include oxides containing aluminum and hafnium (hafnium aluminate). Furthermore, examples of insulators having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen include nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0222] In particular, it is preferable to use aluminum oxide or silicon nitride for the barrier insulating film, which can prevent impurities such as water and hydrogen from diffusing from below the insulating layer IS1 into the transistor MN.

[0223] The conductive film ME1v is a film that will become the conductive layer ME1 in a later process. A portion of the conductive layer ME1 functions as either the source or the drain of the transistor MN. A portion of the conductive layer ME1 functions as wiring connected to either the source or the drain of the transistor MN. For this reason, it is preferable to use a highly conductive material for the conductive film ME1v.

[0224] For the conductive film ME1v, it is preferable to use, for example, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy containing two or more selected from the above-mentioned metal elements, or an alloy combining two or more selected from the above-mentioned metal elements. Alternatively, it is preferable to use, for example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel. Tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen. Furthermore, the conductor may be, for example, a semiconductor with high electrical conductivity, typified by polycrystalline silicon containing an impurity element (e.g., phosphorus or arsenic), or a silicide (e.g., nickel silicide).

[0225] Furthermore, a plurality of conductive films formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element with a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element with a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element with a conductive material containing oxygen and a conductive material containing nitrogen.

[0226] 9B and 9C, the conductive film ME1v may have a stacked structure including a conductive film ME1av, a conductive film ME1bv, and a conductive film ME1cv. The conductive film ME1av will become the conductive layer ME1a in a later process, the conductive film ME1bv will become the conductive layer ME1b in a later process, and the conductive film ME1cv will become the conductive layer ME1c in a later process.

[0227] For the conductive film ME1av and the conductive film ME1cv, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, or ruthenium oxide, which are conductive materials that have the function of suppressing oxygen diffusion. Also, for the conductive film ME1bv, it is preferable to use, for example, a conductive material containing, as a main component, highly conductive tungsten, copper, or aluminum.

[0228] By sandwiching the highly conductive conductive film ME1bv between the conductive films ME1av and ME1cv, which are made of a conductive material that has the function of suppressing oxygen diffusion, it is possible to prevent a decrease in the conductivity of the conductive film ME1bv due to oxidation.

[0229] Furthermore, the conductive film ME1cv preferably functions as a stopper film in, for example, an etching process used when forming the openings KK1, KK2, and KK3 described later. For example, when the opening KK1 is formed by an etching process, it is preferable to select a material for the conductive film ME1cv so that the etching rate of the conductive film ME1cv is lower than that of the insulating films BI1v, IS2v, BI2v, ME2w, BI3v, and IS3v described later. In addition to the above, when the opening KK2 is formed by an etching process, it is preferable to select a material for the conductive film ME1cv so that the etching rate of the conductive film ME1cv is lower than that of the insulating films BGI1v, BI4v, and ME4v described later. In addition to the above, when the opening KK3 is formed by an etching process, it is preferable to select a material for the conductive film ME1cv so that the etching rate of the conductive film ME1cv is lower than that of the insulating film BI5v and the sacrificial layer DGv described later.

[0230] Next, the conductive film ME1v is processed into a strip shape by lithography so that a part of the insulating layer IS1 is exposed, thereby forming the conductive film ME1w (see FIGS. 10A to 10C). Note that FIGS. 10B and 10C show an example in which the conductive film ME1av is processed into the strip shape as the conductive film ME1aw, the conductive film ME1bv is processed into the strip shape as the conductive film ME1bw, and the conductive film ME1cv is processed into the strip shape as the conductive film ME1cw.

[0231] In particular, in this manufacturing method, as an example, the conductive film ME1w is formed to extend in a direction parallel to the dashed dotted line A1-A2 (X direction). The above processing can be performed by dry etching or wet etching.

[0232] In this specification, the lithography method includes, for example, photolithography, ion beam lithography, X-ray lithography, electron beam lithography, multiphoton lithography, interference lithography, and nanoimprinting.

[0233] In addition, in lithography, a resist is first exposed through a mask. Next, the exposed region is removed or left using a developer to form a resist mask. Next, a conductor, semiconductor, insulator, or the like can be processed into a desired shape by etching through the resist mask. For example, a resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. An immersion technique may also be used, in which a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. Alternatively, an electron beam or ion beam may be used instead of the light described above. In particular, when an electron beam or ion beam is used, a mask is not required, thereby reducing the cost of manufacturing a semiconductor device. The resist mask can be removed by dry etching such as ashing, wet etching, dry etching followed by wet etching, or wet etching followed by dry etching.

[0234] Furthermore, a hard mask made of an insulating film, a conductive film, a semiconductor film, or a combination thereof may be used under the resist mask. When using a hard mask, an insulating film or a conductive film that serves as the hard mask material is formed on the conductive film ME1v, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask of a desired shape. Etching of the conductive film ME1v or the like may be performed after removing the resist mask, or may be performed while leaving the resist mask in place. In the latter case, the resist mask may be lost during etching. The hard mask may be removed by etching after etching the conductive film ME1v or the like. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, it is not necessarily necessary to remove the hard mask.

[0235] Furthermore, by using a dry etching method or a wet etching method, a recess (sometimes referred to as a countersink) may be formed in an area that does not overlap with the processed insulating layer, conductive layer, and semiconductor layer. For example, in Figures 10A to 10C, a recess may be formed in an area on the top surface of the insulating layer IS1 that does not overlap with the conductive film ME1w. Note that, unless otherwise specified, this specification does not mention the formation of such a recess by a dry etching method or a wet etching method.

[0236] Furthermore, unless otherwise specified, the above content can be referenced for the lithography method used in the subsequent manufacturing methods.Similarly, unless otherwise specified, the above content can be referenced for the etching method (including dry etching and wet etching) used in the subsequent manufacturing methods.

[0237] Next, an insulating film to be the insulating film BI1v and an insulating film to be the insulating film IS2v are formed in this order on the insulating layer IS1 and the conductive film ME1w. Thereafter, a planarization process such as chemical mechanical polishing (CMP) is performed on the insulating film to be the insulating film IS2v, and the upper surface of the insulating film to be the insulating film IS2v is planarized to form the insulating film IS2v (see FIGS. 11A to 11C).

[0238] The insulating film BI1v is an insulating film that will become the insulating layer BI1 in a later process. The insulating layer BI1 also functions as a barrier insulating film. Therefore, for example, in order to prevent oxidation of the conductive layer ME1, it is preferable to use an insulating material that has a function of suppressing the diffusion of oxygen (e.g., oxygen atoms and / or oxygen molecules) (i.e., oxygen is less likely to permeate) for the barrier insulating film. Furthermore, in order to prevent the diffusion of impurities from below the barrier insulating film to the transistor MN above the barrier insulating film, it is preferable to use an insulating material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms (i.e., impermeability of the impurities).

[0239] Examples of barrier insulating films capable of suppressing the permeation of impurities such as water and hydrogen and oxygen include, for example, a single layer or a stack of insulators containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, examples of insulators capable of suppressing the permeation of impurities such as water and hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Examples of insulating films capable of suppressing the permeation of impurities such as water and hydrogen and oxygen include oxides containing aluminum and hafnium (hafnium aluminate). Examples of insulating films capable of suppressing the permeation of impurities such as water and hydrogen and oxygen include nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0240] In particular, it is preferable to use aluminum oxide or silicon nitride for the barrier insulating film, which can suppress the diffusion of impurities such as water and hydrogen from below the insulating layer IS1 to the transistor MN, and can also suppress the diffusion of oxygen from the insulating layer IS2v to the conductive film ME1w.

[0241] The insulating film IS2v is a film that will become the insulating layer IS2 in a later process. Furthermore, the insulating layer IS2 functions, for example, as an interlayer film that separates the conductive layer ME1 from a conductive layer ME2 described later. Therefore, the insulating film IS2v preferably has an insulating material with a low relative dielectric constant. By using an insulating material with a low relative dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced. Therefore, for example, a material or configuration that can be applied to the insulating layer IS1 can be used for the insulating film IS2v.

[0242] Next, an insulating film BI2v and a conductive film ME2v are formed in this order on the insulating film IS2v (see FIGS. 12A to 12C). Thereafter, the conductive film ME2v may be subjected to a planarization process such as CMP to flatten the upper surface of the conductive film ME2v.

[0243] The insulating film BI2v is a film that will become the insulating layer BI2 in a later process. The insulating layer BI2 also functions as a barrier insulating film. Therefore, for example, in order to prevent oxidation of the conductive layer ME2, it is preferable to use an insulating material for the barrier insulating film that has a function of suppressing oxygen diffusion (that is, the oxygen is less likely to permeate) For this reason, for example, a material or configuration that can be applied to the insulating layer BI1 can be used for the insulating film BI2v.

[0244] The conductive film ME2v is a film that will become the conductive layer ME2 in a later process. A portion of the conductive layer ME2 functions as the back gate of the transistor MN. A portion of the conductive layer ME2 functions as wiring connected to the back gate of the transistor MN. Therefore, it is preferable to use a highly conductive material for the conductive film ME2v. Therefore, for example, a material or configuration that can be applied to the conductive layer ME1 can be used for the conductive film ME2v.

[0245] Next, the conductive film ME2v is processed into a strip shape using lithography so that a portion of the insulating film BI2v is exposed, thereby forming the conductive film ME2w (see FIGS. 13A to 13C). In particular, in this manufacturing method, as an example, the conductive film ME2w is formed so as to have an area overlapping with the conductive film ME1w and to extend in a direction parallel to the dashed-dotted line A3-A4 (the Y direction). Furthermore, the above processing can be performed using a dry etching method or a wet etching method.

[0246] Next, an insulating film to be the insulating film BI3v and an insulating film to be the insulating film IS3v are formed in this order on the insulating layer BI2v and the conductive film ME2w. Thereafter, a planarization process such as a CMP method is performed on the insulating film to be the insulating film IS3v, and the upper surface of the insulating film to be the insulating film IS3v is planarized to form the insulating film IS3v (see FIGS. 14A to 14C).

[0247] The insulating film BI3v is a film that will become the insulating layer BI3 in a later process. The insulating layer BI3 also functions as a barrier insulating film. Therefore, for example, in order to prevent oxidation of the conductive layer ME2, it is preferable to use an insulating material for the barrier insulating film that has a function of suppressing oxygen diffusion (i.e., that the oxygen is less likely to permeate). Therefore, for example, a material or configuration applicable to the insulating layer BI1 or the insulating layer BI2 can be used for the insulating film BI3v.

[0248] The insulating film IS3v is a film that will become the insulating layer IS3 in a later process. Furthermore, the insulating layer IS3 functions, for example, as an interlayer film that separates the conductive layer ME2 from a conductive layer ME3 described later. Therefore, the insulating film IS3v preferably has an insulating material with a low relative dielectric constant. By using an insulating material with a low relative dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced. Therefore, for example, a material or configuration that can be applied to the insulating layer IS1 or the insulating layer IS2 can be used for the insulating film IS3v.

[0249] Next, the conductive film ME1w, insulating film BI1v, insulating film IS2v, insulating film BI2v, conductive film ME2w, insulating film BI3v, and insulating film IS3v are processed using lithography to form the conductive film ME1x, insulating layer BI1, insulating layer IS2, insulating layer BI2, conductive layer ME2, insulating layer BI3, and insulating layer IS3 (see FIGS. 15A to 15C). Each of the conductive film ME1x, insulating layer BI1, insulating layer IS2, insulating layer BI2, conductive layer ME2, insulating layer BI3, and insulating layer IS3 has an opening KK1 formed by the lithography. The opening KK1 is formed in the region where the conductive film ME1x and the conductive film ME2w overlap. The above processing can be performed using dry etching or wet etching, with dry etching being particularly suitable for fine processing. That is, when the area of ​​the opening KK1 in plan view is to be reduced, it is preferable to use the dry etching method for the above processing.

[0250] 15B and 15C, the opening KK1 is formed so that the upper surface of the conductive film ME1x becomes the bottom of the opening KK1. At this time, in the opening KK1, the conductive film ME1x has a recessed portion on its upper surface.

[0251] In some cases, the opening KK1 may be formed so as to expose the upper surface of the conductive film ME1x and the upper surface of the insulating layer IS1 (not shown). Specifically, in the cross-sectional view of FIG. 15C , the width of the opening KK1 may be made larger than the width of the conductive film ME1x, so that the opening KK1 reaches the insulating layer IS1.

[0252] 15A to 15C, the opening KK1 has a tapered shape with a taper angle that is perpendicular or approximately perpendicular (60 degrees or more and 120 degrees or less) to the conductive layer ME1, the insulating layer BI1, or the substrate (not shown), as an example. Alternatively, the opening KK1 may have a tapered shape with a taper angle that is 30 degrees or more and less than 70 degrees, or a taper angle that is greater than 0 degrees and less than 30 degrees, as an example, to the conductive layer ME1, the insulating layer BI1, or the substrate.

[0253] 15A , the opening KK1 may have a circular shape, a curved shape (e.g., an ellipse, a cloud shape, a triangle with rounded corners, a polygon such as a square or a pentagon, etc.), a cornered shape (e.g., a triangle, a polygon such as a square or a pentagon, etc.), or a combination thereof.

[0254] Furthermore, by making the shape of the opening KK1 in a planar view one of the shapes listed above or a combination of the shapes listed above, it may be possible to lengthen the periphery of the opening KK1 in a planar view. By lengthening the periphery of the opening KK1 in a planar view, it is possible to increase the area of ​​the region where the semiconductor layer SC1, insulating layer BGI1, and conductive layer ME4 (described later) are stacked, thereby increasing the gate capacitance of the transistor MN. By increasing the gate capacitance of the transistor MN., it is possible to increase the amount of electrostatic polarization, thereby enabling the logic of "0" and "1" held by the memory element MC to be accurately read.

[0255] Furthermore, by-products generated in the etching step may be formed on the side surfaces of the opening KK1 (the side surfaces of the insulating layers BI1, IS2, BI2, conductive layer ME2, BI3, and IS3). In this case, the by-products are formed between the side surfaces of the opening KK1 and the insulating layer BGI1, which will be described later. Therefore, it is preferable to remove the by-products formed in contact with the side surfaces of the opening KK1.

[0256] Next, the insulating film BGI1v is formed on the bottom and side surfaces of the opening KK1 and on the upper surface of the insulating layer IS3 (see FIGS. 16A to 16C ). Specifically, in the opening KK1, the insulating film BGI1v is formed so as to be in contact with each of the conductive film ME1x, the insulating layer BI1, the insulating layer IS2, the insulating layer BI2, the conductive layer ME2, the insulating layer BI3, and the insulating layer IS3. Furthermore, outside the opening KK1, the insulating film BGI1v is formed on the upper surface of the insulating layer IS3.

[0257] The insulating film BGI1v can be formed using a film formation method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In particular, as shown in FIGS. 16B and 16C , the insulating film BGI1v needs to be formed with good coverage on the bottom and side surfaces of the opening KK1, and therefore, it is preferable to form the insulating film BGI1v using the ALD method. The ALD method is a film formation method in which a precursor and a reactant (e.g., an oxidizer) are alternately introduced, and the film thickness can be adjusted by the number of times this cycle is repeated, thereby enabling precise film thickness adjustment. Examples of the ALD method include a thermal ALD method in which the reaction between the precursor and the reactant is carried out using only thermal energy, and a plasma ALD (PEALD: Plasma Enhanced ALD) method in which a plasma-excited reactant is used. By using the ALD method, atomic layers can be deposited one by one on the bottom and side surfaces of the opening KK1, and therefore the insulating film BGI1v can be formed with good coverage on the bottom and side surfaces of the opening KK1.

[0258] When the taper angle of the side surface of the opening KK1 is less than 90 degrees, the insulating film BGI1v can be formed by, for example, ALD, sputtering, etc. The sputtering method can achieve a faster film formation rate than the ALD method, and therefore can shorten the takt time of the semiconductor device.

[0259] The insulating film BGI1v is a film that will become the insulating layer BGI1 in a later process. Furthermore, a portion of the insulating layer BGI1 functions as the second gate insulating film of the transistor MN. Therefore, it is preferable that the insulating film BGI1v function as a barrier insulating film that suppresses the diffusion of impurities such as water or hydrogen, or oxygen. For example, the insulating film BGI1v functions as a barrier insulating film that suppresses the impurities, thereby preventing the diffusion of the impurities from the insulating layer IS2 and the insulating layer IS3 to the semiconductor layer SC1, which will be described later. Furthermore, for example, the insulating film BGI1v functions as a barrier insulating film that suppresses the diffusion of oxygen, thereby preventing the diffusion of oxygen from the semiconductor layer SC1 to the insulating layer IS2 or the insulating layer IS3.

[0260] Furthermore, since a portion of the insulating layer BGI1 functions as a second gate insulating film of the transistor MN, it is preferable that the insulating film BGI1v includes, for example, an insulating layer containing a high-k material. As transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulating films. By using a high-k material as the insulator that functions as the gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0261] From the above, the insulating film BGI1v may be made of, for example, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ３ ), or (Ba,Sr)TiO ３ It is preferable to use an insulator containing a so-called high-k material such as (BST) in a single layer or a laminated layer.

[0262] In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials that have the function of suppressing the diffusion of impurities, oxygen, etc. (the impurities, oxygen, etc. are less likely to permeate.) As the insulator containing an oxide of one or both of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc.

[0263] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulators. This allows the insulating film BGI1v to be a film that further suppresses the diffusion of impurities, oxygen, and the like.

[0264] Depending on the situation, the insulating film BGI1v may be made of a material or have a structure that can be applied to any one of the insulating layers BI1 to BI6.

[0265] The insulating film BGI1v is preferably thermally stable, for example, silicon oxide and silicon oxynitride are suitable because they are thermally stable.

[0266] The insulating film BGI1v may be formed by stacking insulating materials having different functions to form an insulating layer having those functions. For example, by combining a high-k insulator with silicon oxide or silicon oxynitride, it is possible to obtain the insulating film BGI1v having a thermally stable stacked structure with a high dielectric constant.

[0267] Although the insulating film BGI1v is shown as a single layer in FIGS. 16B and 16C, the insulating film BGI1v may have a laminated structure using a plurality of the above materials.

[0268] Next, using lithography, anisotropic etching, planarization, and the like, the insulating film BGI1v is processed so that a portion of the conductive film ME1x and a portion of the insulating layer IS3 are exposed (see FIGS. 17A to 17C). Through this process, the insulating film BGI1v is processed into a cylindrical shape that conforms to the side surface of the opening KK1 as the insulating layer BGI1. Also, in FIGS. 17B and 17C, this process may result in a recess being formed in the conductive film ME1x located at the bottom of the opening KK1, resulting in the conductive film ME1y. That is, in the opening KK1, the recess in the conductive film ME1y may be formed deeper than the recess in the conductive film ME1x due to the processing of the insulating film BGI1v.

[0269] Furthermore, since the insulating film BGI1v is processed into a cylindrical shape along the side surface of the opening KK1 as the insulating layer BGI1, the insulating layer BGI1 has an opening in a region overlapping with the conductive film ME1y. In this specification, this opening will be described as being included in the opening KK2 described later.

[0270] Next, an insulating film BI4v and a conductive film ME3v are formed in this order on the insulating layer IS3, the insulating layer BGI1, and the conductive layer ME1y, including the opening KK1 (see FIGS. 18A to 18C). Specifically, in the opening KK1, the insulating film BI4v is formed so as to contact the insulating layer BGI1 and the conductive film ME1y, respectively, and outside the opening KK1, the insulating film BI4v is formed so as to contact the insulating layer BGI1 and the insulating layer IS3, respectively. Furthermore, the conductive film ME3v is formed on the insulating film BI4v so as to fill the opening KK1.

[0271] The insulating film BI4v is a film that will become the insulating layer BI4 in a later process. The insulating layer BI4 also functions as a barrier insulating film. Therefore, for example, in order to prevent oxidation of the conductive layer ME3, it is preferable to use an insulating material for the barrier insulating film that has the function of suppressing oxygen diffusion from the insulating layer IS3 (i.e., that the oxygen is less likely to permeate through). Therefore, for example, a material or configuration that can be applied to any one of the insulating layers BI1 to BI6 can be used for the insulating film BI4v.

[0272] The conductive film ME3v is a film that will become the conductive layer ME3 in a later process. A portion of the conductive layer ME3 functions as the other of the source or drain of the transistor MN. A portion of the conductive layer ME3 functions as wiring connected to the other of the source or drain of the transistor MN. Therefore, it is preferable to use a highly conductive material for the conductive film ME3v. Therefore, for example, a material or configuration applicable to the conductive layer ME1 or the conductive layer ME2 can be used for the conductive film ME3v.

[0273] Furthermore, the conductive layer ME3 preferably functions as a stopper film for, for example, an etching process used when forming the opening KK3 described later. For example, when the opening KK3 is formed by an etching process, it is preferable to select a material for the conductive layer ME3 so that the etching rate of the conductive layer ME3 is lower than that of the insulating film BI5v and the sacrificial layer DGv described later.

[0274] 18B and 18C , the insulating film BI4v and the conductive film ME3v are formed in this order on the side surface of the insulating layer BGI1 in the opening KK1, but the insulating film BI4v and the conductive film ME3v formed inside the opening KK1 are removed by the formation of the opening KK2, and therefore the coverage of the insulating film BI4v on the insulating layer BGI1 and the coverage of the conductive film ME3v on the insulating film BI4v do not need to be high. Therefore, each of the insulating film BI4v and the conductive film ME3v may be formed by, for example, a sputtering method instead of the ALD method.

[0275] After the conductive film ME3v is formed, the conductive film ME3v may be subjected to a planarization process such as CMP to planarize the upper surface of the conductive film ME3v.

[0276] Next, the conductive film ME1y, insulating film BI4v, and conductive film ME3v are processed using lithography to form conductive layer ME1, insulating layer BI4, and conductive film ME3w (see FIGS. 19A to 19C). Each of the conductive layer ME1, insulating layer BI4, and conductive film ME3w has an opening KK2 formed by the lithography. The opening KK2 is formed in a region where the conductive layer ME1, conductive layer ME2, and conductive film ME3w overlap. The above processing can be performed using dry etching or wet etching.

[0277] 19B and 19C, the opening KK2 is formed so that the top surface of the conductive layer ME1 becomes the bottom of the opening KK2. At this time, the conductive film ME1 has a recess on its top surface at the opening KK2. Furthermore, the recess in the conductive layer ME1 created by the formation of the opening KK2 may be deeper than the recess in the conductive layer ME1 created by the formation of the opening KK1.

[0278] In this specification, the opening of the conductive layer BGI1 provided in the region overlapping the conductive layer ME1y by the steps of FIGS. 17A to 17C is also described as being included in the opening KK2.

[0279] Next, the conductive film ME3w is processed into a strip shape using lithography to form the conductive layer ME3. In particular, in this manufacturing method, as an example, the conductive layer ME3 is formed to extend in a direction parallel to the dashed-dotted line A1-A2 (X direction) (see FIGS. 20A to 20C). Furthermore, the processing can be performed using a dry etching method or a wet etching method.

[0280] Next, an insulating film BI5v and a sacrificial layer DGv are formed in this order inside the opening KK2, on the upper surface of the insulating layer BI4, and on the upper surface of the conductive layer ME3 (see FIGS. 21A to 21C). Specifically, in the opening KK2, the insulating film BI5v is formed on the upper surface of the insulating layer BGI1 and the upper surface of the conductive layer ME1, and outside the opening KK2, the insulating film BI5v is formed on the upper surface of the insulating layer BI4 and the upper surface of the conductive layer ME3. Furthermore, the sacrificial layer DGv is formed on the upper surface of the insulating film BI5v so as to fill the opening KK2.

[0281] The insulating film BI5v is a film that will become the insulating layer BI5 in a later process. The insulating layer BI5 also functions as a barrier insulating film. Therefore, for example, in order to prevent oxidation of the conductive layer ME3, it is preferable to use an insulating material for the barrier insulating film that has the function of suppressing oxygen diffusion from the insulating layer IS4 (which is described later) (the oxygen is less likely to permeate). Therefore, for example, a material or configuration applicable to any one of the insulating layers BI1 to BI6 can be used for the insulating film BI5v.

[0282] The sacrificial layer DGv is a film that will become the sacrificial layer DGw in a later process, and the sacrificial layer DGw functions as a mask for forming the insulating layer IS4 described below. The sacrificial layer DGv can be made of an organic or inorganic material that can be formed by a coating method. Specifically, for example, the sacrificial layer DGv can be made of an insulating film that can be formed by a coating method, such as an SOC (spin on carbon) film or an SOG (spin on glass) film. The sacrificial layer DGv can also be made of a stacked structure of an SOC film and an SOG film on the SOC film. In addition to the coating method, an insulating film that can be formed by a sputtering method, a CVD method, or the like can also be used.

[0283] Next, the sacrificial layer DGv is processed using lithography to form a sacrificial layer DGw (see FIGS. 22A to 22C). The processing can be performed by dry etching or wet etching.

[0284] Next, an insulating film to be the insulating layer IS4 is formed on the insulating film BI5v and the sacrificial layer DGw. Thereafter, a planarization process such as a CMP method is performed on the insulating film to be the insulating layer IS4, and the upper surface of the insulating film to be the insulating film IS4 is planarized until the sacrificial layer DGw is exposed, thereby forming the insulating layer IS4 (see FIGS. 23A to 23C).

[0285] As an example, the insulating layer IS4 functions as a first interlayer film separating the conductive layer ME3 from a conductive layer ME5 described later. Therefore, the insulating film IS4 preferably has an insulating material with a low dielectric constant. By using an insulating material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced. Therefore, for example, the insulating film IS4 can be made of a material or configuration that can be applied to any one of the insulating layers IS1 to IS3.

[0286] Furthermore, the material used for the insulating layer IS4 may contain an element corresponding to the material contained in the semiconductor layer SC1 in order to increase the conductivity of the region of the semiconductor layer SC1 in contact with the insulating layer IS4. For example, if the semiconductor layer SC1 contains a metal oxide as an oxide semiconductor, the insulating layer IS4 preferably contains a metal element. In this case, a compound containing the metal element may be formed at or near the interface between the semiconductor layer SC1 and the insulating layer IS4. This compound may also be generated by heat treatment or the like. This reduces the resistance of the interface between the semiconductor layer SC1 and the insulating layer IS4 or its vicinity, thereby increasing the conductivity of the region of the semiconductor layer SC1 in contact with the insulating layer IS4. This is thought to be because some of the oxygen contained in the semiconductor layer SC1 reacts with the metal element in the insulating layer IS4, forming oxygen vacancies in that region of the semiconductor layer SC1, resulting in a lower resistance.

[0287] In this case, the insulating layer IS4 may be a nitride containing a metal element, an oxide containing a metal element, etc. Examples of the metal element include aluminum, magnesium, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. The metal element may also be a metal element contained in any one of the conductive layers ME1 to ME5.

[0288] Next, the sacrificial layer DGw is removed using lithography or the like. At this time, a portion of the conductive film BI5v located on the upper surface of the conductive layer ME3 is also removed, as well as the conductive film BI5v in contact with the conductive layer ME3, the insulating layer BI4, the insulating layer BGI1, and the conductive layer ME1 in the opening KK2. This processes the conductive film BI5v into the conductive layer BI5. The insulating layer IS4 and the conductive layer BI5 have an opening KK3 formed by the lithography. The opening KK3 is formed in the region where the conductive layer ME1, the conductive layer ME2, and the conductive layer ME3 overlap. The above processing can be performed using dry etching or wet etching.

[0289] 24B and 24C , the opening KK3 is formed by removing a portion of the conductive film BI5v, exposing a portion of the conductive layer ME3, and forming a bottom portion with a portion of the upper surface of the conductive layer ME3. Therefore, by this manufacturing method, the transistor MN is configured such that the insulating layer BI5 is not provided inside either the opening KK2 or the opening KK3.

[0290] Alternatively, the sacrificial layer DGw may first be removed by a cleaning process using a chemical solution such as a stripping solution or a developing solution, and then the exposed conductive film BI5v may be removed by using a lithography method or the like.

[0291] 24A to 24C, the opening KK3 has a tapered shape with a taper angle that is approximately perpendicular (60 degrees or more and 120 degrees or less) to the X-Y plane, similar to the opening KK1. Alternatively, the opening KK3 may have a tapered shape with a taper angle that is 30 degrees or more and less than 70 degrees, or a taper angle that is greater than 0 degrees and less than 30 degrees, relative to the X-Y plane.

[0292] Furthermore, when the opening KK3 is formed, the recess of the conductive film ME1 in the opening KK2 may be formed deeper than the recess in the steps of FIGS. 23A to 23C.

[0293] Next, a semiconductor film SC1v is formed on the side surfaces and bottom of the opening KK2, the side surfaces and bottom of the opening KK3, and the top surface of the insulating layer IS4 (see FIGS. 25A to 25C). Specifically, in the opening KK2, the semiconductor film SC1v is formed so as to contact the conductive layer ME1, the insulating layer BGI1, the insulating layer BI4, and the conductive layer ME3. In addition, in the opening KK3, the semiconductor film SC1v is formed so as to contact the conductive layer ME3, the insulating layer BI5, and the insulating layer IS4. In addition, outside the openings KK2 and KK3, the semiconductor film SC1v is formed on the top surface of the insulating layer IS4. The semiconductor film SC1v can be formed using a film formation method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. 25B and 25C , the semiconductor film SC1v is preferably formed using the ALD method because it needs to be formed with good coverage on the bottom and side surfaces of the opening KK2 and the opening KK3. By using the ALD method, atomic layers can be deposited one by one on the bottom and side surfaces of the opening KK2 and the opening KK3, and the conductive film can be formed with good coverage on the bottom and side surfaces of the opening KK2 and the opening KK3.

[0294] When the taper angle of the side surface of the opening KK2 or the opening KK3 is less than 90 degrees, the conductive film can be formed by, for example, ALD, sputtering, etc. The sputtering method can achieve a faster film formation rate than the ALD method, and therefore can shorten the takt time of the semiconductor device fabricated by this fabrication method.

[0295] Next, the semiconductor film SC1v is processed using lithography to form a semiconductor layer SC1 so that a portion of the upper surface of the insulating layer IS4 is exposed (FIGS. 26A to 26C). Note that the semiconductor layer SC1 is formed so as to include the region of the opening KK3 in the plan view of FIG. 26A, or so as not to expose the region of the opening KK3. Furthermore, the above processing can be performed using a dry etching method or a wet etching method.

[0296] 26A , when the semiconductor layer SC1 has a shape that includes the region of the opening KK3, the shape of the semiconductor layer SC1 can be an ellipse, a shape including a curve (e.g., an ellipse, a cloud shape, a triangle with rounded corners, a polygon such as a square or a pentagon), a shape with corners (e.g., a triangle, a polygon such as a square or a pentagon), or a combination thereof.

[0297] At this time, a part of the semiconductor layer SC1 functions as a channel formation region of the transistor MN formed in a later process. Note that in this embodiment, the semiconductor layer SC1 is described as including a metal oxide that functions as an oxide semiconductor. The semiconductor layer SC1 will be described in detail later.

[0298] Next, an insulating layer GF1 and a conductive film ME4v are formed in this order on the insulating layer IS4 and the semiconductor layer SC1 (see FIGS. 27A to 27C). The conductive film ME4v is formed on the upper surface of the insulating layer GF1 so as to fill the opening KK2.

[0299] The insulating layer GF1 functions as a first gate insulating film of the transistor MN. As described in the first embodiment, the insulating layer GF1 contains a material that may have ferroelectricity, and therefore the transistor MN is an FeFET.

[0300] Materials that can have ferroelectricity include hafnium oxide, zirconium oxide, and hafnium zirconium oxide (HfZrO Ｘ (where X is a real number greater than 0), and the element J is added to hafnium oxide. １ (Element J here １ refers to one or more elements selected from zirconium (Zr), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), and strontium (Sr), and zirconium oxide is doped with element J. ２ (Element J here ２ Examples of materials that can have ferroelectricity include materials to which one or more elements selected from hafnium (Hf), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), and strontium (Sr) are added. Ｘ Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate, may also be used. Furthermore, as a material that can have ferroelectricity, for example, a mixture or compound of a plurality of materials selected from the materials listed above may be used. Incidentally, hafnium oxide, zirconium oxide, zirconium hafnium oxide, and hafnium oxide containing element J may be used. １ The crystal structure (characteristics) of a material to which an ion beam is added may change depending not only on the film formation conditions but also on various processes. Therefore, in this specification, a material that exhibits ferroelectricity is not only called a ferroelectric but also called a material that can have ferroelectricity.

[0301] Among these, materials having hafnium oxide or materials having hafnium oxide and zirconium oxide are preferable as materials capable of exhibiting ferroelectricity, since they can exhibit ferroelectricity even in a thin film of a few nanometers. In this specification, a layer of a material capable of exhibiting ferroelectricity may be referred to as a ferroelectric layer or a metal oxide film.

[0302] Furthermore, the insulating layer GF1 can have a single layer structure or a multilayer structure. In particular, when the insulating layer GF1 has a multilayer structure, each insulating layer included in the insulating layer GF1 can be made of, for example, a high-k material that can be used for the insulating layer BGI1 and / or one or both of the above-mentioned materials that can have ferroelectricity.

[0303] From the viewpoint of the gate capacitance of the transistor MN, the thickness of the insulating layer GF1 is preferably 1 nm or more, 3 nm or more, or 5 nm or more, and 15 nm or less, 12 nm or less, or 10 nm or less.

[0304] The conductive film ME4v is a film that will become the conductive layer ME4 in a later process. A part of the conductive layer ME4 functions as the gate electrode of the transistor MN. Therefore, it is preferable to use a highly conductive material for the conductive film ME4v.

[0305] The conductive film ME4v can be made of, for example, a material or configuration that can be applied to the conductive layers ME1 to ME3.

[0306] Next, the conductive film ME4v is processed using lithography to form a conductive layer ME4 (see FIGS. 28A to 28C). In particular, the conductive layer ME4 is formed so as to overlap the inside of the region of the semiconductor layer SC1 in the plan view of FIG. 28A. In other words, the conductive layer ME4 is formed so that its end is located more inward than the end of the semiconductor layer SC1 in the cross-sectional views of FIGS. 28B and 28C. Furthermore, the above processing can be performed using a dry etching method or a wet etching method.

[0307] In a plan view, by forming the conductive layer ME4 only inside the region of the semiconductor layer SC1, the transistor MN can be configured so that the conductive layer ME4 is not provided in the step of the insulating layer GF1 caused by the semiconductor layer SC1. The step region of the insulating layer GF1 may have a thinner film thickness than other regions of the insulating layer GF1, so the conductive layer ME4 and the semiconductor layer SC1 may come into contact with each other in the step region of the insulating layer GF1, causing a short circuit. By configuring the transistor MN so that the conductive layer ME4 is not provided in the step of the insulating layer GF1, it is possible to prevent the conductive layer ME4 and the semiconductor layer SC1 from coming into contact with each other and causing a short circuit, and the yield of the transistor MN can be increased.

[0308] Furthermore, the regions of the upper surface of the conductive layer ME4 that overlap with the openings KK1 to KK3 may be formed deeper than the regions of the upper surface of the conductive layer ME4 that do not overlap with the opening KK2 and overlap with the opening KK3. In other words, the upper surface of the conductive layer ME4 may have recesses in the regions that overlap with the openings KK1 to KK3. By having the recesses in the conductive layer ME4, the contact area with the conductive layer ME5, which will be described later, can be increased, and the contact resistance between the conductive layer ME4 and the conductive layer ME5 can be reduced.

[0309] 28A , the conductive layer ME4 may have an elliptical shape, a curved shape (e.g., an ellipse, a cloud shape, a triangle with rounded corners, a polygon such as a square or a pentagon), a cornered shape (e.g., a triangle, a polygon such as a square or a pentagon), or a combination thereof, as long as the conductive layer ME4 has a shape that is included inside the region of the semiconductor layer SC1 in the plan view of FIG.

[0310] Next, an insulating film to be the insulating film IS5v is formed on the insulating layer GF1 and the conductive layer ME4. Thereafter, the insulating film to be the insulating film IS5v is subjected to a planarization process such as a CMP method to planarize the upper surface of the insulating film to be the insulating film IS5v, thereby forming the insulating film IS5v (see FIGS. 29A to 29C).

[0311] The insulating film IS5v is a film that will become the insulating layer IS5 in a later process. Furthermore, the insulating layer IS5, for example, functions as a second interlayer film that separates the conductive layer ME3 from the conductive layer ME5 described below. Therefore, the insulating film IS5v preferably contains an insulating material with a low dielectric constant. By using an insulating material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced. Therefore, the insulating film IS5v can be made of a material or configuration that can be applied to any one of the insulating layers IS1 to IS4, for example.

[0312] Next, the insulating film IS5v is processed using lithography to form an insulating layer IS5 (see FIGS. 30A to 30C). The insulating layer IS5 has an opening KK4 that is formed by the lithography and reaches the conductive layer ME4. Therefore, the opening KK4 is formed in a region that overlaps with the conductive layer ME4. The opening KK4 may also be formed in a region that overlaps with one or more of the openings KK1 to KK3. The above processing may be performed using dry etching or wet etching.

[0313] Furthermore, a recess may be formed by the lithography method in the conductive layer ME4 at the bottom of the opening KK4. Forming a recess in the conductive layer ME4 by the lithography method can also increase the contact area with the conductive layer ME5 described below, thereby reducing the contact resistance between the conductive layer ME4 and the conductive layer ME5.

[0314] 30A to 30C, the opening KK4 has a tapered shape with a taper angle that is approximately perpendicular (60 degrees or more and 120 degrees or less) to the X-Y plane, similar to the openings KK1 and KK3. Alternatively, the opening KK4 may have a tapered shape with a taper angle that is 30 degrees or more and less than 70 degrees, or a taper angle that is greater than 0 degrees and less than 30 degrees, relative to the X-Y plane.

[0315] Furthermore, by-products generated in the etching step may form a layer on the side surface of the opening KK4 (the side surface of the insulating layer IS5). In this case, the layer of by-products is formed between the side surface of the opening KK4 and the conductive layer ME5 described below. Therefore, it is preferable to remove the layer of by-products formed in contact with the side surface of the opening KK4.

[0316] Next, a conductive film ME5v is formed on the side and bottom of the opening KK4 and on the top surface of the insulating layer IS5 (see FIGS. 31A to 31C). Specifically, inside the opening KK4, the conductive film ME5v is formed so as to contact both the conductive layer ME4 and the insulating layer IS5. Outside the opening KK4, the conductive film ME5v is formed on the top surface of the insulating layer IS5. The conductive film ME5v can be formed using a film formation method such as sputtering, CVD, MBE, PLD, or ALD.

[0317] The conductive film ME5v is a film that will become the conductive layer ME5 in a later process. Furthermore, a portion of the conductive layer ME5 functions as wiring that is electrically connected to the gate of the transistor MN. Therefore, it is preferable to use a highly conductive material for the conductive film ME5v. For example, the conductive film ME5v can be made of a material or configuration that can be applied to any one of the conductive layers ME1 to ME4.

[0318] Similarly to the conductive film ME1v, the conductive film ME5v may be formed by stacking multiple conductive films made of the above materials. For example, as shown in Figures 31B and 31C, the conductive film ME5v may have a stacked structure including a conductive film ME5av and a conductive film ME5bv. The conductive film ME5av will become the conductive layer ME5a in a later process, and the conductive film ME1bv will become the conductive layer ME1b in a later process.

[0319] The conductive film ME5av is preferably made of a conductive material that has the function of suppressing oxygen diffusion, similar to the conductive layers ME1a and ME1c, and the conductive film ME5bv is preferably made of a conductive material with high conductivity, similar to the conductive layer ME1b.

[0320] By forming a highly conductive conductive film ME5bv on the upper surface of the insulating layer BI5 and the side surface of the insulating layer IS4 via the conductive film ME5av, which is a conductive material that has the function of suppressing the diffusion of oxygen, it is possible to prevent a decrease in the conductivity of the conductive film ME5bv due to oxidation.

[0321] 31B and 31C , the conductive film ME5av needs to be formed with good coverage on the bottom and side surfaces of the opening KK4, and therefore is preferably formed using the ALD method. By using the ALD method, atomic layers can be deposited one by one on the bottom and side surfaces of the opening KK4, and the conductive film ME5av can be formed with good coverage on the bottom and side surfaces of the opening KK4.

[0322] Furthermore, the conductive film ME5bv located on the conductive film ME5av is formed so as to fill the opening KK4, as shown in FIGS. 31B and 31C.

[0323] Next, the conductive film ME5v (conductive film ME5av and conductive film ME5bv) is subjected to a planarization process such as CMP until a portion of the insulating layer IS5 is exposed, thereby forming the conductive layer ME5 (conductive layer ME5a and conductive layer ME5b) (see FIGS. 32A to 32C). This allows the conductive layer ME5 (conductive layer ME5a and conductive layer ME5b) to be embedded in the opening KK4.

[0324] Next, an insulating film to become insulating layer BI6 and an insulating film to become insulating layer IS6 are formed in this order on insulating layer IS5 and conductive layer ME5. Thereafter, a planarization process such as CMP is performed on the insulating film to become insulating layer IS6, and the upper surface of the insulating film to become insulating layer IS6 is planarized to form insulating layer IS6 (see FIGS. 1A to 1C).

[0325] The insulating layer BI6 functions as a barrier insulating film. Therefore, for example, in order to prevent oxidation of the conductive layer ME5, it is preferable to use an insulating material for the barrier insulating film that has the function of suppressing the diffusion of oxygen from the insulating layer IS6 to the conductive layer ME6 (i.e., that the oxygen is less likely to permeate through). Furthermore, in order to prevent the diffusion of impurities from above the barrier insulating film to the transistor MN below the barrier insulating film, it is preferable to use an insulating material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms (i.e., that the impurities are less likely to permeate through). Therefore, for the insulating layer BI6, a material or configuration that can be applied to either the insulating layer BI1 or the insulating layer BI5 can be used.

[0326] As described in the first embodiment, the insulating layer IS6 functions as an interlayer film separating the conductive layer ME5 from the wiring, circuit elements, and the like above the insulating layer IS6. Therefore, the insulating layer IS6 preferably has an insulating material with a low dielectric constant. By using an insulating material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between the wiring can be reduced. For this reason, the insulating layer IS6 can be made of a material or configuration that can be applied to the insulating layers IS1 to IS4, for example.

[0327] The above-described fabrication method allows fabrication of a transistor MN having a large gate capacitance and a large electrode area. By increasing the electrode area, the remanent polarization can be increased when dielectric polarization occurs, thereby widening the threshold voltage distribution of data in the memory element. Therefore, logic values ​​of "0" and "1" can be accurately read.

[0328] Furthermore, in the above-described method for fabricating the transistor MN, a recess is formed in the conductive layer ME1 by forming one or more of the openings KK1 to KK3. Therefore, the area of ​​the recess in the opening KK2 is slightly larger than the area of ​​the opening KK2 in a planar view of the transistor MN. Increasing the area of ​​the recess increases the contact area between the semiconductor layer SC1 and the conductive layer ME1, thereby reducing the contact resistance between the semiconductor layer SC1 and the conductive layer ME1. Furthermore, by increasing the area of ​​the exposed conductive layer ME3 in the opening KK3, for example, by increasing the area of ​​the opening KK3 in a planar view of the transistor MN, the contact area between the semiconductor layer SC1 and the conductive layer ME3 can be increased, thereby reducing the contact resistance between the semiconductor layer SC1 and the conductive layer ME3. These factors increase the on-current of the transistor MN.

[0329] <<Semiconductor Layer>> The semiconductor layer SC1 can be, for example, a metal oxide that functions as an oxide semiconductor. In this case, the transistor MN formed later becomes an OS transistor. Examples of the metal oxide include indium oxide, gallium oxide, and zinc oxide. Alternatively, the metal oxide can be an oxide containing at least indium or zinc. The metal oxide preferably includes one or more elements selected from indium, the element M, and zinc. The element M can be, for example, one or more elements selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and antimony. In particular, the element M is preferably one or more of aluminum, gallium, yttrium, and tin. The element M more preferably includes one or both of gallium and tin.

[0330] For example, it is preferable to use indium gallium zinc oxide (hereinafter referred to as In—Ga—Zn oxide) for the semiconductor layer SC1. In particular, it is more preferable that the In—Ga—Zn oxide be a metal oxide having a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition thereabout, a composition of 4:2:3 [atomic ratio] or a composition thereabout, or a composition of 3:1:2 [atomic ratio] or a composition thereabout. As another example, it is also preferable to use In—Zn oxide for the semiconductor layer SC1. In particular, it is more preferable that the In—Zn oxide be a metal oxide having a composition of In:Zn=4:1 [atomic ratio] or a composition thereabout.

[0331] In particular, it is preferable to use an oxide semiconductor with a low carrier concentration for the semiconductor layer SC1. For example, the carrier concentration in the channel formation region of the oxide semiconductor is 1×10 １８ cm −３ Below 1 × 10, preferably １７ cm −３ less than 1×10 １６ cm −３ less than 1×10 １３ cm −３ less than 1×10 １０ cm −３ is less than 1×10 −９ cm −３ That is all. Note that when the carrier concentration of an oxide semiconductor film is reduced, it is preferable to reduce the impurity concentration in the oxide semiconductor film and reduce the density of defect states. In this specification, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may also be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0332] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor may have a low density of trap states due to a low density of defect states. Charges trapped in trap states of the oxide semiconductor take a long time to disappear and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0333] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In addition, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in a film adjacent to the oxide semiconductor.

[0334] Furthermore, a transistor including an oxide semiconductor (OS transistor) has a channel formation region in the oxide semiconductor that is impurity- or oxygen-vacancy-containing (hereinafter referred to as V Ｏ In addition, when a V in an oxide semiconductor is present, the electrical characteristics of the OS transistor are likely to fluctuate, which may result in poor reliability. Ｏ A defect in which hydrogen has entered (hereafter referred to as V Ｏ H) and generate electrons that become carriers. Ｏ When H is formed, the donor concentration in the channel formation region may increase. As the donor concentration in the channel formation region increases, the threshold voltage may vary. For this reason, when V Ｏ Therefore, in the channel formation region of the oxide semiconductor, impurities, oxygen vacancies, and V Ｏ It is preferable that H is reduced as much as possible.

[0335] The semiconductor layer SC1 preferably has a stacked structure of multiple oxide layers with different atomic ratios of metal elements. For example, as shown in Figure 33, the semiconductor layer SC1 can have a stacked structure including a semiconductor layer SC1a and a semiconductor layer SC1b. Figure 33 is a schematic cross-sectional view of an enlarged portion of the transistor MN shown in Figure 1B. As shown in Figure 33, the semiconductor layer SC1b is located on the upper surface of the semiconductor layer SC1a.

[0336] Here, the conductivity of the material used for the semiconductor layer SC1a is preferably different from the conductivity of the material used for the semiconductor layer SC1b. For example, a material with a higher conductivity than that of the semiconductor layer SC1b can be used for the semiconductor layer SC1a. As shown in FIG. 33 , the semiconductor layer SC1a has regions in contact with the conductive layers ME1 and ME3, which function as a source or drain. Therefore, by increasing the conductivity of the material used for the semiconductor layer SC1a, the contact resistance between the semiconductor layer SC1 and the conductive layer ME1 and the contact resistance between the semiconductor layer SC1 and the conductive layer ME3 can be reduced. This allows the on-current of the transistor MN to be increased.

[0337] Furthermore, the carrier concentration of the semiconductor material used for the semiconductor layer SC1a is preferably higher than the carrier concentration of the semiconductor material used for the semiconductor layer SC1b. By increasing the carrier concentration of the semiconductor material used for the semiconductor layer SC1a, the conductivity of the semiconductor layer SC1a can be increased.

[0338] Furthermore, the band gap of the first oxide semiconductor used in the semiconductor layer SC1a is preferably different from the band gap of the second oxide semiconductor used in the semiconductor layer SC1b. For example, the difference between the band gap of the first semiconductor material and the band gap of the second oxide semiconductor is preferably 0.1 eV or more, more preferably 0.2 eV or more, and even more preferably 0.3 eV or more. By making the band gap of the first oxide semiconductor lower than the band gap of the second oxide semiconductor, the contact resistance between the semiconductor layer SC1 and the conductive layer ME1 and the contact resistance between the semiconductor layer SC1 and the conductive layer ME3 can be reduced. Note that, depending on the situation, the band gap of the first oxide semiconductor may be higher than the band gap of the second oxide semiconductor.

[0339] As described above, the band gap of the first oxide semiconductor used in the semiconductor layer SC1a can be configured to be lower than the band gap of the second oxide semiconductor used in the semiconductor layer SC1b. The composition of the first oxide semiconductor is preferably different from the composition of the second oxide semiconductor. The band gap can be controlled by making the compositions of the first oxide semiconductor and the second oxide semiconductor different. For example, the content of element M in the first oxide semiconductor is preferably lower than the content of element M in the second oxide semiconductor. Specifically, when the first oxide semiconductor and the second oxide semiconductor are In-M-Zn oxides, the first metal oxide can have an atomic ratio of In:M:Zn=1:1:1 or a composition thereabout, an atomic ratio of In:M:Zn=4:2:3 or a composition thereabout, or an atomic ratio of In:M:Zn=3:1:2 or a composition thereabout, and the second oxide semiconductor can have an atomic ratio of In:M:Zn=1:3:2 or a composition thereabout, an atomic ratio of In:Ga:Zn=1:3:4 or a composition thereabout, or an atomic ratio of In:M:Zn=1:1:0.5 or a composition thereabout. The term "atomic ratios in the vicinity" refers to a range of ±30% of the desired atomic ratio.

[0340] Furthermore, the semiconductor layer SC1a may have a structure in which the first oxide semiconductor does not contain the element M. For example, the first oxide semiconductor used in the semiconductor layer SC1a may be an In—Zn oxide, and the second oxide semiconductor used in the semiconductor layer SC1b may be an In-M-Zn oxide. Specifically, the first oxide semiconductor may be an In—Zn oxide, and the second oxide semiconductor may be an In—Ga—Zn oxide. More specifically, the first oxide semiconductor may have a composition of In:Zn=1:1 (atomic ratio) or a composition therearound, or a composition of In:Zn=4:1 (atomic ratio) or a composition therearound, and the second oxide semiconductor may have a composition of In:Ga:Zn=1:1:1 (atomic ratio) or a composition therearound.

[0341] In addition, in the semiconductor layer SC1a, the first oxide semiconductor preferably contains indium (In) and can be indium oxide (sometimes called InOx or IO). For example, the In content of the first oxide semiconductor used in the semiconductor layer SC1a is preferably higher than the In content of the second oxide semiconductor used in the semiconductor layer SC1b. By using a metal oxide with a high In content as the first oxide semiconductor, the on-state current of the transistor MN can be increased, and the frequency characteristics can be improved.

[0342] The second oxide semiconductor layer used in the semiconductor layer SC1b may also be made of indium oxide, similarly to the semiconductor layer SC1a.

[0343] Here, an example is shown in which the content of the element M in the first oxide semiconductor is lower than the content of the element M in the second oxide semiconductor, but one embodiment of the present invention is not limited to this. The content of the element M in the first oxide semiconductor may be higher than the content of the element M in the second oxide semiconductor. Note that the first oxide semiconductor and the second oxide semiconductor may have different compositions, and the contents of elements other than the element M may be different.

[0344] 33, if a material with high conductivity is used for the semiconductor layer SC1b, the semiconductor layer SC1b is closer to the conductive layer ME4, which functions as a gate, than the semiconductor layer SC1a, and therefore the transistor MN may be more likely to be normally on. In other words, when the gate-source voltage is 0V, the drain current (sometimes called the cutoff current) flowing between the source and drain may become large. In this case, if the transistor MN is an n-channel transistor, the threshold voltage may become low. For this reason, it is preferable that the conductivity of the material used for the semiconductor layer SC1b is at least lower than the conductivity of the material used for the semiconductor layer SC1a.

[0345] From the viewpoint of the gate capacitance of the transistor MN, the thickness of the semiconductor layer SC1 is preferably 1 nm or more, 3 nm or more, or 5 nm or more, and 20 nm or less, 15 nm or less, 12 nm or less, or 10 nm or less.

[0346] The film thicknesses of the semiconductor layers included in the semiconductor layer SC1 (here, the semiconductor layer SC1a and the semiconductor layer SC1b) are preferably determined so that the film thickness of the semiconductor layer SC1 falls within the aforementioned range. The film thickness of the semiconductor layer SC1a can be determined so that the contact resistance between the semiconductor layer SC1 and the conductor ME1 and the contact resistance between the semiconductor layer SC1 and the conductor ME3 fall within the required range. Furthermore, the film thickness of the semiconductor layer SC1b can be determined so that the threshold voltage of the transistor falls within the required range. Note that the film thickness of the semiconductor layer SC1a may be the same as or different from the film thickness of the semiconductor layer SC1b.

[0347] Furthermore, the semiconductor layer SC1a and the semiconductor layer SC1b may have different thicknesses in the portion where the upper surface of the conductive layer ME3 is the surface to be formed, the portion where the side surface of the conductive layer ME3 is the surface to be formed, the portion where the side surface of the insulating layer BI4 is the surface to be formed, and the portion where the upper surface of the insulating layer BGI1 is the surface to be formed.

[0348] Although the above describes the example in which the semiconductor layer SC1 has a single-layer structure and the example in which the semiconductor layer SC1 has a two-layer stacked structure including the semiconductor layer SC1 a and the semiconductor layer SC1 b, one embodiment of the present invention is not limited thereto. The semiconductor layer SC1 may have a stacked structure of three or more layers.

[0349] 34 is a cross-sectional view of a memory element MC in which a semiconductor layer SC1 has a stacked structure including semiconductor layers SC1a, SC1b, and SC1c. Similarly to FIG. 33, FIG. 34 is also a cross-sectional view of an enlarged transistor MN of the memory element MC shown in FIG. 1B. As shown in FIG. 34, the semiconductor layer SC1b is located on the upper surface of the semiconductor layer SC1a, and the semiconductor layer SC1c is located on the upper surface of the semiconductor layer SC1b.

[0350] In the oxide semiconductor used for the semiconductor layer SC1a, the atomic ratio of the element M to In is preferably greater than the atomic ratio of the element M to In in the metal oxide used for the semiconductor layer SC1b. This configuration can suppress the diffusion of impurities and oxygen from structures formed outside the semiconductor layer SC1a to the semiconductor layer SC1b. Furthermore, it can suppress the diffusion of elements contained in the insulating layer BGI1, the conductive layer ME1, or the conductive layer ME3 into the semiconductor layer SC1b.

[0351] Therefore, unlike FIG. 33, the carrier concentration of the first oxide semiconductor included in the semiconductor layer SC1a is preferably higher than the carrier concentration of the second oxide semiconductor included in the semiconductor layer SC1b.

[0352] 34, since the semiconductor layer SC1c is closer to the conductive layer ME4 having a gate function than the semiconductor layers SC1a and SC1b, the conductivity of the material used for the semiconductor layer SC1c is preferably lower than the conductivity of the material used for each of the semiconductor layers SC1a and SC1b. As a result, when the transistor MN is an n-channel transistor, the threshold voltage can be increased and the transistor can have a small cutoff current.

[0353] The carrier concentration of the second oxide semiconductor included in the semiconductor layer SC1b is preferably higher than the carrier concentration of the third oxide semiconductor included in the semiconductor layer SC1c. By increasing the carrier concentration of the second oxide semiconductor included in the semiconductor layer SC1b, the conductivity can be increased, resulting in a transistor with a large on-state current. By decreasing the carrier concentration of the third oxide semiconductor included in the semiconductor layer SC1c, the conductivity can be decreased, resulting in a normally-off transistor.

[0354] Although an example in which the semiconductor layer SC1b is made of a material having higher conductivity than the semiconductor layer SC1c is described here, one embodiment of the present invention is not limited thereto. The semiconductor layer SC1b may be made of a material having lower conductivity than the semiconductor layer SC1c. Furthermore, the carrier concentration of the second oxide semiconductor contained in the semiconductor layer SC1b may be lower than the carrier concentration of the third oxide semiconductor contained in the semiconductor layer SC1c.

[0355] The band gap of the second oxide semiconductor used in the semiconductor layer SC1 b is preferably different from the band gap of the third oxide semiconductor used in the semiconductor layer SC1 c. For example, the difference between the band gap of the second oxide semiconductor and the band gap of the third oxide semiconductor is preferably 0.1 eV or more, more preferably 0.2 eV or more, and even more preferably 0.3 eV or more.

[0356] The band gap of the second oxide semiconductor used for the semiconductor layer SC1b can be lower than the band gap of the third oxide semiconductor used for the semiconductor layer SC1c. This allows the transistor MN to have a high on-state current. Furthermore, when the transistor MN is an n-channel transistor, the threshold voltage can be increased, allowing the transistor MN to be a normally-off transistor.

[0357] Although an example in which the band gap of the second oxide semiconductor is smaller than that of the third oxide semiconductor is described here, one embodiment of the present invention is not limited thereto. The band gap of the second oxide semiconductor may be larger than that of the third oxide semiconductor.

[0358] The first oxide semiconductor used in the semiconductor layer SC1a and the third oxide semiconductor used in the semiconductor layer SC1c may have the same composition or different compositions.

[0359] For example, a metal oxide having an atomic ratio of In:Ga:Zn=1:1:1 or a composition thereabout may be used for the semiconductor layer SC1a, a metal oxide having an atomic ratio of In:Zn=1:1 or a composition thereabout, a metal oxide having an atomic ratio of In:Zn=4:1 or a composition thereabout, or indium oxide may be used for the semiconductor layer SC1b, and a metal oxide having an atomic ratio of In:Ga:Zn=1:1:1 or a composition thereabout may be used for the semiconductor layer SC1c. This configuration can increase the on-state current of the transistor MN and provide a highly reliable transistor structure with little variation.

[0360] Furthermore, by using an oxide semiconductor for the semiconductor film SC1v and providing a conductive layer (corresponding to the conductive layers ME1 and ME3 in FIGS. 33 and 34 ) in contact with the semiconductor layer SC1, the oxygen concentration may be reduced near the conductor in the semiconductor layer SC1. Furthermore, a metal compound layer containing a metal contained in the conductor and a component of the semiconductor layer SC1 may be formed near the conductor in the semiconductor layer SC1. In such a case, the carrier concentration increases in a region near the conductor in the semiconductor layer SC1, and the region becomes a low-resistance region.

[0361] The metal oxide functioning as an oxide semiconductor will also be described in detail in Embodiment 3.

[0362] Furthermore, the semiconductor layer SC1 can be made of a material other than metal oxide, such as silicon. Examples of the silicon include amorphous silicon, microcrystalline silicon, polycrystalline silicon (including low temperature polysilicon (LTPS: Low Temperature Polysilicon)), and single crystal silicon. In the process of forming the semiconductor film SC1v in the opening KK1, it is preferable that the semiconductor region in which the semiconductor film SC1v is formed is changed into a low resistance region at the interface in contact with the conductive layer ME1 and the conductive layer ME3 and in the vicinity thereof. As a result, a low resistance region and a semiconductor region are formed in the semiconductor layer SC1, and therefore the transistor M1 can be a Si transistor.

[0363] <Modification 1 of Manufacturing Method> The transistor MN included in the memory element of one embodiment of the present invention is not limited to the transistor MN manufactured by the manufacturing method described above. The memory element of one embodiment of the present invention can have a configuration in which the transistor MN illustrated in FIGS. 1A to 1C and 2 is modified by appropriately modifying the manufacturing method described above.

[0364] The transistor MN shown in Figures 35A to 35C is a modified example of the transistor MN of Figures 1A to 1C, and is configured such that a portion of the upper surface of the conductive layer ME3 is removed at the opening KK3 when the sacrificial layer DGw is removed in the process of Figures 24A to 24C.

[0365] As shown in Figures 35A to 35C, by removing a portion of the upper surface of the conductive layer ME3 in the opening KK3, the area of ​​the region where the conductive layer ME3, the semiconductor layer SC1, and the insulating layer GF1 are stacked can be made smaller than that of the transistor MN in Figures 1A to 1C. This reduces the parasitic capacitance between the conductive layer ME3, which functions as the other of the source and drain, and the conductive layer ME4, which functions as the gate. By reducing this parasitic capacitance, the time it takes for charge to accumulate in each of the conductive layers ME3 and ME4 can be shortened, thereby increasing the drive frequency of the transistor MN. This increases the operating speed of the memory element MC including the transistor MN.

[0366] 36A to 36C is a modification of the transistor MN of Figures 1A to 1C, and has a configuration in which an insulating layer BI7 is formed on the upper surfaces of the insulating layer GF1 and the conductive layer ME4 before forming the insulating film that will become the insulating film IS5v in the steps of Figures 29A to 29C. Therefore, in the steps of Figures 29A to 29C, an opening KK4 is formed not only in the insulating layer IS5 but also in the region of the insulating layer BI7 that overlaps the conductive layer ME4.

[0367] The insulating layer BI7 functions as a barrier insulating film. Therefore, for example, in order to prevent oxidation of the conductive layer ME4, it is preferable to use an insulating material for the barrier insulating film that has the function of suppressing the diffusion of oxygen from the insulating layer IS5 to the conductive layer ME4 (i.e., that the oxygen is less likely to permeate). Furthermore, in order to prevent the diffusion of impurities from above the barrier insulating film to the transistor MN below the barrier insulating film, it is preferable to use an insulating material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms (i.e., that the impurities are less likely to permeate). Therefore, for the insulating layer BI7, a material or configuration that can be applied to either the insulating layer BI1 or the insulating layer BI6 can be used.

[0368] 36A to 36C, by forming the insulating layer BI7 on the upper surface of the insulating layer GF1 and the upper surface of the conductive layer ME4, it is possible to prevent, for example, a decrease in the conductivity of the conductive layer ME4 due to oxidation. It is also possible to prevent, for example, a deterioration in the characteristics of the transistor MN due to the diffusion of impurities from above to below the insulating layer BI7. These features also improve the reliability of the memory element MC.

[0369] 37A to 37C is a modification of the transistor MN of FIGS. 1A to 1C , and is configured such that the conductive layer ME4 is formed to overlap with the semiconductor layer SC1 in a plan view in the process of FIG. 28A . Also, in the processes of FIGS. 28B and 28C , an end of the conductive layer ME4 is formed to be located outside the end of the semiconductor layer SC1 in a cross-sectional view.

[0370] 28A to 28C , when the film thickness of the step region of the insulating layer GF1 is thinner than other regions of the insulating layer GF1, in order to prevent the conductive layer ME4 and the semiconductor layer SC1 from contacting (short-circuiting) with each other, the conductive layer ME4 is formed only inside the region of the semiconductor layer SC1 in plan view. Meanwhile, when the film thickness of the step region of the insulating layer GF1 is thick enough that the conductive layer ME4 and the semiconductor layer SC1 do not contact each other, the conductive layer ME4 can be formed so as to overlap with the semiconductor layer SC1 in plan view, as in the transistor MN shown in FIGS.

[0371] As shown in the configuration of transistor MN in Figures 37A to 37C, by forming conductive layer ME4 so that it overlaps with semiconductor layer SC1 in a plan view, the area of ​​the region where semiconductor layer SC1, insulating layer GF1, and conductive layer ME4 are stacked can be increased. In other words, the electrode area of ​​the gate capacitance of transistor MN, which is made up of semiconductor layer SC1, insulating layer GF1, and conductive layer ME4, can be made larger than that of transistor MN in Figures 1A to 1C. This allows the threshold voltage distribution of data in the memory element to be increased. As a result, the logic of "0" and "1" can be accurately read.

[0372] 38A to 38C is a modification of the transistor MN of FIGS. 1A to 1C , and has a configuration in which the size of the opening KK3 roughly matches the size of the opening KK2. The transistor MN shown in FIGS. 38A to 38C can be formed by forming the sacrificial layer DGw so that it overlaps the opening KK2 in a planar view when processing the sacrificial layer DGv into the sacrificial layer DGw in the steps of FIGS. 22A to 22C , and then forming the insulating layer IS4. The sacrificial layer DGw is then removed, and the steps of FIGS. 25A to 25C and subsequent steps are carried out.

[0373] The transistor MN shown in Figures 38A to 38C has a configuration in which the side of the conductive layer ME3 is in contact with the semiconductor layer SC1. Therefore, compared to the transistor MN shown in Figures 1A to 1C, the parasitic capacitance between the conductive layer ME3, which functions as the other of the source and drain, and the conductive layer ME4, which functions as the gate, can be reduced. By reducing this parasitic capacitance, the time it takes for charge to accumulate in each of the conductive layers ME3 and ME4 can be shortened, thereby increasing the drive frequency of the transistor MN. This increases the operating speed of the memory element MC including the transistor MN.

[0374] 39A to 39C is a modification of the transistor MN of Fig. 1A to 1 C. Specifically, the transistor MN shown in Fig. 39A to 39C has a configuration in which, after the steps of Fig. 29A to 29C, a planarization process is performed by CMP or the like until the insulating layer IS4 is exposed, and then an insulating layer BI7 and an insulating layer IS5 are formed, each having an opening KK4 that reaches the conductive layer ME4.

[0375] 1A to 1C can be referred to for the method of forming the conductive layer ME5 and the insulating layer BI6 and the insulating layer IS6. Also, for the insulating layer BI7, the description of the insulating layer BI7 in FIGS. 36A to 36C can be referred to.

[0376] 39A to 39C has a conductive layer ME4 with higher planarity than the transistor MN of FIGS. 1A to 1C. Therefore, the transistor MN of FIGS. 39A to 39C can prevent poor formation or poor contact of the conductive layer ME5 on the upper surface of the conductive layer ME4 after the openings KK4 are formed in the insulating layers BI7 and IS5, more effectively than the transistor MN of FIGS. 1A to 1C. In other words, the transistor MN of FIGS. 39A to 39C can achieve a higher yield than the transistor MN of FIGS. 1A to 1C.

[0377] 39A to 39C has a high degree of flatness, the conductive layer ME4 can be easily formed by sputtering as well as ALD and CVD, which increases the number of ways to form the conductive layer ME5 when fabricating the transistor MN of FIG.

[0378] Furthermore, when forming the opening KK4 in the insulating layer BI7 and the insulating layer IS5, a recess may be formed in the upper surface of the conductive layer ME4 (see FIGS. 40A to 40C). The area of ​​the recess in the opening KK4 is slightly larger than the area of ​​the opening KK4 in a plan view of the transistor MN. By increasing the area of ​​the recess, the contact area between the conductive layer ME4 and the conductive layer ME5 increases, thereby reducing the contact resistance between the conductive layer ME4 and the conductive layer ME5. This allows for faster charge accumulation in the gate of the transistor MN, thereby increasing the drive frequency of the transistor MN.

[0379] 41A to 41C is a modified example of the transistor MN of FIGS. 1A to 1C. Specifically, the transistor MN of FIGS. 41A to 41C has a configuration in which, after the formation of the opening KK3 in FIGS. 24A to 24C, an insulating layer DP is formed on the top surface of the insulating layer IS4 and on the side surfaces of the insulating layer IS4 and the insulating layer BI5 in the opening KK3, as shown in FIGS. 42A to 42C. Thereafter, the transistor MN of FIGS. 41A to 41C can be fabricated by proceeding with the steps in and after FIGS. 25A to 25C.

[0380] The insulating layer DP is preferably a layer that reduces the resistance of the semiconductor layer SC1 in contact with the insulating layer DP. For example, when the semiconductor layer SC1 contains a metal oxide as an oxide semiconductor, the insulating layer DP preferably contains a material that absorbs oxygen from the region of the semiconductor layer SC1 in contact with the insulating layer DP. The oxygen-absorbing material can be, for example, a material containing a metal element.

[0381] In this case, a compound containing the metal element may be formed at or near the interface between the semiconductor layer SC1 and the insulating layer DP. The compound may also be generated by heat treatment or the like. This reduces the resistance of the interface between the semiconductor layer SC1 and the insulating layer DP or its vicinity, increasing the conductivity of the region of the semiconductor layer SC1 that contacts the insulating layer DP. This is thought to be because a portion of the oxygen contained in the semiconductor layer SC1 reacts with the metal element in the insulating layer DP, forming oxygen vacancies in the region of the semiconductor layer SC1 and lowering the resistance.

[0382] In this case, the insulating layer DP may be made of a material containing a metal element, such as a nitride containing a metal element or an oxide containing a metal element. Examples of the metal element include aluminum, magnesium, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. The metal element may be a metal element contained in any one of the conductive layers ME1 to ME5.

[0383] The region of the semiconductor layer SC1 in contact with the insulating layer DP functions as one of a pair of electrodes of the gate capacitance of the transistor MN, so it is preferable that this region be highly conductive. In the transistor MN shown in Figures 41A to 41C, the region of the semiconductor layer SC1 in contact with the insulating layer DP has low resistance, which allows for faster charge accumulation in this region. This can therefore increase the operating speed of the memory element and increase the amount of polarization in the insulating layer GF1 when dielectric polarization occurs.

[0384] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0385] Embodiment 3 In this embodiment, a metal oxide that functions as an oxide semiconductor will be described.

[0386] <Metal Oxide> When a metal oxide is used in the semiconductor layer of a transistor, lattice defects in the metal oxide can cause carrier generation or capture. Therefore, if a metal oxide with many lattice defects is used in the semiconductor layer of a transistor, the electrical characteristics of the transistor may become unstable. Therefore, it is preferable that the metal oxide used in the semiconductor layer of a transistor has few lattice defects. Lattice defects include point defects such as atomic vacancies and heteroatoms, line defects such as dislocations, planar defects such as grain boundaries, and volume defects such as voids.

[0387] By using a crystalline metal oxide for an oxide semiconductor layer, the density of defect states in the oxide semiconductor layer can be reduced. Examples of the structure of a crystalline metal oxide include a c-axis aligned crystal (CAAC) structure, a polycrystalline (poly-crystal) structure, and a nanocrystalline (nc) structure.

[0388] The metal oxide according to one embodiment of the present invention has a plurality of microcrystals. Furthermore, no clear grain boundary is observed between the plurality of microcrystals. The metal oxide included in the oxide semiconductor layer according to one embodiment of the present invention preferably has a crystal structure in which the plurality of microcrystals are connected without clear grain boundaries when observed from the orientation direction.

[0389] The metal oxide according to one embodiment of the present invention has a crystal structure different from either a single crystal structure or a polycrystalline structure, and preferably has a CAAC structure.

[0390] The CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals having a hexagonal crystal structure) have a c-axis orientation and are connected in the a-b plane without any clear grain boundaries. When a cross section of an oxide semiconductor layer having the CAAC structure is observed using a high-resolution transmission electron microscope (TEM) image, it can be confirmed that metal atoms are arranged in a layered manner in the crystal parts. Therefore, the oxide semiconductor layer having the CAAC structure can also be said to have a structure having layered crystal parts. The metal atoms arranged in a layered manner can be observed as a row of bright spots in a cross section of the oxide semiconductor layer observed using a TEM image. The bright spots are arranged, for example, in a direction parallel to the surface on which the oxide semiconductor layer is formed.

[0391] In addition, a structure in which metal atoms in each of a plurality of microcrystals are arranged in layers parallel or substantially parallel to the surface on which the metal atoms are formed, and the layers in which the metal atoms are arranged are stacked in a direction perpendicular or substantially perpendicular to the surface on which the metal atoms are formed, is sometimes referred to as a CAAC structure. If the microcrystals have such a configuration, the crystal structure of the microcrystals is not limited to a hexagonal system. For example, some of the plurality of microcrystals may have a crystal structure other than a hexagonal system (e.g., a cubic system crystal structure).

[0392] For example, the CAAC structure is formed so that the c-axis is perpendicular or approximately perpendicular to the surface on which the metal is formed. In the CAAC structure, metal atoms are arranged in layers parallel or approximately parallel to the surface on which the metal is formed. In the region having the CAAC structure, the c-axis is preferably within 90 degrees ± 20 degrees (70 degrees or more and 110 degrees or less) relative to the surface on which the metal is formed, more preferably within 90 degrees ± 15 degrees (75 degrees or more and 105 degrees or less), more preferably within 90 degrees ± 10 degrees (80 degrees or more and 110 degrees or less), and even more preferably within 90 degrees ± 5 degrees (85 degrees or more and 95 degrees or less).

[0393] A polycrystalline structure has crystal grain boundaries. Furthermore, when a heat treatment is performed after forming an oxide semiconductor layer with a polycrystalline structure, tiny gaps (also referred to as nanocracks or microcracks) or tiny spaces (also referred to as nanospaces or microspaces) can be formed between crystalline portions. When tiny gaps or tiny spaces are formed in the oxide semiconductor layer, the electrical resistance of the oxide semiconductor layer increases. This is because the electrical resistance of the tiny gaps or tiny spaces is very high, for example, infinite. When an oxide semiconductor layer having tiny gaps or tiny spaces is used in a channel formation region of a transistor, the contact resistance between the oxide semiconductor layer and one or both of a source electrode and a drain electrode increases. This adversely affects the initial characteristics or reliability of the transistor. In contrast, in the CAAC structure, crystal grain boundaries are not clearly observed in the a-b plane, so a highly reliable semiconductor device can be realized. Furthermore, because there are fewer crystal grain boundaries, the energy barrier against carrier conduction in the transistor channel is small, and an improvement in on-current is expected. Furthermore, it is expected that an increase in the electrical resistance of a semiconductor layer of a transistor using an oxide semiconductor layer can be suppressed or the initial characteristics (particularly on-state current) of the transistor can be improved, making the transistor suitable for high-speed operation.

[0394] A metal oxide that increases the on-state current of a transistor is preferably used for the channel formation region of the transistor. To increase the on-state current of the transistor, it is preferable to increase the mobility of the metal oxide used in the transistor. To increase the mobility of the metal oxide, it is necessary to improve the transport of carriers (electrons in the case of an n-channel transistor) or reduce scattering factors that contribute to the transport of carriers. Carriers flow from the source to the drain through the channel formation region. Therefore, by providing a channel formation region in which carriers can easily flow in the channel length direction, the on-state current of the transistor can be increased.

[0395] The crystallinity of the metal oxide can be analyzed by, for example, X-ray diffraction (XRD), TEM, or electron diffraction (ED). Alternatively, the analysis may be performed by combining a plurality of these techniques.

[0396] When electron diffraction is performed on a metal oxide having a CAAC structure, spots (bright spots) indicating c-axis orientation are observed in the electron diffraction pattern. The c-axis of the CAAC structure is preferably aligned in a direction parallel to the normal vector of the surface on which the metal oxide is formed or the normal vector of the surface of the metal oxide.

[0397] Furthermore, an FFT pattern obtained by subjecting a TEM image to a fast Fourier transform (FFT) process reflects reciprocal lattice space information similar to an electron diffraction pattern.

[0398] A cross-sectional TEM image of a metal oxide having a CAAC structure is obtained, and an FFT pattern is created by performing FFT processing on each region within the cross-sectional TEM image. From the created FFT pattern, the crystal axis direction of each region can be calculated. Specifically, the direction of the line segment connecting two spots observed in the created FFT pattern that have high brightness and are approximately equal distances from the center is taken as the crystal axis direction. The crystal axis direction of each region calculated from the FFT pattern is preferably 70 degrees or more and 110 degrees or less (within 90 degrees ± 20 degrees) relative to the surface to be formed, more preferably 75 degrees or more and 105 degrees or less (within 90 degrees ± 15 degrees), more preferably 80 degrees or more and 100 degrees or less (within 90 degrees ± 10 degrees), and even more preferably 85 degrees or more and 95 degrees or less (within 90 degrees ± 5 degrees). A CAAC structure can be considered to have such a region.

[0399] When a metal oxide having a CAAC structure is viewed in a direction perpendicular to the surface to be formed using a TEM image, a triangular or hexagonal atomic arrangement is observed in the a-b plane, and the metal oxide has crystallinity. In addition, in a Voronoi diagram created by image analysis of a TEM image of a metal oxide having a CAAC structure viewed in a direction perpendicular to the surface to be formed, pentagonal, hexagonal, and heptagonal Voronoi regions are mainly observed, and hexagonal Voronoi regions are typically observed. For example, the proportion of hexagonal Voronoi regions among the Voronoi regions observed in the Voronoi diagram is 30% or more and less than 100%.

[0400] A method for creating a Voronoi diagram will now be described. First, image analysis of a TEM image involves performing FFT processing, filtering to leave only a certain range of information, and then performing an inverse fast Fourier transform to create an FFT-filtered image. Lattice points are extracted from the created FFT-filtered image, and perpendicular bisectors of line segments connecting adjacent lattice points are created. The points where three perpendicular bisectors intersect are defined as Voronoi points, and the polygonal regions enclosed by the lines connecting the Voronoi points are defined as Voronoi regions. In this way, a Voronoi diagram can be created.

[0401] The observation range of the TEM in creating the Voronoi diagram can be, for example, a rectangular region of 50 nm in length and 50 nm in width, although the observation range is not limited to this.

[0402] Furthermore, when the distribution of the orientation of the hexagonal lattice is analyzed using lattice points extracted by image analysis of a planar TEM image, the difference in the orientation of the hexagonal lattice at the boundary between two structures with different hexagonal lattice orientations is small, and the boundary is observed to be blurred, and it appears that the two structures are connected in a manner that makes them intertwine. In other words, no clear boundary is observed in the CAAC structure.

[0403] The orientation of the hexagonal lattice can be calculated by calculating the orientation of a hexagon formed by the six lattice points closest to each lattice point.

[0404] The crystallinity of the semiconductor material of the metal oxide is not limited. The metal oxide may contain one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part). The crystallinity of the metal oxide may suppress deterioration of transistor characteristics.

[0405] The metal oxide according to one embodiment of the present invention preferably contains at least indium or zinc, and particularly preferably contains indium as a main component. Here, the metal oxide contains indium as a main component and may further contain element M. Furthermore, the metal oxide preferably contains one or more elements selected from indium, element M, and zinc, and particularly preferably contains indium and zinc as main components. Here, the metal oxide contains indium and zinc as main components and may further contain element M. The element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from gallium, tin, yttrium, and aluminum, and even more preferably one or more selected from gallium and tin. When the element M contained in the metal oxide is gallium, the metal oxide according to one embodiment of the present invention preferably contains one or more selected from indium, gallium, and zinc. Note that in this specification, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification may also include metalloid elements.

[0406] The main component in a metal oxide refers to a metal element whose proportion relative to all metal elements contained in the metal oxide is, for example, 0.1 atomic % or more, or 1 atomic % or more.

[0407] In a cross section of a metal oxide observed using a TEM image, it is confirmed that metal atoms are arranged in layers parallel or approximately parallel to the surface on which they are formed. Metal atoms are observed as bright spots in the TEM image. For example, in a metal oxide containing indium, it is confirmed that indium is arranged in layers. Furthermore, for example, in a metal oxide containing indium and zinc, it is confirmed that indium and zinc are arranged in layers.

[0408] Examples of metal oxides according to one embodiment of the present invention include indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), and indium aluminum. Examples of usable metal oxides include indium zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also referred to as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO). Other examples include indium tin oxide containing silicon (also referred to as ITSO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide). Indium oxide can be used as a metal oxide according to one embodiment of the present invention. Gallium oxide, zinc oxide, and the like can be used as a metal oxide according to one embodiment of the present invention.

[0409] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the transistor can have a large on-state current and high frequency characteristics.

[0410] Furthermore, by increasing the ratio of the number of zinc atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the metal oxide can be made highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0411] Furthermore, by increasing the ratio of the number of atoms of element M to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, thereby improving reliability.

[0412] Note that the metal oxide may contain one or more metal elements having a higher period number in the periodic table instead of indium. Alternatively, the metal oxide may contain one or more metal elements having a higher period number in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, including a metal element having a higher period number may improve the field-effect mobility of a transistor. Examples of metal elements having a higher period number include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0413] The metal oxide may also contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, fluorine, chlorine, bromine, and hydrogen.

[0414] <Example of Method for Forming Oxide Semiconductor> Next, a method for forming an oxide semiconductor layer included in an active layer of an OS transistor will be described. Note that the oxide semiconductor layer can be formed by forming the above-described metal oxide using two types of film formation methods.

[0415] In the formation of an oxide semiconductor layer according to one embodiment of the present invention, a metal oxide having a CAAC structure is formed. In this case, a sputtering method can be used as a film formation method, which allows the formation of a metal oxide having high crystallinity. Alternatively, a pulsed laser deposition (PLD) method or the like may be used.

[0416] Here, when a metal oxide is formed using the above-described film formation method (hereinafter referred to as the first film formation method), a mixed layer may be formed at the interface between the metal oxide and the surface on which the metal oxide is to be formed. There is a concern that the mixed layer may inhibit the crystallization of the metal oxide. By first forming a metal oxide as a first layer on the surface on which the metal oxide is to be formed using a film formation method (hereinafter referred to as the second film formation method) that causes less damage than the sputtering method, PLD method, etc., which are described as the first film formation method, and then providing a metal oxide formed using the first film formation method as a second layer, the formation of a mixed layer at the interface between the oxide semiconductor layer and the surface on which the metal oxide is to be formed can be suppressed. Furthermore, impurities contained in the surface on which the metal oxide is to be formed can be suppressed from being mixed into the second layer. These factors can further enhance the crystallinity of the second layer.

[0417] Atomic layer deposition (ALD) and chemical vapor deposition (CVD) are suitable as the second film formation method because they can suppress damage to the surface to be formed compared to sputtering. Examples of the second film formation method include molecular beam epitaxy (MBE) and wet methods. Examples of CVD methods include plasma enhanced CVD (PECVD), thermal CVD, photo-assisted CVD, and metal organic CVD (MOCVD). The MBE method is a film formation method that grows a thin film with a crystalline structure that reflects the crystalline system of the substrate, and can be said to be one of the film formation methods that causes less damage to the surface to be formed. The wet method is one of the film formation methods that causes less damage to the surface to be formed. Examples of wet methods include spray coating.

[0418] A third layer can be further formed on the second layer, for example, by the second film formation method.

[0419] After the oxide semiconductor layer is formed, heat treatment is preferably performed.

[0420] In the method for forming an oxide semiconductor layer according to one embodiment of the present invention, the crystallinity of the upper and lower oxide semiconductor layers (the first and third layers) can be increased by using the second layer (i.e., the CAAC) having high crystallinity as a nucleus or seed. This increases the crystallinity of the entire oxide semiconductor layer. In other words, the second layer serves as a nucleus or seed to cause solid-phase growth of a metal oxide in the upper and lower oxide semiconductor layers, thereby forming oxide semiconductor layers with high crystallinity. An oxide semiconductor layer formed by such a film formation method, specifically, an oxide semiconductor layer having a CAAC structure, can be referred to as an axial growth CAAC (AG CAAC).

[0421] Even when a method that easily forms a metal oxide with high crystallinity is not used as a method for forming the first layer and the third layer, the crystallinity of the first layer and the third layer can be increased by using the method for forming an oxide semiconductor layer of one embodiment of the present invention. Furthermore, heat treatment has a function of assisting in increasing the crystallinity of the first layer and the third layer.

[0422] Note that it is preferable to perform a treatment for improving the crystallinity of the oxide semiconductor layer during or after the formation of the oxide semiconductor layer. Examples of the treatment for improving the crystallinity of the oxide semiconductor layer include heat treatment, plasma treatment, microwave (typically, 2.45 GHz) treatment, microwave plasma treatment, and light (e.g., ultraviolet light) irradiation treatment. Note that a plurality of these treatments may be performed simultaneously or sequentially. For example, heat treatment and microwave plasma treatment may be performed simultaneously. Alternatively, microwave plasma treatment may be performed after heat treatment.

[0423] In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz to 300 GHz. Microwave plasma treatment refers to treatment using a device with a power source that generates high-density plasma using microwaves. Microwave plasma treatment can also be called microwave-excited high-density plasma treatment.

[0424] Furthermore, it is more preferable to perform the treatment for increasing the crystallinity of the oxide semiconductor layer multiple times during the formation of the oxide semiconductor layer. For example, when the oxide semiconductor layer is formed by an ALD method, it is preferable to perform a microwave plasma treatment every time an atomic layer is formed. Alternatively, it is preferable to perform a treatment for increasing the crystallinity every time an oxide semiconductor layer having a thickness within a predetermined range is formed, in order to increase productivity. Specifically, it is preferable to form a first oxide semiconductor layer having a thickness of 1 nm to 10 nm, perform the first microwave plasma treatment, and then form a second oxide semiconductor layer having a thickness of 1 nm to 10 nm, and perform the second microwave plasma treatment. Note that the method for forming the first oxide semiconductor layer and the second oxide semiconductor layer is not particularly limited, and ALD or sputtering can be used, respectively. In particular, forming the first oxide semiconductor layer by an ALD method is preferable because it can prevent elements of the layers constituting the formation surface from being mixed (also referred to as mixing) into the first oxide semiconductor layer and the second oxide semiconductor layer. This is particularly suitable when the element contained in the layer constituting the formation surface inhibits crystallization of the oxide semiconductor (for example, when silicon, carbon, or the like is contained). The first oxide semiconductor layer and the second oxide semiconductor layer may have different compositions. Although a stacked structure of the first oxide semiconductor layer and the second oxide semiconductor layer is illustrated here, the present invention is not limited to this. The same treatment can be applied to a single oxide semiconductor layer or a stacked structure of three or more layers.

[0425] Treatment for increasing the crystallinity of the oxide semiconductor layer may be performed after the oxide semiconductor layer is formed. Specifically, the treatment may be performed directly on the formed oxide semiconductor layer, or may be performed through another film such as an insulating film formed on the oxide semiconductor layer. For example, microwave plasma treatment may be performed after the oxide semiconductor layer is formed, or an insulating film (e.g., a silicon nitride film, a silicon oxide film, or an aluminum oxide film) may be formed after the oxide semiconductor layer is formed, and then heat treatment or microwave plasma treatment may be performed on the oxide semiconductor layer through the insulating film.

[0426] Note that the treatment for increasing the crystallinity of the oxide semiconductor layer can also serve as treatment for removing impurities contained in the oxide semiconductor layer. For example, carbon, hydrogen, nitrogen, and the like contained in the oxide semiconductor layer can be preferably removed. Alternatively, by performing the treatment for increasing the crystallinity of the oxide semiconductor layer in an oxygen gas atmosphere, oxygen vacancies in the oxide semiconductor layer can be reduced.

[0427] When the treatment for increasing the crystallinity of the oxide semiconductor layer is performed, the temperature of the substrate is preferably room temperature or higher, 100° C. or higher and 600° C. or lower, or 300° C. or higher and 450° C. The temperature of the heat treatment is preferably 100° C. or higher and 700° C. or lower, or 300° C. or higher and 450° C.

[0428] In addition to the above-described method for forming an oxide semiconductor layer, treatment for increasing the crystallinity of the oxide semiconductor layer can be performed, whereby a highly reliable transistor can be provided.

[0429] In particular, for example, the oxide semiconductor of AG CAAC described in this embodiment can be used for the semiconductor layer SC1 described in Embodiments 1 and 2. By using the oxide semiconductor of AG CAAC for the channel formation region of the semiconductor layer SC1 of the transistor MN, the transistor MN can have a large on-state current, high field-effect mobility, a good S value, high frequency characteristics, and good reliability. Note that the S value is a subthreshold swing value, which indicates the amount of change in gate voltage in the subthreshold region required to change the drain current by one order of magnitude at a constant drain voltage. The smaller the S value, the steeper the slope of the drain current with respect to the gate voltage, resulting in better switching characteristics.

[0430] For example, in FIG. 34 , a semiconductor layer SC1a is formed as a first layer by the second film formation method, a semiconductor layer SC1b is formed as a second layer by the first film formation method, and a semiconductor layer SC1c is formed as a third layer by the second film formation method, whereby an oxide semiconductor that is AG CAAC can be formed as the semiconductor layer SC1.

[0431] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configurations, structures, methods, and the like described in this embodiment mode can be appropriately combined and used with the configurations, structures, methods, and the like described in the other embodiment modes. For example, the configurations, structures, methods, and the like described in this embodiment mode can be appropriately combined and used with the configurations, structures, methods, and the like described in the other embodiment modes.

[0432] Embodiment Mode 4 In this embodiment mode, a memory device including the memory element MC described in the above embodiment mode will be described.

[0433] 43A shows a schematic perspective view illustrating a configuration example of a memory device MDV0 having the memory element MC described in embodiment 1, and FIG. 43B shows a block diagram illustrating a configuration example of the memory device MDV0. The memory device MDV0 has a memory layer 60 and a drive circuit layer 50.

[0434] In particular, in FIG. 43A , the memory layer 60 of the memory device MDV0 is provided by stacking N layers (N is an integer equal to or greater than 1). Furthermore, one layer of the memory layer 60 has the memory cell array MCA described in the first embodiment, and the memory cell array MCA has a plurality of memory cells 10 arranged in a matrix of m rows and n columns. Note that FIG. 43B shows an example in which memory cell 10[1,1], memory cell 10[m,1] (where m is an integer equal to or greater than 1), memory cell 10[1,n] (where n is an integer equal to or greater than 1), memory cell 10[m,n], and memory cell 10[i,j] (where i is an integer equal to or greater than 1 and m, and j is an integer equal to or greater than 1 and n) are arranged in memory layer 60_k.

[0435] The memory cell array MCA included in the memory layer 60 corresponds to the memory cell array MCA described in the first embodiment, and the memory cell 10 included in the memory layer 60 corresponds to the memory element MC described in the first embodiment.

[0436] The drive circuit layer 50 has the function of performing write and read operations on the memory cell arrays MCA included in each of the N memory layers 60. The drive circuit layer 50 is provided below the N memory layers 60. In other words, the N memory cell arrays MCA are arranged so as to overlap on the drive circuit layer 50. By providing the N memory layers 60 on the drive circuit layer 50, the occupied area of ​​the memory device MDV0 can be reduced. Furthermore, the memory capacity per unit area can be increased. Note that in this specification and elsewhere, the drive circuit layer 50 may also be referred to as a circuit layer.

[0437] In the present embodiment and the like, the first memory layer 60 is referred to as memory layer 60_1, the second memory layer 60 is referred to as memory layer 60_2, and the third memory layer 60 is referred to as memory layer 60_3. Furthermore, the kth memory layer 60 (k is an integer of 1 to N) is referred to as memory layer 60_k, and the Nth memory layer 60 is referred to as memory layer 60_N. Note that in the present embodiment and the like, when describing matters relating to all N memory layers 60 or when indicating matters common to each of the N memory layers 60, the term "memory layer 60" may be used.

[0438] The signal propagation distance can be shortened by providing the memory layer 60 overlapping the drive circuit layer 50. The drive circuit layer 50 and the memory cells 10 may be provided on the same plane.

[0439] <Configuration Example of Drive Circuit Layer 50> The drive circuit layer 50 includes a PSW 22 (power switch), a PSW 23, and a peripheral circuit 31. The peripheral circuit 31 includes a peripheral circuit 41, a control circuit 32, and a voltage generation circuit 33.

[0440] In the memory device MDV0, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0441] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 32.

[0442] The control circuit 32 is a logic circuit that has the function of controlling the overall operation of the memory device MDV0. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation or read operation) of the memory device MDV0. Alternatively, the control circuit 32 generates a control signal for the peripheral circuit 41 so that this operation mode is executed.

[0443] The voltage generating circuit 33 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 33. For example, when an H-level signal is applied to the signal WAKE, the signal CLK is input to the voltage generating circuit 33, and the voltage generating circuit 33 generates a negative voltage.

[0444] The peripheral circuit 41 is a circuit for writing and reading data to and from the memory cells 10. The peripheral circuit 41 includes a row decoder 42, a column decoder 44, a row driver 43, a column driver 45, an input circuit 47, an output circuit 48, and a sense amplifier 46.

[0445] The row decoder 42 and the column decoder 44 have the function of decoding the signal ADDR. The row decoder 42 is a circuit for specifying the row to be accessed, and the column decoder 44 is a circuit for specifying the column to be accessed. In other words, the row decoder 42 and the column decoder 44 are sometimes called selection circuits that select the memory cell 10 to be written to or read from.

[0446] 3 described in Embodiment 1. Therefore, the row driver 43 has a function of writing data to the memory cell 10 and a function of selecting a wiring specified by the row decoder 42 (for example, the wiring WL or the wiring BGL in FIG. 3 described in Embodiment 1).

[0447] As an example, the column driver 45 includes the driver circuits SD and BD shown in FIG. 3 described in the first embodiment. Therefore, the row driver 43 has the functions of writing data to the memory cells 10, reading data from the memory cells 10, and retaining the data read from the memory cells 10. The column driver 45 has the function of selecting a wiring specified by the column decoder 44 (for example, the wiring BL or the wiring SL shown in FIG. 3 described in the first embodiment). As described above, the column driver 45 contributes to the write operation to the memory cells 10, and therefore may be referred to as a write circuit that transmits write data to the memory cells 10. Similarly, the column driver 45 also contributes to the read operation to the memory cells 10, and therefore may be referred to as a read circuit that reads read data from the memory cells 10.

[0448] The input circuit 47 has a function of holding a signal WDA. The data held by the input circuit 47 is output to the column driver 45. The output data of the input circuit 47 is data (Din) to be written to the memory cell 10. The data (Dout) read from the memory cell 10 by the column driver 45 is amplified by the sense amplifier 46 and output to the output circuit 48. The output circuit 48 has a function of holding Dout. The output circuit 48 also has a function of outputting Dout to the outside of the memory device MDV0. The data output from the output circuit 48 is a signal RDA.

[0449] PSW22 has a function of controlling the supply of VDD to the peripheral circuit 31. PSW23 has a function of controlling the supply of VHM to the row driver 43. Here, the high power supply voltage of the memory device MDV0 is VDD, and the low power supply voltage is GND (ground potential). VHM is a high power supply voltage used to set the word line to a high level and is higher than VDD. Signal PON1 switches PSW22 between the ON and OFF states, and signal PON2 switches PSW23 between the ON and OFF states. In FIG. 43B, the number of power domains to which VDD is supplied in the peripheral circuit 31 is one, but multiple domains may also be used. In this case, a power switch may be provided for each power domain.

[0450] Next, a cross-sectional configuration example of a memory device MDV0 according to one embodiment of the present invention is shown in FIG. 44 . The memory device MDV0A shown in FIG. 44 has a configuration in which the memory element MC described in Embodiment 1 is used as the memory cell 10 included in the memory layer 60. In FIG. 44 , the memory device MDV0A has multiple memory layers 60 above the driver circuit layer 50. Note that in the memory device MDV0A shown in FIG. 44 , memory layers 60_1 to 60_100 are illustrated as the multiple memory layers 60. That is, the memory device MDV0A in FIG. 44 has a configuration in which N=100 in the memory layer 60_N shown in FIG. 43A .

[0451] 44 illustrates a transistor 400 included in the driver circuit layer 50. The transistor 400 is provided over a substrate 311 and includes a conductive layer 316 having a function as a gate, an insulating layer 315 having a function as a gate insulating film, an insulating layer 317 formed on a side surface of the gate, a semiconductor region 313 including a part of the substrate 311, and low-resistance regions 314a and 314b having a function as a source region and a drain region. The transistor 400 can be a p-channel transistor or an n-channel transistor. The substrate 311 can be, for example, a single crystal silicon substrate.

[0452] Here, in the transistor 400 shown in FIG. 44 , a semiconductor region 313 (a part of a substrate 311) where a channel is formed has a convex shape. A conductive layer 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulating layer 315 interposed therebetween. Note that the conductive layer 316 may be made of a material that adjusts the work function. Such a transistor 400 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulating layer that is in contact with the top of the convex portion and functions as a mask for forming the convex portion may be provided. Here, the case where the convex portion is formed by processing a part of the semiconductor substrate is shown, but a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0453] Note that the transistor 400 shown in FIG. 44 is just an example, and the structure is not limited thereto. It is preferable to use an appropriate transistor depending on the circuit configuration or driving method.

[0454] Between each structure, a wiring layer provided with an interlayer film, wiring, and plugs may be provided. Furthermore, multiple wiring layers may be provided depending on the design. Furthermore, in this specification, the wiring and the plug conducting with the wiring may be integrated. That is, there are cases where a part of the conductor functions as the wiring, and cases where a part of the conductor functions as the plug.

[0455] For example, an insulating layer 320, an insulating layer 301, an insulating layer 324, and an insulating layer 326 are stacked in this order as an interlayer film over the transistor 400. A conductive layer 328 and the like are embedded in the insulating layer 320 and the insulating layer 301. A conductive layer 330 and the like are embedded in the insulating layer 324 and the insulating layer 326. The conductive layer 328 and the conductive layer 330 function as contact plugs or wirings.

[0456] The insulating film having a function as an interlayer film may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulating layer 301 may be planarized by a planarization process using a CMP method or the like to improve the planarity.

[0457] A wiring layer may be provided over the insulating layer 326 and the conductive layer 330. For example, in FIG. 44 , an insulating layer 350, an insulating layer 357, an insulating layer 352, and an insulating layer 353 are stacked in this order over the insulating layer 326 and the conductive layer 330. A conductive layer 356 is formed in the insulating layer 350, the insulating layer 357, and the insulating layer 352, and a conductive layer 358 is formed in the insulating layer 353. The conductive layer 356 and the conductive layer 358 function as contact plugs or wirings. For example, the transistor 400 is connected to the memory cell 10 in the memory layer 60 via the conductive layer 358, the conductive layer 356, the conductive layer 330, and the like, via a wiring VCP, which will be described later. Note that although FIG. 44 shows a configuration in which the transistor 400 is connected to the wiring VCP, the transistor 400 may be connected to another wiring.

[0458] <Configuration Example of Memory Layer 60> Next, the memory layers 60_1 to 60_100 will be described.

[0459] 44, each of the memory layers 60_1 to 60_100 includes the memory element MC shown in FIGS. 1A to 1C described in Embodiment 1 as the memory cell 10 shown in FIGS. 43A and 43B. Therefore, in FIG. 44, the memory cell 10 includes the transistor MN shown in FIGS. 1A to 1C. Note that for a specific configuration example and a manufacturing method of the transistor MN, refer to Embodiments 1 and 2.

[0460] 44, a plurality of wirings WL, a plurality of wirings BL, a plurality of wirings SL, and a plurality of wirings BGL extend in each of the memory layers 60_1 to 60_100. In particular, the wirings WL in FIG. 44 are formed by the conductive layer ME5 shown in FIGS. 1A to 1C. The wirings BGL in FIG. 44 are formed by the conductive layer ME2 shown in FIGS. 1A to 1C. The wirings BL in FIG. 44 are formed by the conductive layer ME3 shown in FIGS. 1A to 1C. The wirings SL in FIG. 44 are formed by the conductive layer ME1 shown in FIGS. 1A to 1C.

[0461] 44, the wiring BL is disposed above the wiring SL, and part of the wiring SL is illustrated as the source or drain of the transistor MN, and part of the wiring BL is illustrated as the other of the source or drain of the transistor MN, but the wiring SL and the wiring BL may be interchanged. In other words, the wiring SL may be disposed above the wiring BL, and part of the wiring BL may be the source or drain of the transistor MN, and part of the wiring SL may be the other of the source or drain of the transistor MN.

[0462] Further, a wiring VCP is provided in each of the memory layers 60_1 to 60_100 to connect to a circuit included in the driver circuit layer 50. The wiring VCP is formed of a conductive layer embedded in an opening provided in each of the interlayer films of the memory layers 60_1 to 60_100. Note that although an example in which the wiring BL included in the memory layer 60 is connected to the conductive layer 358 having a function as a wiring via the wiring VCP is shown in FIG. 44 , the wiring WL, the wiring SL, or the wiring BGL may be connected to the conductive layer 358 having a function as a wiring via the wiring VCP.

[0463] 44 corresponds to the wiring WL shown in FIG. 3 and functions as a first write data line and a read word line for the memory cell 10, for example. That is, the wiring WL functions as a wiring that transmits data to be written to the memory cell 10 and as a wiring that applies a selection signal (which may be called a variable potential (including, for example, a pulse signal and a pulse voltage)). Depending on the situation, the wiring WL may also function as a wiring that applies a fixed potential, for example.

[0464] The wiring BL corresponds to the wiring BL shown in FIG. 3 , for example, and functions as a second write data line for the memory cell 10. The wiring SL corresponds to the wiring SL shown in FIG. 3 , for example, and functions as a third write data line and a source line for the memory cell 10. In particular, when data is written to the memory cell 10, a signal with the logic of data transmitted to the wiring WL inverted is transmitted to the wiring BL and the wiring SL. The wiring BL also functions as a read bit line, for example. That is, when data is read from the memory cell 10, a data signal read from the memory cell 10 is transmitted to the wiring BL. The wiring SL may also function as a wiring that applies a fixed potential when data is read from the memory cell 10.

[0465] 3, and has a function as a wiring that applies different fixed potentials when writing or reading data to or from the memory cell 10. The fixed potential can be, for example, a low-level potential during a write operation and a high-level potential during a read operation. When neither writing nor reading data to or from the memory cell 10 is performed, the fixed potential can be a low-level potential, a ground potential, a negative potential, or the like.

[0466] Next, a configuration example of the memory layer 60 in a plan view will be described.

[0467] 45 is a plan view schematic diagram showing an example of a memory cell array MCA in which memory cells 10 are arranged in a matrix in a memory layer 60. Also, Fig. 45 shows memory cells 10 selected from the i-th row (where i is an integer of 1 to m-1 inclusive) to the i+1-th row and from the j-th row (where j is an integer of 1 to n-1 inclusive) to the j+1-th row, among the memory cells 10 included in the memory cell array MCA. Also, only memory cell 10[i, j] is shown as the reference symbol for the memory cells 10.

[0468] Therefore, Figure 45 shows only wiring WL[i] and wiring WL[i+1] from among the multiple wirings WL extending within the memory cell array MCA. Also, Figure 45 shows only wiring BGL[i] and wiring BL[j+1] from among the multiple wirings BGL extending within the memory cell array MCA. Also, Figure 45 shows only wiring BL[j] and wiring BL[j+1] from among the multiple wirings BL extending within the memory cell array MCA. Also, Figure 45 shows only wiring SL[j] and wiring SL[j+1] from among the multiple wirings SL extending within the memory cell array MCA.

[0469] 45, the wirings WL and BGL extend parallel or substantially parallel to each other and in the Y direction. The wirings SL and BL extend parallel or substantially parallel to each other and in the X direction. The wirings WL and BL are arranged so as to be orthogonal or substantially orthogonal to each other.

[0470] Furthermore, the conductive layer ME5 forming the wiring WL is provided so as to be shared by each of the plurality of memory cells 10 arranged in the X direction. Specifically, in Fig. 45, the conductive layer ME5 of each of the memory cells 10[i, j] and 10[i, j+1] is provided so as to be shared as the wiring WL[i], and the conductive layer ME5 of each of the memory cells 10[i+1, j] and 10[i+1, j+1] is provided so as to be shared as the wiring WL[i+1].

[0471] Similarly, the conductive layer ME3 forming the wiring BL is provided so as to be shared by each of the multiple memory cells 10 arranged in the Y direction. Specifically, in Fig. 45, the conductive layer ME3 of each of the memory cells 10[i, j] and 10[i+1, j] is provided so as to be shared as the wiring BL[j], and the conductive layer ME3 of each of the memory cells 10[i, j+1] and 10[i+1, j+1] is provided so as to be shared as the wiring BL[j+1].

[0472] Similarly, the conductive layer ME2 forming the wiring BGL is provided so as to be shared by each of the multiple memory cells 10 arranged in the X direction. Specifically, in Fig. 45, the conductive layer ME2 of each of the memory cells 10[i, j] and 10[i, j+1] is provided so as to be shared as the wiring BGL[i], and the conductive layer ME2 of each of the memory cells 10[i+1, j] and 10[i+1, j+1] is provided so as to be shared as the wiring BGL[i+1].

[0473] Similarly, the conductive layer ME1 forming the wiring SL is provided so as to be shared by each of the multiple memory cells 10 arranged in the Y direction. Specifically, in Fig. 45, the conductive layer ME1 of each of the memory cells 10[i, j] and 10[i+1, j] is provided so as to be shared as the wiring SL[j], and the conductive layer ME1 of each of the memory cells 10[i, j+1] and 10[i+1, j+1] is provided so as to be shared as the wiring SL[j+1].

[0474] Note that the configuration of the memory cell array MCA in the semiconductor device of one embodiment of the present invention is not limited to that shown in Fig. 45. For example, the direction in which the wirings WL, BL, BGL, and SL extend is not limited to that shown in Fig. 45.

[0475] For example, in the memory cell array MCA of the semiconductor device of one embodiment of the present invention, the wirings WL and BL may be configured so as to be orthogonal or not substantially orthogonal to each other. Figure 46 shows, as an example, a configuration in which the wirings WL and BGL are provided parallel to each other or substantially parallel to each other, the wirings SL and BL are provided parallel to each other or substantially parallel to each other, and the wirings WL (or BGL) and BL (or SL) intersect at an angle φ. Note that φ is an acute angle formed by the u direction in which the wirings WL (or BGL) extend and the v direction in which the wirings BL (or SL) extend, and can be greater than 0 degrees and less than 90 degrees.

[0476] Fig. 47 is a schematic perspective view showing an example of a memory cell array MCA in which memory cells 10 are arranged in a matrix, which is included in the memory layer 60 of Fig. 44. Fig. 47 can also be said to be a schematic perspective view of the memory cell array MCA shown in Fig. 45. Note that Fig. 47 omits some insulating layers in order to clearly show the conductive layers and semiconductor layers.

[0477] 47 shows, as in Fig. 45, memory cells 10 from the i-th row to the i+1-th row and from the j-th row to the j+1-th row selected from the memory cells 10 included in the memory cell array MCA. As the reference numerals of the memory cells 10, only memory cell 10[i+1, j+1] is selected and shown.

[0478] 48 is a schematic perspective view of the stacked structure of memory layers 60_1 to 60_100 in the memory device MDV0A in FIG. 44. In other words, FIG. 48 shows a configuration in which 100 memory cell arrays MCA in FIG. 47 are stacked. By stacking multiple memory layers 60, the storage capacity of the memory device MDV0A can be increased. Furthermore, the memory device of one embodiment of the present invention is not limited in the number of memory layers 60, and may have 1 to 99 layers, or more than 100 layers.

[0479] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0480] In this embodiment, electronic components, electronic devices, mainframes, space equipment, and data centers (also referred to as data centers (DCs)) that can use the semiconductor device described in the above embodiment will be described. The electronic components, electronic devices, mainframes, space equipment, and data centers that use the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0481] [Electronic Component] FIG. 49A shows a perspective view of a substrate (mounting substrate 704) on which electronic component 700 is mounted. Electronic component 700 shown in FIG. 49A has semiconductor device 710 inside mold 711. FIG. 49A omits some parts to show the interior of electronic component 700. Electronic component 700 has lands 712 on the outside of mold 711. Lands 712 are connected to electrode pads 713, and electrode pads 713 are connected to semiconductor device 710 via wires 714. Electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and connected on printed circuit board 702 to complete mounting substrate 704.

[0482] The semiconductor device 710 also includes a drive circuit layer 715 and a memory layer 716. The memory layer 716 has a configuration in which a plurality of memory cell arrays are stacked. The stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology (e.g., TSV (Through Silicon Via)) or bonding technology such as Cu-Cu direct bonding. By configuring the drive circuit layer 715 and the memory layer 716 as a monolithic stacked configuration, for example, a so-called on-chip memory configuration can be achieved in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster.

[0483] Furthermore, by configuring an on-chip memory, it is possible to reduce the size of connection wiring, etc., compared to technologies that use through electrodes such as TSVs, and therefore it is possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0484] It is also preferable that the memory cell arrays included in the memory layer 716 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked structure, it is possible to improve either or both of the memory bandwidth and the memory access latency. Note that the bandwidth refers to the amount of data transferred per unit time, and the access latency refers to the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 716, it is more difficult to form a monolithic stacked structure than when OS transistors are used. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked structure.

[0485] The semiconductor device 710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes during the semiconductor chip manufacturing process. Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0486] 49B shows a perspective view of electronic component 730. Electronic component 730 is an example of a SiP (System in Package) or MCM (Multi-Chip Module). Electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 provided on interposer 731.

[0487] The electronic component 730 shows an example in which the semiconductor device 710 is used as a high bandwidth memory (HBM). The semiconductor device 735 can be used in an integrated circuit such as a CPU, a GPU, or an FPGA (Field Programmable Gate Array).

[0488] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 732. For example, a silicon interposer or a resin interposer can be used as the interposer 731.

[0489] The interposer 731 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 731, and the integrated circuits and the package substrate 732 are connected using the through electrodes. In addition, in a silicon interposer, TSVs can also be used as through electrodes.

[0490] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0491] Furthermore, in SiP and MCM using silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, since the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on the interposer.

[0492] On the other hand, when connecting multiple integrated circuits with different terminal pitches using a silicon interposer and TSVs, space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 730, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings necessary to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked configuration using OS transistors is preferable. Also, for example, a memory cell array stacked using TSVs and a monolithically stacked memory cell array can be combined. A structure combining a memory cell array stacked using TSVs and a monolithically stacked memory cell array is sometimes called a composite structure.

[0493] Furthermore, if the temperature of the electronic component 730 increases due to heat generated by electric current or the like, the characteristics of the circuit elements (e.g., transistors) included in the electronic component 730 may be degraded, and therefore, it is preferable to provide a heat sink (heat sink) so as to overlap the electronic component 730. When providing a heat sink, it is preferable to align the height of the integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the semiconductor device 710 and the height of the semiconductor device 735.

[0494] Electrodes 733 may be provided on the bottom of package substrate 732 in order to mount electronic component 730 on another substrate. FIG. 49B shows an example in which electrodes 733 are formed with solder balls. By providing solder balls in a matrix on the bottom of package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Electrodes 733 may also be formed with conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0495] The electronic component 730 can be mounted on other substrates using various mounting methods, including, but not limited to, BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0496] [Electronic Device] Next, a perspective view of an electronic device 6500 is shown in FIG. 50A . The electronic device 6500 shown in FIG. 50A is a portable information terminal that can be used as a smartphone. The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and a control device 6509. Note that the control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a memory device. The semiconductor device of one embodiment of the present invention can be applied to the display portion 6502, the control device 6509, and the like.

[0497] 50B is an information terminal that can be used as a laptop personal computer. The electronic device 6600 includes a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display portion 6615, and a control device 6616. Note that the control device 6616 includes, for example, one or more selected from a CPU, a GPU, and a storage device. The semiconductor device of one embodiment of the present invention can be used for the display portion 6615, the control device 6616, and the like.

[0498] The semiconductor device of one embodiment of the present invention is preferably used for the control devices 6509 and 6616 because power consumption can be reduced.

[0499] [Mainframe] Next, Fig. 50C shows a perspective view of a mainframe 5600. The mainframe 5600 shown in Fig. 50C has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe 5600 is sometimes called a supercomputer.

[0500] The computer 5620 can have the configuration shown in the perspective view in Fig. 50D, for example. In Fig. 50D, the computer 5620 has a motherboard 5630, which has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0501] PC card 5621 shown in Figure 50E is an example of a processing board equipped with a CPU, GPU, storage device, etc. PC card 5621 has board 5622. Board 5622 also has connection terminals 5623, 5624, 5625, semiconductor devices 5626, 5627, 5628, and 5629. Note that Figure 50E illustrates semiconductor devices other than semiconductor devices 5626, 5627, and 5628, but for these semiconductor devices, the following descriptions of semiconductor devices 5626, 5627, and 5628 can be referenced.

[0502] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0503] The connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621, inputting signals, etc. Furthermore, they can be, for example, interfaces for outputting signals calculated by the PC card 5621. Examples of the standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of the standards for each include HDMI (registered trademark).

[0504] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 can be connected to the board 5622 by inserting the terminal into a socket (not shown) provided on the board 5622.

[0505] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 can be connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 730 can be used for the semiconductor device 5627.

[0506] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 can be connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5628 include a memory device. For example, the electronic component 700 can be used as the semiconductor device 5628.

[0507] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations necessary for learning and inference in artificial intelligence, for example.

[0508] [Space Equipment] The semiconductor device of one embodiment of the present invention can be suitably used in space equipment (for example, equipment having a function of processing and storing information).

[0509] The semiconductor device of one embodiment of the present invention can include an OS transistor. The OS transistor exhibits small changes in electrical characteristics due to radiation exposure. That is, the OS transistor has high radiation resistance and can be suitably used in an environment where radiation may be incident. For example, the OS transistor can be suitably used in outer space.

[0510] Figure 51 shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Note that Figure 51 illustrates a planet 6804 in outer space. Note that outer space refers to an altitude of 100 km or higher, for example, but the outer space described in this specification may also include the thermosphere, mesosphere, and stratosphere.

[0511] 51 , a battery management system (also referred to as a BMS) or a battery control circuit may be provided for the secondary battery 6805. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it consumes low power and has high reliability even in space.

[0512] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0513] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is preferable to provide a secondary battery 6805 in the satellite 6800. Note that the solar panel may be called a solar cell module.

[0514] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received, for example, by a receiver on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0515] The control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that the semiconductor device of one embodiment of the present invention is preferably used for the control device 6807. The OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure than a Si transistor. That is, the OS transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.

[0516] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Or, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0517] Although an artificial satellite is given as an example of space equipment in this embodiment, the invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

[0518] As described above, OS transistors have excellent advantages over Si transistors, such as the ability to achieve a wide memory bandwidth and high radiation resistance.

[0519] [Data Center] The semiconductor device of one embodiment of the present invention can be suitably used in a storage system applied to, for example, a data center. The data center is required to perform long-term management of data, such as ensuring data immutability. To manage long-term data, the building must be large enough to accommodate the installation of storage and servers for storing a huge amount of data, a stable power supply for maintaining the data, and cooling equipment required for maintaining the data.

[0520] By using a storage device according to one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and to miniaturize the storage device that stores the data. This makes it possible to miniaturize the storage system, the power supply for storing data, and the cooling equipment. This allows for space saving in the data center.

[0521] Furthermore, the storage device of one embodiment of the present invention consumes low power, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the storage device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0522] Fig. 52 shows a storage system applicable to a data center. The storage system 7000 shown in Fig. 52 has a plurality of servers 7001sb as hosts 7001 (illustrated as Host Computers). It also has a plurality of storage devices 7003md as storage 7003 (illustrated as Storage). The host 7001 and storage 7003 are shown connected via a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as Storage Controller).

[0523] The host 7001 corresponds to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0524] Although the storage 7003 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, this time is significantly longer than the time required for DRAM (Dynamic Random Access Memory), which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 7003, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0525] The above-mentioned cache memory is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.

[0526] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refresh operations can be reduced, and power consumption can be reduced.

[0527] Note that the application of the semiconductor device of one embodiment of the present invention to any one or more selected from electronic components, electronic devices, mainframe computers, space equipment, and data centers is expected to have an effect of reducing power consumption. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present inventio...

Claims

a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a first insulating layer, a second insulating layer, and a semiconductor layer; a first interlayer film is located on the first conductive layer; a second interlayer film is located on the first interlayer film; the second conductive layer is sandwiched between the first interlayer film and the second interlayer film and has a region overlapping the first conductive layer; the first interlayer film, the second conductive layer, and the second interlayer film have a first opening reaching the first conductive layer; the first insulating layer has a region in contact with the first interlayer film, the second conductive layer, and the second interlayer film in the first opening; the third conductive layer has a region overlapping the first insulating layer and a region overlapping the second interlayer film; the third conductive layer and the first insulating layer have a second opening reaching the first conductive layer; a third interlayer film is located on the third conductive layer; the third interlayer film has a third opening reaching the third conductive layer; the third opening has a region that includes an overlap with the second opening in a plan view, the semiconductor layer has a region in contact with the first conductive layer, the first insulating layer, and the third conductive layer in the second opening; the semiconductor layer has a region in contact with the third conductive layer and the third interlayer film in the third opening; the second insulating layer has a region in contact with the semiconductor layer in the second opening and the third opening; the fourth conductive layer has a region facing the semiconductor layer with the second insulating layer interposed therebetween in the second opening and the third opening; the second insulating layer comprises a material that may have ferroelectric properties; Memory element. 　 In claim 1, a fifth conductive layer; a fourth interlayer film is located on each of the upper surfaces of the second insulating layer and the fourth conductive layer; the fourth interlayer film has a fourth opening reaching the fourth conductive layer; the fifth conductive layer has a region in contact with an upper surface of the fourth conductive layer and a side surface of the fourth interlayer film in the fourth opening; the fifth conductive layer has a region in contact with an upper surface of the fourth interlayer film; Memory element. 　 In claim 2, the first conductive layer and the third conductive layer are positioned to overlap each other and extend in a first direction; the second conductive layer and the fifth conductive layer are positioned to overlap each other and extend in a second direction, In a plan view, an angle between the first direction and the second direction is greater than 0 degrees and is equal to or less than 90 degrees. Memory element. 　 In any one of claims 1 to 3, The material that can have ferroelectric properties has an oxide containing one or both of hafnium and zirconium. Memory element. 　 In any one of claims 1 to 3, the semiconductor layer has one or more elements selected from indium, zinc, and an element M in a channel formation region; The element M is one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, magnesium, and antimony; Memory element. 　 A memory cell array including the memory element according to any one of claims 1 to 3, and a circuit layer, the memory cell array is located above the circuit layer; the circuit layer includes a first drive circuit, a second drive circuit, a third drive circuit, and a fourth drive circuit; the first driving circuit has a function of transmitting a data signal corresponding to data to the fourth conductive layer when writing data to the memory element, and a function of transmitting a selection signal for selecting the memory element to the fourth conductive layer when reading the data from the memory element; The second drive circuit a function of transmitting a signal obtained by inverting the logic of the data signal to each of the first conductive layer and the third conductive layer when writing the data to the memory element; a function of precharging one of the first conductive layer and the third conductive layer with a first potential and applying a second potential to the other of the first conductive layer and the third conductive layer when reading the data from the memory element; the third driving circuit has a function of transmitting a selection signal to the second conductive layer to select the memory element when reading the data from the memory element; the fourth driver circuit has a function of reading out a potential of one of the first conductive layer and the third conductive layer as the data read from the memory element; storage device. 　 An electronic device comprising the storage device of claim 6 and a housing.

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