Semiconductor device and power conversion device

Abstract

A semiconductor device comprising: a gallium oxide semiconductor layer; an impurity layer which is formed in the surface of a first main face of the gallium oxide semiconductor layer and has acceptor-type first impurities, in which at least some of the first impurities have been activated; a first recess which is provided by removing a part of the impurity layer and the gallium oxide semiconductor layer, and is shallower than the impurity layer; a first main electrode which is provided upon the first main face; and a second main electrode which is provided upon a second main face of the gallium oxide semiconductor layer.

Description

Semiconductor device and power conversion device

[0001] The present disclosure relates to a semiconductor device and a power conversion device, and more particularly to a semiconductor device made of gallium oxide and a power conversion device using the semiconductor device.

[0002] Gallium oxide (Ga ２ O ３ ) has a band gap exceeding that of silicon carbide (SiC) and gallium nitride (GaN), and is an advantageous material for increasing the breakdown voltage and decreasing the resistance of power devices. ２ O ３ is expected to be a material for next-generation power devices.

[0003] Ga ２ O ３ As a semiconductor device using the above, for example, as disclosed in FIG. 4 of Patent Document 1, a DI-MOS (Double Implanted Metal-Oxide-Semiconductor) structure using a deep acceptor layer formed by implanting nitrogen (N) into an n-type gallium oxide layer is known.

[0004] International Publication No. 2018 / 199241

[0005] Generally, the fabrication of DI-MOS structures requires an annealing process to recover implantation damage and activate the implanted ion species. ２ O ３ Annealing the surface of a semiconductor device can easily cause defects. In particular, defects occurring in the region under the gate electrode, known as the JFET region in a DI-MOS structure, can reduce the donor concentration, potentially affecting the rise of the transistor's Id-Vd characteristics. Even if the JFET region is doped with a donor element such as silicon to restore the donor concentration reduced by the annealing process, defects remain, potentially reducing the breakdown voltage of the semiconductor device. Furthermore, if the defective portion is completely etched and removed after the annealing process, the thickness of the well layer is reduced, potentially reducing the breakdown voltage of the semiconductor device.

[0006] The present disclosure has been made to solve the above-mentioned problems, and aims to provide a semiconductor device in which a decrease in breakdown voltage is suppressed, and a power conversion device using the semiconductor device.

[0007] The semiconductor device according to the present disclosure includes a gallium oxide semiconductor layer; an impurity layer formed within a surface of a first main surface of the gallium oxide semiconductor layer and containing acceptor-type first impurities, at least a portion of which is activated; a first recess formed by removing a portion of the impurity layer and the gallium oxide semiconductor layer and shallower than the impurity layer; a first main electrode provided on an upper portion of the first main surface; and a second main electrode provided on an upper portion of a second main surface of the gallium oxide semiconductor layer.

[0008] According to the semiconductor device according to the present disclosure, the area where the first recess is provided is limited and the thickness of the impurity layer is maintained, so that a decrease in breakdown voltage can be suppressed.

[0009] FIG. 1 is a cross-sectional view showing a structure of a semiconductor device according to a first embodiment. FIG. 2 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a first embodiment. FIG. 3 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a first embodiment. FIG. 4 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a first embodiment. FIG. 5 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a first embodiment. FIG. 6 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a first embodiment. FIG. 7 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a first embodiment. FIG. 8 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a first embodiment. FIG. 9 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a first embodiment. FIG. 10 is a diagram showing an effect of the semiconductor device according to the first embodiment. FIG. 11 is a cross-sectional view showing a structure of a semiconductor device according to a second embodiment. FIG. 12 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment. FIG. 13 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a third embodiment. FIG. 14 is a cross-sectional view illustrating a structure of a semiconductor device according to a fourth embodiment. FIG. 15 is a cross-sectional view illustrating a structure of a semiconductor device according to a fifth embodiment. FIG. 16 is a block diagram showing a power conversion device according to a sixth embodiment.

[0010] Hereinafter, embodiments of the technology according to the present disclosure will be described with reference to the drawings. The present technology is not limited to the embodiments shown here, and can be modified as appropriate without departing from the spirit of the technology. In addition, in the drawings shown below, the scale of each component or each component may differ from the actual scale in order to facilitate understanding, and the same applies between the drawings.

[0011] In addition, in the following description, terms such as "upper" and "lower" that indicate specific positions and directions may be used, but these terms are used for convenience to make it easier to understand the contents of the embodiments, and do not relate to the directions in which they are actually implemented.

[0012] First Embodiment Device Configuration FIG. 1 is a diagram showing the configuration of a semiconductor device 100 according to a first embodiment, and is a cross-sectional view showing the structure of a unit cell constituting the semiconductor device. A plurality of unit cells shown in FIG. 1 are arranged in an active area of ​​the semiconductor device 100. In this embodiment, a semiconductor device using gallium oxide (Ga ２ O ３ ), especially β-type gallium oxide (β-Ga ２ O ３ Here, the crystal structure of gallium oxide is not limited to β type, and may be α type or the like.

[0013] The semiconductor device 100 according to the first embodiment is a β-Ga ２ O ３ The gallium oxide semiconductor layer 20 is formed using a gallium oxide semiconductor layer 20 consisting of an n-type gallium oxide support layer 1, a first gallium oxide layer 2 provided on the n-type gallium oxide support layer 1, a second gallium oxide layer 3 provided on the first gallium oxide layer 2, and a third gallium oxide layer 4 provided on the second gallium oxide layer 3. The upper surface of the gallium oxide semiconductor layer 20 in FIG. 1 (the upper surface of the third gallium oxide layer 4) is defined as the "first main surface," and the lower surface of the gallium oxide semiconductor layer 20 (the lower surface of the n-type gallium oxide support layer 1) is defined as the "second main surface."

[0014] The n-type gallium oxide support layer 1 is an n-type β-Ga layer having a (001) plane as its main surface. ２ O ３ Here, the n-type gallium oxide support layer 1 may be a semiconductor substrate made of gallium oxide, or may be a semiconductor substrate made of a material different from gallium oxide, on which a layer made of gallium oxide epitaxially grown is separated. In addition, the crystal plane of the n-type gallium oxide support layer 1 is not limited to the (001) plane, and may have other plane orientations.

[0015] The first gallium oxide layer 2 contains at least one of silicon, chlorine, tin, and germanium, which are n-type dopants, in an amount of 1×10 １６ cm －３ It is added at a moderate concentration.

[0016] The second gallium oxide layer 3 (impurity layer) contains 1×10 １８ cm －３ The second gallium oxide layer 3 is doped at a concentration of about 1000 Å, and at least a portion of the impurities is activated. Candidates for acceptor-type impurities include, for example, nitrogen, magnesium, zinc, and phosphorus. The second gallium oxide layer 3 may contain linear defects extending in directions including the

[010] direction due to the activation annealing treatment, but these may be present to an extent that does not affect the device characteristics. By not removing the defects, the defect removal process can be reduced, and productivity can be improved.

[0017] The third gallium oxide layer 4 contains at least one of silicon, chlorine, tin, and germanium, which are n-type dopants, at a concentration of 5×10 １９ cm －３ It is added at a moderate concentration.

[0018] A plurality of gate recesses 5 are formed in the first main surface of the gallium oxide semiconductor layer 20. The gate recesses 5 are concave portions provided in the first main surface of the gallium oxide semiconductor layer 20, formed by partially removing the first gallium oxide layer 2, the second gallium oxide layer 3, and the third gallium oxide layer 4. The bottom of the gate recess 5 is in contact with the first gallium oxide layer 2, and the side surfaces of the gate recess 5 are in contact with the second gallium oxide layer 3 and the third gallium oxide layer 4.

[0019] A gate insulating film 6 is formed from the inner surface of the gate recess 5 to a part of the upper surface of the third gallium oxide layer 4. A gate electrode 7 is formed on the gate insulating film 6 so as to fill the gate recess 5. The gate electrode 7 is preferably formed of polysilicon, and in particular, a high concentration p-type (p ＋ It is more preferable that the gate electrode is formed of polysilicon (type).

[0020] An interlayer insulating film 8 is formed on the first main surface of the gallium oxide semiconductor layer 20 so as to cover the gate electrode 7 and the outside thereof. A source pad electrode 10 is formed on the interlayer insulating film 8. The gate electrode 7 and the source pad electrode 10 are electrically isolated from each other by the interlayer insulating film 8.

[0021] A contact hole 9 is formed in the interlayer insulating film 8, reaching the gallium oxide semiconductor layer 20. The source pad electrode 10 is electrically connected to the third gallium oxide layer 4 of the gallium oxide semiconductor layer 20 through the contact hole 9. A source recess 12 is formed in the gallium oxide semiconductor layer 20 (third gallium oxide layer 4) at the bottom of the contact hole 9, and the source pad electrode 10 is connected to the third gallium oxide layer 4 within the source recess 12.

[0022] A drain electrode 11 is formed on the second major surface of the gallium oxide semiconductor layer 20. The drain electrode 11 is electrically connected to the n-type gallium oxide support layer 1.

[0023] <Manufacturing Method> Next, an example of a method for manufacturing the semiconductor device 100 according to the first embodiment will be described with reference to Figures 2 to 9. Figures 2 to 9 are cross-sectional views showing the manufacturing method of the semiconductor device 100 according to the first embodiment in the order of steps.

[0024] First, a conductive n-type gallium oxide support layer 1 having a (001) plane as its principal surface is prepared. Then, a first gallium oxide layer 2 is formed on the n-type gallium oxide support layer 1 using a halide vapor phase epitaxy (HVPE) method, a metal organic chemical vapor deposition (MOCVD) method, a molecular beam epitaxy (MBE) method, or the like, as shown in Fig. 2. This results in a gallium oxide semiconductor layer 20 consisting of the n-type gallium oxide support layer 1 and the first gallium oxide layer 2.

[0025] The thickness of the n-type gallium oxide support layer 1 can be determined depending on the breakdown voltage level of the semiconductor device 100, and can be, for example, about 10 μm. The donor concentration of the n-type gallium oxide support layer 1 is 1×10 １６ cm －３ That's about it.

[0026] Next, an implantation mask is formed on the first main surface of the gallium oxide semiconductor layer 20 (on the upper surface of the first gallium oxide layer 2), and then at least one dopant among dopants that form acceptor levels, such as nitrogen, zinc, phosphorus, and magnesium, is ion-implanted into the gallium oxide semiconductor layer 20. The implantation energy at this time is about 20 keV to 500 keV, and the dose is 1×10 １４ cm －２ To mitigate damage caused by ion implantation, a heated implantation method or a thermal diffusion method may be used.

[0027] After removing the implantation mask, a heat treatment is performed to recover damage caused by the dopant implantation and to activate the dopant. The heat treatment temperature is about 800°C to 1200°C, and the heat treatment atmosphere is nitrogen, oxygen, or a mixture thereof. As a result, a second gallium oxide layer 3 having a depth of about 700 nm is formed on the upper layer of the first gallium oxide layer 2.

[0028] Subsequently, an implantation mask is formed on the first main surface of the gallium oxide semiconductor layer 20 (on the upper surface of the second gallium oxide layer 3), and silicon (Si) ions are then implanted into the gallium oxide semiconductor layer 20. The implantation energy at this time is approximately 10 keV to 200 keV, and the dose is 1×10 １５ cm －２ After the implantation mask is removed, a heat treatment is performed at a temperature of about 900° C. to recover from damage caused by the ion implantation and to activate the dopants. As a result, a third gallium oxide layer 4 having a depth of about 200 nm is formed on the upper layer of the second gallium oxide layer 3.

[0029] As a result, as shown in FIG. 3, a gallium oxide semiconductor layer 20 is formed, which is composed of an n-type gallium oxide support layer 1, a first gallium oxide layer 2, a second gallium oxide layer 3, and a third gallium oxide layer 4.

[0030] Subsequently, the first main surface of the gallium oxide semiconductor layer 20, including parts of the second gallium oxide layer 3 and the third gallium oxide layer 4, is partially removed to form the gate recess 5. As a forming method, an etching mask having an opening corresponding to the part to be removed is formed on the first main surface of the gallium oxide semiconductor layer 20, and the gallium oxide semiconductor layer 20 is dry-etched to form the gate recess 5 in the gallium oxide semiconductor layer 20 as shown in FIG.

[0031] The etching gas is chlorine (Cl) or boron trichloride (BCl ３ A chlorine-based gas such as chlorine-based gallium oxide (C10) or chlorine-based gallium oxide (C20) is preferred. The depth of the gate recess 5 is set to be deeper than the third gallium oxide layer 4 and shallower than the second gallium oxide layer 3. This allows the corners of the gate recess 5 to be protected by the second gallium oxide layer 3, thereby improving the breakdown voltage. More preferably, etching is performed so that the lower corners of the gate recess 5 are rounded, which makes it difficult for an electric field to concentrate, further improving the breakdown voltage.

[0032] Subsequently, the etching mask is removed, and the gallium oxide semiconductor layer 20 is subjected to RCA cleaning. Then, as shown in FIG. 5, Al is deposited on the first main surface of the gallium oxide semiconductor layer 20 including the inner surface of the gate recess 5. ２ O ３The gate insulating film 6 is formed from an Al film. ２ O ３ The film may be formed by atomic layer deposition (ALD). The gate insulating film 6 may have a multi-layer structure, for example, SiO ２ , HfO ２ , AlON, AlN, SiN, SiON and Al ２ O ３ It is assumed that the gate insulating film 6 is a laminated film made of two or more materials selected from the above.

[0033] Thereafter, a gate electrode 7 is formed on the entire surface of the gate insulating film 6. The gate electrode 7 is made of, for example, a high concentration p-type (p ＋ A polysilicon film of the type (type) is suitable.

[0034] Next, the gate electrode 7 is etched through an etching mask using a chlorine-based gas, thereby leaving the gate electrode 7 in the gate recess 5 and outside thereof. As a result, the gate electrode 7 is formed in the gate recess 5 and outside thereof, as shown in FIG. 6 . At this time, the edge of the gate electrode 7 outside the gate recess 5 is left to a position beyond the edge of the third gallium oxide layer 4. As a result, a gate overlap structure is formed in which the gate electrode 7 overlaps the edge of the third gallium oxide layer 4, and an increase in on-resistance is suppressed.

[0035] 7, an interlayer insulating film 8 is formed on the first main surface of the gallium oxide semiconductor layer 20. It is known that the electric field generated at the interface between the semiconductor and the insulating film is affected by the relative dielectric constants of the semiconductor and the insulating film. ２ The dielectric constant of the film is 3.9, which is ２ O ３ Therefore, the interlayer insulating film 8 in contact with the gallium oxide semiconductor layer 20 is made of SiO ２ If the interlayer insulating film 8 is made of a gallium oxide semiconductor layer 20, an electric field nearly three times that of the gallium oxide semiconductor layer 20 will be applied to the interlayer insulating film 8. Therefore, from the viewpoint of breakdown resistance, the relative dielectric constant of the interlayer insulating film 8 is set to be equal to that of a silicon oxide film (SiO ２) is preferable. However, generally, the relative dielectric constant and the band gap are inversely proportional to each other, and the higher the relative dielectric constant of a material, the smaller the band gap. Therefore, if the interlayer insulating film 8 is made of a material with a high relative dielectric constant, it is difficult to ensure a sufficient band offset with respect to the gallium oxide semiconductor layer 20. Therefore, it is preferable to use a material with a high relative dielectric constant of SiO ２ The lower layer is a high-k film with a higher band gap than the lower layer, and the SiO ２ A two-layer structure can be used in which a high-k film is placed on the upper layer. This allows for both high breakdown voltage and low leakage current. ２ , HfO ２ , Al ２ O ３ , BaTiO ３ , MgF ２ Possible reasons include:

[0036] 8, contact holes 9 are formed in the interlayer insulating film 8 by selective dry etching using photolithography. The contact holes 9 penetrate the interlayer insulating film 8 and the gate insulating film 6 to reach the third gallium oxide layer 4. At this time, source recesses 12 are formed in the gallium oxide semiconductor layer 20 (third gallium oxide layer 4) exposed at the bottom of the contact holes 9.

[0037] The surface of the gallium oxide semiconductor layer 20 is roughened by dry etching, that is, unevenness is formed, so that the β-Ga constituting the gallium oxide semiconductor layer 20 ２ O ３ Since the donor type defects in the source pad electrode 10 increase and the contact resistance decreases, the ohmic characteristics between the source pad electrode 10 and the third gallium oxide layer 4 improve.

[0038] Subsequently, as shown in FIG. 9, a source pad electrode 10 is formed on the interlayer insulating film 8, and a drain electrode 11 is formed on the second main surface of the gallium oxide semiconductor layer 20 (the lower surface of the n-type gallium oxide support layer 1).

[0039] The source pad electrode 10 is formed by depositing a metal film on the interlayer insulating film 8 using a sputtering device and then patterning the metal film by selective wet etching using photolithography. A Ti / Al laminated structure is suitable as the material for the source pad electrode 10. The film thickness of the source pad electrode 10 is, for example, 20 nm for Ti and 3 μm for Al.

[0040] The drain electrode 11 is formed after removing the film that has spread onto the second main surface of the gallium oxide semiconductor layer 20 using a dry etcher or a grinding / polishing device. The drain electrode 11 is formed by depositing a Ti / Au electrode on the second main surface of the gallium oxide semiconductor layer 20 using a sputtering device or an EB deposition machine. Finally, ohmic sintering is performed to complete the semiconductor device 100 of FIG. 1 .

[0041] 10 is a graph showing the results of an experiment comparing the on-current of a normal DI-MOS structure with that of semiconductor device 100 having gate recess 5 according to the first embodiment, i.e., a recessed DI-MOS structure. In Fig. 10, the horizontal axis represents the activation annealing temperature [°C] after the formation of second gallium oxide layer 3, and the temperature was changed in 50°C intervals from 900°C to 1100°C. The vertical axis represents the normalized on-current, which is normalized with the on-current during annealing at 900°C set to 1.

[0042] 10, the on-current of the normal DI-MOS structure is plotted with triangle marks, and the on-current of the recessed DI-MOS structure is plotted with square marks. In the normal DI-MOS structure, the on-current drops sharply as the annealing temperature increases, whereas in the recessed DI-MOS structure, the on-current remains almost the same as the on-current during annealing at 900°C, even when the annealing temperature increases.

[0043] That is, when β-type gallium oxide is annealed at high temperatures, the surface donor concentration decreases. Therefore, in the case of a conventional DI-MOS structure, the potential barrier in the JFET region increases as the temperature increases during annealing, such as RTA (rapid thermal annealing), resulting in a significant decrease in on-current. On the other hand, in the recessed DI-MOS structure of the present disclosure, the surface altered layer (defect layer) below the gate electrode 7 is removed when the gate recess 5 is formed, so no potential barrier is generated. This makes it easy to maintain the on-current value even after annealing at high temperatures. Furthermore, because high-temperature annealing can be performed without concern for deterioration of forward characteristics, the introduced acceptors are easily activated, reducing reverse leakage. As a result, the trade-off between on-current and off-leakage current is improved.

[0044] Furthermore, in the recessed DI-MOS structure of the present disclosure, the surface alteration layer below the gate electrode 7 is removed when the gate recess 5 is formed, thereby suppressing a decrease in the donor concentration at the outermost surface of the first gallium oxide layer 2, which serves as the drift layer. This suppresses the extension of the depletion layer from the second gallium oxide layer 3, thereby eliminating the offset in the rise of the Id-Vd characteristics of the transistor.

[0045] Furthermore, since the portion where the gate recess 5 is formed is limited to the lower portion of the gate electrode 7, the thickness of the second gallium oxide layer 3 is maintained, and punch-through is less likely to occur compared to when the entire surface alteration layer is removed by etching such as CMP (chemical mechanical polishing). As a result, a semiconductor device 100 in which a decrease in breakdown voltage is suppressed can be obtained.

[0046] Second Preferred Embodiment <Device Configuration> FIG. 11 is a diagram showing the configuration of a semiconductor device 200 according to a second preferred embodiment, and is a cross-sectional view showing the structure of a unit cell that constitutes the semiconductor device.

[0047] In the semiconductor device 200 according to the second embodiment, a source recess 12 formed in the gallium oxide semiconductor layer 20 at the bottom of the contact hole 9 penetrates the third gallium oxide layer 4 and the second gallium oxide layer 3, and reaches the first gallium oxide layer 2. The other configurations are similar to those of the semiconductor device 100 according to the first embodiment.

[0048] According to the semiconductor device 200 of the second embodiment, the source pad electrode 10 is connected to the first gallium oxide layer 2 via a Schottky connection. This allows a Schottky barrier diode (SBD) to be built into the MOSFET. Therefore, when the MOSFET is incorporated into an inverter, there is no need to provide an external freewheeling diode. This reduces the component costs of the inverter.

[0049] <Manufacturing Method> Next, an example of a manufacturing method for the semiconductor device 200 according to the second embodiment will be described with reference to Figures 12 and 13. Only differences from the manufacturing method for the semiconductor device 100 according to the first embodiment will be described.

[0050] FIG. 12 corresponds to FIG. 3 of the first embodiment, and is a cross-sectional view of a stage in which a second gallium oxide layer 3 and a third gallium oxide layer 4 have been selectively formed on the upper layer portion of the first gallium oxide layer 2 by ion implantation.

[0051] 12 , the second gallium oxide layer 3 in contact with the third gallium oxide layer 4 is provided so as to include only both end portions of the third gallium oxide layer 4 by changing the opening of the implantation mask. This is because the third gallium oxide layer 4 is not required in the portion where the contact hole 9 will be formed later. Note that the second gallium oxide layer 3 may be provided so as to cover the lower surface of the third gallium oxide layer 4. In this case, the contact hole 9 may be provided so as to penetrate the second gallium oxide layer 3 and reach the first gallium oxide layer 2.

[0052] Next, after forming the third gallium oxide layer 4, the first main surface of the gallium oxide semiconductor layer 20 including the second gallium oxide layer 3 and a part of the third gallium oxide layer 4 is partially removed to form the gate recess 5 and the source recess 12.

[0053] As a forming method, an etching mask having openings corresponding to the portions to be removed is formed on the first main surface of the gallium oxide semiconductor layer 20, and the gallium oxide semiconductor layer 20 is dry-etched to form the gate recess 5 and the source recess 12 in the gallium oxide semiconductor layer 20 as shown in Fig. 13. The region where the gate recess 5 is formed can be called the MOS region, and the region where the source recess 12 is formed can be called the SBD region.

[0054] Third Preferred Embodiment FIG. 14 is a diagram showing the configuration of a semiconductor device 300 according to a third preferred embodiment, and is a cross-sectional view showing the structure of a unit cell that constitutes the semiconductor device.

[0055] In the semiconductor device 300 according to the third embodiment, in the configuration of the semiconductor device 200 according to the second embodiment, in which the source recess 12 formed in the gallium oxide semiconductor layer 20 at the bottom of the contact hole 9 penetrates the third gallium oxide layer 4 and the second gallium oxide layer 3 and reaches the first gallium oxide layer 2, an intermediate film 13 which is a High-k film is formed between the source recess 12 and the source pad electrode 10, and the source pad electrode 10 is electrically connected to the first gallium oxide layer 2 via the intermediate film 13 in the source recess 12. The other configurations are similar to those of the semiconductor device 200 according to the second embodiment.

[0056] The manufacturing process is the same as that of the second embodiment, except that after forming contact hole 9, a step of forming intermediate film 13 by, for example, ALD on the entire surface of gallium oxide semiconductor layer 20, including source recess 12 and the inner surfaces of contact hole 9, is added. The thickness of intermediate film 13 can be determined appropriately depending on the material of the source electrode in the MOSFET, the donor species and donor concentration in the source region, etc., but it is preferably a thickness that suppresses a chemical reaction between source pad electrode 10 and first gallium oxide layer 2 while not increasing the series resistance component in the forward characteristics of the SBD, and is preferably about 100 nm or less, particularly about 10 nm or less, and further preferably about 5 nm or less.

[0057] As a high-k film, SiO ２ It has a higher dielectric constant than β-Ga ２ O ３A material with a band gap smaller than that of TiO is preferred, for example. ２ can be used, but HfO ２ , Al ２ O ３ , BaTiO ３ , MgF ２ can also be used.

[0058] The band gap of the intermediate film 13 is β-Ga ２ O ３ By making the band gap smaller than that of the first gate, no new barrier is generated in the conduction band, and the forward characteristics of the SBD are not deteriorated.

[0059] In addition, the β-Ga that constitutes the first gallium oxide layer 2 and the like ２ O ３ However, by providing an intermediate film 13 between the source recess 12 and the source pad electrode 10, the source pad electrode 10 and the β-Ga ２ O ３ This suppresses the reaction with HCl and improves temperature stability.

[0060] According to the semiconductor device 300 of the third embodiment, similarly to the semiconductor device 200 of the second embodiment, when incorporated into an inverter, the cost of components of the inverter can be reduced. In addition, by providing the intermediate film 13 of a high-k film, the forward characteristics of the SBD are not deteriorated and temperature stability is improved.

[0061] Fourth Preferred Embodiment FIG. 15 is a cross-sectional view showing the configuration of a semiconductor device 400 according to a fourth preferred embodiment, which shows a vertical SBD made of β-type gallium oxide.

[0062] The semiconductor device 400 according to the fourth embodiment is a β-Ga ２ O ３The semiconductor device 100 of the present embodiment is formed using a gallium oxide semiconductor layer 30 made of the above-mentioned gallium oxide. The gallium oxide semiconductor layer 30 is composed of an n-type gallium oxide support layer 1, a first gallium oxide layer 2 provided on the n-type gallium oxide support layer 1, and a second gallium oxide layer 3 (impurity layer) provided on the first gallium oxide layer 2. These layers are the same as those in the semiconductor device 100 of the first embodiment, and therefore redundant explanations of the materials, impurities, etc. will be omitted.

[0063] A plurality of Schottky recesses 17 are formed in the first main surface of the gallium oxide semiconductor layer 30. The Schottky recesses 17 are recesses provided in the first main surface of the gallium oxide semiconductor layer 30, formed by partially removing the first gallium oxide layer 2 and the second gallium oxide layer 3. The bottom of the Schottky recess 17 is in contact with the first gallium oxide layer 2, and the side of the Schottky recess 17 is in contact with the second gallium oxide layer 3.

[0064] The Schottky recess 17 is formed by dry etching, similar to the method for forming the gate recess 5 described in the first embodiment, and the depth of the Schottky recess 17 is set shallower than the depth of the second gallium oxide layer 3 .

[0065] As a result, the corners of the Schottky recess 17 are protected by the second gallium oxide layer 3, thereby improving the breakdown voltage. More preferably, etching is performed so that the lower corners of the Schottky recess 17 are rounded, which makes it difficult for the electric field to concentrate, further improving the breakdown voltage.

[0066] A Schottky electrode 14 is formed on the entire first main surface of the gallium oxide semiconductor layer 30, including the inner surface of the Schottky recess 17 and the upper surface of the second gallium oxide layer 3. The material of the Schottky electrode 14 is preferably Ti, Ni, Pt, Au, or the like, and the Schottky electrode 14 is formed to a thickness of about 200 nm by EB evaporation, sputtering, or the like.

[0067] An anode pad electrode 15 is formed on the Schottky electrode 14. The anode pad electrode 15 is formed by depositing a metal film on the Schottky electrode 14 using a sputtering device and then patterning the metal film by selective wet etching using photolithography. A Ti / Al laminated structure is suitable as the material for the anode pad electrode 15. The film thickness of the anode pad electrode 15 is, for example, 20 nm for Ti and 3 μm for Al.

[0068] A cathode electrode 16 is formed on the second main surface of the gallium oxide semiconductor layer 30. The cathode electrode 16 is electrically connected to the n-type gallium oxide support layer 1. The cathode electrode 16 is formed by depositing a Ti / Au electrode on the second main surface of the gallium oxide semiconductor layer 20 using a sputtering device or an EB deposition machine.

[0069] According to the semiconductor device 400 of the fourth embodiment, the surface alteration layer (defect layer) below the Schottky electrode 14 is removed when the Schottky recess 17 is formed, and therefore, an SBD with a Junction Barrier Schottky (JBS) structure can be obtained in which the forward characteristics are not degraded.

[0070] Furthermore, since the area where the Schottky recess 17 is formed is limited, the thickness of the second gallium oxide layer 3 is maintained, and breakdown of the junction is less likely to occur compared to when the surface alteration layer is completely removed by etching such as CMP. As a result, a semiconductor device 400 in which a decrease in breakdown voltage is suppressed can be obtained.

[0071] Fifth Preferred Embodiment FIG. 16 is a cross-sectional view showing the configuration of a semiconductor device 500 according to a fifth preferred embodiment, which shows a vertical SBD made of β-type gallium oxide.

[0072] In a semiconductor device 500 according to the fifth embodiment, in the configuration of the semiconductor device 400 according to the fourth embodiment, an intermediate film 13 which is a High-k film is formed on the entire first main surface of the gallium oxide semiconductor layer 30, including the inner surface of the Schottky recess 17 and the upper surface of the second gallium oxide layer 3, and a Schottky electrode 14 is formed on the intermediate film 13. The other configurations are the same as those of the semiconductor device 400 according to the fourth embodiment.

[0073] The high-k film is the same as the intermediate film 13 of the semiconductor device 300 of the third embodiment, and the band gap of the intermediate film 13 is set to β-Ga. ２ O ３ By making the band gap smaller than that of the first gate, no new barrier is generated in the conduction band, and the forward characteristics of the SBD are not deteriorated.

[0074] In addition, the β-Ga that constitutes the first gallium oxide layer 2 and the like ２ O ３ However, by providing an intermediate film 13 between the Schottky recess 17 and the Schottky electrode 14, the anode pad electrode 15 and the β-Ga ２ O ３ This suppresses the reaction with HCl and improves temperature stability.

[0075] Sixth Embodiment In this embodiment, the semiconductor device according to any one of the above-described first to fifth embodiments is applied to a power conversion device. Although application of the semiconductor device according to any one of the first to fifth embodiments is not limited to a specific power conversion device, the sixth embodiment will be described below as a case where the semiconductor device according to any one of the first to fifth embodiments is applied to a three-phase inverter.

[0076] FIG. 17 is a block diagram showing the configuration of a power conversion system to which the power conversion device according to this embodiment is applied.

[0077] The power conversion system shown in Fig. 17 is composed of a power supply 1000, a power conversion device 2000, and a load 3000. The power supply 1000 is a DC power supply and supplies DC power to the power conversion device 2000. The power supply 1000 can be composed of various components, such as a DC system, a solar cell, or a storage battery, or it can be composed of a rectifier circuit connected to an AC system or an AC / DC converter. The power supply 1000 can also be composed of a DC / DC converter that converts DC power output from a DC system into a predetermined power.

[0078] The power conversion device 2000 is a three-phase inverter connected between the power supply 1000 and the load 3000, and converts DC power supplied from the power supply 1000 into AC power and supplies the AC power to the load 3000. As shown in Fig. 17 , the power conversion device 2000 includes a main conversion circuit 201 that converts DC power into AC power and outputs it, a drive circuit 202 that outputs drive signals that drive each switching element of the main conversion circuit 201, and a control circuit 203 that outputs control signals to the drive circuit 202.

[0079] The load 3000 is a three-phase electric motor driven by AC power supplied from the power conversion device 2000. The load 3000 is not limited to a specific application, but is an electric motor mounted on various electrical devices, and is used as an electric motor for, for example, a hybrid vehicle, an electric vehicle, a railroad car, an elevator, or an air conditioning device.

[0080] The power conversion device 2000 will be described in detail below. The main conversion circuit 201 includes switching elements and freewheel diodes (not shown). The switching elements convert DC power supplied from the power supply 1000 into AC power, which is supplied to the load 3000. The main conversion circuit 201 can have a variety of specific circuit configurations. The main conversion circuit 201 according to this embodiment is a two-level, three-phase full-bridge circuit, which can be configured with six switching elements and six freewheel diodes connected in anti-parallel to each switching element. At least one of the switching elements and freewheel diodes of the main conversion circuit 201 is configured with a semiconductor device according to any one of the first to fifth embodiments. Two of the six switching elements are connected in series to form upper and lower arms, which form each phase (U phase, V phase, and W phase) of the full-bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 201, are connected to the load 3000.

[0081] The drive circuit 202 generates drive signals for driving the switching elements of the main conversion circuit 201 and supplies them to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, in accordance with control signals from a control circuit 203 (described later), the drive circuit 202 outputs to the control electrodes of each switching element a drive signal that turns the switching element on and a drive signal that turns the switching element off. When maintaining a switching element in the on state, the drive signal is a voltage signal (on signal) that is equal to or higher than the threshold voltage of the switching element, and when maintaining a switching element in the off state, the drive signal is a voltage signal (off signal) that is equal to or lower than the threshold voltage of the switching element.

[0082] The control circuit 203 controls the switching elements of the main conversion circuit 201 so that the desired power is supplied to the load 3000. Specifically, it calculates the time (on time) that each switching element of the main conversion circuit 201 should be in the on state based on the power to be supplied to the load 3000. For example, the main conversion circuit 201 can be controlled by PWM control, which modulates the on time of the switching elements according to the voltage to be output. The control circuit 203 then outputs a control command (control signal) to the drive circuit 202 so that an on signal is output to the switching element that should be in the on state at each time point, and an off signal is output to the switching element that should be in the off state at each time point. In accordance with this control signal, the drive circuit 202 outputs an on signal or an off signal as a drive signal to the control electrode of each switching element.

[0083] In the power conversion device of this embodiment, a semiconductor device according to any one of embodiments 1 to 5 is applied as the switching element of the main conversion circuit 201, so that a power conversion device using a semiconductor device in which a decrease in withstand voltage is suppressed is obtained.

[0084] In the present embodiment, an example has been described in which the semiconductor device according to any one of the first to fifth embodiments is applied to a two-level three-phase inverter, but the application of the semiconductor device according to any one of the first to fifth embodiments is not limited to this, and the semiconductor device can be applied to various power conversion devices. In the present embodiment, a two-level power conversion device is described, but a three-level or multi-level power conversion device may also be used, and when power is supplied to a single-phase load, the semiconductor device according to any one of the first to fifth embodiments may be applied to a single-phase inverter. Furthermore, when power is supplied to a DC load or the like, the semiconductor device according to any one of the first to fifth embodiments can also be applied to a DC / DC converter or an AC / DC converter.

[0085] Furthermore, a power conversion device to which the semiconductor device according to any one of the first to fifth embodiments is applied is not limited to cases in which the load described above is an electric motor, but can also be used, for example, as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a contactless power supply system, and can also be used as a power conditioner for a solar power generation system, a power storage system, etc.

[0086] The above description is illustrative in all respects, and it is understood that countless variations not illustrated can be envisioned.

[0087] It is possible to freely combine, modify, or omit the embodiments as appropriate. For example, since the gate recess 5 essentially serves to remove a surface defect layer caused by annealing, if surface defects are formed at a deep position in the gallium oxide semiconductor layer 20 or the gallium oxide semiconductor layer 30, it is also possible to form the gate recess 5 at the same depth as or deeper than the bottom end of the second gallium oxide layer 3.

[0088] 1 n-type gallium oxide support layer, 2 first gallium oxide layer, 3 second gallium oxide layer, 4 third gallium oxide layer, 5 gate recess, 6 gate insulating film, 7 gate electrode, 8 interlayer insulating film, 9 contact hole, 10 source pad electrode, 11 drain electrode, 12 source recess, 13 intermediate film, 14 Schottky electrode, 15 anode pad electrode, 16 cathode electrode, 17 Schottky recess, 20, 30 gallium oxide semiconductor layer, 1000 power supply, 2000 power conversion device, 201 main conversion circuit, 202 drive circuit, 203 control circuit, 3000 load.

Claims

1. A semiconductor device comprising: a gallium oxide semiconductor layer; an impurity layer formed within a first main surface of the gallium oxide semiconductor layer, the impurity layer having acceptor-type first impurities, at least a portion of which is activated; a first recess formed by removing a portion of the impurity layer and the gallium oxide semiconductor layer, the first recess being shallower than the impurity layer; a first main electrode provided on an upper portion of the first main surface; and a second main electrode provided on an upper portion of a second main surface of the gallium oxide semiconductor layer.

2. The semiconductor device according to claim 1, wherein the gallium oxide semiconductor layer comprises: an n-type gallium oxide support layer; a first gallium oxide layer provided on the n-type gallium oxide support layer; a second gallium oxide layer provided on the first gallium oxide layer; and a third gallium oxide layer provided on the second gallium oxide layer; the impurity layer is the second gallium oxide layer; the first recess is provided by removing portions of the third gallium oxide layer, the second gallium oxide layer, and the first gallium oxide layer; a gate insulating film provided on an inner surface of the first recess and on a portion of the third gallium oxide layer; and a gate electrode provided on the gate insulating film and filling the first recess.

3. The semiconductor device according to claim 2, wherein the first gallium oxide layer and the third gallium oxide layer contain a larger amount of a donor-type second impurity than the first impurity, and the second gallium oxide layer contains a larger amount of the first impurity than the second impurity.

4. The semiconductor device according to claim 2 or 3, wherein said first recess is formed deeper than said third gallium oxide layer.

5. The semiconductor device according to any one of claims 2 to 4, wherein the gate electrode is provided above an edge portion of the third gallium oxide layer so as to overlap the edge portion.

6. The semiconductor device according to any one of claims 2 to 5, wherein the first recess is provided so that its corners are rounded.

7. The semiconductor device according to claim 6, wherein the first recess is provided so that the corner portion is in contact with the second gallium oxide layer.

8. A semiconductor device according to any one of claims 2 to 7, further comprising a second recess formed by removing a portion of the third gallium oxide layer in a portion where the gate insulating film is not formed, the second recess being formed to a depth such that its bottom does not reach the second gallium oxide layer, and the first main electrode being formed so as to be in contact with the third gallium oxide layer via the second recess.

9. The semiconductor device according to claim 2, further comprising a second recess formed by removing a portion of the third gallium oxide layer, the second gallium oxide layer and the first gallium oxide layer in an area where the gate insulating film is not formed, the second recess being formed deeper than the third gallium oxide layer, and the first main electrode being electrically connected to the first gallium oxide layer via the second recess.

10. The semiconductor device according to claim 9, further comprising an intermediate film provided between said second recess and said first main electrode, said intermediate film having a band gap smaller than that of gallium oxide.

11. The semiconductor device according to claim 1, wherein the gallium oxide layer comprises: an n-type gallium oxide support layer; a first gallium oxide layer provided on the n-type gallium oxide support layer; and a second gallium oxide layer provided on the first gallium oxide layer; the impurity layer is the second gallium oxide layer; the first recess is provided by removing the second gallium oxide layer and the first gallium oxide layer; and a Schottky electrode is provided between the first recess and the first main electrode.

12. The semiconductor device according to claim 11, wherein the first gallium oxide layer contains a donor-type second impurity in a larger amount than the first impurity, and the second gallium oxide layer contains the first impurity in a larger amount than the second impurity.

13. The semiconductor device according to claim 11 or 12, wherein the first recess is provided so that its corners are rounded.

14. The semiconductor device according to any one of claims 11 to 13, further comprising an intermediate film provided between the first recess and the Schottky electrode, the intermediate film having a band gap smaller than that of gallium oxide.

15. A semiconductor device according to claim 10 or claim 14, wherein the intermediate film is made of a high-k film having a higher dielectric constant than a silicon oxide film.

16. A semiconductor device according to claim 2 or claim 11, wherein said second gallium oxide layer includes a linear defect extending in a direction including the [010] direction.

17. A power conversion device comprising: a main conversion circuit having a semiconductor device according to any one of claims 1 to 16, which converts input power and outputs it; a drive circuit which outputs a drive signal to the semiconductor device for driving the semiconductor device; and a control circuit which outputs a control signal to the drive circuit for controlling the drive circuit.

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