Current detection device and motor drive device

Abstract

This current detection device comprises: main current detection circuits (11u, 11v) for detecting a current in a current path; a reference circuit (12) for detecting the current at the same detection point as the main current detection circuits; a short-circuit unit (13) for establishing a short circuit between current input terminals of an AD converter in the reference circuit; a first offset correction unit (15) for removing a first offset from the output of the reference circuit; second offset correction units (16u, 16v) for calculating a second offset output from the main current detection circuits on the basis of the outputs of the main current detection circuits and the output first-offset-corrected by the first offset correction unit when the short-circuit unit does not establish a short circuit, and removing the second offset from the outputs of the main current detection circuits; and gain correction units (17u, 17v) for performing gain correction on the second-offset-corrected outputs on the basis of the outputs of the main current detection circuits and the first-offset-corrected output when the short-circuit unit does not establish a short circuit.

Description

Current detection device and motor drive device

[0001] The present disclosure relates to a current detection device and a motor drive device.

[0002] A motor drive device is provided with a current detection device that detects the current flowing through the motor in order to control the driving of the motor.

[0003] International Publication No. 2023 / 162246 International Publication No. 2022 / 064702 Japanese Patent Application Laid-Open No. 2014-230411

[0004] Conventionally, correction to eliminate gain imbalances among multiple current detection circuits has been achieved by acquiring the current values ​​output from each current detection circuit when the same current is passed through the multiple current detection circuits and eliminating the difference between them. Therefore, in order to perform correction to eliminate gain imbalances, a dedicated test current for gain correction must be passed through the current detection circuits, which requires changing the connection of the current detection circuits and temporarily halting normal current detection processing, resulting in inefficiency. For example, when correcting the gain of a current detection circuit provided in a motor drive device, it is necessary to stop the operation of the motor drive device, change the wiring of the current detection circuit, and pass the test current through the current detection circuit. Therefore, a technology that can continuously correct the gain of a current detection circuit without halting current detection processing is desired.

[0005] According to one aspect of the present disclosure, a current detection device includes a main current detection circuit that detects a current on a current path and outputs digital data corresponding to the current; a reference circuit that detects a current on the current path at the same detection point as the main current detection circuit and outputs digital data corresponding to the current; a short-circuiting section that short-circuits current input terminals of an AD converter in the reference circuit; a storage section that stores a first offset output from the reference circuit when the short-circuiting section shorts the current input terminals; a first offset correction section that performs first offset correction to remove an amount corresponding to the first offset from the output of the reference circuit; and a main current detection circuit that detects a current on the current path at the same detection point as the main current detection circuit and outputs digital data corresponding to the current. a second offset correction unit that calculates a second offset output from the main current detection circuit based on the output of the main current detection circuit and the first offset-corrected output by the first offset correction unit of the reference circuit, and performs second offset correction to remove an amount equivalent to the second offset from the output of the main current detection circuit; and a gain correction unit that performs gain correction on the second offset-corrected output by the second offset correction unit of the main current detection circuit based on the output of the main current detection circuit obtained at the same detection timing when the short-circuiting part does not short-circuit between the current input terminals and the first offset-corrected output by the first offset correction unit of the reference circuit.

[0006] FIG. 1 is a circuit diagram illustrating a current detection device according to an embodiment of the present disclosure. FIG. 2 is a block diagram illustrating a calculation method of a second offset output from a main current detection circuit. FIG. 3 is a block diagram illustrating the operation of a second offset correction unit and a gain correction unit. FIG. 4 is a flowchart illustrating the operation flow of correction processing according to the first mode of the current detection device according to an embodiment of the present disclosure. FIG. 5 is a timing chart illustrating the operation flow of correction processing according to the first mode shown in FIG. 4. FIG. 6 is a flowchart illustrating the operation flow of correction processing according to the second mode of the current detection device according to an embodiment of the present disclosure. FIG. 7 is a circuit diagram illustrating the configuration of a switching unit. FIG. 8 is a diagram illustrating a motor drive device including a current detection device according to an embodiment of the present disclosure.

[0007] Hereinafter, embodiments of a current detection device and a motor drive device will be described with reference to the drawings. In the following description, components having the same or similar functions are designated by the same reference numerals. Duplicate descriptions of those components may be omitted. The scale of the drawings has been appropriately changed to facilitate understanding.

[0008] In the following description, the offset of a reference circuit, which is a type of current detection circuit, is referred to as a “first offset,” and the offset of a main current detection circuit is referred to as a “second offset.” The term “on” for a switch means that the switch is closed and an electric path is formed through the switch. The term “off” for a switch means that the switch is opened and the electric path through the switch is interrupted. A converter that converts AC power supplied from an AC power source into DC power and outputs the DC power is also referred to as a “rectifier,” “rectifier device,” “rectifier circuit,” or “forward converter.” An inverter that converts DC power into AC power and outputs the DC power is also referred to as an “inverter.” A “DC link” refers to a circuit portion that electrically connects the DC output side of a converter and the DC input side of an inverter. A “DC link” is also referred to as a “DC link unit,” “DC link,” “DC link unit,” “DC bus,” or “DC intermediate circuit.” “Connected” means “electrically connected.”

[0009] <Configuration of a Current Detecting Device According to an Embodiment of the Present Disclosure> FIG. 1 is a circuit diagram illustrating a current detecting device according to an embodiment of the present disclosure.

[0010] A current detection device 1 according to one embodiment of the present disclosure includes main current detection circuits 11u and 11v, a reference circuit 12, a short-circuiting unit 13, a memory unit 14, a first offset correction unit 15, second offset correction units 16u and 16v, gain correction units 17u and 17v, and a switching unit 18.

[0011] The main current detection circuits 11u and 11v are provided in machines such as motor drive devices, robots, and machine tools to detect currents flowing in electrical circuits within the machines, and are distinguished from a reference circuit 12, which will be described later. Fig. 1 shows, as an example, a case in which the current detection device 1 includes two main current detection circuits 11u and 11v. The number of main current detection circuits included in the current detection device 1 may be one or more.

[0012] The main current detection circuit 11u detects the current on the current path 2u and outputs digital data corresponding to the current. The main current detection circuit 11v detects the current on the current path 2v and outputs digital data corresponding to the current. For example, the current path 2u is a u-phase power line connecting the inverter and the motor in the motor drive device, and the current path 2v is a v-phase power line connecting the inverter and the motor in the motor drive device. Here, an example in which the main current detection circuit is provided in the motor drive device has been shown, but the main current detection circuit may also be provided in other machines.

[0013] The main current detection circuits 11u and 11v may be shunt resistor current detection circuits, Hall element current detection circuits, or core current detection circuits. In FIG. 1, as an example, the main current detection circuits 11u and 11v are configured as shunt resistor current detection circuits.

[0014] The main current detection circuit 11u includes an isolated AD converter 22u, filter resistors 31u and 32u, and a filter capacitor 33u. A current detection resistor (shunt resistor) 21u provided on the current path 2u is connected to the input side of the main current detection circuit 11u. The AD converter 22u uses various analog-to-digital conversion methods, including successive approximation, delta-sigma, double integration, flash (parallel comparison), and pipeline. A filter composed of filter resistors 31u and 32u and a filter capacitor 33u is provided on the input side of the AD converter 22u. The filter capacitor 33u is electrically connected between the non-inverting input terminal (+) and the inverting input terminal (-) of the AD converter 22u, and the filter resistors 31u and 32u are electrically connected to both terminals of the filter capacitor 33u, respectively. When a current flows through the current path 2u, a potential difference occurs between the two terminals of the current detection resistor 21u, and each potential signal is input to the non-inverting input terminal (+) and the inverting input terminal (-) of the AD converter 22u via filter resistors 31u and 32u and a filter capacitor 33u. The AD converter 22u outputs digital data corresponding to the current through the current path 2u based on each input potential signal. The digital data output from the AD converter 22u is input to an LSI (large-scale integrated circuit) 40, which is a digital arithmetic circuit, and after undergoing second offset correction and gain correction (described later), is output to the outside as current value digital data.

[0015] The main current detection circuit 11v has the same configuration as the main current detection circuit 11u.

[0016] The main current detection circuit 11v includes an isolated AD converter 22v, filter resistors 31v and 32v, and a filter capacitor 33v. A current detection resistor (shunt resistor) 21v is connected to the input side of the main current detection circuit 11v, which is provided on the current path 2v. The AD converter 22v uses various analog-to-digital conversion methods, including successive approximation, delta-sigma, double integration, flash (parallel comparison), and pipeline. A filter composed of filter resistors 31v and 32v and a filter capacitor 33v is provided on the input side of the AD converter 22v. The filter capacitor 33v is electrically connected between the non-inverting input terminal (+) and the inverting input terminal (-) of the AD converter 22v, and the filter resistors 31v and 32v are electrically connected to both terminals of the filter capacitor 33v, respectively. When a current flows through the current path 2v, a potential difference occurs between the two terminals of the current detection resistor 21v, and each potential signal is input to the non-inverting input terminal (+) and the inverting input terminal (-) of the AD converter 22v via filter resistors 31v and 32v and a filter capacitor 33v. The AD converter 22v outputs digital data corresponding to the current on the current path 2v based on each input potential signal. The digital data output from the AD converter 22v is input to the LSI 40, where it is subjected to second offset correction and gain correction (described later) and then output to the outside as current value digital data.

[0017] The reference circuit 12 is a current detection circuit that serves as a reference when performing second offset correction and gain correction on the main current detection circuits 11u and 11v, and is distinguished from the main current detection circuits 11u and 11v. The reference circuit 12 has a configuration similar to that of the main current detection circuits 11u and 11v.

[0018] The reference circuit 12 detects the current on the current path 2u at the same detection point as the main current detection circuit 11u and outputs digital data corresponding to the detected current. The reference circuit 12 also detects the current on the current path 2v at the same detection point as the main current detection circuit 11v and outputs digital data corresponding to the detected current.

[0019] The reference circuit 12 may be a shunt resistor type current detection circuit, a Hall element type current detection circuit, or a core type current detection circuit. Fig. 1 shows an example in which the reference circuit 12 is configured as a shunt resistor type current detection circuit. The reference circuit 12 is preferably installed near the main current detection circuits 11u and 11v.

[0020] The reference circuit 12 includes an isolated AD converter 23, filter resistors 34 and 35, and a filter capacitor 36. The conversion methods of the AD converter 23 include successive approximation, delta-sigma, double integration, flash (parallel comparison), and pipeline. A filter composed of filter resistors 34 and 35 and a filter capacitor 36 is provided on the input side of the AD converter 23. The filter capacitor 36 is electrically connected between the non-inverting input terminal (+) and the inverting input terminal (-) of the AD converter 23, and the filter resistors 34 and 35 are electrically connected to both terminals of the filter capacitor 36, respectively. The digital data output from the AD converter 23 is input to an LSI 40.

[0021] By turning on switch SW1 and turning off switch SW2 in the switching unit 18, the main current detection circuit 11u and the reference circuit 12 can share the current detection resistor 21u. This allows the main current detection circuit 11u and the reference circuit 12 to detect the current on the current path 2u at the same detection point. When current flows on the current path 2u with switch SW1 on and switch SW2 off in the switching unit 18, a potential difference occurs between the two terminals of the current detection resistor 21u, and each potential signal is input to the non-inverting input terminal (+) and the inverting input terminal (−) of the AD converter 23 via filter resistors 34 and 35 and a filter capacitor 36. The AD converter 23 outputs digital data corresponding to the current on the current path 2u based on each input potential signal.

[0022] By turning off switch SW1 and turning on switch SW2 in the switching unit 18, the main current detection circuit 11v and the reference circuit 12 can share the current detection resistor 21v. This allows the main current detection circuit 11v and the reference circuit 12 to detect the current on the current path 2v at the same detection point. When current flows on the current path 2v with switch SW1 and SW2 in the switching unit 18 turned off and on, a potential difference is generated between the two terminals of the current detection resistor 21v, and each potential signal is input to the non-inverting input terminal (+) and the inverting input terminal (−) of the AD converter 23, respectively, via filter resistors 34 and 35 and a filter capacitor 36. The AD converter 23 outputs digital data corresponding to the current on the current path 2v based on each input potential signal.

[0023] The short-circuiting unit 13 is an open / close switch that shorts and opens the non-inverting input terminal (+) and the inverting input terminal (-), which are current input terminals of the AD converter 23 in the reference circuit 12. The short-circuiting unit 13 is configured with a switching element such as a unipolar transistor such as an FET, a bipolar transistor, an IGBT, a thyristor, or a GTO, but the type of the switching element itself is not limited to this embodiment and other switching elements may be used. Under the control of the first offset correction unit 15 in the LSI 40, the short-circuiting unit 13 periodically repeats short-circuiting and opening.

[0024] When the current input terminals of AD converter 23 in reference circuit 12 are short-circuited by short-circuiting unit 13, no current flows from current path 2u or 2v to AD converter 23 in reference circuit 12, and therefore only the offset of reference circuit 12 (i.e., the first offset) is output from AD converter 23 in reference circuit 12. Memory unit 14 stores the first offset output from reference circuit 12 when the current input terminals of AD converter 23 are short-circuited by short-circuiting unit 13.

[0025] The first offset correction unit 15 reads the first offset from the storage unit 14. Then, the first offset correction unit 15 performs first offset correction to remove an amount corresponding to the first offset from the output of the reference circuit 12 so that the output of the reference circuit 12 does not contain the first offset.

[0026] Writing of the first offset to the memory unit 14 and first offset correction of the output of the reference circuit 12 by the first offset correction unit 15 are performed when the current input terminals of the AD converter 23 are short-circuited by the short-circuiting unit 13. Because the short-circuiting unit 13 repeatedly shorts and opens at predetermined intervals, writing of the first offset to the memory unit 14 and first offset correction of the output of the reference circuit 12 by the first offset correction unit 15 are repeatedly performed at predetermined intervals. Even if the first offset of the reference circuit 12 changes due to temperature drift, the first offset correction is immediately performed on the output of the reference circuit 12 when the current input terminals of the AD converter 23 are short-circuited by the short-circuiting unit 13. When the current input terminals of the AD converter 23 are opened following the short-circuit, the reference circuit 12 outputs first offset-corrected digital data with the first offset removed. In this way, the first offset correction minimizes the effect of temperature drift on the output of the reference circuit 12.

[0027] When the short-circuiting unit 13 does not short-circuit the current input terminals of the AD converter 23 (i.e., when the current input terminals of the AD converter 23 are open), first offset-corrected digital data from which the first offset has been removed is output from the reference circuit 12. In order to obtain multiple outputs from the main current detection circuit and multiple first offset-corrected outputs from the first offset correction unit 15 of the reference circuit 12, simultaneous detection (simultaneous input) of the current on the current path 2u in the main current detection circuit 11u and the reference circuit 12 is performed multiple times while the short-circuiting unit 13 does not short-circuit the current input terminals of the AD converter 23. The multiple outputs from the main current detection circuit obtained by these multiple simultaneous detections and the multiple first offset-corrected outputs from the first offset correction unit 15 of the reference circuit 12 are used in the second offset correction by the second offset correction units 16u and 16v and the gain correction by the gain correction units 17u and 17v.

[0028] The second offset correction unit 16u calculates a second offset to be output from the main current detection circuit 11u based on multiple outputs of the main current detection circuit 11u obtained at the same detection timing when the short-circuiting unit 13 does not short-circuit the current input terminals of the AD converter 23 (i.e., when the current input terminals of the AD converter 23 are open) and multiple outputs after the first offset correction by the first offset correction unit 15 of the reference circuit 12. Then, the second offset correction unit 16u performs second offset correction to remove (subtract) an amount equivalent to the second offset from the output of the main current detection circuit 11u.

[0029] Similarly, the second offset correction unit 16v calculates a second offset to be output from the main current detection circuit 11v based on multiple outputs of the main current detection circuit 11v obtained at the same detection timing when the short-circuiting unit 13 does not short-circuit the current input terminals of the AD converter 23 (i.e., when the current input terminals of the AD converter 23 are open) and multiple outputs after the first offset correction by the first offset correction unit 15 of the reference circuit 12. Then, the second offset correction unit 16v performs second offset correction to remove (subtract) an amount equivalent to the second offset from the output of the main current detection circuit 11v.

[0030] A method for calculating the second offsets output from the main current detection circuits 11u and 11v will be described later.

[0031] The gain correction unit 17u performs gain correction on the second offset-corrected output by the second offset correction unit 16u of the main current detection circuit 11u based on the output of the main current detection circuit 11u obtained at the same detection timing when the short-circuiting unit 13 does not short-circuit the current input terminals of the AD converter 23 (i.e., when the current input terminals of the AD converter 23 are open) and the first offset-corrected output by the first offset correction unit of the reference circuit 12.

[0032] Similarly, the gain correction unit 17v performs gain correction on the second offset-corrected output by the second offset correction unit 16v of the main current detection circuit 11v based on the output of the main current detection circuit 11v obtained at the same detection timing when the short-circuiting unit 13 does not short-circuit the current input terminals of the AD converter 23 (i.e., when the current input terminals of the AD converter 23 are open) and the first offset-corrected output by the first offset correction unit of the reference circuit 12.

[0033] The gain correction performed by the gain correction unit 17u is performed using the gain G u The gain G of the reference circuit 12 for r The ratio G r / G u The gain correction performed by the gain correction unit 17v uses the gain G v The gain G of the reference circuit 12 for r The ratio G r / G v The gain ratio G r / G u and G r / G v The calculation method will be described later.

[0034] A switching unit 18 is provided so that the second offset correction by the second offset correction units 16u and 16v and the gain correction by the gain correction units 17u and 17v are switched and executed for each output of the multiple main current detection circuits (for each output of the main current detection circuit 11u and for each output of the main current detection circuit 11v in the example shown in Figure 1).

[0035] 1 , the switching unit 18 has a switch SW1 for connecting the input side of the reference circuit 12 to the current detection resistor 21u and a switch SW2 for connecting the input side of the reference circuit 12 to the current detection resistor 21v. When performing the second offset correction and gain correction on the main current detection circuit 11u, it is necessary for the reference circuit 12 to be able to detect the current flowing through the current path 2u, so the switch SW1 of the switching unit 18 is turned on and the switch SW2 is turned off. When performing the second offset correction and gain correction on the main current detection circuit 11v, it is necessary for the reference circuit 12 to be able to detect the current flowing through the current path 2v, so the switch SW1 of the switching unit 18 is turned off and the switch SW2 is turned on. A specific configuration example of the switching unit 18 will be described later.

[0036] The storage unit 14, the first offset correction unit 15, the second offset correction units 16u and 16v, and the gain correction units 17u and 17v are provided in the LSI 40. A switch control unit (not shown) for controlling the on / off of the switches SW1 and SW2 of the switching unit 18 is also provided in the LSI 40. Power for driving the LSI 40 may be supplied from a machine in which the current detection device 1 is provided, or may be supplied from a battery (not shown).

[0037] <Calculation of Second Offset> A method for calculating the second offset output from the main current detection circuits 11u and 11v will be described. Fig. 2 is a block diagram illustrating a method for calculating the second offset output from the main current detection circuits.

[0038] When the short-circuiting unit 13 does not short-circuit the current input terminals of the AD converter 23 (i.e., when it is open), the value of the current on the current path 2u at time t is I u(t), the output of the main current detection circuit 11u is I 1u (t), the output after the first offset correction by the first offset correction unit 15 of the reference circuit 12 is I r Let (t).

[0039] The gain of the main current detection circuit 11u is G u , the second offset of the main current detection circuit 11u is I ofu When the output I of the main current detection circuit 11u at time t is 1u (t) is expressed as in Equation 1.

[0040]

[0041] The gain of the reference circuit 12 is G r , the first offset-corrected output I by the first offset correction unit 15 of the reference circuit 12 at time t is r (t) is expressed as in Equation 2. The output I of the reference circuit 12 r Since (t) has already been corrected by the first offset correction unit 15 at the time of the short circuit between the current input terminals of the AD converter 23 before the open circuit, the first offset is 0, i.e., the first offset of the reference circuit 12 does not appear in Equation 2.

[0042]

[0043] Substituting Equation 2 into Equation 1, Equation 3 is obtained.

[0044]

[0045] Using equations 1 to 3, the second offset is calculated based on the output of the main current detection circuit 11u obtained at the same detection timing at each of the two times and the first offset-corrected output of the reference circuit 12 as follows:

[0046] In order to obtain two outputs at different times from the main current detection circuit 11u and two outputs at different times after first offset correction by the first offset correction unit 15 of the reference circuit 12, simultaneous detection processing (simultaneous input processing) of the current on the current path 2u in the main current detection circuit 11u and the reference circuit 12 is performed twice with a stagger while the short-circuiting unit 13 does not short-circuit between the current input terminals of the AD converter 23.

[0047] When the short-circuiting unit 13 does not short-circuit the current input terminals of the AD converter 23 (i.e., when the current input terminals of the AD converter 23 are open), the output I of the main current detection circuit 11u at time t1 is u (t1) is expressed by Equation 4, and the first offset-corrected output I by the first offset correction unit 15 of the reference circuit 12 at time t1 is r (t1) is expressed by Equation 5.

[0048]

[0049]

[0050] When the short-circuiting portion 13 does not short-circuit the current input terminals of the AD converter 23 (i.e., when the current input terminals of the AD converter 23 are open), the output I of the main current detection circuit 11u at time t u (t) is expressed by Equation 6, and the first offset-corrected output I by the first offset correction unit 15 of the reference circuit 12 at time t r (t2) is expressed by Equation 7.

[0051]

[0052]

[0053] Subtracting the sides of equation 4 and equation 6 gives equation 8.

[0054]

[0055] Subtracting the sides of equation 5 and equation 7 gives equation 9.

[0056]

[0057] Substituting Equation 9 into Equation 8 and rearranging the equation, Equation 10 is obtained.

[0058]

[0059] When equation 10 is substituted into equation 3 when t=t1, equation 11 is obtained.

[0060]

[0061] By rearranging Equation 11, Equation 12 is obtained.

[0062]

[0063] The second offset correction unit 16u calculates the second offset I of the main current detection circuit 11u according to Equation 12. ofu Calculate.

[0064] Similarly, the gain of the main current detection circuit 11v is set to G v , the second offset of the main current detection circuit 11u is I ofv When this is the case, the output I of the main current detection circuit 11v at time t is 1v (t) is expressed as in Equation 13.

[0065]

[0066] I in Equation 12 u (t1), I u (t2), I ofu respectively v (t1), I v (t2), I ofv Substituting this gives Equation 14.

[0067]

[0068] The second offset correction unit 16v calculates the second offset I of the main current detection circuit 11v according to Equation 14. ofv Calculate.

[0069] Generalizing Equation 12 and Equation 14, Equation 15 is obtained. That is, when the short-circuiting unit 13 does not short-circuit the current input terminals of the AD converter 23, the output of the main current detection circuit at time t1 is expressed as I x (t1), the first offset-corrected output by the first offset correction unit of the reference circuit 12 at time t1 is Ir (t1), the output of the main current detection circuit at time t2 is I x (t2), the first offset-corrected output by the first offset correction unit of the reference circuit 12 at time t2 is I r (t2), the second offset I as shown in Equation 15 of is obtained.

[0070]

[0071] In the above-described embodiment, the second offset is calculated based on the outputs obtained at the same detection timing at each of two times, but the second offset may also be calculated based on the outputs obtained at the same detection timing at each of three or more times.

[0072] <Second Offset Correction> FIG. 3 is a block diagram illustrating the operation of the second offset correction unit and the gain correction unit.

[0073] The second offset correction unit 16u calculates the second offset I expressed by Equation 12 from the output of the main current detection circuit 11u. ofu The second offset corrected output by the second offset corrector 16u of the main current detection circuit 11u at time t is denoted by I u2 (t) can be expressed as in Equation 16.

[0074]

[0075] Similarly, the second offset correction unit 16v calculates the second offset I shown in Equation 14 from the output of the main current detection circuit 11v. ofv The second offset corrected output by the second offset corrector 16v of the main current detection circuit 11v at time t is denoted by I v2 (t) can be expressed as in Equation 17.

[0076]

[0077] <Gain Correction> The gain correction performed by the gain correction unit 17u is performed by adjusting the gain G u The gain G of the reference circuit 12 for r The ratio G r / G u The above-mentioned equation 10 is used to express the gain G u The gain G of the reference circuit 12 for r The ratio of G r / G u This shows:

[0078] The gain correction unit 17u calculates the second offset-corrected output I from the second offset correction unit 16u of the main current detection circuit u. u2 For (t), G shown in Equation 10 r / G u The gain correction is performed by multiplying the gain corrected output I by the gain correction unit 17u of the main current detection circuit 11u at time t. u3 (t) can be expressed as in Equation 18.

[0079]

[0080] As shown in Equation 18, the gain-corrected output I u3 (t) is the second offset I ofu is removed and the gain is G r It has become.

[0081] I in Equation 10 u (t1), I u (t2), G u respectively v (t1), I v (t2), G v Equation 19 is obtained by substituting the gain G v The gain G of the reference circuit 12 for r The ratio of G r / G v This shows:

[0082]

[0083] The gain correction unit 17v calculates the second offset-corrected output I from the second offset correction unit 16v of the main current detection circuit v. v2 For (t), G shown in Equation 19 r / G v The gain correction is performed by multiplying the gain corrected output I by the gain correction unit 17v of the main current detection circuit 11v at time t. v3 (t) can be expressed as in Equation 20.

[0084]

[0085] As shown in Equation 20, the gain-corrected output I v3 (t) is the second offset I ofv is removed and the gain is G r It has become.

[0086] In this way, the gain-corrected output I by the gain correction unit 17u of the main current detection circuit 11u shown in Equation 18 is u3 (t) and the gain-corrected output I by the gain correction unit 17v of the main current detection circuit 11v shown in Equation 20. v3 (t) is the gain G of the reference circuit 12 r That is, according to an embodiment of the present disclosure, it is possible to remove the imbalance in gain among a plurality of current detection circuits.

[0087] Furthermore, when Equation 10 and Equation 19 are generalized, the gain G of the main current detection circuit is x The gain G of the reference circuit 12 for r The ratio of G r / G x can also be expressed as in Equation 21.

[0088]

[0089] <Operation Flow of a Series of Correction Processes According to an Embodiment of the Present Disclosure> As described above, the second offset correction and gain correction for the main current detection circuit are both performed based on the output of the main current detection circuit obtained at the same detection timing when the short-circuiting unit 13 does not short-circuit the current input terminals of the AD converter 23 and the output after the first offset correction by the first offset correction unit of the reference circuit 12. In addition, the second offset correction and gain correction for the main current detection circuit are performed for each output of the multiple main current detection circuits. Several examples of the operation flow of a series of correction processes in a current detection device according to an embodiment of the present disclosure are listed below.

[0090] 4 is a flowchart illustrating an operation flow of the correction process in the first mode of the current detection device according to the embodiment of the present disclosure, as an example, illustrating the operation flow of the correction process in the current detection device 1 including the two main current detection circuits 11u and 11v shown in FIG.

[0091] In the first form, after the output of the main current detection circuit and the first offset-corrected output by the first offset correction unit of the reference circuit 12 are obtained, a second offset correction and gain correction are immediately performed on the main current detection circuit.

[0092] In step S100, which is the initial state, the switches SW1 and SW2 in the switching unit 18 are both off.

[0093] In step S101, short-circuiting unit 13 shorts the current input terminals of AD converter 23 in reference circuit 12. Since no current flows from current path 2u or 2v to AD converter 23 in reference circuit 12, the first offset of reference circuit 12 is output from AD converter 23 in reference circuit 12.

[0094] In step S102, the first offset of the reference circuit 12 is detected and stored in the storage unit 14.

[0095] In step S103, the first offset correction unit 15 reads the first offset from the storage unit 14. Then, the first offset correction unit 15 performs first offset correction to remove an amount corresponding to the first offset from the output of the reference circuit 12 so that the output of the reference circuit 12 does not contain the first offset.

[0096] In step S104 , the short-circuiting unit 13 opens the current input terminals of the AD converter 23 in the reference circuit 12 .

[0097] In step S105, the switch SW1 is turned on while the switch SW2 remains off. As a result, the current flowing through the current path 2u flows into the reference circuit 12.

[0098] In step S106, the main current detection circuit 11u and the reference circuit 12 simultaneously detect the current flowing through the current path 2u multiple times.

[0099] In step S107, the second offset correction unit 16u calculates a second offset output from the main current detection circuit 11u based on the multiple outputs of the main current detection circuit 11u obtained at the same detection timing in step S106 and the multiple outputs after first offset correction by the first offset correction unit 15 of the reference circuit 12, and performs second offset correction to remove (subtract) an amount equivalent to the second offset from the output of the main current detection circuit 11u.

[0100] In step S108, the gain correction unit 17u performs gain correction on the second offset-corrected output by the second offset correction unit 16 of the main current detection circuit 11u based on the multiple outputs of the main current detection circuit 11u obtained at the same detection timing in step S106 and the multiple outputs after first offset correction by the first offset correction unit 15 of the reference circuit 12.

[0101] In step S109, the switch SW1 is turned off, so that the current flowing through the current path 2u does not flow into the reference circuit 12.

[0102] In step S110, short-circuiting unit 13 shorts the current input terminals of AD converter 23 in reference circuit 12. Since no current flows from current path 2u or 2v to AD converter 23 in reference circuit 12, the first offset of reference circuit 12 is output from AD converter 23 in reference circuit 12.

[0103] In step S111, the first offset of the reference circuit 12 is detected and stored in the storage unit 14.

[0104] In step S112, the first offset correction unit 15 reads the first offset from the storage unit 14. Then, the first offset correction unit 15 performs first offset correction to remove an amount corresponding to the first offset from the output of the reference circuit 12 so that the output of the reference circuit 12 does not contain the first offset.

[0105] In step S113 , the short-circuiting unit 13 opens the current input terminals of the AD converter 23 in the reference circuit 12 .

[0106] In step S114, the switch SW2 is turned on while the switch SW1 remains off. As a result, the current flowing through the current path 2v flows into the reference circuit 12.

[0107] In step S115, the main current detection circuit 11v and the reference circuit 12 simultaneously detect the current flowing through the current path 2v multiple times.

[0108] In step S116, the second offset correction unit 16v calculates a second offset output from the main current detection circuit 11v based on the multiple outputs of the main current detection circuit 11v obtained at the same detection timing in step S115 and the multiple outputs after first offset correction by the first offset correction unit 15 of the reference circuit 12, and performs second offset correction to remove (subtract) an amount equivalent to the second offset from the output of the main current detection circuit 11v.

[0109] In step S117, the gain correction unit 17v performs gain correction on the second offset-corrected output by the second offset correction unit 16 of the main current detection circuit 11v based on the multiple outputs of the main current detection circuit 11v obtained at the same detection timing in step S115 and the multiple outputs after first offset correction by the first offset correction unit 15 of the reference circuit 12.

[0110] In step S118, the switch SW2 is turned off, which prevents the current flowing through the current path 2v from flowing into the reference circuit 12. After that, the process returns to step S101.

[0111] The processes of steps S101 to S118 are repeatedly executed at predetermined intervals.

[0112] Fig. 5 is a timing chart illustrating an operation flow of the correction process according to the first embodiment shown in Fig. 4. Fig. 5 shows, from top to bottom, the short-circuiting (ON) and opening (OFF) of the short-circuiting unit 13, the execution timing of the first offset correction, the on / off of the switch SW1 in the switching unit 18, the execution timing of U-phase current detection by the main current detection circuit 11u and the reference circuit 12, the on / off of the switch SW2 in the switching unit 18, the execution timing of V-phase current detection by the main current detection circuit 11v and the reference circuit 12, the execution timing of the second offset correction and gain correction for the U phase, and the execution timing of the second offset correction and gain correction for the V phase. The execution timing of the first offset correction, the execution timing of U-phase current detection by the main current detection circuit 11u and the reference circuit 12, the execution timing of V-phase current detection by the main current detection circuit 11v and the reference circuit 12, the execution timing of the second offset correction and gain correction for the U phase, and the execution timing of the second offset correction and gain correction for the V phase are indicated by "thick bars."

[0113] As shown in FIG. 5, the short-circuiting unit 13 periodically repeats short-circuiting (ON) and opening (OFF) between the current input terminals of the AD converter 23 in the reference circuit 12 under the control of the first offset correction unit 15 in the LSI 40.

[0114] When the short-circuiting unit 13 shorts (ON) the current input terminals of the AD converter 23, the first offset of the reference circuit 12 is stored in the memory unit 14 at time t1, and the first offset correction unit 15 performs correction to remove (subtract) an amount corresponding to the first offset from the output of the reference circuit 12. Thereafter, the short-circuiting unit 13 opens (OFF) the current input terminals of the AD converter 23. Next, the switch SW1 in the switching unit 18 is turned ON. At times t2 and t3, the main current detection circuit 11u and the reference circuit 12 detect the current on the current path 2u. At time t3, the second offset correction unit 16u performs second offset correction and the gain correction unit 17u performs gain correction for the U phase. Thereafter, the switch SW1 in the switching unit 18 is turned OFF.

[0115] Next, the short-circuiting unit 13 shorts (ON) the current input terminals of the AD converter 23. At time t4, the first offset of the reference circuit 12 is stored in the memory unit 14, and the first offset correction unit 15 performs correction to remove (subtract) an amount equivalent to the first offset from the output of the reference circuit 12. Thereafter, the short-circuiting unit 13 opens (OFF) the current input terminals of the AD converter 23. Next, the switch SW2 in the switching unit 18 is turned ON. At times t5 and t6, the main current detection circuit 11v and the reference circuit 12 detect the current on the current path 2v. At time t6, the second offset correction unit 16v performs second offset correction and the gain correction unit 17v performs gain correction for the V phase. Thereafter, the switch SW2 in the switching unit 18 is turned OFF.

[0116] Next, the short-circuiting unit 13 shorts (ON) the current input terminals of the AD converter 23. At time t7, the first offset of the reference circuit 12 is stored in the memory unit 14, and the first offset correction unit 15 performs a correction to remove (subtract) an amount equivalent to the first offset from the output of the reference circuit 12. Thereafter, the short-circuiting unit 13 opens (OFF) the current input terminals of the AD converter 23. Next, the switch SW1 in the switching unit 18 is turned ON. At times t8 and t9, the main current detection circuit 11u and the reference circuit 12 detect the current on the current path 2u. At time t9, the second offset correction unit 16u performs a second offset correction and the gain correction unit 17u performs a gain correction for the U phase. Thereafter, the switch SW1 in the switching unit 18 is turned OFF.

[0117] Next, the short-circuiting unit 13 shorts (ON) the current input terminals of the AD converter 23. 10 The first offset of the reference circuit 12 is stored in the storage unit 14, and the first offset correction unit 15 performs correction to remove (subtract) an amount corresponding to the first offset from the output of the reference circuit 12. After that, the short-circuit unit 13 opens (turns OFF) the current input terminals of the AD converter 23. Next, the switch SW2 in the switching unit 18 is turned ON. At time t 11 and time t 11 At time t 11 Then, the second offset correction unit 16v performs the second offset correction and the gain correction unit 17v performs the gain correction for the V phase. After that, the switch SW2 in the changeover unit 18 is turned off. After that, the above-described processing is repeatedly executed.

[0118] 6 is a flowchart illustrating an operation flow of the correction process in the current detection device 1 according to the second embodiment of the present disclosure, which includes the two main current detection circuits 11u and 11v shown in FIG.

[0119] In the second form, after a set of the output of the main current detection circuit 11u and the first offset-corrected output by the first offset correction unit of the reference circuit 12, and a set of the output of the main current detection circuit 11v and the first offset-corrected output by the first offset correction unit of the reference circuit 12 are obtained, a second offset correction and gain correction for the main current detection circuit 11u and a second offset correction and gain correction for the main current detection circuit 11v are performed together.

[0120] In step S200, which is the initial state, the switches SW1 and SW2 in the switching unit 18 are both off.

[0121] In step S201, short-circuiting unit 13 shorts the current input terminals of AD converter 23 in reference circuit 12. Since no current flows from current path 2u or 2v to AD converter 23 in reference circuit 12, the first offset of reference circuit 12 is output from AD converter 23 in reference circuit 12.

[0122] In step S202, the first offset of the reference circuit 12 is detected and stored in the storage unit 14.

[0123] In step S203, the first offset correction unit 15 reads the first offset from the storage unit 14. Then, the first offset correction unit 15 performs first offset correction to remove an amount corresponding to the first offset from the output of the reference circuit 12 so that the output of the reference circuit 12 does not contain the first offset.

[0124] In step S204 , the short-circuiting unit 13 opens the current input terminals of the AD converter 23 in the reference circuit 12 .

[0125] In step S205, the switch SW1 is turned on while the switch SW2 remains off. As a result, the current flowing through the current path 2u flows into the reference circuit 12.

[0126] In step S206, the main current detection circuit 11u and the reference circuit 12 simultaneously detect the current flowing through the current path 2u multiple times.

[0127] In step S207, the switch SW1 is turned off, so that the current flowing through the current path 2u does not flow into the reference circuit 12.

[0128] In step S208, short-circuiting unit 13 short-circuits the current input terminals of AD converter 23 in reference circuit 12. Since no current flows from current path 2u or 2v to AD converter 23 in reference circuit 12, the first offset of reference circuit 12 is output from AD converter 23 in reference circuit 12.

[0129] In step S209, the first offset of the reference circuit 12 is detected and stored in the storage unit .

[0130] In step S210, the first offset correction unit 15 reads the first offset from the storage unit 14. Then, the first offset correction unit 15 performs first offset correction to remove an amount corresponding to the first offset from the output of the reference circuit 12 so that the output of the reference circuit 12 does not contain the first offset.

[0131] In step S211 , the short-circuiting unit 13 opens the current input terminals of the AD converter 23 in the reference circuit 12 .

[0132] In step S212, the switch SW2 is turned on while the switch SW1 remains off. As a result, the current flowing through the current path 2v flows into the reference circuit 12.

[0133] In step S213, the main current detection circuit 11v and the reference circuit 12 simultaneously detect the current flowing through the current path 2u multiple times.

[0134] In step S214, the second offset correction unit 16u calculates a second offset to be output from the main current detection circuit 11u based on the multiple outputs of the main current detection circuit 11u obtained at the same detection timing in step S206 and the multiple outputs after the first offset correction by the first offset correction unit 15 of the reference circuit 12, and performs second offset correction to remove (subtract) an amount corresponding to the second offset from the output of the main current detection circuit 11u. Also, in step S213, the second offset correction unit 16v calculates a second offset to be output from the main current detection circuit 11v based on the multiple outputs of the main current detection circuit 11v obtained at the same detection timing and the multiple outputs after the first offset correction by the first offset correction unit 15 of the reference circuit 12, and performs second offset correction to remove (subtract) an amount corresponding to the second offset from the output of the main current detection circuit 11v.

[0135] In step S215, the gain correction unit 17u performs gain correction on the second offset-corrected output by the second offset correction unit 16u of the main current detection circuit 11u, based on the multiple outputs of the main current detection circuit 11u obtained at the same detection timing in step S206 and the multiple outputs after the first offset correction by the first offset correction unit 15 of the reference circuit 12. Furthermore, the gain correction unit 17v performs gain correction on the second offset-corrected output by the second offset correction unit 16v of the main current detection circuit 11v, based on the multiple outputs of the main current detection circuit 11v obtained at the same detection timing in step S213 and the multiple outputs after the first offset correction by the first offset correction unit 15 of the reference circuit 12.

[0136] Note that steps S214 and S215 may be executed simultaneously.

[0137] In step S216, the switch SW2 is turned off, which prevents the current flowing through the current path 2v from flowing into the reference circuit 12. After that, the process returns to step S201.

[0138] The processes of steps S201 to S216 are repeatedly executed at predetermined intervals.

[0139] Fig. 7 is a timing chart illustrating an operation flow of the correction process according to the second embodiment shown in Fig. 6. Fig. 7 shows, from top to bottom, the short-circuiting (ON) and opening (OFF) of the short-circuiting unit 13, the execution timing of the first offset correction, the on / off of the switch SW1 in the switching unit 18, the execution timing of U-phase current detection by the main current detection circuit 11u and the reference circuit 12, the on / off of the switch SW2 in the switching unit 18, the execution timing of V-phase current detection by the main current detection circuit 11v and the reference circuit 12, the execution timing of the second offset correction and gain correction for the U phase, and the execution timing of the second offset correction and gain correction for the V phase. The execution timing of the first offset correction, the execution timing of U-phase current detection by the main current detection circuit 11u and the reference circuit 12, the execution timing of V-phase current detection by the main current detection circuit 11v and the reference circuit 12, the execution timing of the second offset correction and gain correction for the U phase, and the execution timing of the second offset correction and gain correction for the V phase are indicated by "thick bars."

[0140] As shown in FIG. 7, the short-circuiting unit 13 periodically repeats short-circuiting (ON) and opening (OFF) between the current input terminals of the AD converter 23 in the reference circuit 12 under the control of the first offset correction unit 15 in the LSI 40.

[0141] When the short-circuiting unit 13 shorts (ON) the current input terminals of the AD converter 23, the first offset of the reference circuit 12 is stored in the memory unit 14 at time t1, and the first offset correction unit 15 performs correction to remove (subtract) an amount corresponding to the first offset from the output of the reference circuit 12. Thereafter, the short-circuiting unit 13 opens (OFF) the current input terminals of the AD converter 23. Next, the switch SW1 in the switching unit 18 is turned on. At times t2 and t3, the main current detection circuit 11u and the reference circuit 12 detect the current on the current path 2u. Then, the switch SW1 in the switching unit 18 is turned off. Next, the short-circuiting unit 13 shorts (ON) the current input terminals of the AD converter 23. At time t4, the first offset of the reference circuit 12 is stored in the memory unit 14, and the first offset correction unit 15 performs correction to remove (subtract) an amount corresponding to the first offset from the output of the reference circuit 12. Thereafter, the short-circuiting unit 13 opens (OFF) the current input terminals of the AD converter 23. Next, the switch SW2 in the switching unit 18 is turned ON. At times t5 and t6, the main current detection circuit 11v and the reference circuit 12 detect the current on the current path 2v. At time t6, the second offset correction by the second offset correction unit 16u and the gain correction by the gain correction unit 17u are performed for the U phase, and the second offset correction by the second offset correction unit 16v and the gain correction by the gain correction unit 17v are performed for the V phase. Thereafter, the switch SW2 in the switching unit 18 is turned OFF.

[0142] Next, the short-circuiting unit 13 shorts (ON) the current input terminals of the AD converter 23. At time t7, the first offset of the reference circuit 12 is stored in the memory unit 14, and the first offset correction unit 15 performs a correction to remove (subtract) an amount equivalent to the first offset from the output of the reference circuit 12. Thereafter, the short-circuiting unit 13 opens (OFF) the current input terminals of the AD converter 23. Next, the switch SW1 in the switching unit 18 is turned ON. At time t8 and time t9, the main current detection circuit 11u and the reference circuit 12 detect the current on the current path 2u. Thereafter, the switch SW1 in the switching unit 18 is turned OFF. Next, the short-circuiting unit 13 shorts (ON) the current input terminals of the AD converter 23. At time t 10The first offset of the reference circuit 12 is stored in the storage unit 14, and the first offset correction unit 15 performs correction to remove (subtract) an amount corresponding to the first offset from the output of the reference circuit 12. After that, the short-circuit unit 13 opens (turns OFF) the current input terminals of the AD converter 23. Next, the switch SW2 in the switching unit 18 is turned ON. At time t 11 and time t 12 At time t 12 Then, the second offset correction by the second offset correction unit 16u and the gain correction by the gain correction unit 17u are performed for the U phase, and the second offset correction by the second offset correction unit 16v and the gain correction by the gain correction unit 17v are performed for the V phase. After that, the switch SW2 in the changeover unit 18 is turned off. The above-described processing is repeated thereafter.

[0143] <Configuration of Switching Unit> FIG. 8 is a circuit diagram illustrating the configuration of the switching unit.

[0144] The switching unit 18 includes switches SW1 and SW2 and an insulating driver 51.

[0145] 8, the switches SW1 and SW2 are configured with FETs as an example, but alternatively, the switches SW1 and SW2 may be configured with bipolar transistors or analog switches that combine two FETs.

[0146] A switch control unit 52 is connected to the switches SW1 and SW2 via an isolation driver 51. The switch control unit 52 controls the on / off operations of the switches SW1 and SW2. The switch control unit 52 is provided within the LSI 40. The isolation driver 51 is composed of a photocoupler, a photovoltaic coupler, a pulse transformer, an isolation IC, or the like.

[0147] An isolated power supply circuit 61u is connected to the main current detection circuit 11u. The isolated power supply circuit 61u includes a transformer 71u, a diode 72u, and a capacitor 73u. An isolated power supply circuit 61v is connected to the main current detection circuit 11v. The isolated power supply circuit 61v includes a transformer 71v, a diode 72v, and a capacitor 73v. An isolated power supply circuit 61r is connected to the reference circuit 12. The isolated power supply circuit 61r includes a transformer 71r, a diode 72r, and a capacitor 73r. The provision of the isolated power supply circuits 61u, 61v, and 61r allows the main current detection circuits 11u and 11v and the reference circuit 12 to operate stably even when the reference potential is switched by the on / off operation of the switches SW1 and SW2 in the switching unit 18.

[0148] <Configuration of a Motor Drive Device According to an Embodiment of the Present Disclosure> FIG. 9 is a diagram illustrating a motor drive device including a current detection device according to an embodiment of the present disclosure.

[0149] As an example, a case will be described in which a three-phase AC motor 300 is controlled by a motor drive device 100 connected to a three-phase AC power supply 200. In the illustrated example, the AC power supply 200 has three phases. However, the number of phases of the AC power supply 200 is not particularly limited to the present invention, and the AC power supply may be, for example, a single-phase or other multi-phase AC power supply. Examples of the AC power supply 200 include a three-phase 400V AC power supply, a three-phase 200V AC power supply, a three-phase 600V AC power supply, and a single-phase 100V AC power supply. In the illustrated example, the motor 300 has three phases. However, the number of phases of the motor 300 is not particularly limited to the present invention, and the motor may be, for example, a single-phase or other multi-phase motor. The motor 300 may be an induction motor or a synchronous motor. The motor 300 is used, for example, as a drive source for the feed shaft or spindle of a machine tool, or the arm of an industrial machine or industrial robot.

[0150] The motor drive device 100 includes a current detection device 1, a converter 3, an inverter 4, a smoothing capacitor 5, and a motor control unit 10.

[0151] The converter 3 converts AC power supplied from the AC power supply 200 into DC power and outputs it to a DC link. The converter 3 is configured as a three-phase bridge circuit when three-phase AC power is supplied from the AC power supply 200, and is configured as a single-phase bridge circuit when single-phase AC power is supplied from the AC power supply 200. In the example shown in the figure, the AC power supply 200 is a three-phase AC power supply, so the converter 3 is configured as a three-phase bridge circuit. Examples of the converter 3 include a diode rectifier circuit, a 120-degree conduction type rectifier circuit, and a PWM switching control type rectifier circuit.

[0152] A smoothing capacitor 5 is provided in a DC link, which is a circuit portion that electrically connects the DC output side of the converter 3 and the DC input side of the inverter 4. The smoothing capacitor 5 is sometimes referred to as a "DC link capacitor." The smoothing capacitor 5 has the function of storing energy (DC power) in the DC link and the function of suppressing pulsation in the DC side output of the converter 3. When the smoothing capacitor 5 is charged, DC power is stored in the DC link.

[0153] The inverter 4 converts DC power in the DC link into AC power and outputs it to the motor 300. The inverter 4 is composed of a bridge circuit of switching elements and diodes connected in anti-parallel to the switching elements. The inverter 4 is composed of a three-phase bridge circuit when the motor 300 is a three-phase AC motor, and is composed of a single-phase bridge circuit when the motor 300 is a single-phase AC motor. In the illustrated example, the motor 300 is a three-phase AC motor, so the inverter 4 is composed of a three-phase bridge circuit. An example of the inverter 4 is a PWM inverter equipped with internal switching elements. The switching elements are composed of, for example, unipolar transistors such as FETs, bipolar transistors, IGBTs, thyristors, GTOs, etc., but the type of switching elements themselves is not limited to this embodiment and other switching elements may also be used.

[0154] The inverter 4 and the motor 300 are connected by a U-phase current path 2u, a V-phase current path 2v, and a W-phase current path 2w. For example, the current detection device 1 is provided on the U-phase current path 2u and the V-phase current path 2v that connect the inverter 4 and the motor 300.

[0155] The motor control unit 10 generates drive commands for controlling the on / off of each switching element of the inverter 4 and outputs these to the inverter 4. The motor control unit 10 controls the power conversion operation of the inverter 4 based on the current value digital data (corrected by the second offset correction unit 16) output from the current detection device 1, the rotational speed (speed feedback) of the motor 300 detected by a position detector (not shown), a predetermined torque command, and an operation program for the motor 300. The speed, torque, or rotor position of the motor 300 is controlled based on the AC power supplied from the inverter 4. Note that the configuration of the motor control unit 10 described here is merely an example, and the configuration of the motor control unit 10 may be defined using terms such as a position command generator, a position control unit, a speed control unit, a current control unit, and a torque command creation unit. The motor control unit 10 includes an arithmetic processing unit (processor). Examples of the arithmetic processing unit include an IC, an LSI, a CPU, an MPU, and a DSP. The motor control unit 10, which includes the arithmetic processing unit, is a functional module implemented by a computer program executed on the processor. For example, if the motor control unit 10 is implemented in the form of a computer program, the functions of each unit can be realized by operating a processing unit in accordance with the computer program. The computer program for executing the processing of the motor control unit 10 may be provided in the form of a computer-readable recording medium such as a semiconductor memory, a magnetic recording medium, or an optical recording medium. Alternatively, the motor control unit 10 may be realized as a semiconductor integrated circuit into which a computer program for realizing the functions is written.

[0156] Note that the installation location and application of the current detection device 1 shown in FIG. 9 are merely examples. For example, the current detection device 1 may be provided on a power line on the input side of the converter 3 and used to detect an input current to the motor drive device 100. Furthermore, the current detection device 1 may be provided on a DC link and used to detect a DC link current. Furthermore, the current detection device 1 may be used to detect various currents in a motor drive device that controls the drive of a DC motor. Furthermore, the current detection device 1 is not limited to motor drive devices, and may be used to detect currents in various electrical devices such as computers, home appliances, trains, automobiles, and aircraft. In any of the above-described application examples, the digital current value data output from the current detection device 1 is used as a detected current value in the electrical device.

[0157] Advantages of the Embodiments of the Present Disclosure According to the embodiments of the present disclosure, the gain of the current detection circuit can be continuously corrected without stopping the current detection process.

[0158] Conventionally, correction to eliminate gain imbalances among multiple current detection circuits has been achieved by acquiring the current values ​​output by each current detection circuit when the same current is passed through the multiple current detection circuits and eliminating the difference between them. Therefore, to perform correction to eliminate gain imbalances, a dedicated test current for gain correction must be passed through the current detection circuits, which requires changing the current detection circuit's connection and temporarily halting normal current detection processing, resulting in inefficiency. For example, when correcting the gain of a current detection circuit provided in a motor drive device, operation of the motor drive device must be stopped, the current detection circuit's wiring must be changed, and the test current must be passed through the current detection circuit. In contrast, according to embodiments of the present disclosure, gain imbalances among multiple current detection circuits can be eliminated by matching the gain of each of the multiple main current detection circuits to the gain of a reference circuit. According to embodiments of the present disclosure, there is no need to pass a dedicated test current for gain correction through the main current detection circuit, so normal current detection processing of the main current detection circuit does not have to be halted. Correcting the gain of a main current detection circuit provided in a motor drive device also does not require stopping the operation of the motor drive device.

[0159] Although the present disclosure has been described in detail above, the present disclosure is not limited to the individual embodiments and individual variations described above. Various additions, substitutions, modifications, partial deletions, etc. are possible for these embodiments and variations within the scope of the gist of the present disclosure, or within the scope of the gist of the present disclosure derived from the content of the claims and their equivalents. These embodiments and variations can also be implemented in combination. For example, in the above-described embodiments and variations, the order of each operation and the order of each process are shown as examples and are not limited to these. The same applies when numerical values ​​or mathematical formulas are used in the description of the above-described embodiments and variations.

[0160] <Supplementary Notes> The following supplementary notes are further disclosed regarding the above-described embodiment and modifications.

[0161] (Supplementary Note 1) A main current detection circuit that detects a current on a current path and outputs digital data corresponding to the current; a reference circuit that detects a current on the current path at the same detection point as the main current detection circuit and outputs digital data corresponding to the current; a short-circuiting section that short-circuits current input terminals of an AD converter in the reference circuit; a storage section that stores a first offset output from the reference circuit when the current input terminals are short-circuited by the short-circuiting section; a first offset correction section that performs first offset correction to remove an amount equivalent to the first offset from the output of the reference circuit; and a second offset correction section that calculates a second offset output from the main current detection circuit based on the output of the main current detection circuit obtained at the same detection timing when the short-circuiting section does not short-circuit the current input terminals and the first offset-corrected output by the first offset correction section of the reference circuit, and performs second offset correction to remove an amount equivalent to the second offset from the output of the main current detection circuit. a gain correction unit that performs gain correction on a second offset-corrected output by the second offset correction unit of the main current detection circuit, based on an output of the main current detection circuit obtained at the same detection timing when the short-circuiting portion does not short-circuit the current input terminals and a first offset-corrected output by the first offset correction unit of the reference circuit. (Supplementary Note 2) The current detection device according to Supplementary Note 1, wherein the gain correction unit calculates a ratio of the gain of the reference circuit to the gain of the main current detection circuit, based on the output of the main current detection circuit obtained at the same detection timing at each of a plurality of times when the short-circuiting portion does not short-circuit the current input terminals and the first offset-corrected output by the first offset correction unit of the reference circuit, and performs gain correction on the second offset-corrected output by the second offset correction unit of the main current detection circuit, using the ratio. (Supplementary Note 3) When the short-circuiting portion does not short-circuit the current input terminals, the output of the main current detection circuit at time t1 is set to I x (t1), the first offset-corrected output by the first offset correction unit of the reference circuit at time t1 is I r (t1), the output of the main current detection circuit at time t2 is I x(t2), the first offset-corrected output by the first offset correction unit of the reference circuit at time t2 is I r (t2), the gain of the main current detection circuit is G x , the gain of the reference circuit is G r Then, the gain correction unit is According to the above ratio, G r / G x The current detection device according to claim 2, wherein the gain correction unit calculates the ratio G r / G x (Supplementary Note 5) The current detection device according to Supplementary Note 1, wherein the second offset correction unit calculates the second offset based on the output of the main current detection circuit obtained at the same detection timing at each of a plurality of times when the short-circuiting portion does not short-circuit the current input terminals and the output of the reference circuit after the first offset correction by the first offset correction unit. (Supplementary Note 6) When the short-circuiting portion does not short-circuit the current input terminals, the output of the main current detection circuit at time t1 is multiplied by I x (t1), the first offset-corrected output by the first offset correction unit of the reference circuit at time t1 is I r (t1), the output of the main current detection circuit at time t2 is I x (t2), the first offset-corrected output by the first offset correction unit of the reference circuit at time t2 is I r (t2), the second offset correction unit The second offset I of(Supplementary Note 7) The current detection device according to any one of Supplementary Notes 1 to 6, comprising: a plurality of main current detection circuits; and a switching unit for performing second offset correction by the second offset correction unit and gain correction by the gain correction unit for each output of the plurality of main current detection circuits. (Supplementary Note 8) A motor drive device comprising: the current detection device according to any one of Supplementary Notes 1 to 6; and a motor control unit that controls drive of the motor using the second offset-corrected and gain-corrected output of the main current detection circuit. (Supplementary Note 9) A motor drive device comprising: the current detection device according to Supplementary Note 7; and a motor control unit that controls drive of the motor using the second offset-corrected and gain-corrected output of the main current detection circuit.

[0162] REFERENCE SIGNS LIST 1 Current detection device 2u, 2v, 2w Current path 3 Converter 4 Inverter 5 Smoothing capacitor 10 Motor control unit 11u, 11v Main current detection circuit 12 Reference circuit 13 Short circuit unit 14 Memory unit 15 First offset correction unit 16u, 16v Second offset correction unit 17u, 17v Gain correction unit 18 Switching unit 21u, 21v Current detection resistor 22u, 22v, 23 AD converter 31u, 31v, 32u, 32v, 34, 35 Filter resistor 33u, 33v, 36 Filter capacitor 40 LSI 51 Insulated driver 52 Switch control unit 52 61u, 61v, 61r Insulated power supply circuit 71u, 71v, 71r Transformer 72u, 72v, 72r Diode 73u, 73v, 73r Capacitors 100 Motor drive device 200 AC power supply 300 Motor SW1, SW2 Switches

Claims

1. A main current detection circuit that detects a current on a current path and outputs digital data corresponding to the current; a reference circuit that detects the current on the current path at the same detection point as the main current detection circuit and outputs digital data corresponding to the current; a short-circuiting section that short-circuits current input terminals of an AD converter in the reference circuit; a memory section that stores a first offset output from the reference circuit when the short-circuiting section shorts the current input terminals; a first offset correction section that performs first offset correction to remove an amount equivalent to the first offset from the output of the reference circuit; and a second offset correction section that calculates a second offset output from the main current detection circuit based on the output of the main current detection circuit obtained at the same detection timing when the short-circuiting section does not short-circuit the current input terminals and the first offset-corrected output by the first offset correction section of the reference circuit, and performs second offset correction to remove an amount equivalent to the second offset from the output of the main current detection circuit. a gain correction unit that performs gain correction on a second offset-corrected output by the second offset correction unit of the main current detection circuit, based on an output of the main current detection circuit obtained at the same detection timing when the short-circuiting unit does not short-circuit the current input terminals and a first offset-corrected output by the first offset correction unit of the reference circuit.

2. The current detection device according to claim 1, wherein the gain correction unit calculates a ratio of the gain of the reference circuit to the gain of the main current detection circuit based on the output of the main current detection circuit obtained at the same detection timing at each of multiple times when the short-circuiting portion does not short-circuit the current input terminals and the first offset-corrected output by the first offset correction unit of the reference circuit, and uses the ratio to perform gain correction on the second offset-corrected output by the second offset correction unit of the main current detection circuit.

3. When the short-circuiting portion does not short-circuit the current input terminals, the output of the main current detection circuit at time t1 is I x (t1), the first offset-corrected output by the first offset correction unit of the reference circuit at the time t1 is I r (t1), the output of the main current detection circuit at time t2 is I x (t2), the first offset-corrected output by the first offset correction unit of the reference circuit at the time t2 is I r (t2), the gain of the main current detection circuit is G x , the gain of the reference circuit is G r When this is the case, the gain correction unit According to the above, the ratio G r / G x The current detection device according to claim 2 , wherein the current detection device calculates:

4. The gain correction unit calculates the ratio G with respect to the second offset-corrected output by the second offset correction unit of the main current detection circuit. r / G x 4. The current detection device according to claim 3, wherein a gain correction is performed by multiplying 5. The current detection device described in claim 1, wherein the second offset correction unit calculates the second offset based on the output of the main current detection circuit obtained at the same detection timing at each of multiple times when the short-circuiting portion does not short-circuit the current input terminals and the first offset-corrected output by the first offset correction unit of the reference circuit.

6. When the short-circuiting portion does not short-circuit the current input terminals, the output of the main current detection circuit at time t1 is I x (t1), the first offset-corrected output by the first offset correction unit of the reference circuit at the time t1 is I r (t1), the output of the main current detection circuit at time t2 is I x (t2), the first offset-corrected output by the first offset correction unit of the reference circuit at the time t2 is I r (t2), the second offset correction unit The second offset I of The current detection device according to claim 5, wherein the current detection device calculates:

7. A current detection device according to any one of claims 1 to 6, comprising: a plurality of said main current detection circuits; and a switching unit for executing second offset correction by said second offset correction unit and gain correction by said gain correction unit for each output of said plurality of said main current detection circuits.

8. A motor drive device comprising: the current detection device according to any one of claims 1 to 6; and a motor control unit that controls the drive of the motor using the second offset-corrected and gain-corrected output of the main current detection circuit.

9. A motor drive device comprising: the current detection device according to claim 7; and a motor control unit that controls the drive of the motor using the second offset-corrected and gain-corrected output of the main current detection circuit.

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