Semiconductor device, electric circuit, and electronic apparatus

Abstract

A semiconductor device according to an embodiment of the present invention comprises: a first semiconductor layer including a carrier gas region; a second semiconductor layer provided on the first semiconductor layer; a first protective layer provided on the second semiconductor layer; a gate electrode penetrating the first protective layer and joined to the second semiconductor layer; and a source electrode and a drain electrode provided, with the gate electrode therebetween, on the first semiconductor layer. The first protective layer has a first region contacting the gate electrode and a second region other than the first region. The first region is a region in which the density of an element constituting the first protective layer is lower than that in the second region.

Description

Semiconductor devices, electric circuits and electronic devices

[0001] The present disclosure relates to semiconductor devices, electric circuits, and electronic devices.

[0002] An example of a semiconductor device is a high electron mobility transistor (HEMT). HEMTs have characteristics such as high breakdown voltage, high heat resistance, high saturation electron velocity, and high channel electron concentration, and are expected to be applied to small, high-performance power devices and high-frequency devices. Among these HEMTs, HEMTs with a Schottky gate structure have been developed. The Schottky gate structure is a structure in which a gate electrode is connected to a semiconductor layer via a Schottky junction.

[0003] Japanese Patent Application Laid-Open No. 2014-165501

[0004] In semiconductor devices such as the above-mentioned Schottky gate HEMT, drain lag may occur, in which the drain current changes transiently in response to a sudden change in drain voltage. Suppression of this drain lag is required.

[0005] Therefore, the present disclosure provides a semiconductor device, an electric circuit, and an electronic device that can suppress drain lag.

[0006] The semiconductor device according to the embodiment comprises a first semiconductor layer including a carrier gas region, a second semiconductor layer provided on the first semiconductor layer, a first protective layer provided on the second semiconductor layer, a gate electrode that penetrates the first protective layer and is joined to the second semiconductor layer, and a source electrode and a drain electrode that are provided on the first semiconductor layer with the gate electrode between them, wherein the first protective layer has a first region that contacts the gate electrode and a second region other than the first region, and the first region is a region in which the density of elements that make up the first protective layer is lower than that of the second region.

[0007] An electric circuit according to an embodiment includes a semiconductor device, the semiconductor device including a first semiconductor layer including a carrier gas region, a second semiconductor layer provided on the first semiconductor layer, a first protective layer provided on the second semiconductor layer, a gate electrode bonded to the second semiconductor layer through the first protective layer, and a source electrode and a drain electrode provided on the first semiconductor layer with the gate electrode between them, the first protective layer having a first region in contact with the gate electrode and a second region other than the first region, the first region being a region in which the density of elements constituting the first protective layer is lower than that of the second region.

[0008] The electronic device according to the embodiment comprises an electrical circuit having a semiconductor device, the semiconductor device comprising a first semiconductor layer including a carrier gas region, a second semiconductor layer provided on the first semiconductor layer, a first protective layer provided on the second semiconductor layer, a gate electrode bonded to the second semiconductor layer through the first protective layer, and a source electrode and a drain electrode provided on the first semiconductor layer with the gate electrode between them, the first protective layer having a first region in contact with the gate electrode and a second region other than the first region, the first region being a region in which the density of elements constituting the first protective layer is lower than that of the second region.

[0009] FIG. 1 is a cross-sectional view showing a configuration example of a semiconductor device according to an embodiment. FIG. 2 is a cross-sectional view showing a configuration example of a first protective layer according to an embodiment. FIG. 3 is a diagram for explaining a configuration example of the first protective layer according to an embodiment. FIG. 4 is a diagram for explaining examples of materials of the first protective layer and the second protective layer according to an embodiment. FIG. 5 is a diagram for explaining numerical examples of the density of a first region of the first protective layer according to an embodiment. FIG. 6 is a diagram for explaining numerical examples of the region width of the first region of the first protective layer according to an embodiment. FIG. 7 is a diagram for explaining a modified example of the semiconductor device according to an embodiment. FIG. 8 is a cross-sectional view for explaining an example of a manufacturing process of the semiconductor device according to an embodiment. FIG. 9 is a cross-sectional view for explaining an example of a manufacturing process of the semiconductor device according to an embodiment. FIG. 10 is a block diagram showing an example of a configuration of a wireless communication device according to a second application example.

[0010] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The embodiments include examples and modifications. Note that the technology according to the present disclosure is not limited to the embodiments. Furthermore, in the embodiments, essentially identical components are designated by the same reference numerals, and redundant explanations will be omitted.

[0011] The present disclosure will be described in the following order: 1. Embodiments 1-1. Configuration example of semiconductor device 1-2. Configuration example of first protective layer 1-3. Material example of first protective layer and second protective layer 1-4. Numerical example of density of first region of first protective layer 1-5. Numerical example of region width of first region of first protective layer 1-6. Modified example of semiconductor device 1-7. Process example of semiconductor device manufacturing process 1-8. Actions and effects 2. Other embodiments 3. Application example 4. Supplementary notes

[0012] 1. Embodiment 1-1. Configuration Example of Semiconductor Device A configuration example of a semiconductor device 1A according to this embodiment will be described with reference to Fig. 1. Fig. 1 is a cross-sectional view showing a configuration example of a semiconductor device 1A according to this embodiment.

[0013] As shown in FIG. 1, the semiconductor device 1A according to this embodiment includes a substrate 11, a first semiconductor layer 12, a second semiconductor layer 13, a first protective layer 14, a source electrode 15, a drain electrode 16, a second protective layer 17, a gate electrode 18, and an insulating layer 19.

[0014] The first semiconductor layer 12 is provided on the substrate 11. The second semiconductor layer 13 is provided on the first semiconductor layer 12. The first protective layer 14 is provided on the second semiconductor layer 13. That is, the first semiconductor layer 12, the second semiconductor layer 13, and the first protective layer 14 are stacked on the substrate 11 in that order.

[0015] The source electrode 15 and the drain electrode 16 are provided on the first semiconductor layer 12, avoiding the second semiconductor layer 13 and the first protective layer 14. The second protective layer 17 is provided on the first protective layer 14, the source electrode 15, and the drain electrode 16 so as to cover the first protective layer 14, the source electrode 15, and the drain electrode 16. The gate electrode 18 passes through the first protective layer 14 and the second protective layer 17 and is joined to the second semiconductor layer 13.

[0016] The expression "a layer, an electrode, etc. is provided on an object" includes a case in which a layer, an electrode, etc. is provided directly on an object in contact with the object, and a case in which a layer, an electrode, etc. is provided on the object without contacting the object, with another layer, etc., in between.

[0017] Hereinafter, the above-mentioned components constituting the semiconductor device 1A according to this embodiment will be described in detail in order, starting from the substrate 11.

[0018] (Substrate) The substrate 11 is a support that supports each component (layer, electrode, etc.) of the semiconductor device 1A. The substrate 11 is made of, for example, a semiconductor material or an insulating material. As an example, the substrate 11 may be made of a single crystal of GaN, which is a semi-insulating III-V compound semiconductor material. In this case, the lattice constants of the substrate 11 and the first semiconductor layer 12 are approximately the same, making it possible to epitaxially grow the first semiconductor layer 12 on the substrate 11. The substrate 11 may also be made of, for example, Si, SiC, sapphire, etc.

[0019] (First Semiconductor Layer) The first semiconductor layer 12 is, for example, a compound semiconductor layer formed by epitaxial growth on the substrate 11. The first semiconductor layer 12 may contain, for example, two or more elements selected from Al, Ga, In, and N. For example, the first semiconductor layer 12 may be composed of GaN or u-GaN with no added impurities. The first semiconductor layer 12 may also be composed of a single layer film or a stacked film. The first semiconductor layer 12 functions, for example, as a buffer layer and a channel layer. The channel layer is provided on the buffer layer. Therefore, when the buffer layer is not included in the first semiconductor layer 12 but is treated as a separate layer, the channel layer may be treated as the first semiconductor layer 12.

[0020] The first semiconductor layer 12 has a carrier gas region 12a. The carrier gas region 12a, for example, constitutes a part of the current path between the source electrode 15 and the drain electrode 16. The carrier gas region 12a is a region where carriers, i.e., two-dimensional electron gas (2DEG), exist. Specifically, due to the difference in polarization charge between the first semiconductor layer 12 and the second semiconductor layer 13, carriers (e.g., electrons) are accumulated at the interface of the first semiconductor layer 12 on the second semiconductor layer 13 side. The region where these carriers are accumulated (the region where the carriers are distributed) is the carrier gas region 12a. The carrier gas region 12a functions, for example, as a channel through which the carriers flow. Note that, when the carriers are holes, the carrier gas region 12a is a region where two-dimensional hole gas (2DHG) exists.

[0021] (Second Semiconductor Layer) The second semiconductor layer 13 is, for example, composed of a compound semiconductor formed by epitaxial growth on the first semiconductor layer 12. The second semiconductor layer 13 is, for example, heterojunctioned with the first semiconductor layer 12. The second semiconductor layer 13 may contain, for example, two or more elements selected from Al, Ga, In, N, and Si. For example, the second semiconductor layer 13 may be composed of AlInN. The second semiconductor layer 13 may also be composed of a single-layer film or a stacked film. Note that the material used for the second semiconductor layer 13 may be any semiconductor material that allows carriers (e.g., electrons) to accumulate at the interface of the first semiconductor layer 12 on the second semiconductor layer 13 side due to the difference in polarization charge between the first semiconductor layer 12 and the second semiconductor layer 13. The second semiconductor layer 13 functions, for example, as a barrier layer.

[0022] (First Protective Layer) The first protective layer 14 is formed on the second semiconductor layer 13 so as to cover the second semiconductor layer 13. The first protective layer 14 protects, for example, the second semiconductor layer 13. The first protective layer 14 functions, for example, as an etching stopper. The first protective layer 14 may contain, for example, one or more elements selected from Si, Al, Hf, Zr, Ta, and Ti. The first protective layer 14 may also be composed of a single layer film or a stacked film. At least a part or all of the first protective layer 14 may be amorphous.

[0023] (Source Electrode / Drain Electrode) The source electrode 15 and the drain electrode 16 are formed on the first semiconductor layer 12 so as to sandwich the second semiconductor layer 13 and the first protective layer 14. Each of the source electrode 15 and the drain electrode 16 is formed of a conductive material and is in contact with a portion of the second semiconductor layer 13 and the first protective layer 14, respectively. Each of the source electrode 15 and the drain electrode 16 may contain, for example, one or more elements selected from Al, Ni, Au, Pt, Ti, Pd, and Ga. Each of the source electrode 15 and the drain electrode 16 may be formed of a single layer film or a laminated film. Each of the source electrode 15 and the drain electrode 16 functions, for example, as an ohmic electrode.

[0024] (Second Protective Layer) The second protective layer 17 is formed on the first protective layer 14, the source electrode 15, and the drain electrode 16 so as to cover the first protective layer 14, the source electrode 15, and the drain electrode 16. The second protective layer 17 protects, for example, the source electrode 15, the drain electrode 16, etc. The second protective layer 17 may contain, for example, one or more elements selected from Si, Al, Hf, Zr, Ta, and Ti. The second protective layer 17 may be formed as a single layer film or a laminated film.

[0025] (Gate electrode) The gate electrode 18 is formed on the second protective layer 17 so as to be in contact with the second semiconductor layer 13. The gate electrode 18 is formed of a conductive material and is Schottky junctioned to the second semiconductor layer 13, penetrating the first protective layer 14 and the second protective layer 17. The gate electrode 18 may contain at least one element selected from the group consisting of Ni, Au, Pt, Ti, and Pd. The gate electrode 18 may also be formed of a single layer film or a multilayer film.

[0026] Here, the first protective layer 14 has a first opening 14 a, and the second protective layer 17 has a second opening 17 a. The first opening 14 a or the second opening 17 a may be, for example, a through hole or a through trench. The gate electrode 18 is bonded to the second semiconductor layer 13 through the first opening 14 a and the second opening 17 a.

[0027] (Insulating Layer) The insulating layer 19 is formed on the second protective layer 17 and the gate electrode 18 so as to cover the second protective layer 17 and the gate electrode 18. The insulating layer 19 is made of an insulating material.

[0028] <1-2. Configuration Example of First Protective Layer> A configuration example of the first protective layer 14 according to this embodiment will be described with reference to Fig. 2 and Fig. 3. Fig. 2 is a cross-sectional view showing a configuration example of the first protective layer 14 according to this embodiment. Fig. 3 is a diagram for explaining a configuration example of the first protective layer 14 according to this embodiment.

[0029] Fig. 2 shows an enlarged view of a portion (near the Schottky junction) of the semiconductor device 1A shown in Fig. 1. Fig. 3 shows a cross-sectional view (left side in Fig. 3) and a plan view (right side in Fig. 3) of the portion shown in Fig. 2. The cross-sectional view corresponds to line A1 in the plan view, and the plan view corresponds to line A2 in the cross-sectional view.

[0030] As shown in FIG. 2 , the first protective layer 14 has a first region R1 in contact with the gate electrode 18 and a second region R2 (the second region R2 not in contact with the gate electrode 18) other than the first region R1. The density of elements in the first region R1 is lower than the density of elements in the second region R2, for example, due to the effects of wet etching. Elements are an example of a material constituting the first protective layer 14. The first region R1 functions as a low-density region, and the second region R2 functions as a high-density region. Note that when the first protective layer 14 is composed of a compound containing multiple types of elements, the density of the compound in the first region R1 may be lower than the density of the compound in the second region R2. The compound is also an example of a material constituting the first protective layer 14.

[0031] The opening width L1 of the first opening 14a is narrower than the opening width L2 of the second opening 17a. Specifically, the opening width L1 at the lower end of the first opening 14a is narrower than the opening width L2 at the lower end of the second opening 17a (the opening width L2 at the upper end of the first opening 14a). Widths such as opening width L1 and opening width L2 are lengths in the X-axis direction in FIGS. 2 and 3 . The X-axis direction, Y-axis direction, and Z-axis direction are mutually perpendicular. Specifically, the Z-axis direction is the stacking direction (thickness direction) of each layer, and the X-axis direction and Y-axis direction are mutually perpendicular in a planar direction perpendicular to the Z-axis direction.

[0032] Each of the first opening 14a and the second opening 17a is tapered. Specifically, the lower portion of each of the first opening 14a and the second opening 17a is tapered. The taper angle θ1 of the first opening 14a is smaller than the taper angle θ2 of the second opening 17a.

[0033] The inner surface of first opening 14a (the surface facing gate electrode 18) and the inner surface of second opening 17a (the surface facing gate electrode 18) are each inclined downward toward gate electrode 18. The inclination angle (gradient) of the inner surface of first opening 14a is taper angle θ1, and the inclination angle (gradient) of the inner surface of second opening 17a is taper angle θ2. These inner surfaces of first opening 14a and second opening 17a function as contact surfaces that come into contact with gate electrode 18.

[0034] 3, the gate electrode 18 extends, for example, along the Y-axis direction, which is an example of a planar direction. In this case, for example, the density of elements (or compounds containing multiple types of elements) in each of the first region R1 and the second region R2 may be the average value of the densities of elements (or compounds containing multiple types of elements) in the extension direction (Y-axis direction) of the gate electrode 18 in each of the first region R1 and the second region R2.

[0035] The planar shape of the first region R1 is not rectangular, and the lines indicating the boundaries of the first region R1 are wavy. The lines indicating the boundaries of the first region R1 extend in the extension direction (Y-axis direction) of the gate electrode 18. In the first region R1 having such a planar shape, for example, an average value of the element density in the extension direction of the gate electrode 18 can be obtained. Similarly, in the second region R2, for example, an average value of the element density in the extension direction of the gate electrode 18 can be obtained. Note that, for example, if the first region R1 is averaged to become a low-density region as described above, a portion B1 without a low-density region or a void portion B2 may exist within the first region R1.

[0036] <1-3. Examples of Materials for First Protective Layer and Second Protective Layer> Examples of materials for the first protective layer 14 and the second protective layer 17 according to this embodiment will be described with reference to Fig. 4. Fig. 4 is a diagram for explaining examples of materials for the first protective layer 14 and the second protective layer 17 according to this embodiment.

[0037] FIG. 4 shows a protective layer material (e.g., HfO ２ / SiN, SiN / SiN, Al ２ O ３ The Pout change rate (output power change rate) due to the RF aging test is shown for each HfO / SiN.２ / SiN, the first protective layer 14 is HfO ２ indicates that the second protective layer 17 is made of SiN. SiN / SiN indicates that the first protective layer 14 is made of SiN and the second protective layer 17 is made of SiN. Al ２ O ３ / SiN is a material in which the first protective layer 14 is Al ２ O ３ and indicates that the second protective layer 17 is made of SiN. The RF aging test may be, for example, an RF-HTOL (Radio Frequency-High Temperature Operating Life) test.

[0038] As shown in FIG. ２ When SiN / SiN is used as the protective layer material, the Pout change rate is almost constant at around 0. However, when SiN / SiN or Al ２ O ３ When / SiN was used as the protective layer material, the rate of change in Pout decreased over time. As described above, the rate of change in Pout differs depending on the type of protective layer material, and the output power (Pout) may decrease depending on the type of protective layer material.

[0039] HfO ２ / SiN is other protective film structure, for example, SiN / SiN, Al ２ O ３ Since a good interface with fewer traps than HfO / SiN is formed, for example, output power can be maintained for a long time in an RF aging test, and stable operation is possible. ２ It is preferable to use SiN as the material of the second protective layer 17. It is also preferable that the materials of the first protective layer 14 and the second protective layer 17 are different from each other.

[0040] <1-4. Numerical Value Example of Density in First Region of First Protective Layer> Numerical values ​​example of the density in the first region R1 of the first protective layer 14 according to this embodiment will be described with reference to Fig. 5. Fig. 5 is a diagram for explaining numerical values ​​example of the density in the first region R1 of the first protective layer 14 according to this embodiment.

[0041] FIG. 5 shows HfO ２ The density and etching rate in wet etching are shown. Here, the first protective layer 14 is made of HfO ２ and HfO ２ The density of HfO in the second region R2 of the first protective layer 14 is ２ corresponds to the density. ２ is an example of a compound containing multiple elements. The first region R1 of the first protective layer 14 is made lower density than the second region R2 by wet etching. That is, HfO ２ The density of HfO in the second region R2 ２ Less than density.

[0042] As shown in FIG. 5, HfO ２ The density is 9.32 g / cm ３ or more, for example, 9.3 g / cm ３ On the other hand, HfO ２ The density is 8.72 g / cm ３ For example, 8.7 g / cm ３ Therefore, the HfO of the first protective layer 14 ２ Density: 8.7 g / cm ３ By performing the following, it is possible to perform wet etching on the first protective layer 14. Therefore, the compound (e.g., HfO ２ ) has a density of 8.7 g / cm ３ Furthermore, due to the influence of wet etching, the density of the first region R1 of the first protective layer 14 is preferably 8.7 g / cm ３ It is desirable that it is smaller than

[0043] <1-5. Numerical Examples of the Region Width of the First Region of the First Protective Layer> Numerical examples of the region width of the first region R1 of the first protective layer 14 according to this embodiment will be described with reference to Fig. 6. Fig. 6 is a diagram for explaining numerical examples of the region width of the first region R1 of the first protective layer 14 according to this embodiment. Note that the region width of the first region R1 is the length in the X-axis direction (see Figs. 2 and 3).

[0044] As shown in FIG. 6, the drain lag decreases as the width of the first region R1 increases (see graph C1). The width of the first region R1 that is smaller than the value D1% and does not affect the stable operation of the device is 6 nm or more, specifically 5.3 nm or more. The value D1 is, for example, approximately 5 to 20%, but is not particularly limited. Based on the results shown in FIG. 6, it is desirable for the width of the first region R1 to be 6 nm or more, specifically 5.3 nm or more.

[0045] <1-6. Modified Examples of Semiconductor Devices> Modified examples of the semiconductor device 1A according to this embodiment (semiconductor devices 1B to 1H) will be described with reference to Fig. 7 and Fig. 8. Each of Fig. 7 and Fig. 8 is a diagram for explaining modified examples of the semiconductor device 1A according to this embodiment (semiconductor devices 1B to 1H).

[0046] 7 shows the combination of the configurations for each of the semiconductor devices 1A to 1H. (a) shows the configuration of the ohmic electrodes, (b) shows the configuration of the first protective layer 14, and (c) shows the configuration of the second semiconductor layer 13. The ohmic electrodes correspond to the source electrode 15 and the drain electrode 16.

[0047] (a): The ohmic electrode (1) contacts the interface (carrier gas region 12 a ) between the first semiconductor layer 12 and the second semiconductor layer 13 , or (2) contacts the second semiconductor layer 13 .

[0048] (b): The first protective layer 14 (1) contacts only the side surfaces of the ohmic electrodes, or (2) contacts both the side surfaces and the top surface of the ohmic electrodes.

[0049] (c): The second semiconductor layer 13 (1) contacts only the bottom surface of the gate electrode 18 , or (2) contacts the bottom surface and the side surface of the gate electrode 18 .

[0050] 7, in the semiconductor device 1A, (a) is (1), (b) is (1), and (c) is (1). In this case, in the semiconductor device 1A, (a)=(1): the ohmic electrode is in contact with the interface between the first semiconductor layer 12 and the second semiconductor layer 13, (b)=(1): the first protective layer 14 is in contact only with the side surface of the ohmic electrode, and (c)=(1): the second semiconductor layer 13 is in contact only with the bottom surface of the gate electrode 18, as shown in FIG.

[0051] 7, in the semiconductor device 1B, (a) is (1), (b) is (2), and (c) is (1). In this case, in the semiconductor device 1B, (a)=(1): the ohmic electrode is in contact with the interface between the first semiconductor layer 12 and the second semiconductor layer 13, (b)=(2): the first protective layer 14 is in contact with the side and top surfaces of the ohmic electrode, and (c)=(1): the second semiconductor layer 13 is in contact only with the bottom surface of the gate electrode 18, as shown in FIG.

[0052] 7, in the semiconductor device 1C, (a) is (2), (b) is (1), and (c) is (1). In this case, in the semiconductor device 1C, (a)=(2): the ohmic electrode is in contact with the second semiconductor layer 13, (b)=(1): the first protective layer 14 is in contact only with the side surface of the ohmic electrode, and (c)=(1): the second semiconductor layer 13 is in contact only with the bottom surface of the gate electrode 18, as shown in FIG.

[0053] 7, in semiconductor device 1D, (a) is (2), (b) is (2), and (c) is (1). In this case, in semiconductor device 1C, (a)=(2): the ohmic electrode is in contact with second semiconductor layer 13, (b)=(2): the first protective layer 14 is in contact with the side and top surfaces of the ohmic electrode, and (c)=(1): the second semiconductor layer 13 is in contact only with the bottom surface of gate electrode 18, as shown in FIG.

[0054] In the same manner as described above, for each of the other semiconductor devices 1E to 1H, either (1) or (2) is determined for each of (a), (b), and (c) as shown in Fig. 7. This allows the semiconductor devices 1A to 1H of various configurations to be realized as shown in Fig. 8.

[0055] <1-7. Example of Manufacturing Process of Semiconductor Device> An example of a manufacturing process of the semiconductor device 1B according to this embodiment will be described with reference to Fig. 9 to Fig. 11. Each of Fig. 9 to Fig. 11 is a cross-sectional view for explaining an example of a manufacturing process of the semiconductor device 1B according to this embodiment.

[0056] 9, in step S1, a first semiconductor layer 12 is formed on a substrate 11 such as a silicon substrate. For example, GaN is deposited as the first semiconductor layer 12 on the substrate 11 by MOCVD (metal organic chemical vapor deposition).

[0057] In step S2, the second semiconductor layer 13 is formed on the first semiconductor layer 12 formed on the substrate 11. For example, AlInN is deposited as the second semiconductor layer 13 on the first semiconductor layer 12 by MOCVD, and a heterojunction is formed between the first semiconductor layer 12 and the second semiconductor layer 13.

[0058] In step S3, the photoresist pattern is used as a mask, and the second semiconductor layer 13 formed on the first semiconductor layer 12 is dry-etched. For example, both ends of the second semiconductor layer 13 are removed by dry etching, and a pair of contact vias between the source electrode 15 and the drain electrode 16 and the carrier gas region 12 a are formed.

[0059] 10, in step S4, a source electrode 15 and a drain electrode 16 are formed on the first semiconductor layer 12, avoiding the second semiconductor layer 13 formed on the first semiconductor layer 12. For example, the source electrode 15 and the drain electrode 16 are formed in the region including the pair of contact vias by forming a lift-off resist and vapor-depositing Ti / Al / Ni / Au. In order to reduce the contact resistance, a SiO ２ Using this as a mask, a GaN film may be formed by MOCVD in the region of the pair of contact vias.

[0060] In step S5, the first protective layer 14 is formed on the second semiconductor layer 13, the source electrode 15, and the drain electrode 16. For example, a HfO 2 layer is formed on the second semiconductor layer 13, the source electrode 15, and the drain electrode 16 as the first protective layer 14. ２is formed by ALD (atomic layer deposition). In order to form a semiconductor layer / protective layer interface with few interface states and to ensure etching processability of the protective layer, for example, amorphous HfO ２ It is preferable to form a film of

[0061] In step S6, a second protective layer 17 is formed on the first protective layer 14. For example, a SiN film is formed as the second protective layer 17 on the first protective layer 14 by CVD. From the viewpoint of controlling the tapered shape, the SiN may be configured as two layers with different film densities. Note that by dividing the protective layer into two layers, such as the first protective layer 14 and the second protective layer 17, a highly precise shape can be achieved.

[0062] 11 , in step S7, a photoresist pattern is used as a mask to remove a portion (gate contact portion) of the second protective layer 17, thereby forming a second opening 17a in the second protective layer 17. For example, a portion of the SiN serving as the second protective layer 17 is removed. From the viewpoint of fine processing, dry etching of the SiN is preferable.

[0063] In step S8, a part (gate contact part) of the first protective layer 14 is removed, and a first opening 14a is formed in the first protective layer 14. For example, HfO ２ In order to prevent damage to the semiconductor layers such as the second semiconductor layer 13, the removal is performed by wet etching. ２ The structure of the end of the gate electrode 18 is determined by the SiN film quality. This structure affects the characteristics and reliability of the semiconductor device 1B. In step S8, a first region R1 of the first protective layer 14 is also formed. The density of the elements (or compounds) in this first region R1 is lower than the density of the elements (or compounds) in the second region R2.

[0064] In step S9, gate electrode 18 is formed on second protective layer 17. For example, gate electrode 18 is formed on second protective layer 17 by forming a lift-off resist and depositing Ni / Au. At this time, gate electrode 18 is Schottky-junctioned with second semiconductor layer 13 through first opening 14a and second opening 17a. Thereafter, insulating layer 19 is formed on second protective layer 17 and gate electrode 18, thereby completing semiconductor device 1B.

[0065] <1-8. Actions and Effects> As described above, the semiconductor device 1A (or each of the semiconductor devices 1B to 1H) according to this embodiment includes the first semiconductor layer 12 including the carrier gas region 12 a, the second semiconductor layer 13 provided on the first semiconductor layer 12, the first protective layer 14 provided on the second semiconductor layer 13, the gate electrode 18 that penetrates the first protective layer 14 and is joined to the second semiconductor layer 13, and the source electrode 15 and the drain electrode 16 that are provided on the first semiconductor layer 12 with the gate electrode 18 between them, and the first protective layer 14 has a first region R1 that contacts the gate electrode 18 and a second region R2 other than the first region R1, and the first region R1 is a region in which the density of elements that make up the first protective layer 14 is lower than that in the second region R2 (see FIGS. 1 to 3 , etc.). This forms a first region R1 with a low element density near the gate electrode 18, and, for example, reduces the level that affects drain lag at the interface between the second semiconductor layer 13 and the first protective layer 14, thereby suppressing drain lag.

[0066] The first region R1 has a lower density of the compound containing multiple elements than the second region R2 (see FIG. 5 ), which makes it possible to suppress drain lag even when the first protective layer 14 is made of a compound.

[0067] The density of the compound in the first region R1 is 8.7 g / cm ３ It may be smaller (see FIG. 5). This makes it possible to perform wet etching on the first region R1.

[0068] The width of the first region R1 may be 5.3 nm or more (see FIG. 6), which makes it possible to reliably suppress drain lag.

[0069] Furthermore, the gate electrode 18 may be connected to the second semiconductor layer 13 by a Schottky junction (see FIGS. 1 and 2). Even in this configuration, drain lag can be reliably suppressed.

[0070] Furthermore, the gate electrode 18 extends along the planar direction (e.g., the Y-axis direction) of the first semiconductor layer 12, and the element density in each of the first region R1 and the second region R2 may be the average value of the element density in the extension direction of the gate electrode 18 in each of the first region R1 and the second region R2 (see FIG. 3 ). This makes it possible to reliably suppress drain lag.

[0071] The first protective layer 14 may also contain one or more elements selected from Si, Al, Hf, Zr, Ta, and Ti (see FIGS. 1 and 4, etc.). This allows for an appropriate selection of the material for the first protective layer 14, thereby suppressing a decrease in output power due to an RF aging test (e.g., RF-HTOL).

[0072] The first protective layer 14 is made of HfO ２ (See FIG. 4.) This makes it possible to reliably suppress a decrease in output power due to the RF aging test.

[0073] The first semiconductor layer 12 may also contain two or more elements selected from Al, Ga, In, and N (see FIG. 1, etc.). This allows the material of the first semiconductor layer 12 to be selected appropriately.

[0074] The second semiconductor layer 13 may also contain two or more elements selected from Al, Ga, In, N, and Si (see FIG. 1, etc.). This allows the material of the second semiconductor layer 13 to be selected appropriately.

[0075] Furthermore, each of the source electrode 15 and the drain electrode 16 may contain one or more elements selected from Al, Ni, Au, Pt, Ti, Pd, and Ga (see FIG. 1 , etc.), which allows the materials of the source electrode 15 and the drain electrode 16 to be appropriately selected.

[0076] Furthermore, the semiconductor device 1A (or each of the semiconductor devices 1B to 1H) further includes a second protective layer 17 provided on the first protective layer 14, and the gate electrode 18 is bonded to the second semiconductor layer 13 through the first protective layer 14 and the second protective layer 17, and the first protective layer 14 may have a first opening 14a through which the gate electrode 18 passes, and the second protective layer 17 may have a second opening 17a through which the gate electrode 18 passes (see FIGS. 1 and 2). This allows two protective layers to be provided as the first protective layer 14 and the second protective layer 17.

[0077] Furthermore, the opening width L1 of the first opening 14a may be narrower than the opening width L2 of the second opening 17a (see FIG. 2), thereby making it possible to reliably suppress drain lag.

[0078] Each of the first opening 14a and the second opening 17a may be tapered, and the taper angle θ1 of the first opening 14a may be smaller than the taper angle θ2 of the second opening 17a (see FIG. 2). This reliably suppresses drain lag.

[0079] Furthermore, the surface of first opening 14a that contacts gate electrode 18 and the surface of second opening 17a that contacts gate electrode 18 may be inclined downward toward gate electrode 18 (see FIG. 2). This makes it possible to reliably suppress drain lag.

[0080] The second protective layer 17 may also contain one or more elements selected from the group consisting of Si, Al, Hf, Zr, Ta, and Ti (see FIGS. 1 and 4, etc.), allowing the material of the second protective layer 17 to be appropriately selected.

[0081] The material of the first protective layer 14 and the material of the second protective layer 17 may be different (see FIG. 4 ). This allows the materials of the first protective layer 14 and the second protective layer 17 to be appropriately selected, thereby suppressing a decrease in output power due to an RF aging test.

[0082] The material of the first protective layer 14 is HfO ２The material of the second protective layer 17 may be SiN (see FIG. 4), which can reliably suppress the decrease in output power due to the RF aging test.

[0083] 2. Other Embodiments The configurations and processes according to the above-described embodiments (including examples and modified examples) may be implemented in various different forms other than the above-described embodiments. For example, the configurations and processes are not limited to the above-described examples and may be implemented in various forms. Furthermore, for example, the configurations, processing procedures, specific names, or information including various data and parameters shown in the above documents and drawings may be changed arbitrarily unless otherwise specified.

[0084] Furthermore, the components and processes according to the above-described embodiments (including examples and modifications) do not necessarily have to be physically configured as shown in the drawings. In other words, the specific forms of distribution and integration of the components and processes are not limited to those shown in the drawings, and all or part of them may be functionally or physically distributed or integrated in any unit depending on various loads, usage conditions, etc.

[0085] Furthermore, the configurations and processes of the above-described embodiments (including examples and modified examples) may be combined as appropriate. For example, at least a part of an embodiment may be combined as appropriate with at least a part of another embodiment. Furthermore, the effects of the embodiments are merely examples and are not intended to be limiting, and other effects may also be obtained.

[0086] <3. Application Examples> Each of the semiconductor devices 1A to 1H according to this embodiment is applied to a variety of products. For example, any of the semiconductor devices 1A to 1H according to this embodiment is applied to various electric circuits (e.g., electronic circuits) and various electronic devices. Examples of electronic devices include power devices and high-frequency devices. Specific examples include power supply devices and wireless communication devices. Power supply devices and wireless communication devices include electric circuits having, for example, power amplifiers and high-frequency switches.

[0087] The wireless communication device may be mounted on any mobile object, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, a robot, a construction machine, an agricultural machine (tractor), etc. The wireless communication device may also be mounted on any surgical system, such as an endoscopic surgery system or a microsurgery system. Note that the wireless communication device is merely an example of an electronic device.

[0088] A wireless communication device (e.g., a wireless communication device 100 and a wireless communication device 200) to which any of the semiconductor devices 1A to 1H according to this embodiment is applied will be described with reference to Fig. 12 and Fig. 13. Fig. 12 is a perspective view showing a configuration example of the wireless communication device 100 according to a first application example. Fig. 13 is a block diagram showing a configuration example of the wireless communication device 200 according to a second application example.

[0089] 12 , a wireless communication device 100 according to a first application example includes, for example, a substrate 110, a plurality of edge antennas 120, and a front-end component group 130. The wireless communication device 100 is an antenna-integrated module in which the edge antennas 120 and the front-end component group 130 are integrated and mounted as a single module. The edge antennas 120 are formed in an array on the substrate 110. The front-end component group 130 includes a switch 131, a low-noise amplifier 132, a band-pass filter 133, a power amplifier 134, and the like. The front-end component group 130 functions as an electric circuit.

[0090] Such a wireless communication device 100 is used, for example, as a transceiver for communications. Any of the semiconductor devices 1A to 1H according to the present embodiment may be applied to, for example, transistors constituting the switch 131, the low-noise amplifier 132, or the power amplifier 134. This allows the wireless communication device 100 to achieve the same effects as any of the above-described embodiments (embodiments and modifications).

[0091] (Second Application Example) As shown in FIG. 13 , a wireless communication device 200 according to the second application example includes an antenna (ANT) 210, an antenna switch circuit 220, a high power amplifier (HPA) 230, a radio frequency integrated circuit (RFIC) 240, a baseband unit 250, an audio output unit (MIC) 260, a data output unit (DT) 270, and an interface unit (I / F) 280.

[0092] Such a wireless communication device 200 is used, for example, as a mobile phone system having multiple functions such as voice and data communication and LAN (local area network) connection. Any of the semiconductor devices 1A to 1H according to the present embodiment may be applied to transistors that constitute, for example, an antenna switch circuit 220, a high-power amplifier 230, a high-frequency integrated circuit 240, or a baseband unit 250. This allows the wireless communication device 200 to achieve the same effects as any of the above-described embodiments (embodiments and modifications).

[0093] <4. Supplementary Notes> The present technology may also be configured as follows. (1) A semiconductor device including: a first semiconductor layer including a carrier gas region; a second semiconductor layer provided on the first semiconductor layer; a first protective layer provided on the second semiconductor layer; a gate electrode penetrating the first protective layer and joined to the second semiconductor layer; and a source electrode and a drain electrode provided on the first semiconductor layer with the gate electrode between them, wherein the first protective layer has a first region in contact with the gate electrode and a second region other than the first region, and the first region is a region in which the density of elements constituting the first protective layer is lower than in the second region. (2) The semiconductor device according to (1), wherein the first region is a region in which the density of a compound containing a plurality of types of the elements is lower than in the second region. (3) The density of the compound in the first region is 8.7 g / cm ３(4) The semiconductor device according to any one of (1) to (3), wherein the width of the first region is 5.3 nm or more. (5) The semiconductor device according to any one of (1) to (4), wherein the gate electrode is Schottky-junctioned to the second semiconductor layer. (6) The semiconductor device according to any one of (1) to (5), wherein the gate electrode extends along a planar direction of the first semiconductor layer, and the density of the element in each of the first region and the second region is an average value of the density of the element in the extension direction of the gate electrode in each of the first region and the second region. (7) The semiconductor device according to any one of (1) to (6), wherein the first protective layer contains one or more elements selected from Si, Al, Hf, Zr, Ta, and Ti. (8) The semiconductor device according to any one of (1) to (6), wherein the first protective layer is HfO ２(7) The semiconductor device according to (9), wherein the first semiconductor layer contains two or more elements selected from Al, Ga, In, and N. (10) The semiconductor device according to any one of (1) to (9), wherein the second semiconductor layer contains two or more elements selected from Al, Ga, In, N, and Si. (11) The semiconductor device according to any one of (1) to (10), wherein each of the source electrode and the drain electrode contains one or more elements selected from Al, Ni, Au, Pt, Ti, Pd, and Ga. (12) The semiconductor device according to any one of (1) to (11), further comprising a second protective layer provided on the first protective layer, wherein the gate electrode is joined to the second semiconductor layer through the first protective layer and the second protective layer, the first protective layer having a first opening through which the gate electrode passes, and the second protective layer having a second opening through which the gate electrode passes. (13) The semiconductor device according to (12), wherein the opening width of the first opening is narrower than the opening width of the second opening. (14) The semiconductor device according to (12) or (13), wherein the first opening and the second opening are each formed in a tapered shape, and the taper angle of the first opening is smaller than the taper angle of the second opening. (15) The semiconductor device according to (14), wherein a surface of the first opening that contacts the gate electrode and a surface of the second opening that contacts the gate electrode are inclined downward toward the gate electrode. (16) The semiconductor device according to any one of (12) to (15), wherein the second protective layer contains one or more elements from Si, Al, Hf, Zr, Ta, and Ti. (17) The semiconductor device according to any one of (12) to (16), wherein the material of the first protective layer and the material of the second protective layer are different. (18) The material of the first protective layer is HfO ２(19) An electric circuit comprising: a first semiconductor layer including a carrier gas region, a second semiconductor layer provided on the first semiconductor layer, a first protective layer provided on the second semiconductor layer, a gate electrode joined to the second semiconductor layer through the first protective layer, and a source electrode and a drain electrode provided on the first semiconductor layer with the gate electrode interposed therebetween, wherein the first protective layer has a first region in contact with the gate electrode and a second region other than the first region, and the first region is a region in which a density of elements constituting the first protective layer is lower than that of the second region. (20) An electronic device comprising an electric circuit having a semiconductor device, the semiconductor device comprising: a first semiconductor layer including a carrier gas region, a second semiconductor layer provided on the first semiconductor layer, a first protective layer provided on the second semiconductor layer, a gate electrode joining to the second semiconductor layer through the first protective layer, and a source electrode and a drain electrode provided on the first semiconductor layer with the gate electrode between them, the first protective layer having a first region in contact with the gate electrode and a second region other than the first region, the first region being a region in which the density of elements constituting the first protective layer is lower than in the second region. (21) An electric circuit comprising the semiconductor device according to any one of (1) to (18). (22) An electronic device comprising the electric circuit according to (21).

[0094] DESCRIPTION OF SYMBOLS 1A Semiconductor device 1B Semiconductor device 1C Semiconductor device 1D Semiconductor device 1E Semiconductor device 1F Semiconductor device 1G Semiconductor device 1H Semiconductor device 11 Substrate 12 First semiconductor layer 12a Carrier gas region 13 Second semiconductor layer 14 First protective layer 14a First opening 15 Source electrode 16 Drain electrode 17 Second protective layer 17a Second opening 18 Gate electrode 19 Insulating layer 100 Wireless communication device 110 Substrate 120 Edge antenna 130 Front-end component group 131 Switch 132 Low-noise amplifier 133 Band-pass filter 134 Power amplifier 200 Wireless communication device 210 Antenna 220 Antenna switch circuit 230 High-power amplifier 240 High-frequency integrated circuit 250 Baseband section 260 Audio output section 270 Data output section 280 Interface section L1 Aperture width L2 Opening width R1 First region R2 Second region θ1 Taper angle θ2 Taper angle

Claims

1. A semiconductor device comprising: a first semiconductor layer including a carrier gas region; a second semiconductor layer provided on the first semiconductor layer; a first protective layer provided on the second semiconductor layer; a gate electrode that penetrates the first protective layer and is joined to the second semiconductor layer; and a source electrode and a drain electrode that are provided on the first semiconductor layer with the gate electrode between them, wherein the first protective layer has a first region that contacts the gate electrode and a second region other than the first region, and the first region is a region in which the density of elements that make up the first protective layer is lower than that of the second region.

2. The semiconductor device according to claim 1, wherein the first region is a region in which the density of compounds containing the plurality of types of elements is lower than that of the second region.

3. The density of the compound in the first region is 8.7 g / cm ３ The semiconductor device according to claim 2 , wherein the semiconductor device is smaller than the first embodiment.

4. The semiconductor device according to claim 1, wherein the width of the first region is 5.3 nm or more.

5. The semiconductor device according to claim 1, wherein the gate electrode is connected to the second semiconductor layer by a Schottky junction.

6. The semiconductor device according to claim 1, wherein the gate electrode extends along a planar direction of the first semiconductor layer, and the density of the element in each of the first region and the second region is an average value of the density of the element in the extension direction of the gate electrode in each of the first region and the second region.

7. The semiconductor device according to claim 1, wherein the first protective layer contains one or more elements selected from the group consisting of Si, Al, Hf, Zr, Ta, and Ti.

8. The first protective layer is made of HfO ２ The semiconductor device according to claim 7 , wherein the semiconductor device is configured by:

9. The semiconductor device according to claim 1, wherein the first semiconductor layer contains two or more elements selected from the group consisting of Al, Ga, In, and N.

10. The semiconductor device according to claim 1, wherein the second semiconductor layer contains two or more elements selected from the group consisting of Al, Ga, In, N, and Si.

11. The semiconductor device according to claim 1, wherein each of the source electrode and the drain electrode contains one or more elements selected from the group consisting of Al, Ni, Au, Pt, Ti, Pd, and Ga.

12. The semiconductor device according to claim 1, further comprising a second protective layer provided on the first protective layer, wherein the gate electrode is bonded to the second semiconductor layer through the first protective layer and the second protective layer, the first protective layer having a first opening through which the gate electrode passes, and the second protective layer having a second opening through which the gate electrode passes.

13. The semiconductor device according to claim 12, wherein the opening width of the first opening is narrower than the opening width of the second opening.

14. The semiconductor device according to claim 12, wherein the first opening and the second opening are each formed in a tapered shape, and the taper angle of the first opening is smaller than the taper angle of the second opening.

15. The semiconductor device according to claim 14, wherein a surface of the first opening that contacts the gate electrode and a surface of the second opening that contacts the gate electrode are inclined downward toward the gate electrode.

16. The semiconductor device according to claim 12, wherein the second protective layer contains one or more elements selected from the group consisting of Si, Al, Hf, Zr, Ta, and Ti.

17. The semiconductor device according to claim 12, wherein the first protective layer and the second protective layer are made of different materials.

18. The material of the first protective layer is HfO ２ The semiconductor device according to claim 17 , wherein the material of the second protective layer is SiN.

19. An electric circuit comprising a semiconductor device comprising: a first semiconductor layer including a carrier gas region; a second semiconductor layer provided on the first semiconductor layer; a first protective layer provided on the second semiconductor layer; a gate electrode that penetrates the first protective layer and is joined to the second semiconductor layer; and a source electrode and a drain electrode that are provided on the first semiconductor layer with the gate electrode between them; wherein the first protective layer has a first region that contacts the gate electrode and a second region other than the first region, and the first region is a region in which the density of elements that make up the first protective layer is lower than in the second region.

20. An electronic device comprising an electric circuit having a semiconductor device, the semiconductor device comprising: a first semiconductor layer including a carrier gas region; a second semiconductor layer provided on the first semiconductor layer; a first protective layer provided on the second semiconductor layer; a gate electrode that penetrates the first protective layer and is joined to the second semiconductor layer; and a source electrode and a drain electrode that are provided on the first semiconductor layer with the gate electrode between them, the first protective layer having a first region in contact with the gate electrode and a second region other than the first region, and the first region being a region in which the density of elements that make up the first protective layer is lower than that of the second region.

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