Storage device and electronic equipment

Abstract

A storage device according to one embodiment of the present disclosure comprises a plurality of memory cells, each of the plurality of memory cells having: a memory element in which a resistance value or the direction of polarization is variable; and an inverter circuit connected to the memory element or an inverter circuit including the memory element. In the plurality of memory cells, an output of the inverter circuit of the memory cell is connected to an input of the inverter circuit of another of the memory cells.

Description

Storage devices and electronic equipment

[0001] The present disclosure relates to a storage device and an electronic device.

[0002] Nonvolatile memories include various types of memories such as VC-MRAM (Voltage Control-Magnetic Random Memory). VC-MRAM is a next-generation memory used in cache memory, main memory, storage memory, etc., and is characterized by small memory cells, high speed, and low power consumption. A memory cell (bit cell) of VC-MRAM is typically composed of a circuit in which a magnetic tunnel junction (MTJ) element, whose resistance is variable when an external voltage is applied, and a select transistor (access transistor) are connected in series (see, for example, Patent Document 1).

[0003] JP 2018-92696 A

[0004] However, in a memory such as a VC-MRAM, for example, it is necessary in principle to apply a steep signal (for example, a write pulse rise time Tr / fall time Tf of 100 ps or less) during writing, but as the memory array becomes larger, the signal waveform becomes dull and data may not be written correctly to the memory. For example, in an MTJ element located far from the write driver, the signal waveform may become dull due to the wiring resistance and capacitance connected to the signal transmission path to the MTJ element, and a write error may occur.

[0005] Therefore, the present disclosure provides a storage device and an electronic device that can suppress write errors.

[0006] A memory device according to one embodiment of the present disclosure includes a plurality of memory cells, each of which has a memory element having a variable resistance value or polarization direction, and an inverter circuit connected to the memory element or an inverter circuit including the memory element, and in the plurality of memory cells, the output of the inverter circuit of one memory cell is connected to the input of the inverter circuit of another memory cell.

[0007] An electronic device according to one embodiment of the present disclosure includes a memory device having a plurality of memory cells, each of which has a memory element whose resistance value or polarization direction is variable, and an inverter circuit connected to the memory element or an inverter circuit including the memory element, and in the plurality of memory cells, the output of the inverter circuit of one memory cell is connected to the input of the inverter circuit of another memory cell.

[0008] 1 is a diagram illustrating a configuration example of a memory device according to an embodiment of the present disclosure. FIG. 2 is a diagram illustrating a configuration example of a portion of a memory device according to an embodiment of the present disclosure. FIG. 3 is a diagram illustrating a write operation according to an embodiment of the present disclosure. FIG. 4 is a diagram illustrating a write pulse according to an embodiment of the present disclosure. FIG. 5 is a diagram illustrating a write pulse waveform for a memory cell to be written to according to an embodiment of the present disclosure. FIG. 6 is a diagram illustrating a write pulse waveform for a memory cell to be written to in a comparative example according to an embodiment of the present disclosure. FIG. 7 is a diagram illustrating memory cells in the first stage, the 511th stage, and the 512th stage to be written to according to an embodiment of the present disclosure. FIG. 8 is a diagram illustrating write pulse waveforms for a memory cell in the first stage, the 511th stage, and the 512th stage to be written to according to an embodiment of the present disclosure. FIG. 9 is a diagram illustrating a read operation according to an embodiment of the present disclosure. FIG. 10 is a diagram illustrating voltages during read according to an embodiment of the present disclosure. FIG. 11 is a diagram illustrating specific input signals for write and read according to an embodiment of the present disclosure. FIG. 12 is a diagram illustrating a timing chart during write according to an embodiment of the present disclosure. FIG. 13 is a diagram illustrating a timing chart during read according to an embodiment of the present disclosure. FIG. 14 is a diagram illustrating a current flowing in a transistor of a memory cell according to an embodiment of the present disclosure. FIG. 15 is a diagram illustrating adjusting a current flowing in a transistor of a memory cell by a back bias according to an embodiment of the present disclosure. FIG. 16 is a diagram illustrating adjusting a current flowing in a transistor of a memory cell by a power supply voltage according to an embodiment of the present disclosure. FIG. 1 is a diagram showing a configuration example of a memory cell of Modification 1 according to an embodiment of the present disclosure. FIG. 2 is a diagram showing a configuration example of a memory cell of Modification 2 according to an embodiment of the present disclosure. FIG. 3 is a diagram showing a configuration example of a memory cell of Modification 3 according to an embodiment of the present disclosure. FIG. 4 is a diagram showing a configuration example of a memory cell of Modification 4 according to an embodiment of the present disclosure. FIG. 5 is a diagram showing a configuration example of a memory cell of Modification 5 according to an embodiment of the present disclosure. FIG. 6 is a diagram showing the relationship between voltage and current of a ReRAM (Resistive Random Access Memory) according to an embodiment of the present disclosure. FIG. 7 is a diagram showing the relationship between voltage and current of a PRAM (Phase-change Random Access Memory) according to an embodiment of the present disclosure. FIG. 8 is a diagram showing an example of a configuration example of a memory cell of Modification 6 according to an embodiment of the present disclosure.FIG. 1 is a diagram illustrating a relationship between voltage and polarization of a Ferroelectric Random Access Memory (FeRAM) according to an embodiment of the present disclosure; FIG. 2 is a diagram for explaining a read operation when a memory cell according to an embodiment of the present disclosure is an FeRAM; FIG. 3 is a diagram illustrating an application example of a storage device according to the above-described embodiment; FIG. 4 is a diagram illustrating a configuration example of an imaging device according to an application example; and FIG. 5 is a diagram illustrating a configuration example of a distance measuring device according to an application example.

[0009] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The embodiments include examples and modified examples. Note that the embodiments do not limit the devices, equipment, methods, etc. according to the present disclosure. Furthermore, in the following embodiments, essentially identical components are designated by the same reference numerals, and redundant explanations will be omitted.

[0010] The present disclosure will be described in the following order: 1. Embodiment 1-1. Configuration example of memory device 1-2. Example of write operation 1-3. Example of read operation 1-4. Specific examples of write operation and read operation 1-5. Example of current adjustment of memory cell transistor 1-6. Modified examples of memory cell 1-6-1. Modified example 1 1-6-2. Modified example 2 1-6-3. Modified example 3 1-6-4. Modified example 4 1-6-5. Modified example 5 1-6-6. Modified example 6 1-7. Actions and effects 2. Other embodiments 3. Application examples 3-1. Various devices 3-2. Imaging device 3-3. Distance measuring device 4. Supplementary notes

[0011] <1. Embodiment> <1-1. Configuration example of storage device> A configuration example of a storage device 10 according to this embodiment will be described with reference to Fig. 1 and Fig. 2. Fig. 1 is a diagram showing a configuration example of the storage device 10 according to this embodiment. Fig. 2 is a diagram showing a configuration example of a part of the storage device 10 according to this embodiment.

[0012] 1 and 2, the memory device 10 includes a memory cell array 11. The memory device 10 is an example of a memory device that stores data.

[0013] The memory cell array 11 includes a plurality of memory cells (bit cells) 100. These memory cells 100 are arranged in a matrix. Each memory cell 100 is connected to a bit line BL (e.g., BL0...BLj-1, BLj, BLj+1...) and a word line WL (e.g., WL00, WL01...WL0j-1, WL0j, WL0j+1...WLi0, WLi1, WLij-1, WLij, WLij+1...).

[0014] Each of the plurality of word lines WL is wired to extend, for example, in the row direction, and each of the plurality of bit lines BL is wired to extend, for example, in the column direction, and each of the bit lines BL and word lines WL functions as a signal line (control line).

[0015] Each memory cell 100 includes a memory element 110 and an inverter circuit 120. The inverter circuit 120 may also be called, for example, a NOT circuit or a NOT gate.

[0016] The memory element 110 is, for example, a magnetoresistive element (magnetoresistive effect element) with a variable resistance value. For example, a magnetic tunnel junction (MTJ) element is used as this magnetoresistive element. Examples of the magnetoresistive element include a voltage-driven magnetoresistive element (VC-MRAM) that writes data by applying a pulse voltage.

[0017] An MTJ element is an element in which a nonmagnetic insulating layer is disposed between two ferromagnetic layers, and its resistance value changes depending on the magnetization direction of the two ferromagnetic layers. The MTJ element is in a high-resistance state when the magnetization directions of the two ferromagnetic layers are different, and in a low-resistance state when the magnetization directions are the same. The state in which the magnetization directions are the same is called a parallel state, and the state in which the magnetization directions are different is called an anti-parallel state. This magnetization direction changes by applying a write voltage to the MTJ element. For example, values ​​"0" and "1" can be associated with the low-resistance state and high-resistance state of the MTJ element to store one bit of data. The values ​​"0" and "1" are also called low-level voltage (L) and high-level voltage (H).

[0018] The inverter circuit 120 has a plurality of transistors 121 and 122. The inverter circuit 120 is configured by combining the transistors 121 and 122. The inverter circuit 120 is a circuit that controls the application of voltage, current, and the like to the memory element 110. In the examples of FIGS. 1 and 2 , the transistor 121 is an NMOS transistor (N-channel Metal-Oxide-Semiconductor Field-Effect Transistor: NMOSFET), and the transistor 122 is a PMOS transistor (P-channel Metal-Oxide-Semiconductor Field-Effect Transistor: PMOSFET).

[0019] The output (output terminal) of the inverter circuit 120 is connected to the input (input terminal) of the inverter circuit 120 in the next stage adjacent to the inverter circuit 120 via a word line WL. The output (output terminal) of the inverter circuit 120 is also connected to one end of the memory element 110 via the word line WL. The other end of the memory element 110 is connected to a bit line BL. The input terminal of the inverter circuit 120 is connected to the gates of the transistors 121 and 122, respectively, and the output terminal of the inverter circuit 120 is connected to the drain and source of the transistors 121 and 122.

[0020] In addition, the inverter circuit 120 most upstream in the direction of signal flow is the first stage (first stage) circuit, the inverter circuit 120 downstream of the first stage is the second stage circuit, the inverter circuit 120 downstream of the second stage is the third stage circuit, and the inverter circuit 120 downstream of the third stage is the fourth stage circuit. In this way, the number of stages increases toward the downstream side, and the most downstream inverter circuit 120 is the final stage circuit.

[0021] The inputs of the inverter circuits 120 in the first stage are connected to the word line control circuit 27, and the outputs of the inverter circuits 120 in the last stage are connected to the output circuit 28. In the example of Figure 2, the outputs of the inverter circuits 120 located at the left end of the memory cell array 11 are connected to the word line control circuit 27 by word lines WL (e.g., WL00 to WLn0), and the outputs of the inverter circuits 120 located at the right end of the memory cell array 11 are connected to the output circuit 28 by word lines WL (e.g., WL0m to WLnm). Each of the word lines WL also functions as a source line that transmits a signal from the memory element 110 during readout.

[0022] 1 and 2, the peripheral circuit 20 includes an I / O (input / output circuit) 21, a control circuit 22, a voltage generating circuit 23, a bit line address decoder 24, a bit line control circuit 25, a word line address decoder 26, a word line control circuit 27, and an output circuit 28. The bit line control circuit 25 is connected to the bit line BL, and the word line control circuit 27 and the output circuit 28 are connected to the word line WL.

[0023] The I / O 21 enables the exchange of commands related to reading and writing data, addresses of memory cells 100 to be accessed, data, etc. between an external circuit (e.g., an arithmetic circuit) of the memory device 10 and the control circuit 22 of the memory device 10.

[0024] In response to a command, the control circuit 22 controls writing and reading of data to and from the memory cell 100. For example, the control circuit 22 receives a command (such as a write or read command) from an external circuit, and controls writing and reading of data based on the received command.

[0025] For example, the control circuit 22 outputs write and read addresses to a bit line address decoder 24 and a word line address decoder 26. The control circuit 22 also outputs control signals to a word line control circuit 27 and the like, and obtains read data from an output circuit 28.

[0026] The voltage generating circuit 23 generates a voltage (for example, a pulse voltage) used to write and read data to and from the memory cell 100 .

[0027] The bit line address decoder 24 selects a bit line BL of the memory cell array 11 based on a control signal from the control circuit 22. For example, the bit line address decoder 24 selects a bit line BL corresponding to an address received at the I / O 21.

[0028] The bit line control circuit 25 outputs a control signal to the bit line BL selected by the bit line address decoder 24 .

[0029] The word line address decoder 26 selects a word line WL of the memory cell array 11 based on a control signal from the control circuit 22. For example, the word line address decoder 26 selects a word line WL corresponding to an address received at the I / O 21.

[0030] The word line control circuit 27 outputs a control signal to the word line WL selected by the word line address decoder 26 .

[0031] The output circuit 28 includes a holding circuit 28a and a data output circuit 28b (see FIG. 2). The holding circuit 28a holds data read from each memory cell 100. The data output circuit 28b outputs the data held by the holding circuit 28a.

[0032] The above-mentioned writing to the memory cell 100 is performed, for example, when the stored data in the memory cell 100 differs from the write data. Specifically, data is read from the memory cell 100, and the read data is compared with the write data. If the comparison shows that the two data differ, writing is performed. Writing is performed by inverting the stored data (memory state) of the memory cell 100. The memory state of the memory element 110 is inverted, for example, by applying a predetermined write voltage to the memory element 110. Reading is performed, for example, by applying a predetermined read current to the memory element 110 and detecting the output voltage of the memory cell 100. It is preferable that the read voltage has a polarity different from that of the write voltage. Details of writing and reading to the memory element 110 will be described later.

[0033] <1-2. Example of Write Operation> An example of a write operation according to this embodiment will be described with reference to FIGS.

[0034] Fig. 3 is a diagram for explaining an example of a write operation according to this embodiment, and Fig. 4 is a diagram for explaining a write pulse (write signal) according to this embodiment.

[0035] 3, a high write voltage Vw (see FIG. 4) is applied to the bit line BLj to which the memory cell 100 (memory element 110) to be written is connected. A voltage Vdd / 2, for example, is applied to the bit lines BL (e.g., BL0...BLj-1, BLj+1...) other than the bit line BLj to which the memory cell 100 to be written is connected. Vdd is the power supply voltage.

[0036] In this voltage application state, when a write pulse is input to word line WL00 to which the memory cell 100 to be written is connected, the write pulse propagates through each memory cell 100 and each word line WL (WL01...WL0j-1, WL0j, WL0j+1...).

[0037] 3 and 4, the write pulse on word line WL00 is inverted by inverter circuit 120 and propagates to the next word line WL01. This inversion and propagation is repeated for each inverter circuit 120. Then, the write pulse on word line WL0j-1 is inverted by inverter circuit 120 and propagates to the next word line WL0j. In the example of FIGS. 3 and 4, the write pulse is a downward pulse on word line WL00, an upward pulse on word line WL01, then an upward pulse on word line WL0j-1, a downward pulse on word line WL0j, and an upward pulse on word line WL0j+1.

[0038] When a write pulse reaches a transistor 121 (e.g., an NMOS transistor) that drives a memory element 110 in a memory cell 100 to be written, the transistor 121 turns on and a current flows, generating a voltage in the memory element 110. This voltage is a voltage V ＭＴＪ The voltage generated in the memory element 110 is V ＭＴＪ The write voltage Vw is adjusted so that the resistance of the memory element 110 in the memory cell 100 to be written can be changed.

[0039] As mentioned above, a voltage that prevents writing is applied to the bit lines BL (e.g., BL0, BLj-1, BLj+1, etc.) other than the bit line BLj to which the memory cell 100 to be written is connected. In the examples of FIGS. 3 and 4, Vdd / 2 is used as the voltage that prevents writing, but if there is a possibility that data may be rewritten, a voltage lower than Vdd / 2 may be used while maintaining a voltage that can contribute to propagation. This makes it possible to reliably suppress erroneous writing.

[0040] FIG. 5 is a diagram for explaining a write pulse waveform for the memory cell 100 to be written according to this embodiment.

[0041] 5, the write pulse waveform is shaped by the inverter circuits 120 as it propagates through each inverter circuit 120 and each bit line BL (write pulse propagation path), so the write pulse waveform does not become dull. As a result, the write pulse waveform is steep, and the write is successful (resistance transition successful). Whether the memory cell 100 to be written is close or far from the word line control circuit 27, that is, regardless of its position relative to the word line control circuit 27, the write pulse waveform for the memory cell 100 to be written is steep, so the write is successful.

[0042] The memory cell 100 is composed of a memory element 110 and an inverter circuit 120 that treats the memory element 110 as a load. Specifically, one terminal of the memory element 110 is connected to the output of the inverter circuit 120, and the other terminal of the memory element 110 is connected to the bit line BL. The output of the inverter circuit 120 is connected to the input of the inverter circuit 120 of the memory cell 100 in the next stage. As a result, the inverter circuits 120 of each memory cell 100 are connected in sequence, so that the write pulse propagates through the inverter chain (the connection structure of each inverter circuit 120) without any waveform distortion.

[0043] Furthermore, a high write voltage Vw required for writing is applied to the bit line BL to which the memory cell 100 to be written is connected. As a result, the voltage V required for writing is applied only to the memory element 110 of that memory cell 100. ＭＴＪ A pulse of Vdd / 2 is applied to write data. A low voltage Vdd / 2, which does not cause writing, is applied to the bit line BL connected to the memory cells 100 that are not the target of writing. This allows the memory cells 100 that are not the target of writing to contribute only to pulse propagation.

[0044] Comparative Example FIG. 6 is a diagram for explaining a write pulse waveform for a memory cell 100a to be written in a comparative example according to the present embodiment.

[0045] As shown in FIG. 6, the memory cell 100a is composed of a magnetoresistive element 110a and a selection element 130. The selection element 130 has a drain, a source, and a gate. One end of the magnetoresistive element 110a is connected to a bit line BL, and the other end of the magnetoresistive element 110a is connected to the source or drain of the selection element 130. The gate of the selection element 130 is connected to a word line WL, and the source or drain of the selection element 130 is grounded. In the example of FIG. 6, a write driver 140 is provided for each bit line BL.

[0046] If the memory cell 100a is close to the write driver 140, the write pulse waveform is steep (near-end waveform: small wiring delay), and the write is successful (resistance transition successful). On the other hand, if the memory cell 100a is far from the write driver 140, the write pulse waveform becomes gentle (far-end waveform: large wiring delay), and the write may fail (resistance transition failed). The farther the memory cell 100a is from the write driver 140, the more likely the write pulse waveform becomes dull due to the influence of the wiring resistance R1 and capacitance C1, and the write may fail.

[0047] To prevent such pulse waveform distortion, for example, limiting the size of the memory cell array 11 or multi-layering the metal of the bit line BL would result in increased cost due to increased area and process steps. Furthermore, for readout, the resistance of the magnetoresistive element 110a must be made sufficiently higher than that of the selection element 130. In this case, the cell current of the memory cell 100a would decrease, resulting in a decrease in readout speed.

[0048] On the other hand, according to this embodiment, it is possible to suppress these cost increases and reductions in read speed. Since the write pulse propagates through the write pulse propagation path while its waveform is shaped by the inverter circuit 120, it is possible to suppress distortion of the write pulse waveform and reduce write errors. This makes it possible to suppress cost increases such as increases in area and process steps. Furthermore, since the only thing driven by the current of a memory cell 100 is the input capacitance of the memory cell 100 in the next stage, even if the resistance of the memory element 110 is increased, it has almost no effect on the read speed. This makes it possible to suppress reductions in read speed.

[0049] (Maintaining Write Pulse Waveform) Fig. 7 is a diagram showing the memory cells 100 in the first stage, the 511th stage, and the 512th stage to be written to according to this embodiment. Fig. 8 is a diagram showing write pulse waveforms for the memory cells 100 in the first stage, the 511th stage, and the 512th stage to be written to according to this embodiment.

[0050] 7, the memory cell 100 connected to word line WL00 is the first stage, and the memory cell 100 connected to word line WL01 is the second stage. The number of stages increases in this manner. The memory cell 100 connected to word line WL0j-1 is the 511th stage, and the memory cell 100 connected to word line WL0j is the 512th stage. This 512th stage memory cell 100 is the target for writing.

[0051] 8, the write pulse of the word line WL00 is a steep pulse. The fall time Tf of the write pulse of this word line WL00 is, for example, 41.19 ps. The write pulses of the word lines WL0j-1 and WL0j are also steep pulses. The resistance R of the memory element 110 ＭＴＪ The resistance of the word line WL0j changes from low to high, and the write is successful (resistance transition successful). The fall time Tf of the write pulse on the word line WL0j is, for example, 6.37 ps. Note that in the comparative example described above (see FIG. 6), the fall time Tf of the write pulse on the word line WL0j can be, for example, about 500 ps, ​​which is about 10 times longer than that of the first stage.

[0052] These results show that even if the memory cell 100 to be written to is far from the word line control circuit 27 (stage 512), the write pulse waveform is steep rather than gradual, and therefore the write is successful. Furthermore, the fall time Tf (=6.37 ps) of the write pulse on word line WL0j is shorter than the fall time Tf (=41.19 ps) of the write pulse on word line WL00. Therefore, it can be seen that the write pulse on stage 512 may be a pulse that is steeper (e.g., a pulse with a steeper fall) than the write pulse on the first stage.

[0053] 1-3. Example of Read Operation An example of a write operation according to this embodiment will be described with reference to Fig. 9 and Fig. 10. Fig. 9 is a diagram for explaining the read operation according to this embodiment. Fig. 10 is a diagram for explaining voltages during read according to this embodiment.

[0054] 9, a negative read voltage Vr (see FIG. 10) is applied to the bit line BLj to which the memory cell 100 (memory element 110) to be read is connected. A voltage of, for example, Vdd / 2 is applied to the bit lines BL (e.g., BL0, BLj-1, BLj+1, . . .) other than the bit line BLj to which the memory cell 100 to be read is connected.

[0055] In this voltage application state, a signal is input to word line WL00 so that a high-level signal (H) is output from word line WL00 connected to the first-stage memory cell 100 to word line WL0j connected to the memory cell 100 being read. The output voltage of this high-level signal is determined by, for example, Vr, the resistance of the memory element 110, the amount of current in the transistor 122 (e.g., a PMOS transistor) that drives the memory element 110 being read, and the like.

[0056] 9 and 10 , the intermediate voltage between the voltage VrH when the memory element 110 has a high resistance and the voltage VrL when the memory element 110 has a low resistance is designed to be the logic threshold (e.g., Vdd / 2) of the inverter circuit 120 (a sense amplifier) ​​in the next stage. This allows the inverter circuit 120, which functions as the sense amplifier in the next stage, to read a high-level (H) signal or a low-level (L) signal. The read signal (high-level signal or low-level signal) is input to the output circuit 28 via each inverter circuit 120 and each word line WL.

[0057] As described above, a voltage that prevents writing is applied to the bit lines BL (e.g., BL0, BLj-1, BLj+1, etc.) other than the bit line BLj to which the memory cell 100 to be read is connected. In the examples of FIGS. 9 and 10, Vdd / 2 is used as the voltage that prevents writing, but if there is a possibility that data may be rewritten, a voltage lower than Vdd / 2 may be used while maintaining a voltage that can contribute to propagation. This makes it possible to reliably suppress erroneous writing.

[0058] 1-4. Specific Examples of Write and Read Operations Specific examples of write and read operations according to this embodiment will be described with reference to FIGS. 11 to 13. FIG.

[0059] (Input Signals) FIG. 11 is a diagram for explaining specific input signals for writing and reading according to this embodiment. As shown in FIG. 11, input signals are determined for each column and row. Columns correspond to bit lines BL, and rows correspond to word lines WL. The write voltage Vw, read voltage Vr, and voltage VddM (Vdd / 2) are analog signals. The upward pulse, downward pulse, low level (L), and high level (H) are digital signals.

[0060] During writing (Write), if the selected column (bit line BL) is an even column (Even: BL0, BL2, ...), the selected column is given a write voltage Vw, the unselected columns are given a voltage VddM (Vdd / 2), the selected row (word line WL) is given an upward pulse, and the unselected rows are given a low level (L).

[0061] During writing (Write), if the selected column (bit line BL) is an odd column (Odd: BL1, BL3, ...), the selected column is given a write voltage Vw, the unselected columns are given a voltage VddM (Vdd / 2), the selected row (word line WL) is given a downward pulse, and the unselected rows are given a high level (H).

[0062] During read (Read), if the selected column (bit line BL) is an even column (Even: BL0, BL2, ...), the selected column is given a read voltage Vr, the unselected columns are given a voltage VddM (Vdd / 2), the selected row (word line WL) is given a low level (L), and the unselected rows are given a high level (H).

[0063] During read (Read), if the selected column (bit line BL) is an odd column (Odd: BL1, BL3, ...), the selected column is given a read voltage Vr, the unselected columns are given a voltage VddM (Vdd / 2), the selected row (word line WL) is given a high level (H), and the unselected rows are given a low level (L).

[0064] (Timing chart during writing) Figure 12 is a diagram showing a timing chart during writing according to this embodiment. In the example of Figure 12, CK corresponds to the clock, CE corresponds to the chip select, WE corresponds to writing, Address corresponds to the write address, and DATAI corresponds to the input data (write data). The input data is, for example, 0 (L) or 1 (H).

[0065] The control circuit 22 functions as, for example, a timing control circuit, and controls a bit line address decoder 24, a bit line control circuit 25, a word line address decoder 26, a word line control circuit 27, an output circuit 28, etc. (see FIG. 2).

[0066] 12, at write timing T1, input signals are applied to the word lines WL and bit lines BL based on the write address. As described above (see FIG. 11), the input signals differ depending on whether the word lines WL and bit lines BL are active or inactive. Active signals correspond to selected rows and selected columns, and inactive signals correspond to unselected rows and unselected columns.

[0067] A write pulse (upward pulse or downward pulse) is applied to the active word line WL00 depending on whether the active bit line BL is an even-numbered column or an odd-numbered column, and a low level (L) or a high level (H) is applied to the inactive word line WLn0 other than the active word line WL00 depending on whether the active bit line BL is an even-numbered column or an odd-numbered column.

[0068] A write voltage Vw is applied to the active bit lines BL (e.g., BLj), and a voltage Vdd / 2 is applied to the inactive bit lines BL (e.g., BLs other than BLj).

[0069] The write pulse applied to the word line WL00 propagates through each of the word lines WL00, . . . WL0j-1, WL0j (write target). At this time, the write pulse also propagates through each inverter circuit 120. When the write pulse reaches the word line WL0j (write target), a voltage V based on the write voltage Vw is applied. ＭＴＪ is applied to the memory element 110. This changes the resistance state of the memory element 110. For example, the resistance state of the memory element 110 is switched from a high resistance state to a low resistance state, or from a low resistance state to a high resistance state.

[0070] (Timing chart during reading) Figure 13 is a diagram showing a timing chart during reading according to this embodiment. In the example of Figure 13, CK corresponds to the clock, CE corresponds to the chip select, WE corresponds to the write, Address corresponds to the read address, and DATAO corresponds to the output data (read data). The output data is, for example, 0 (L) or 1 (H).

[0071] 13, at read timing T2, input signals are applied to the word line WL and the bit line BL based on the read address. As described above (see FIG. 11), the input signals differ depending on whether the word line WL and the bit line BL are active or inactive.

[0072] A low level (L) or a high level (H) is applied as a read signal to the active word line WL00 depending on whether the active bit line BL is in an even-numbered column or an odd-numbered column. Similarly, a high level (H) or a low level (L) is applied to an inactive word line WLn0 other than the active word line WL00 depending on whether the active bit line BL is in an even-numbered column or an odd-numbered column.

[0073] A read voltage Vr is applied to the active bit lines BL (e.g., BLj), and a voltage Vdd / 2 is applied to the inactive bit lines BL (e.g., BLs other than BLj).

[0074] A read signal applied to word line WL00 propagates through each active word line WL00...WL0j-1, WL0j (read target). At this time, the read signal also propagates through each inverter circuit 120. When the read signal reaches word line WL0j (read target), a voltage VrL or voltage VrH based on the read voltage Vr is read from the memory element 110. The read voltage VrL or voltage VrH is input to the next-stage inverter circuit 120. This inverter circuit 120 compares the voltage VrL or voltage VrH with voltage Vdd / 2 and outputs the comparison result. This determines whether the resistance state of the memory element 110 is a high resistance state or a low resistance state.

[0075] 1-5. Example of Current Adjustment of Transistor of Memory Cell> An example of current adjustment of the transistor 121 of the memory cell 100 according to this embodiment will be described with reference to FIGS. 14 to 16. FIG. 14 shows the current I ＮＭ 15 is a diagram for explaining the current I flowing through the transistor 121 of the memory cell 100 according to this embodiment. ＮＭ 16 is a diagram for explaining how the current I flows through the transistor 121 of the memory cell 100 according to this embodiment. ＮＭ is adjusted by the power supply voltage Vpp (=Vdd).

[0076] As shown in FIG. 14, the current flowing through the memory element 110 is I ＭＴＪ and the current flowing through the transistor 121 is I ＮＭ The power supply voltage is Vpp (=Vdd), and the back bias is Vc. The back bias Vc is, for example, a substrate bias of a semiconductor.

[0077] When the current driving capability of the transistor 121 is sufficiently high, the write voltage Vw (=voltage V ＭＴＪ ) is applied to the memory element 110. On the other hand, if the current driving capability of the transistor 121 is not high enough, the amount of current (I ＮＭ ) is adjusted appropriately, and the voltage V ＭＴＪ must be applied to the memory element 110.

[0078] As shown in FIGS. 15 and 16, the amount of current (I ＮＭ ) is adjusted. This adjusts the amount of current (current I ＮＭ The amount of voltage V ＭＴＪ can be applied to the memory element 110.

[0079] <1-6. Modified Examples of Memory Cell> Modified examples 1 to 6 of the memory cell 100 according to this embodiment will be described with reference to FIGS. 17 to 26. FIG.

[0080] <1-6-1. Modification 1> Fig. 17 is a diagram showing an example configuration of a memory cell 100 according to Modification 1 of this embodiment. As shown in Fig. 17, the memory cell 100 according to Modification 1 has an inverter circuit 120A. The inverter circuit 120A is composed of a memory element 110 and a transistor 121. The transistor 121 is, for example, an NMOS transistor.

[0081] According to the first modification, by reducing the number of components of the memory cell 100, it is possible to reduce the size of the memory cell 100, thereby improving area efficiency.

[0082] <1-6-2. Modification 2> Fig. 18 is a diagram showing an example configuration of a memory cell 100 according to Modification 2 of this embodiment. As shown in Fig. 18, the memory cell 100 according to Modification 2 has an inverter circuit 120B. The inverter circuit 120B is composed of a memory element 110, a transistor 121, and a resistor 125. The transistor 121 is, for example, an NMOS transistor.

[0083] According to the second modification, by connecting the resistor 125 to the transistor 121, it is possible to shorten the rise time Tr of the pulse waveform, and therefore it is possible to realize a pulse waveform that is steeper than that of the first modification.

[0084] <1-6-3. Modification 3> FIG. 19 is a diagram showing an example configuration of a memory cell 100 according to Modification 3 of this embodiment. As shown in FIG. 19, each memory cell 100 according to Modification 3 has an inverter circuit 120A (see FIG. 17 for Modification 1) or an inverter circuit 120C. The inverter circuits 120A and 120C are alternately arranged along the row direction. The inverter circuit 120C is composed of a memory element 110 and a transistor 122. The transistor 122 is, for example, a PMOS transistor.

[0085] According to the third modification, as in the first modification, the number of components of the memory cell 100 can be reduced, thereby making it possible to reduce the size of the memory cell 100, thereby improving area efficiency.

[0086] <1-6-4. Modification 4> FIG. 20 is a diagram showing an example of the configuration of a memory cell 100 according to Modification 4 of this embodiment. As shown in FIG. 20, each memory cell 100 according to Modification 4 has an inverter circuit 120B (see FIG. 18 for Modification 2) or an inverter circuit 120D. The inverter circuits 120B and 120D are alternately arranged along the row direction. The inverter circuit 120D is composed of a memory element 110, a transistor 122, and a resistor 126. The transistor 122 is, for example, a PMOS transistor.

[0087] According to the fourth modification, by connecting a resistor 125 to the transistor 121, it is possible to shorten the rise time Tr of the pulse waveform, and by connecting a resistor 126 to the transistor 122, it is possible to shorten the fall time Tf of the pulse waveform, so that a steeper pulse waveform can be realized compared to the first modification.

[0088] 21 is a diagram showing a configuration example of a memory cell 100 according to Modification 5 of the present embodiment. As shown in Fig. 21, a memory element 110A of the memory cell 100 according to Modification 5 is, for example, a ReRAM or PRAM whose resistance value is variable.

[0089] 22 is a diagram showing the relationship between voltage and current in the ReRAM according to this embodiment. As shown in FIG. 22, a write bit line bias (e.g., write voltage Vw) is applied to the write bit line BLj (see FIG. 21). Also, a propagation bit line bias (e.g., Vdd / 2) is applied to the propagation bit lines BL (e.g., BL0...BLj-1, BLj+1...) (see FIG. 21). The propagation bit line bias is set to a low voltage at which writing does not occur.

[0090] In the ReRAM, the propagation of write and read signals is basically the same as when the memory element 110 is a magnetoresistive element (e.g., VC-MRAM). During the signal propagation process, the voltage applied to the bit line BL is kept low to prevent writing. A desired voltage is applied to the bit line BL to be written.

[0091] 23 is a diagram showing the relationship between voltage and current in the PRAM according to this embodiment. As shown in FIG. 23, a write bit line bias (e.g., write voltage Vw) is applied to the write bit line BLj (see FIG. 21). Also, a propagation bit line bias (e.g., Vdd / 2) is applied to the propagation bit lines BL (e.g., BL0...BLj-1, BLj+1...) (see FIG. 21). The propagation bit line bias is set to a low voltage at which writing does not occur.

[0092] In the PRAM, the write and read signals are propagated in the same manner as in the case where the memory element 110 is a magnetoresistive element (e.g., VC-MRAM). During the signal propagation process, the voltage applied to the bit line BL is kept low to prevent writing. A desired voltage is applied to the bit line BL to be written.

[0093] 24 is a diagram showing a configuration example of a memory cell 100 according to Modification 6 of the present embodiment. As shown in Fig. 24, a memory element 110B of the memory cell 100 according to Modification 6 is, for example, an FeRAM.

[0094] 25 is a diagram showing the relationship between voltage and polarization in the FeRAM according to this embodiment. As shown in FIG. 25, a write bit line bias (e.g., write voltage Vw: −write VFRAMP or +write VFRAMP) is applied to the write bit line BLj (see FIG. 24). Also, a propagation bit line bias (e.g., Vdd / 2) is applied to the propagation bit lines BL (e.g., BL0...BLj-1, BLj+1...). The propagation bit line bias is set to a low voltage at which writing does not occur.

[0095] In FeRAM, the propagation of write and read signals is basically the same as when the memory element 110 is a magnetoresistive element (e.g., VC-MRAM). During the signal propagation process, the voltage applied to the bit line BL is kept low to prevent writing. A desired voltage is applied to the bit line BL to be written to or read from. By applying a small read voltage Vr, data "0" can be read without being inverted.

[0096] FIG. 26 is a diagram illustrating a read operation when the memory cell 100 according to this embodiment is an FeRAM. As shown in FIG. 26, during read, a negative bias is applied to the bit line BLj to which the memory cell 100 to be read is connected. During read, the potential of the word line WL0j changes depending on the polarization direction of the memory element 110B, and this potential is detected by the inverter circuit 120 (deemed sense amplifier) ​​in the next stage. Note that, for example, Vdd / 2 is applied to the bit lines BL other than the bit line to be read (e.g., BL0...BLj-1, BLj+1...).

[0097] During the aforementioned negative polarization, transistor 121 of the preceding inverter circuit 120 turns on, lowering the potential of word line WL0j. On the other hand, during positive polarization, transistor 122 of the preceding inverter circuit 120 turns on, attempting to lower the potential of word line WL0j, but a negative bias is applied to memory element 110B, causing memory element 110B to reverse to negative polarization. At this time, a displacement current flows, acting in the direction of raising the potential. As a result, the drop in potential is suppressed.

[0098] <1-7. Actions and Effects> As described above, the memory device 10 according to this embodiment includes a plurality of memory cells 100. Each of the plurality of memory cells 100 includes a memory element 110 (or memory element 110A or memory element 110B) having a variable resistance value or polarization direction, and an inverter circuit 120 connected to the memory element 110 or an inverter circuit 120A (or inverter circuit 120B, inverter circuit 120C, or inverter circuit 120D) including the memory element 110. In the plurality of memory cells 100, the output of the inverter circuit 120 of one memory cell 100 is connected to the input of the inverter circuit 120 of another memory cell 100 (see, for example, FIGS. 1 and 2 ). As a result, regardless of which of the plurality of memory cells 100 is the memory cell 100 to be written to, the waveform of the write signal (e.g., a write pulse) input to the memory cell 100 to be written to will be steep, resulting in successful writing. Therefore, write errors can be suppressed.

[0099] Furthermore, the output of the inverter circuit 120 of a memory cell 100 may be connected to the input of the inverter circuit 120 of another memory cell 100 adjacent to the memory cell 100 (see FIGS. 1 and 2, etc.). This makes it possible to reliably suppress write errors.

[0100] Furthermore, the output of the inverter circuit 120 of the memory cell 100 may be connected to the input of the inverter circuit 120 of another memory cell 100 via a signal line (e.g., a word line WL) through which a write signal (e.g., a write pulse) passes (see FIGS. 1 and 2, etc.). This makes it possible to reliably suppress write errors.

[0101] Furthermore, a voltage (e.g., a write voltage Vw) that causes writing by a write signal (e.g., a write pulse) may be applied to the memory element 110 of the memory cell 100 to be written (see, for example, FIGS. 3 to 5). This ensures reliable writing.

[0102] Furthermore, a voltage (e.g., voltage Vdd / 2) that does not cause writing by a write signal (e.g., a write pulse) may be applied to the memory elements 110 of memory cells 100 other than the memory cell to be written (see, for example, FIGS. 3 to 5). This makes it possible to reliably suppress write errors.

[0103] Also, a control circuit (e.g., bit line control circuit 25) may be further provided that applies a voltage (e.g., write voltage Vw) that causes writing to occur to the memory element 110 of the memory cell 100 that is the write target, and a voltage (e.g., voltage Vdd / 2) that does not cause writing to the memory element 110 of the memory cell 100 that is not the write target (see FIGS. 1 and 2, etc.). This allows writing to be performed reliably, and furthermore, write errors can be reliably suppressed.

[0104] Furthermore, the input of the inverter circuit 120 of the first-stage memory cell 100 among the plurality of memory cells 100 may be connected to a control circuit (e.g., word line control circuit 27) that outputs a write signal (e.g., a write pulse) (see FIGS. 1 and 2, etc.). This allows the write signal to be reliably input from the control circuit to the inverter circuit 120 of the first-stage memory cell 100.

[0105] Furthermore, the output of the inverter circuit 120 of the final stage memory cell 100 among the plurality of memory cells 100 may be connected to an output circuit 28 that outputs data (see FIGS. 1 and 2, etc.). This allows the inverter circuit 120 of the final stage memory cell 100 to reliably output an output signal to the output circuit 28.

[0106] Furthermore, the inverter circuit 120 of the memory cell 100 may function as a sense amplifier for the memory cell 100 in the preceding stage of the memory cell 100 (see FIGS. 9 and 10). This allows reading to be performed with a simple configuration.

[0107] Furthermore, the inverter circuit 120 connected to the memory element 110 may include a plurality of transistors 121 and 122 connected to the memory element 110 (see, for example, FIGS. 1 and 2). This allows the inverter circuit 120 to be realized with a simple configuration.

[0108] Furthermore, the plurality of transistors 121 and 122 may include an NMOS transistor and a PMOS transistor (see FIGS. 1 and 2, etc.), thereby enabling the inverter circuit 120 to be reliably realized with a simple configuration.

[0109] In addition, the current amount of one of the plurality of transistors 121 and 122 (for example, I ＮＭ ) may be adjusted by the back bias Vc or the power supply voltage Vpp (=Vdd) (see FIGS. 14 to 16). This allows the amount of current flowing through the transistor 121 to be appropriately adjusted, and the voltage V ＭＴＪ can be applied to the memory element 110.

[0110] Furthermore, the inverter circuit 120A (or the inverter circuit 120C) including the memory element 110 may include a transistor 121 (or a transistor 122) connected to the memory element 110 (see FIGS. 17 and 19). This allows the inverter circuit 120A (or the inverter circuit 120C) to be realized with a simple configuration.

[0111] Furthermore, the transistor 121 (or the transistor 122) may be an NMOS transistor or a PMOS transistor (see FIGS. 17 and 19). This allows the inverter circuit 120 to be reliably realized with a simple configuration.

[0112] Furthermore, the inverter circuit 120A (or inverter circuit 120B) including NMOS transistors and the inverter circuit 120C (or inverter circuit 120D) including PMOS transistors may be provided alternately (see FIGS. 19 and 20), thereby improving the degree of freedom in design.

[0113] Furthermore, the inverter circuit 120B (or inverter circuit 120D) including the memory element 110 may further include a resistor 125 (or resistor 126) connected to the transistor 121 (or transistor 122) (see FIGS. 18 and 20). This allows the waveform of the write signal (e.g., write pulse) to be steeper.

[0114] In addition, the amount of current (for example, I ＮＭ ) may be adjusted by the back bias Vc or the power supply voltage Vpp (=Vdd) (see FIGS. 14 to 16). This allows the transistor 121 to be appropriately adjusted, and the voltage V ＭＴＪ can be applied to the memory element 110.

[0115] Furthermore, the configuration of the inverter circuit 120A (or inverter circuit 120B) of a memory cell 100 may be different from the configuration of the inverter circuit 120C (or inverter circuit 120D) of another memory cell 100 adjacent to that memory cell 100 (see FIGS. 19 and 20). This allows for greater design flexibility.

[0116] The memory element 110 may be a magnetic tunnel junction (MTJ) element, a resistive random access memory (ReRAM), a phase-change random access memory (PRAM), or a ferroelectric random access memory (FeRAM) (see FIGS. 1 and 21 to 26). Even with such a configuration, write errors can be suppressed. Furthermore, design flexibility can be improved.

[0117] 2. Other Embodiments The configurations and processes according to the above-described embodiments (including examples and modified examples) may be implemented in various different forms other than the above-described embodiments. For example, the configurations and processes are not limited to the above-described examples and may be implemented in various forms. Furthermore, for example, the configurations, processing procedures, specific names, or information including various data and parameters shown in the above documents and drawings may be changed arbitrarily unless otherwise specified.

[0118] Furthermore, the components and processes according to the above-described embodiments (including examples and modifications) do not necessarily have to be physically configured as shown in the drawings. In other words, the specific forms of distribution and integration of the components and processes are not limited to those shown in the drawings, and all or part of them may be functionally or physically distributed or integrated in any unit depending on various loads, usage conditions, etc.

[0119] Furthermore, the configurations and processes of the above-described embodiments (including examples and modified examples) may be combined as appropriate. For example, at least a part of an embodiment may be combined as appropriate with at least a part of another embodiment. Furthermore, the effects of the embodiments are merely examples and are not intended to be limiting, and other effects may also be obtained.

[0120] <3. Application Examples> <3-1. Various Devices> An application example of the storage device 10 according to the above-described embodiment (including modifications) will be described with reference to Fig. 27. Fig. 27 is a diagram showing an application example of the storage device 10 according to the above-described embodiment.

[0121] The storage device 10 according to the above-described embodiment may be applied to various cases where light such as visible light, infrared light, ultraviolet light, and X-rays is sensed, for example, as follows: For example, the storage device 10 may be applied to various devices (electronic devices) such as those described below, or electronic devices mounted on various devices.

[0122] As shown in FIG. 27 , the storage device 10 according to any of the above-described embodiments is used in, for example, "devices for capturing images for viewing, such as digital cameras and portable devices with camera functions," "devices for traffic use, such as in-vehicle sensors for capturing images of the front, rear, surroundings, and interior of a vehicle for safe driving such as automatic stopping and for recognizing the driver's state, surveillance cameras for monitoring moving vehicles and roads, and distance measurement sensors for measuring distances between vehicles," "devices for home appliances such as TVs, refrigerators, and air conditioners for capturing images of user gestures and operating the device in accordance with the gestures," "devices for medical and healthcare use, such as endoscopes and devices for capturing blood vessel images by receiving infrared light," "devices for security use, such as surveillance cameras for crime prevention and cameras for person authentication," "devices for beauty use, such as skin measuring devices for capturing images of the skin and microscopes for capturing images of the scalp," "devices for sports use, such as action cameras and wearable cameras for sports use," and "devices for agriculture, such as cameras for monitoring the condition of fields and crops."

[0123] The technology according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure may be realized as an electronic device mounted on any type of moving body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, a robot, a construction machine, or an agricultural machine (tractor). Furthermore, for example, the technology according to the present disclosure may be realized as an electronic device mounted on an endoscopic surgery system, a microsurgery system, or the like.

[0124] <3-2. Imaging Device> An imaging device 300 according to an application example will be described with reference to Fig. 28. Fig. 28 is a diagram showing an example of the configuration of the imaging device 300 according to an application example. This imaging device 300 is an example of an electronic device to which the storage device 10 according to any of the above-described embodiments is applied. Examples of the imaging device 300 include electronic devices such as digital still cameras, video cameras, smartphones and mobile phones with imaging functions.

[0125] 28, the imaging device 300 includes an optical system 301, a shutter device 302, an imaging element (solid-state imaging device) 303, a control circuit (drive circuit) 304, a signal processing circuit 305, a monitor 306, and a memory 307. The imaging device 300 is capable of capturing still images and moving images.

[0126] The optical system 301 includes one or more lenses. The optical system 301 guides light from a subject (incident light) to the image sensor 303, and forms an image on the light receiving surface of the image sensor 303.

[0127] The shutter device 302 is disposed between the optical system 301 and the image sensor 303. The shutter device 302 controls the light irradiation period and the light blocking period for the image sensor 303 under the control of the control circuit 304.

[0128] The image sensor 303 accumulates signal charges for a certain period of time in response to light that is focused on the light receiving surface via the optical system 301 and the shutter device 302. The signal charges accumulated in the image sensor 303 are transferred in accordance with a drive signal (timing signal) supplied from the control circuit 304. The image sensor 303 may be, for example, a solid-state image sensor.

[0129] The control circuit 304 outputs a drive signal that controls the transfer operation of the image sensor 303 and the shutter operation of the shutter device 302 , thereby driving the image sensor 303 and the shutter device 302 .

[0130] The signal processing circuit 305 performs various signal processing on the signal charges output from the image sensor 303. The image (image data) obtained by the signal processing performed by the signal processing circuit 305 is supplied to a monitor 306 and also to a memory 307.

[0131] The monitor 306 displays moving or still images captured by the image sensor 303 based on the image data supplied from the signal processing circuit 305. As the monitor 306, for example, a panel-type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel is used.

[0132] The memory 307 stores image data supplied from the signal processing circuit 305, i.e., image data of moving images or still images captured by the image sensor 303. As the memory 307, for example, the storage device 10 according to any one of the above-described embodiments is used.

[0133] Even in the imaging device 300 configured in this manner, by applying the storage device 10 according to the above-described embodiment (including the modified example) as the memory 307, it is possible to obtain the same effects as those of the above-described embodiment.

[0134] <3-3. Distance Measuring Device> A distance measuring device 400 according to an application example will be described with reference to Fig. 29. Fig. 29 is a diagram showing an example of the configuration of the distance measuring device 400 according to an application example. This distance measuring device 400 is an example of an electronic device to which the storage device 10 according to any of the above-described embodiments is applied.

[0135] 29 , distance measuring device (distance image sensor) 400 includes a light source unit 401, an optical system 402, an image sensor (solid-state image sensor) 403, a control circuit (drive circuit) 404, a signal processing circuit 405, a monitor 406, and a memory 407. Distance measuring device 400 projects light from light source unit 401 toward an object and receives light (modulated light or pulsed light) reflected from the surface of the object, thereby obtaining a distance image according to the distance to the object.

[0136] The light source unit 401 projects light toward the subject. For example, a vertical cavity surface emitting laser (VCSEL) array that emits laser light as a surface light source, or a laser diode array in which laser diodes are arranged in a line, is used as the light source unit 401. The laser diode array is supported by a predetermined drive unit (not shown) and scanned in a direction perpendicular to the direction in which the laser diodes are arranged.

[0137] The optical system 402 includes one or more lenses. The optical system 402 guides light from a subject (incident light) to the image sensor 403, and forms an image on the light receiving surface (sensor portion) of the image sensor 403.

[0138] The image sensor 403 accumulates signal charges in response to light that is imaged on the light receiving surface via the optical system 402. A distance signal indicating a distance determined from a light receiving signal (APD OUT) output from the image sensor 403 is supplied to a signal processing circuit 405. As the image sensor 403, for example, a solid-state image sensor such as an image sensor is used.

[0139] The control circuit 404 outputs a drive signal (control signal) that controls the operation of the light source unit 401, the image sensor 403, and the like, thereby driving the light source unit 401, the image sensor 403, and the like.

[0140] The signal processing circuit 405 performs various signal processing on the distance signal supplied from the image sensor 403. For example, the signal processing circuit 405 performs image processing (e.g., histogram processing, peak detection processing, etc.) to construct a distance image based on the distance signal. The image (image data) obtained by the signal processing performed by the signal processing circuit 405 is supplied to a monitor 406 and also to a memory 407.

[0141] The monitor 406 displays the distance image captured by the image sensor 403 based on the image data supplied from the signal processing circuit 405. The monitor 406 may be, for example, a panel display device such as a liquid crystal panel or an organic EL panel.

[0142] The memory 407 stores image data supplied from the signal processing circuit 405, i.e., image data of the distance image captured by the image sensor 403. As the memory 407, for example, the storage device 10 according to any one of the above-described embodiments is used.

[0143] In the distance measuring device 400 configured in this manner, by applying the storage device 10 according to the above-described embodiment (including the modified example) as the memory 407, it is possible to obtain the same effects as those of the above-described embodiment.

[0144] As described above, the storage device 10 according to the above-described embodiments can be implemented in various electronic devices. For example, the storage device 10 according to any of the above-described embodiments (including modified examples) may be installed in various electronic devices, such as an HDD (hard disk drive), a notebook PC (personal computer), a mobile device (e.g., a smartphone or tablet PC), a PDA (personal digital assistant), a wearable device, a game device, or a music device, in addition to the imaging device 300 or the distance measuring device 400. For example, the storage device 10 may be used as various types of memory, such as storage.

[0145] <4. Supplementary Note> The present technology may also be configured as follows. (1) A storage device including a plurality of memory cells, each of which has: a memory element having a variable resistance value or a variable polarization direction; and an inverter circuit connected to the memory element or an inverter circuit including the memory element, wherein, among the plurality of memory cells, an output of the inverter circuit of one memory cell is connected to an input of the inverter circuit of another memory cell. (2) The storage device according to (1), wherein an output of the inverter circuit of one memory cell is connected to an input of the inverter circuit of another memory cell adjacent to the memory cell. (3) The storage device according to (1) or (2), wherein an output of the inverter circuit of one memory cell is connected to an input of the inverter circuit of another memory cell via a signal line through which a write signal passes. (4) The storage device according to (3), wherein a voltage that causes writing to occur in response to the write signal is applied to the memory element of the memory cell to be written. (5) The storage device according to (4), wherein a voltage that does not cause writing in response to the write signal is applied to the memory elements of memory cells other than the memory cell to be written. (6) The storage device according to (5), further comprising a control circuit that applies a voltage that causes the writing to the memory element of the memory cell to be written to and a voltage that does not cause the writing to the memory element of the memory cells other than the memory cell to be written to. (7) The storage device according to any one of (3) to (6), wherein an input of the inverter circuit of the memory cell in a first stage among the plurality of memory cells is connected to a control circuit that outputs the write signal. (8) The storage device according to any one of (3) to (7), wherein an output of the inverter circuit of the memory cell in a last stage among the plurality of memory cells is connected to an output circuit that outputs data. (9) The storage device according to any one of (1) to (8), wherein the inverter circuit of the memory cell functions as a sense amplifier for the memory cell in a stage preceding the memory cell.(10) The storage device according to any one of (1) to (9), wherein the inverter circuit connected to the memory element includes a plurality of transistors connected to the memory element. (11) The storage device according to (10), wherein the plurality of transistors include an NMOS transistor and a PMOS transistor. (12) The storage device according to (10) or (11), wherein the amount of current of any one of the plurality of transistors is adjusted by a back bias or a power supply voltage. (13) The storage device according to any one of (1) to (9), wherein the inverter circuit including the memory element includes a transistor connected to the memory element. (14) The storage device according to (13), wherein the transistor is an NMOS transistor or a PMOS transistor. (15) The storage device according to (14), wherein the inverter circuit including the NMOS transistor and the inverter circuit including the PMOS transistor are provided alternately. (16) The storage device according to any one of (13) to (15), wherein the inverter circuit including the memory element further includes a resistor connected to the transistor. (17) The storage device according to any one of (13) to (16), wherein the amount of current in the transistor is adjusted by a back bias or a power supply voltage. (18) The storage device according to any one of (1) to (17), wherein a configuration of the inverter circuit of the memory cell is different from a configuration of the inverter circuit of another memory cell adjacent to the memory cell. (19) The storage device according to any one of (1) to (18), wherein the memory element is an MTJ (Magnetic Tunnel Junction) element, a ReRAM (Resistive Random Access Memory), a PRAM (Phase-change Random Access Memory), or an FeRAM (Ferroelectric Random Access Memory).(20) An electronic device comprising a memory device having a plurality of memory cells, each of the plurality of memory cells comprising: a memory element having a variable resistance value or a variable polarization direction; and an inverter circuit connected to the memory element or including the memory element, wherein an output of the inverter circuit of one of the plurality of memory cells is connected to an input of the inverter circuit of another of the memory cells. (21) An electronic device comprising the memory device according to any one of (1) to (18).

[0146] 10 Memory device 11 Memory cell array 20 Peripheral circuit 21 I / O 22 Control circuit 23 Voltage generation circuit 24 Bit line address decoder 25 Bit line control circuit 26 Word line address decoder 27 Word line control circuit 28 Output circuit 28a Holding circuit 28b Data output circuit 100 Memory cell 110 Memory element 110A Memory element 110B Memory element 120 Inverter circuit 120A Inverter circuit 120B Inverter circuit 120C Inverter circuit 120D Inverter circuit 121 Transistor 122 Transistor 125 Resistor 126 Resistor 300 Imaging device 307 Memory 400 Distance measuring device 407 Memory BL Bit line WL Word line

Claims

1. A memory device comprising a plurality of memory cells, each of which has a memory element having a variable resistance value or polarization direction, and an inverter circuit connected to the memory element or an inverter circuit including the memory element, wherein, among the plurality of memory cells, the output of the inverter circuit of one memory cell is connected to the input of the inverter circuit of another memory cell.

2. The memory device according to claim 1, wherein the output of said inverter circuit of said memory cell is connected to the input of said inverter circuit of another said memory cell adjacent to said memory cell.

3. The memory device according to claim 1, wherein the output of said inverter circuit of said memory cell is connected to the input of said inverter circuit of another said memory cell via a signal line through which a write signal passes.

4. The storage device according to claim 3, wherein a voltage that causes writing by the write signal is applied to the memory element of the memory cell to be written.

5. The storage device according to claim 4, wherein a voltage that does not cause writing by the write signal is applied to the memory elements of the memory cells other than the memory cells to be written.

6. The storage device according to claim 5, further comprising a control circuit that applies a voltage that causes the writing to occur to the memory element of the memory cell that is the writing target, and applies a voltage that does not cause the writing to the memory element of the memory cell other than the writing target.

7. The memory device according to claim 3, wherein the input of the inverter circuit of the memory cell in the first stage of the plurality of memory cells is connected to a control circuit that outputs the write signal.

8. The memory device according to claim 3, wherein the output of the inverter circuit of the memory cell at the final stage of the plurality of memory cells is connected to an output circuit that outputs data.

9. The memory device according to claim 1, wherein the inverter circuit of the memory cell functions as a sense amplifier for the memory cell in the preceding stage of the memory cell.

10. The memory device according to claim 1, wherein the inverter circuit connected to the memory element includes a plurality of transistors connected to the memory element.

11. The memory device according to claim 10, wherein the plurality of transistors includes an NMOS transistor and a PMOS transistor.

12. The memory device according to claim 10, wherein the amount of current flowing through any one of the plurality of transistors is adjusted by a back bias or a power supply voltage.

13. The memory device according to claim 1, wherein the inverter circuit including the memory element includes a transistor connected to the memory element.

14. The memory device according to claim 13, wherein the transistor is an NMOS transistor or a PMOS transistor.

15. The memory device according to claim 14, wherein the inverter circuits including the NMOS transistors and the inverter circuits including the PMOS transistors are provided alternately.

16. The memory device according to claim 13, wherein the inverter circuit including the memory element further includes a resistor connected to the transistor.

17. The memory device according to claim 13, wherein the amount of current flowing through the transistor is adjusted by a back bias or a power supply voltage.

18. The memory device according to claim 1, wherein the configuration of the inverter circuit of the memory cell is different from the configuration of the inverter circuit of another memory cell adjacent to the memory cell.

19. The storage device according to claim 1, wherein the memory element is a magnetic tunnel junction (MTJ) element, a resistive random access memory (ReRAM), a phase-change random access memory (PRAM), or a ferroelectric random access memory (FeRAM).

20. An electronic device comprising a memory device having a plurality of memory cells, each of the plurality of memory cells having a memory element whose resistance value or polarization direction is variable, and an inverter circuit connected to the memory element or an inverter circuit including the memory element, wherein, in the plurality of memory cells, the output of the inverter circuit of one memory cell is connected to the input of the inverter circuit of another memory cell.

Images