Semiconductor device, electric circuit, and electronic apparatus

Abstract

A semiconductor device according to an embodiment of the present invention comprises: a channel layer including a two-dimensional electron gas region; a barrier layer provided on the channel layer; a gate electrode provided on the barrier layer; and a contact layer provided on the channel layer. The contact layer has an inclined surface inclined downward toward the gate electrode side.

Description

Semiconductor devices, electric circuits and electronic devices

[0001] The present disclosure relates to semiconductor devices, electric circuits, and electronic devices.

[0002] An example of a semiconductor device is a high electron mobility transistor (HEMT) using a nitride semiconductor. HEMTs have characteristics such as high breakdown voltage, high heat resistance, high saturation electron velocity, and high channel electron concentration, and are expected to be applied to small, high-performance power devices and high-frequency devices.

[0003] Typically, a HEMT has a barrier layer on the channel layer. The potential barrier of the barrier layer makes it difficult to form a good ohmic contact, and the contact resistance tends to be high. One method for reducing this contact resistance is to regrow a contact layer in the source and drain regions on the channel layer (see, for example, Patent Document 1). The contact resistance can be reduced by connecting the channel layer to the source electrode with a contact layer, and similarly connecting the channel layer to the drain electrode with a contact layer.

[0004] JP 2017-085062 A

[0005] When applying HEMTs to high-frequency applications, it is desirable to use HEMTs with low on-resistance. To achieve this, it is effective to narrow the source-drain distance, in addition to selecting the right barrier layer material and reducing the contact resistance. However, a shorter source-drain distance increases the gate-source capacitance and gate-drain capacitance (interelectrode capacitance), and reduces the breakdown voltage and reliability due to increased electric field strength at the edges of the gate and drain regions. Furthermore, the unevenness caused by the contact layer typically formed by regrowth impairs the resist flatness during subsequent source-drain electrode and gate formation processes, making microfabrication more difficult.

[0006] Therefore, the present disclosure provides a semiconductor device, an electric circuit, and an electronic device that can reduce inter-electrode capacitance, improve breakdown voltage and reliability, and improve microfabrication.

[0007] The semiconductor device according to the embodiment comprises a channel layer including a two-dimensional electron gas region, a barrier layer provided on the channel layer, a gate electrode provided on the barrier layer, and a contact layer provided on the channel layer, and the contact layer has an inclined surface that slopes downward toward the gate electrode.

[0008] An electric circuit according to an embodiment includes a semiconductor device, the semiconductor device including a channel layer including a two-dimensional electron gas region, a barrier layer provided on the channel layer, a gate electrode provided on the barrier layer, and a contact layer provided on the channel layer, the contact layer having an inclined surface that slopes downward toward the gate electrode.

[0009] An electronic device according to an embodiment includes an electrical circuit having a semiconductor device, the semiconductor device including a channel layer including a two-dimensional electron gas region, a barrier layer provided on the channel layer, a gate electrode provided on the barrier layer, and a contact layer provided on the channel layer, the contact layer having an inclined surface that slopes downward toward the gate electrode.

[0010] FIG. 1 is a cross-sectional view showing a configuration example of a semiconductor device according to an embodiment; FIG. 2 is a view for explaining the gradient of the inclined surface of the contact layer according to an embodiment; FIG. 3 is a view for explaining an effect example of the semiconductor device according to an embodiment; FIG. 4 is a view for explaining a configuration example of the contact layer for each case according to an embodiment; FIG. 5 is a view for explaining the contact resistance for each case according to an embodiment; FIG. 6 is a cross-sectional view showing a configuration example of a semiconductor device of Modified Example 1 according to an embodiment; FIG. 7 is a cross-sectional view showing a configuration example of a semiconductor device of Modified Example 2 according to an embodiment; FIG. 8 is a cross-sectional view showing a configuration example of a semiconductor device of Modified Example 3 according to an embodiment; FIG. 9 is a cross-sectional view showing a configuration example of a semiconductor device of Modified Example 4 according to an embodiment; FIG. 10 is a perspective view showing a configuration example of a wireless communication device of Application Example 1; FIG. 11 is a block diagram showing a configuration example of a wireless communication device of Application Example 2;

[0011] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The embodiments include examples and modifications. Note that the technology according to the present disclosure is not limited to the embodiments. Furthermore, in the embodiments, essentially identical components are designated by the same reference numerals, and redundant explanations will be omitted.

[0012] The present disclosure will be described in the following order: 1. Embodiment 1-1. Configuration example of semiconductor device 1-2. Example of gradient of inclined surface of contact layer 1-3. Example of effect of semiconductor device 1-3-1. Example of effect 1 to 3 1-3-2. Example of effect 4 1-4. Modified examples of semiconductor device 1-4-1. Modified example 1 1-4-2. Modified example 2 1-4-3. Modified example 3 1-4-4. Modified example 4 1-5. Actions and effects 2. Other embodiments 3. Application examples 4. Supplementary notes

[0013] 1. Embodiment 1-1. Configuration Example of Semiconductor Device A configuration example of a semiconductor device 1A according to this embodiment will be described with reference to Fig. 1. Fig. 1 is a cross-sectional view showing a configuration example of a semiconductor device 1A according to this embodiment.

[0014] As shown in FIG. 1, the semiconductor device 1A according to this embodiment includes a substrate 11, a buffer layer 12, a back barrier layer 15A, a channel layer 13, a spacer layer 14, a barrier layer 15, a cap layer 16, two contact layers 17, a source electrode 18, a drain electrode 19, and a gate electrode 20.

[0015] The buffer layer 12 is provided on the substrate 11. The back barrier layer 15A is provided on the buffer layer 12. The channel layer 13 is provided on the back barrier layer 15A. The spacer layer 14 is provided on the channel layer 13. The barrier layer 15 is provided on the spacer layer 14. The cap layer 16 is provided on the barrier layer 15. That is, the buffer layer 12, the back barrier layer 15A, the channel layer 13, the spacer layer 14, the barrier layer 15, and the cap layer 16 are stacked in this order on the substrate 11.

[0016] Each of the contact layers 17 is provided on the channel layer 13. One side of each contact layer 17 is formed in the source region, and the other side is formed in the drain region. For example, each of the contact layers 17 is formed by crystal growth from the upper surface of the channel layer 13. Each of the contact layers 17 is in contact with the upper portion (convex portion) of the channel layer 13 and the side surfaces of the spacer layer 14, the barrier layer 15, and the cap layer 16.

[0017] The source electrode 18 is provided on a part of the cap layer 16 and on the contact layer 17. Similarly, the drain electrode 19 is provided on a part of the cap layer 16 and on the contact layer 17. The gate electrode 20 is provided on the cap layer 16. The gate electrode 20 is formed so as to be located between the source electrode 18 and the drain electrode 19.

[0018] The expression "a layer, an electrode, etc. is provided on an object" includes a case in which a layer, an electrode, etc. is provided directly on an object in contact with the object, and a case in which a layer, an electrode, etc. is provided on the object without contacting the object, with another layer, etc., in between.

[0019] Hereinafter, the above-mentioned components constituting the semiconductor device 1A according to this embodiment will be described in detail in order, starting from the substrate 11.

[0020] (Substrate) The substrate 11 is a support that supports each component (layers, electrodes, etc.) of the semiconductor device 1A. The substrate 11 is made of, for example, a compound semiconductor material. As an example, the substrate 11 is made of a single crystal of GaN, which is a semi-insulating III-V group compound semiconductor material. Note that the substrate 11 may be made of a substrate having a different lattice constant from that of the channel layer 13, such as a SiC substrate, a sapphire substrate, or a Si substrate, by controlling the lattice constant with the buffer layer 12.

[0021] (Buffer Layer) The buffer layer 12 is composed of, for example, a compound semiconductor layer formed by epitaxial growth on the substrate 11. When the lattice constants of the substrate 11 and the channel layer 13 are different, the lattice constant can be controlled by the buffer layer 12, thereby improving the crystal quality of the channel layer 13 and controlling warpage after the formation of the channel layer 13. For example, when the substrate 11 is made of single crystal Si and the channel layer 13 is made of GaN, the buffer layer 12 is made of AlN, AlGaN, GaN, AlInGaN, or the like.

[0022] (Back Barrier Layer) The back barrier layer 15A is made of, for example, a compound semiconductor layer formed by epitaxial growth on the buffer layer 12. By providing this back barrier layer 15A, the short channel effect can be suppressed. The back barrier layer 15A may be made of, for example, AlGaN. Note that, as long as the short channel effect can be suppressed, an AlGaN layer containing Al or In in addition to Ga may be used. ｘ In ｙ Ga １－ｘ－ｙ N (0≦x≦1, 0≦y≦1, x+y≦1).

[0023] (Channel Layer) The channel layer 13 is made of, for example, a compound semiconductor layer formed by epitaxial growth on the buffer layer 12. For example, the channel layer 13 is made of an epitaxially grown layer of GaN. The channel layer 13 may be made of u-GaN to which no impurities are added. In this case, impurity scattering of carriers in the channel layer 13 is suppressed, and carrier transport with high mobility is achieved. The channel layer 13 is also made of Al ｘ In ｙ Ga １－ｘ－ｙ N (0≦x<1, 0≦y≦1, x+y≦1). The channel layer 13 is preferably formed to a thickness (for example, in the range of 30 to 300 nm) that can suppress the short channel effect.

[0024] The channel layer 13 has a two-dimensional electron gas region 13a. The two-dimensional electron gas region 13a constitutes, for example, a part of the current path between the source electrode 18 and the drain electrode 19. This two-dimensional electron gas region 13a is a region where carriers, i.e., two-dimensional electron gas (2DEG), exist. Specifically, electrons accumulate at the interface of the channel layer 13 on the barrier layer 15 side due to the difference in polarization charge between the channel layer 13 and the barrier layer 15. The region where these electrons accumulate (the region where electrons are distributed) is the two-dimensional electron gas region 13a. The two-dimensional electron gas region 13a functions, for example, as a channel through which electrons flow. Note that the two-dimensional electron gas region 13a may include, for example, a region where the electron concentration is close to zero (a region where the two-dimensional electron gas is depleted) or a region where the electron concentration becomes zero. In other words, the two-dimensional electron gas region 13a does not have to be a region with a uniform electron concentration and may include, for example, one or both of a region where the electron concentration is close to zero and a region where the electron concentration becomes zero.

[0025] (Spacer Layer) The spacer layer 14 is composed of, for example, an AlN layer formed by epitaxial growth on the channel layer 13. The spacer layer 14 is provided between the channel layer 13 and the barrier layer 15. By providing the spacer layer 14 of AlN, which is a binary compound, between the channel layer 13 and the barrier layer 15, the influence of alloy scattering from the barrier layer 15, which is a ternary or quaternary compound, on carriers accumulated at the interface of the channel layer 13 on the barrier layer 15 side, i.e., two-dimensional electron gas, can be reduced, thereby increasing carrier mobility. Note that if a reduction in carrier mobility is tolerable, the spacer layer 14 does not need to be present.

[0026] Such a spacer layer 14 may contain Ga or In due to the influence of diffusion from the channel layer 13 or the barrier layer 15. The spacer layer 14 may also be an Al layer intentionally doped with Ga or In to such an extent that the channel characteristics are not impaired. ｘ In ｙ Ga １－ｘ－ｙ N (0≦x≦1, 0≦y≦1, x+y≦1).

[0027] (Barrier Layer) The barrier layer 15 is composed of, for example, a compound semiconductor layer formed by epitaxial growth on the spacer layer 14. For example, the barrier layer 15 is composed of an AlInN layer. As the AlInN, it is desirable to use AlInN with an In composition of 17 to 18%, which is lattice-matched with the GaN of the channel layer 13. On the other hand, in order to achieve a lower on-resistance due to a lower sheet resistance (Rs), AlInN with an In composition smaller than 17%, such as 10% or 14%, may be used to the extent that crystallinity is not impaired. Note that the barrier layer 15 may be formed directly on the channel layer 13 without the spacer layer 14 interposed therebetween.

[0028] The material used for such a barrier layer 15 may be a nitride semiconductor material that allows two-dimensional electron gas to accumulate at the interface of the channel layer 13 on the barrier layer 15 side due to the difference in polarization charge between the channel layer 13 and the barrier layer 15. For example, the barrier layer 15 may be made of Al ｘ In ｙ Ga １－ｘ－ｙ The barrier layer 15 may be made of an epitaxially grown layer of u-AlN (0≦x≦1, 0≦y<1, x+y≦1). ｘ In ｙ Ga １－ｘ－ｙ The barrier layer 15 may be made of N. In this case, impurity scattering of carriers in the channel layer 13 is suppressed, and carrier movement with high mobility is realized. When it is desired to increase the two-dimensional electron gas concentration, the barrier layer 15 may be doped with n-type impurities such as Si or Ge.

[0029] Here, the sheet carrier concentration of the two-dimensional electron gas region 13a, which is mainly composed of two-dimensional electron gas, is 5×10 １２ cm －２ It is desirable that the ratio is 7×10 or more, and more preferably 7×10 １２ cm －２ The sheet resistance of the two-dimensional electron gas region 13a is preferably 300 Ω / □ (Ω / sq) or less. The two-dimensional electron gas concentration below the gate electrode 20 is not limited to the above characteristics in order to obtain a desired threshold voltage, and is controlled to a required value by the gate formation process.

[0030] Among GaN-based HEMTs, a structure using AlInN for the barrier layer 15 is very promising for high-frequency device applications. This is because the In composition of AlInN is set to about 17 to 18%, which makes the lattice constant the same as that of GaN used for the channel layer 13, and therefore good crystallinity can be expected, and at the same time, a high sheet carrier concentration (>1×10 １３ cm －２ The reason for this is that a low sheet resistance (<300 Ω / □) can be obtained. Examples of nitride semiconductors include GaN, AlGaN, and AlInN. By using AlInN for the barrier layer 15, for example, the sheet resistance can be reliably suppressed.

[0031] (Cap Layer) The cap layer 16 is composed of, for example, a GaN layer formed by epitaxial growth on the barrier layer 15. When a material with a high Al composition such as AlInN is used for the barrier layer 15, the barrier layer 15 is easily oxidized in the atmosphere, but by forming the cap layer 16 on the barrier layer 15, this oxidation is suppressed. The cap layer 16 may also be composed of, for example, an insulating layer such as SiN. If an oxidation suppression effect is obtained, the cap layer 16 may be composed of, for example, an Al ｘ In ｙ Ga １－ｘ－ｙ N (0≦x<1, 0≦y<1, x+y≦1) where 0≦x<1, 0≦y<1, x+y≦1. If adverse effects such as oxidation when the barrier layer 15 is formed on the outermost surface are not a problem, the cap layer 16 may not be present.

[0032] (Contact Layer) Each of the contact layers 17 is formed on the channel layer 13. The contact layers 17 are formed, for example, by regrowth in the source and drain regions on the channel layer 13. The contact layers 17 are made of, for example, GaN, the same material as the channel layer 13. By connecting the channel layer 13 and the source electrode 18 with the contact layer 17, and by connecting the channel layer 13 and the drain electrode 19 with the contact layer 17, the contact resistance can be reduced.

[0033] When forming each contact layer 17, the source and drain regions above the channel layer 13 are opened by patterning. Then, the source and drain regions are extruded by, for example, about 30 nm by dry etching or wet etching, thereby forming recesses 17A as exposed regions. At this time, the end (outer peripheral end) of the two-dimensional electron gas region 13a formed at the interface of the channel layer 13 on the barrier layer 15 side is exposed from a surface 17B of the recess 17A on the barrier layer 15 side. Thereafter, the contact layer 17 is formed in the recess 17A.

[0034] In this way, each of the contact layers 17 is formed so as to contact at least the two-dimensional electron gas region 13a at the interface on the barrier layer 15 side of the channel layer 13. As a result, each of the contact layers 17 is adjacent to the two-dimensional electron gas region 13a, and the contact resistance can be further reduced.

[0035] The surface 17B (inner surface) of each recess 17A facing the barrier layer 15 may be formed to intersect with a vertical direction (the stacking direction of each layer) perpendicular to the plane of the substrate 11, or may be perpendicular to the plane of the substrate 11. In the example of FIG. 1 , the surface 17B of each of the two recesses 17A facing the barrier layer 15 is formed in a tapered shape so as to intersect with the vertical direction. The surface 17B of each of the two recesses 17A facing the barrier layer 15 may also be formed in an inverse tapered shape. The larger the taper angle, for example, the more likely a two-dimensional electron gas region 13a with a high electron concentration is formed near each contact layer 17. Therefore, it is desirable that the surface 17B of each recess 17A facing the barrier layer 15, i.e., the surface of each contact layer 17 facing the two-dimensional electron gas region 13a, be perpendicular to the plane of the substrate 11.

[0036] Each contact layer 17 has an inclined surface 17a and a flat surface 17b. The inclined surface 17a slopes downward toward the gate electrode 20. More specifically, the inclined surface 17a is a surface (inclined region) where the thickness (layer thickness) of the contact layer 17 gradually decreases from the end of the flat surface 17b toward the gate electrode 20. The flat surface 17b is a flat surface (flat region) that is connected to the inclined surface 17a. The contact layer 17 is formed in a shape having at least two regions, the inclined surface 17a and the flat surface 17b.

[0037] Each of the contact layers 17 is formed, for example, so that the height of the inclined surface 17a is higher than the surface of the cap layer 16 on the gate electrode 20 side (top surface in FIG. 1 ). The height of the surface is the height position in the vertical direction (the stacking direction of each layer) described above. Note that each of the contact layers 17 may be formed so that the height of the inclined surface 17a is the same as the surface of the cap layer 16 on the gate electrode 20 side. Furthermore, if the cap layer 16 is not present, each of the contact layers 17 is formed, for example, so that the height of the inclined surface 17a is higher than the surface of the barrier layer 15 on the gate electrode 20 side (top surface in FIG. 1 ).

[0038] Each of the contact layers 17 is formed by, for example, MOCVD (metal organic chemical vapor deposition), MBE (molecular beam epitaxy), PLD (pulsed laser deposition), sputtering, etc. In this case, the contact layer 17 is preferably made of a material whose main component is a C-axis oriented surface, but may be polycrystalline or amorphous.

[0039] Each contact layer 17 may be doped with a high concentration of N-type impurities. This reduces the contact resistance between the contact layer 17 and the source electrode 18, and the contact resistance between the contact layer 17 and the drain electrode 19. The N-type impurities may be, for example, Si or Ge. The carrier concentration of the contact layer 17 is 1×10 １９ pieces / cm －３ To achieve this, the N-type impurity concentration is set to be equal to or higher than the carrier concentration of the contact layer 17 (≧1×10 １９ pieces / cm －３The N-type impurity may be added during the formation of the contact layer 17 or may be added after the formation of the contact layer 17 by ion implantation or diffusion. The sheet resistance of the contact layer 17 is 250 Ω / □ or less, and the mobility of the contact layer 17 is 30 cm ２ The contact layer 17 is preferably made of, for example, Al. ｘ In ｙ Ga １－ｘ－ｙ N (0≦x≦1, 0≦y≦1, x+y≦1).

[0040] (Source Electrode / Drain Electrode) The source electrode 18 and the drain electrode 19 are each formed on the contact layer 17 so as to cover the entire surface (inclined surface and flat surface 17b) of the contact layer 17. The source electrode 18 and the drain electrode 19 are each configured to be connected to the contact layer 17. The source electrode 18 or the drain electrode 19 is formed of a conductive material, and is configured, for example, by stacking Ti, Al, Ni, and Au in this order from bottom to top. The stack of Ti, Al, Ni, and Au is subjected to heat treatment as necessary.

[0041] (Gate electrode) The gate electrode 20 is formed on the cap layer 16. If the cap layer 16 is not present, the gate electrode 20 is formed on the barrier layer 15. The gate electrode 20 is made of a conductive material, and is configured by laminating, for example, Ni and Au in this order from the bottom up. An insulating film may be formed between the gate electrode 20 and the cap layer 16, forming a MIS (Metal Insulator Oxide) gate structure. In this case, the insulating film may be made of, for example, SiO ２ , Si ３ N ４ , Al ２ O ３ , AlTiO, HfO ２ , NiO, MgO, or a laminated film of any of them. If the cap layer 16 does not exist, the insulating film is formed on the barrier layer 15.

[0042] <1-2. Examples of gradient of inclined surface of contact layer> Examples of the gradient of the inclined surface 17a of the contact layer 17 according to this embodiment will be described with reference to Fig. 2. Fig. 2 is a diagram for explaining the gradient of the inclined surface 17a of the contact layer 17 according to this embodiment.

[0043] As shown in Figure 2, the inclined surface 17a preferably has a gentle slope (gradient) such that the aspect ratio (gradient) between the vertical length A1 of the inclined surface 17a and the horizontal length A2 of the inclined surface 17a is 0.5 or less, and more preferably has an aspect ratio of 0.05 to 0.5. The vertical direction is the stacking direction described above, and the horizontal direction is a direction perpendicular to the stacking direction. Furthermore, the horizontal length A2 of the inclined surface 17a is preferably 0.1 µm or more, and more preferably 0.15 µm or more.

[0044] <1-3. Examples of Effects of Semiconductor Device> <1-3-1. Examples of Effects 1 to 3> Examples of Effects 1 to 3 of the semiconductor device 1A according to this embodiment will be described with reference to Fig. 3. Fig. 3 is a diagram for explaining examples of effects 1 to 3 according to this embodiment.

[0045] In the example of Figure 3, as a comparative example, each contact layer 17C, source electrode 18C, and drain electrode 19C are indicated by dashed lines. As shown in Figure 3, each contact layer 17C does not have an inclined surface 17a but has a flat surface 17b. Therefore, each contact layer 17C has a right-angled corner (see dashed lines) or a nearly right-angled corner (e.g., a rounded corner) toward the gate electrode 20. Correspondingly, each source electrode 18C and drain electrode 19C also has a right-angled corner (see dashed lines) or a nearly right-angled corner (e.g., a rounded corner) toward the gate electrode 20.

[0046] On the other hand, in the semiconductor device 1A according to this embodiment, each of the contact layers 17 has an inclined surface 17a facing the gate electrode 20. Accordingly, each of the source electrode 18 and the drain electrode 19 also has an inclined portion (inclined surface) facing the gate electrode 20. This inclined portion has a gradient equivalent to that of the inclined surface 17a.

[0047] In the semiconductor device 1A, each contact layer 17 has an inclined surface 17a facing the gate electrode 20, eliminating the right-angled corners of each contact layer 17C facing the gate electrode 20 in the comparative example. Accordingly, the areas of the surface of the source electrode 18 facing the gate electrode 20 and the surface of the drain electrode 19 facing the gate electrode 20 are smaller than the areas of the surface of the source electrode 18C facing the gate electrode 20 and the surface of the drain electrode 19C facing the gate electrode 20 in the comparative example. As a result, the gate-source capacitance Cgs and the gate-drain capacitance Cgd in this embodiment are smaller than those in the comparative example. Therefore, by providing the inclined surface 17a in each contact layer 17, the gate-source capacitance Cgs and the gate-drain capacitance Cgd can be reduced (Effective Example 1).

[0048] Furthermore, each of the contact layers 17 in this embodiment has an inclined surface 17a on the gate electrode 20 side, which makes it possible to reduce the electric field at the end of the source electrode 18 on the gate electrode 20 side and the electric field at the end of the drain electrode 19 on the gate electrode 20 side. This reduces the electric field strength at the end of the source electrode 18 on the gate electrode 20 side and the electric field strength at the end of the drain electrode 19 on the gate electrode 20 side, thereby achieving improvements in breakdown voltage and reliability (Effective Example 2).

[0049] Furthermore, since each of the contact layers 17 in this embodiment has an inclined surface 17a on the gate electrode 20 side, the unevenness caused by these contact layers 17 is smaller than the unevenness caused by each contact layer 17C in the comparative example. By reducing this unevenness, it is possible to suppress deterioration in resist flatness during source / drain electrode formation and gate formation, which are processes subsequent to the contact layer 17 formation process, thereby achieving improved microfabrication (Effective Example 3).

[0050] 1-3-2. Effect Example 4 An effect example 4 of the semiconductor device 1A according to this embodiment will be described with reference to Fig. 4 and Fig. 5. Fig. 4 is a diagram for explaining a configuration example of the contact layer 17 for each of Cases A to C according to this embodiment. Fig. 5 is a diagram for explaining the contact resistance for each of Cases A to C according to this embodiment.

[0051] 4, in Case A, the depth of the recess 17A (recess depth) is d1 (nm), and the thickness of the contact layer 17 (contact layer thickness) is d1+d2 (nm). In this case, the height of the upper surface of the contact layer 17 is higher by d2 (nm) than the height of the upper surface of the barrier layer 15. At this time, the contact layer 17 is in contact with the two-dimensional electron gas region 13a. Note that, for example, d1 is about several tens of nm, and d2 is about several nm to a dozen nm.

[0052] In Case B, the depth of the recess 17A (recess depth) is d1 (nm) as in Case A, and the thickness of the contact layer 17 (contact layer thickness) is d1 (nm). In this case, the height of the upper surface of the contact layer 17 is the same as the height of the upper surface of the barrier layer 15. At this time, the contact layer 17 is in contact with the two-dimensional electron gas region 13a.

[0053] In Case C, the depth of the recess 17A (recess depth) is d1 (nm) as in Cases A and B, and the thickness of the contact layer 17 (contact layer thickness) is d1-d2 (nm). In this case, the height of the upper surface of the contact layer 17 is lower by d2 (nm) than the height of the upper surface of the barrier layer 15. In this case, the contact layer 17 is not in contact with the two-dimensional electron gas region 13a.

[0054] 5, the contact resistance of each of the aforementioned cases A and B is about a (Ω). On the other hand, the contact resistance of the aforementioned case C is about 4a (Ω). It can be seen that the contact resistance of each of cases A and B is about 1 / 4 of the contact resistance of case C, and is therefore very small.

[0055] The main difference between Case A and Case B and Case C is whether or not the contact layer 17 is in contact with the two-dimensional electron gas region 13 a. In Cases A and B, the contact layer 17 is in contact with the two-dimensional electron gas region 13 a, but in Case C, the contact layer 17 is not in contact with the two-dimensional electron gas region 13 a. Therefore, by forming the contact layer 17 so that it is in contact with the two-dimensional electron gas region 13 a, the contact resistance can be reduced (Effective Example 4).

[0056] <1-4. Modifications of Semiconductor Device> <1-4-1. Modification 1> A semiconductor device 1B according to Modification 1 of this embodiment will be described with reference to Fig. 6. Fig. 6 is a cross-sectional view showing an example of the configuration of the semiconductor device 1B according to Modification 1 of this embodiment.

[0057] 6 , in the semiconductor device 1B of the first modification, the source electrode 18 is formed on the flat surface 17b of the contact layer 17 so that the entire inclined surface 17a of the contact layer 17 is exposed. Similarly, the drain electrode 19 is formed on the flat surface 17b so that the entire inclined surface 17a of the contact layer 17 is exposed. This further reduces the gate-source capacitance Cgs and the gate-drain capacitance Cgd, and also further improves the breakdown voltage and reliability. The source electrode 18 or the drain electrode 19 may be formed so that only a portion of the inclined surface 17a of the contact layer 17 is exposed.

[0058] <1-4-2. Modification 2> A semiconductor device 1C according to Modification 2 of this embodiment will be described with reference to Fig. 7. Fig. 7 is a cross-sectional view showing an example of the configuration of the semiconductor device 1C according to Modification 2 of this embodiment.

[0059] As shown in Fig. 7 , in the semiconductor device 1C of the second modification, each of the contact layers 17 is formed so that the height of the inclined surface 17a is lower than the height of the surface of the cap layer 16 facing the gate electrode 20 (the upper surface in Fig. 7 ). In the example of Fig. 7 , each of the contact layers 17 is formed so that the height of the inclined surface 17a is lower than the height of the surface of the barrier layer 15 facing the gate electrode 20 (the upper surface in Fig. 7 ). In either case, the contact layer 17 is in contact with the two-dimensional electron gas region 13a. In this way, it is possible to achieve an improved degree of design freedom.

[0060] <1-4-3. Modification 3> A semiconductor device 1D according to Modification 3 of this embodiment will be described with reference to Fig. 8. Fig. 8 is a cross-sectional view showing an example of the configuration of the semiconductor device 1D according to Modification 3 of this embodiment.

[0061] As shown in FIG. 8 , in the semiconductor device 1D of Modification 3, the inclined surface 17 a of the contact layer 17 on the drain electrode 19 side is a curved surface. The curved surface is curved toward the channel layer 13 side (the lower side in FIG. 8 ). For example, the curved surface is formed so that the gradient becomes steeper with increasing distance from the gate electrode 20 side. This can improve the resist application properties during source / drain electrode formation and gate formation. For example, during source / drain electrode formation and gate formation, the resist spreads due to centrifugal force caused by the rotation of the object to be applied. At this time, the resist gradually spreads, but because the inclined surface 17 a is a curved surface, the resist can be applied neatly to the surface of the object to be applied.

[0062] According to this embodiment, since there are two contact layers 17, one of the inclined surfaces 17a of each of the two contact layers 17 may be a curved surface, or both of them may be curved surfaces.

[0063] <1-4-4. Modification 4> A semiconductor device 1E according to a modification 4 of this embodiment will be described with reference to Fig. 9. Fig. 9 is a cross-sectional view showing an example of the configuration of the semiconductor device 1E according to the modification 4 of this embodiment.

[0064] 9 , in the semiconductor device 1E of the fourth modification, the inclined surface 17a of the contact layer 17 on the drain electrode 19 side includes an uneven portion 17c. For example, the unevenness is formed over the entire surface of the inclined surface 17a. This increases the contact area between the contact layer 17 and the drain electrode 19, thereby reducing the contact resistance between the contact layer 17 and the drain electrode 19.

[0065] According to this embodiment, since there are two contact layers 17, one of the inclined surfaces 17 a of each of the two contact layers 17 may include the uneven portion 17 c, or both of the inclined surfaces 17 a may include the uneven portion 17 c. Furthermore, the unevenness may not be formed on the entire inclined surface 17 a, but may be formed only on a part of the inclined surface 17 a.

[0066] For example, the inclined surface 17a of the contact layer 17 on the source electrode 18 side may include the uneven portion 17c, similar to the inclined surface 17a of the contact layer 17 on the drain electrode 19 side. In this case, the contact area between the contact layer 17 on the source electrode 18 side and the source electrode 18 increases, thereby reducing the contact resistance between the contact layer 17 and the source electrode 18.

[0067] <1-5. Actions and Effects> As described above, the semiconductor device 1A (or each of the semiconductor devices 1B to 1E) according to this embodiment includes a channel layer 13 including a two-dimensional electron gas region 13a, a barrier layer 15 provided on the channel layer 13, a gate electrode 20 provided on the barrier layer 15, and a contact layer 17 provided on the channel layer 13. The contact layer 17 has an inclined surface 17a that slopes downward toward the gate electrode 20 (see, for example, FIG. 1 ). This reduces the inter-electrode capacitance (e.g., gate-source capacitance Cgs or gate-drain capacitance Cgd) between the gate electrode 20 and the source electrode 18 or drain electrode 19 provided on the contact layer 17, thereby reducing the inter-electrode capacitance. Furthermore, this configuration can reduce the electric field at the end of the source electrode 18 or drain electrode 19 on the gate electrode 20 side, thereby improving breakdown voltage and reliability. Furthermore, this configuration can prevent deterioration of resist flatness during source / drain electrode formation and gate formation, which are subsequent processes after the contact layer 17 formation process, thereby improving microfabrication.

[0068] Furthermore, the contact layer 17 may be in contact with the two-dimensional electron gas region 13a (see FIG. 1, etc.). This allows the contact layer 17 to be in contact with the two-dimensional electron gas region 13a, thereby reducing the contact resistance.

[0069] Furthermore, the contact layer 17 may be formed so that the height of the inclined surface 17a is higher than the height of the surface of the barrier layer 15 on the gate electrode 20 side (see FIG. 1, etc.). This allows for improved design flexibility.

[0070] Furthermore, the contact layer 17 may be formed so that the height of the inclined surface 17a is lower than the height of the surface of the barrier layer 15 on the gate electrode 20 side (see FIG. 7 ). This allows for improved design flexibility.

[0071] Furthermore, the semiconductor device 1A (or each of the semiconductor devices 1B to 1E) may further include a cap layer 16 provided on the barrier layer 15, and the gate electrode 20 may be provided on the cap layer 16 (see FIG. 1, etc.). As a result, the cap layer 16 exists on the barrier layer 15, and therefore the barrier layer 15 can be protected.

[0072] Furthermore, the contact layer 17 may be formed so that the height of the inclined surface 17a is higher than the height of the surface of the cap layer 16 on the gate electrode 20 side (see FIG. 1, etc.). This allows for improved design flexibility.

[0073] Furthermore, the contact layer 17 may be formed so that the height of the inclined surface 17a is lower than the height of the surface of the cap layer 16 on the gate electrode 20 side (see FIG. 7 ). This allows for improved design flexibility.

[0074] In addition, the inclined surface 17a may be a curved surface that curves toward the channel layer 13 (see FIG. 8 ). This makes it possible to apply the resist neatly to the surface of the object to be applied, thereby reliably realizing improved microfabrication.

[0075] The inclined surface 17a may also include a concave-convex portion 17c (see FIG. 9), which increases the contact area between the contact layer 17 and an electrode (for example, the source electrode 18 or the drain electrode 19), thereby reducing the contact resistance.

[0076] The ratio (gradient) of the length A1 of the inclined surface 17a in the vertical direction to the length A2 of the inclined surface 17a in the horizontal direction may be 0.5 or less (see FIG. 2), which reliably reduces the inter-electrode capacitance, improves the withstand voltage and reliability, and improves the microfabrication properties.

[0077] The lateral length A2 of the inclined surface 17a may be 0.1 μm or more (see FIG. 2), which reliably reduces the inter-electrode capacitance, improves the breakdown voltage and reliability, and improves the microfabrication properties.

[0078] Furthermore, the semiconductor device 1A (or each of the semiconductor devices 1B to 1E) may further include an electrode (e.g., a source electrode 18 or a drain electrode 19) that covers the entire or part of the inclined surface 17a (see FIG. 1, etc.). This allows for improved design flexibility.

[0079] Furthermore, the semiconductor device 1A (or each of the semiconductor devices 1B to 1E) may further include a spacer layer 14 provided between the channel layer 13 and the barrier layer 15 (see FIG. 1, etc.). This can increase carrier mobility, for example.

[0080] The contact layer 17 may further have a flat surface 17b connected to the inclined surface 17a (see FIG. 1, etc.), which can improve the degree of freedom in design.

[0081] Furthermore, the semiconductor device 1A (or each of the semiconductor devices 1B to 1E) may further include an electrode (e.g., a source electrode 18 or a drain electrode 19) that covers the entire or part of the inclined surface 17a and the flat surface 17b (see FIGS. 1 and 6, etc.). This allows for greater design freedom.

[0082] Two contact layers 17 may be provided, and each of the two contact layers 17 may have an inclined surface 17a (see FIG. 1, etc.). This makes it possible to reliably reduce the inter-electrode capacitance, improve the breakdown voltage and reliability, and improve the microfabrication properties.

[0083] The material of the barrier layer 15 may be AlInN (see FIG. 1, etc.), which makes it possible to improve the sheet carrier concentration and suppress the sheet resistance, thereby suppressing the on-resistance of the semiconductor device 1A (or each of the semiconductor devices 1B to 1E).

[0084] The sheet carrier concentration of the two-dimensional electron gas region 13a is 5×10 １２ cm －２ As described above, the sheet resistance of the two-dimensional electron gas region 13a may be 300 Ω / □ or less (see FIG. 1, etc.), which makes it possible to suppress the on-resistance of the semiconductor device 1A (or each of the semiconductor devices 1B to 1E).

[0085] 2. Other Embodiments The configurations and processes according to the above-described embodiments (including examples and modified examples) may be implemented in various different forms other than the above-described embodiments. For example, the configurations and processes are not limited to the above-described examples and may be implemented in various forms. Furthermore, for example, the configurations, processing procedures, specific names, or information including various data and parameters shown in the above documents and drawings may be changed arbitrarily unless otherwise specified.

[0086] Furthermore, the components and processes according to the above-described embodiments (including examples and modifications) do not necessarily have to be physically configured as shown in the drawings. In other words, the specific forms of distribution and integration of the components and processes are not limited to those shown in the drawings, and all or part of them may be functionally or physically distributed or integrated in any unit depending on various loads, usage conditions, etc.

[0087] Furthermore, the configurations and processes of the above-described embodiments (including examples and modified examples) may be combined as appropriate. For example, at least a part of an embodiment may be combined as appropriate with at least a part of another embodiment. Furthermore, the effects of the embodiments are merely examples and are not intended to be limiting, and other effects may also be obtained.

[0088] <3. Application Examples> Each of the semiconductor devices 1A to 1E according to this embodiment is applied to a variety of products. For example, any of the semiconductor devices 1A to 1E according to this embodiment is applied to various electric circuits (e.g., electronic circuits) and various electronic devices. Examples of electronic devices include power devices and high-frequency devices. Specific examples include power supply devices and wireless communication devices. Power supply devices and wireless communication devices include electric circuits having, for example, power amplifiers and high-frequency switches.

[0089] The wireless communication device may be mounted on any mobile object, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, a robot, a construction machine, an agricultural machine (tractor), etc. The wireless communication device may also be mounted on any surgical system, such as an endoscopic surgery system or a microsurgery system. Note that the wireless communication device is merely an example of an electronic device.

[0090] A wireless communication device (for example, a wireless communication device 100 and a wireless communication device 200) to which any of the semiconductor devices 1A to 1E according to this embodiment is applied will be described with reference to Fig. 10 and Fig. 11. Fig. 10 is a perspective view showing a configuration example of the wireless communication device 100 according to application example 1. Fig. 11 is a block diagram showing a configuration example of the wireless communication device 200 according to application example 2.

[0091] 10 , a wireless communication device 100 of application example 1 includes, for example, a substrate 110, a plurality of edge antennas 120, and a front-end component group 130. This wireless communication device 100 is an antenna-integrated module in which the edge antennas 120 and the front-end component group 130 are integrated and mounted as a single module. The edge antennas 120 are formed in an array on the substrate 110. The front-end component group 130 includes a switch 131, a low-noise amplifier 132, a band-pass filter 133, and a power amplifier 134. The front-end component group 130 functions as an electric circuit.

[0092] Such a wireless communication device 100 is used, for example, as a transceiver for communications. Any of the semiconductor devices 1A to 1E according to the present embodiment may be applied to, for example, transistors constituting the switch 131, the low-noise amplifier 132, or the power amplifier 134. This allows the wireless communication device 100 to achieve the same effects as any of the above-described embodiments (embodiments and modifications).

[0093] As shown in FIG. 11 , the wireless communication device 200 of application example 2 includes an antenna (ANT) 210, an antenna switch circuit 220, a high power amplifier (HPA) 230, a radio frequency integrated circuit (RFIC) 240, a baseband unit 250, an audio output unit (MIC) 260, a data output unit (DT) 270, and an interface unit (I / F) 280.

[0094] Such a wireless communication device 200 is used, for example, as a mobile phone system having multiple functions such as voice and data communication and LAN (local area network) connection. Any of the semiconductor devices 1A to 1E according to the present embodiment may be applied to transistors that constitute, for example, an antenna switch circuit 220, a high-power amplifier 230, a high-frequency integrated circuit 240, or a baseband unit 250. This allows the wireless communication device 200 to achieve the same effects as any of the above-described embodiments (embodiments and modifications).

[0095] <4. Supplementary Notes> The present technology may also be configured as follows. (1) A semiconductor device comprising: a channel layer including a two-dimensional electron gas region; a barrier layer provided on the channel layer; a gate electrode provided on the barrier layer; and a contact layer provided on the channel layer, wherein the contact layer has an inclined surface that slopes downward toward the gate electrode. (2) The semiconductor device according to (1), wherein the contact layer is in contact with the two-dimensional electron gas region. (3) The semiconductor device according to (2), wherein the contact layer is formed so that the inclined surface is higher than the surface of the barrier layer facing the gate electrode. (4) The semiconductor device according to (2), wherein the contact layer is formed so that the inclined surface is lower than the surface of the barrier layer facing the gate electrode. (5) The semiconductor device according to (2), further comprising a cap layer provided on the barrier layer, wherein the gate electrode is provided on the cap layer. (6) The semiconductor device according to (5), wherein the contact layer is formed so that the height of the inclined surface is higher than the height of the surface of the cap layer on the gate electrode side. (7) The semiconductor device according to (5), wherein the contact layer is formed so that the height of the inclined surface is lower than the height of the surface of the cap layer on the gate electrode side. (8) The semiconductor device according to any one of (1) to (7), wherein the inclined surface is a curved surface that curves toward the channel layer. (9) The semiconductor device according to any one of (1) to (8), wherein the inclined surface includes an uneven portion. (10) The semiconductor device according to any one of (1) to (9), wherein the ratio of the vertical length of the inclined surface to the horizontal length of the inclined surface is 0.5 or less. (11) The semiconductor device according to any one of (1) to (10), wherein the horizontal length of the inclined surface is 0.1 μm or more. (12) The semiconductor device according to any one of (1) to (11), further comprising an electrode covering all or part of the inclined surface. (13) The semiconductor device according to any one of (1) to (12), further comprising a spacer layer provided between the channel layer and the barrier layer.(14) The semiconductor device according to any one of (1) to (13), wherein the contact layer further has a flat surface connected to the inclined surface. (15) The semiconductor device according to (14), further comprising an electrode covering the entire or part of the inclined surface and the flat surface. (16) The semiconductor device according to any one of (1) to (15), wherein two contact layers are provided, and each of the two contact layers has the inclined surface. (17) The semiconductor device according to any one of (1) to (16), wherein the material of the barrier layer is AlInN. (18) The two-dimensional electron gas region has a sheet carrier concentration of 5×10. １２ cm －２ The semiconductor device according to any one of (1) to (17), wherein the sheet resistance of the two-dimensional electron gas region is 300 Ω / □ or less. (19) An electric circuit comprising a semiconductor device, the semiconductor device comprising: a channel layer including a two-dimensional electron gas region, a barrier layer provided on the channel layer, a gate electrode provided on the barrier layer, and a contact layer provided on the channel layer, wherein the contact layer has an inclined surface that slopes downward toward the gate electrode. (20) An electronic device, comprising: an electric circuit having a semiconductor device, the semiconductor device comprising: a channel layer including a two-dimensional electron gas region, a barrier layer provided on the channel layer, a gate electrode provided on the barrier layer, and a contact layer provided on the channel layer, wherein the contact layer has an inclined surface that slopes downward toward the gate electrode. (21) An electric circuit comprising the semiconductor device according to any one of (1) to (18). (22) An electronic device comprising the electric circuit according to (21).

[0096] 1A Semiconductor device 1B Semiconductor device 1C Semiconductor device 1D Semiconductor device 1E Semiconductor device 11 Substrate 12 Buffer layer 13 Channel layer 13a Two-dimensional electron gas region 14 Spacer layer 15 Barrier layer 15A Back barrier layer 16 Cap layer 17 Contact layer 17a Inclined surface 17A Concave portion 17b Flat surface 17B Surface 17c Concave / convex portion 17C Contact layer 18 Source electrode 18C Source electrode 19 Drain electrode 19C Drain electrode 20 Gate electrode 100 Wireless communication device 130 Front-end component group 131 Switch 132 Low-noise amplifier 133 Band-pass filter 134 Power amplifier 200 Wireless communication device 210 Antenna 220 Antenna switch circuit 230 High-power amplifier 240 High-frequency integrated circuit 250 Baseband section 260 Audio output unit 270 Data output unit 280 Interface unit

Claims

1. A semiconductor device comprising: a channel layer including a two-dimensional electron gas region; a barrier layer provided on the channel layer; a gate electrode provided on the barrier layer; and a contact layer provided on the channel layer, wherein the contact layer has an inclined surface that slopes downward toward the gate electrode.

2. The semiconductor device according to claim 1, wherein the contact layer is in contact with the two-dimensional electron gas region.

3. The semiconductor device according to claim 2, wherein the contact layer is formed so that the height of the inclined surface is higher than the height of the surface of the barrier layer on the gate electrode side.

4. The semiconductor device according to claim 2, wherein the contact layer is formed so that the height of the inclined surface is lower than the height of the surface of the barrier layer on the gate electrode side.

5. The semiconductor device according to claim 2, further comprising a cap layer provided on the barrier layer, wherein the gate electrode is provided on the cap layer.

6. The semiconductor device according to claim 5, wherein the contact layer is formed so that the height of the inclined surface is higher than the height of the surface of the cap layer on the gate electrode side.

7. The semiconductor device according to claim 5, wherein the contact layer is formed so that the height of the inclined surface is lower than the height of the surface of the cap layer on the gate electrode side.

8. The semiconductor device according to claim 1, wherein the inclined surface is a curved surface that curves toward the channel layer.

9. The semiconductor device according to claim 1, wherein the inclined surface includes an uneven portion.

10. The semiconductor device according to claim 1, wherein the ratio of the vertical length of said inclined surface to the horizontal length of said inclined surface is 0.5 or less.

11. The semiconductor device according to claim 1, wherein the lateral length of said inclined surface is 0.1 μm or more.

12. The semiconductor device according to claim 1, further comprising an electrode covering all or part of the inclined surface.

13. The semiconductor device according to claim 1, further comprising a spacer layer provided between the channel layer and the barrier layer.

14. The semiconductor device according to claim 1, wherein the contact layer further has a flat surface connected to the inclined surface.

15. The semiconductor device according to claim 14, further comprising an electrode covering all or part of the inclined surface and the flat surface.

16. The semiconductor device according to claim 1, wherein two contact layers are provided, and each of the two contact layers has the inclined surface.

17. The semiconductor device according to claim 1, wherein the material of the barrier layer is AlInN.

18. The sheet carrier concentration of the two-dimensional electron gas region is 5×10 １２ cm －２ 2. The semiconductor device according to claim 1, wherein the two-dimensional electron gas region has a sheet resistance of 300 Ω / □ or less.

19. An electrical circuit comprising a semiconductor device comprising: a channel layer including a two-dimensional electron gas region; a barrier layer provided on the channel layer; a gate electrode provided on the barrier layer; and a contact layer provided on the channel layer, wherein the contact layer has an inclined surface that slopes downward toward the gate electrode.

20. An electronic device comprising an electric circuit having a semiconductor device, the semiconductor device comprising: a channel layer including a two-dimensional electron gas region; a barrier layer provided on the channel layer; a gate electrode provided on the barrier layer; and a contact layer provided on the channel layer, the contact layer having an inclined surface that slopes downward toward the gate electrode.

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