Semiconductor device and method for manufacturing same

Abstract

This semiconductor device (1) comprises: a channel layer (14); a barrier layer (16) that is provided above the channel layer (14) and has a larger band gap than the channel layer (14); a p-type semiconductor layer (18) provided above the barrier layer (16); a source electrode (32) and a drain electrode (34) between which the p-type semiconductor layer (18) is interposed; an i-type Al-containing layer (20) that is provided above the p-type semiconductor layer (18), has a larger band gap than the p-type semiconductor layer (18), and contains Al; an i-type Al-free layer (22) that is provided above the Al-containing layer (20) and does not contain Al; and a gate electrode (30) that is provided above the Al-free layer (22).

Description

Semiconductor device and manufacturing method thereof

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same.

[0002] Patent Documents 1 and 2 disclose field effect transistors aimed at reducing gate leakage current. In the field effect transistors disclosed in Patent Documents 1 and 2, a p-type GaN layer is provided between a semiconductor stack structure in which a two-dimensional electron gas layer is generated and a gate electrode. In the field effect transistor disclosed in Patent Document 1, an AlGaN layer is provided between the p-type GaN layer and the gate electrode. In the field effect transistor disclosed in Patent Document 2, a GaN layer is provided between the p-type GaN layer and the gate electrode.

[0003] JP 2014-140024 A JP 2014-110345 A

[0004] However, in the field-effect transistor disclosed in Patent Document 1, the AlGaN layer is exposed to the atmosphere before the gate electrode is formed, resulting in the formation of an oxide layer on the surface of the AlGaN layer. The formation of the oxide layer makes the Schottky characteristics between the AlGaN layer and the gate electrode unstable. In addition, the thickness of the oxide layer is prone to variation, which causes variation in the threshold voltage.

[0005] In the field effect transistor disclosed in Patent Document 2, a Schottky junction is formed between the GaN layer and the gate electrode. However, the effect of reducing gate leakage current is insufficient with just the Schottky junction.

[0006] Therefore, the present disclosure provides a semiconductor device that can reduce gate leakage current and suppress variations in threshold voltage, and a manufacturing method thereof.

[0007] A semiconductor device according to one aspect of the present disclosure includes: a first nitride semiconductor layer; a second nitride semiconductor layer provided above the first nitride semiconductor layer and having a larger band gap than the first nitride semiconductor layer; a p-type third nitride semiconductor layer provided above the second nitride semiconductor layer; a source electrode and a drain electrode provided so as to sandwich the third nitride semiconductor layer; an i-type fourth nitride semiconductor layer provided above the third nitride semiconductor layer and having a larger band gap than the third nitride semiconductor layer and containing Al; an i-type fifth nitride semiconductor layer provided above the fourth nitride semiconductor layer and not containing Al; and a gate electrode provided above the fifth nitride semiconductor layer.

[0008] A semiconductor device according to one aspect of the present disclosure includes a first nitride semiconductor layer, a second nitride semiconductor layer provided above the first nitride semiconductor layer and having a larger band gap than the first nitride semiconductor layer, a p-type third nitride semiconductor layer provided above the second nitride semiconductor layer, a source electrode and a drain electrode provided so as to sandwich the third nitride semiconductor layer, a fourth nitride semiconductor layer provided above the third nitride semiconductor layer and having a larger band gap than the third nitride semiconductor layer and containing Al, a fifth nitride semiconductor layer provided above the fourth nitride semiconductor layer and not containing Al, a gate electrode provided above the fifth nitride semiconductor layer, and at least a portion of the fifth nitride semiconductor layer has a thickness of less than 3 nm.

[0009] A method for manufacturing a semiconductor device according to one aspect of the present disclosure includes: a first step of forming, in this order, a first nitride semiconductor layer and a second nitride semiconductor layer having a larger band gap than the first nitride semiconductor layer; a second step of forming, in this order above the second nitride semiconductor layer, a p-type third nitride semiconductor layer, a fourth nitride semiconductor layer having a larger band gap than the third nitride semiconductor layer and containing Al, and an i-type fifth nitride semiconductor layer not containing Al; a third step of forming a source electrode and a drain electrode to sandwich the third nitride semiconductor layer therebetween; and a fourth step of forming a gate electrode above the fifth nitride semiconductor layer.

[0010] A method for manufacturing a semiconductor device according to one aspect of the present disclosure includes: a first step of forming, in this order, a first nitride semiconductor layer and a second nitride semiconductor layer having a larger band gap than the first nitride semiconductor layer; a second step of forming, in this order above the second nitride semiconductor layer, a p-type third nitride semiconductor layer, a fourth nitride semiconductor layer having a larger band gap than the third nitride semiconductor layer and containing Al, and a fifth nitride semiconductor layer not containing Al; a third step of forming a source electrode and a drain electrode to sandwich the third nitride semiconductor layer; and a fourth step of forming a gate electrode above the fifth nitride semiconductor layer, wherein at least a portion of the fifth nitride semiconductor layer has a thickness of less than 3 nm.

[0011] According to the present disclosure, it is possible to reduce gate leakage current and suppress variations in threshold voltage.

[0012] FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment. FIG. 2A is a cross-sectional view illustrating a step of a manufacturing method of a semiconductor device according to the first embodiment. FIG. 2B is a cross-sectional view illustrating a step of a manufacturing method of a semiconductor device according to the first embodiment. FIG. 2C is a cross-sectional view illustrating a step of a manufacturing method of a semiconductor device according to the first embodiment. FIG. 2D is a cross-sectional view illustrating a step of a manufacturing method of a semiconductor device according to the first embodiment. FIG. 3 is a cross-sectional view of a semiconductor device according to a second embodiment. FIG. 4 is a cross-sectional view illustrating an enlarged view of the vicinity of a gate structure of a semiconductor device according to the second embodiment. FIG. 5A is a cross-sectional view illustrating a step of a manufacturing method of a semiconductor device according to the second embodiment. FIG. 5B is a cross-sectional view illustrating a step of a manufacturing method of a semiconductor device according to the second embodiment. FIG. 6 is a cross-sectional view of a semiconductor device according to a third embodiment. FIG. 7A is a cross-sectional view illustrating a step of a manufacturing method of a semiconductor device according to the third embodiment. FIG. 7B is a cross-sectional view illustrating a step of a manufacturing method of a semiconductor device according to the third embodiment. FIG. 7C is a cross-sectional view illustrating a step of a manufacturing method of a semiconductor device according to the third embodiment. FIG. 7D is a cross-sectional view illustrating a step of a manufacturing method of a semiconductor device according to the third embodiment. FIG. 7E is a cross-sectional view illustrating a step of a manufacturing method of a semiconductor device according to the third embodiment. FIG. 8 is a cross-sectional view of a semiconductor device according to a fourth embodiment. FIG. 9A is a cross-sectional view illustrating one step of a method for manufacturing a semiconductor device according to the fourth embodiment. FIG. 9B is a cross-sectional view illustrating one step of a method for manufacturing a semiconductor device according to the fourth embodiment. FIG. 9C is a cross-sectional view illustrating one step of a method for manufacturing a semiconductor device according to the fourth embodiment. FIG. 9D is a cross-sectional view illustrating one step of a method for manufacturing a semiconductor device according to the fourth embodiment. FIG. 10 is a cross-sectional view of a semiconductor device according to the fifth embodiment. FIG. 11A is a cross-sectional view illustrating one step of a method for manufacturing a semiconductor device according to the fifth embodiment. FIG. 11B is a cross-sectional view illustrating one step of a method for manufacturing a semiconductor device according to the fifth embodiment. FIG. 11C is a cross-sectional view illustrating one step of a method for manufacturing a semiconductor device according to the fifth embodiment. FIG. 11D is a cross-sectional view illustrating one step of a method for manufacturing a semiconductor device according to the fifth embodiment.FIG. 11E is a cross-sectional view illustrating a step of a method for manufacturing a semiconductor device according to embodiment 5. FIG. 11F is a cross-sectional view illustrating a step of a method for manufacturing a semiconductor device according to embodiment 5. FIG. 12 is a cross-sectional view of a semiconductor device according to a modification of embodiment 5. FIG. 13 is a cross-sectional view of a semiconductor device according to embodiment 6. FIG. 14A is a cross-sectional view illustrating a step of a method for manufacturing a semiconductor device according to embodiment 6. FIG. 14B is a cross-sectional view illustrating a step of a method for manufacturing a semiconductor device according to embodiment 6. FIG. 14C is a cross-sectional view illustrating a step of a method for manufacturing a semiconductor device according to embodiment 6. FIG. 14D is a cross-sectional view illustrating a step of a method for manufacturing a semiconductor device according to embodiment 6. FIG. 14E is a cross-sectional view illustrating a step of a method for manufacturing a semiconductor device according to embodiment 6.

[0013] (Summary of the Present Disclosure) A semiconductor device according to a first aspect of the present disclosure includes a first nitride semiconductor layer, a second nitride semiconductor layer provided above the first nitride semiconductor layer and having a larger band gap than the first nitride semiconductor layer, a p-type third nitride semiconductor layer provided above the second nitride semiconductor layer, a source electrode and a drain electrode provided so as to sandwich the third nitride semiconductor layer, an i-type fourth nitride semiconductor layer provided above the third nitride semiconductor layer and having a larger band gap than the third nitride semiconductor layer and containing Al, an i-type fifth nitride semiconductor layer provided above the fourth nitride semiconductor layer and not containing Al, and a gate electrode provided above the fifth nitride semiconductor layer.

[0014] As a result, since the fifth nitride semiconductor layer not containing Al is provided above the fourth nitride semiconductor layer containing Al, oxidation of the upper surface of the fourth nitride semiconductor layer can be suppressed. This stabilizes the Schottky characteristics and the threshold voltage. Furthermore, since the fourth nitride semiconductor layer containing Al has a larger band gap than the third nitride semiconductor layer, the gate leakage current can be reduced. Thus, the semiconductor device according to this aspect can reduce the gate leakage current and suppress variations in the threshold voltage.

[0015] Furthermore, when a Schottky junction is formed between the gate electrode and the fourth nitride semiconductor layer having a large band gap, two-dimensional electron gas (2DEG) is not generated near the interface between the first nitride semiconductor layer and the second nitride semiconductor layer unless a large positive bias is applied to the gate electrode. In other words, a normally-off transistor having a large threshold voltage can be realized.

[0016] A semiconductor device according to a second aspect of the present disclosure is the semiconductor device according to the first aspect, wherein at least a portion of the fifth nitride semiconductor layer has a thickness of less than 3 nm.

[0017] This makes it possible to suppress oxidation of the upper surface of the fourth nitride semiconductor layer and stabilize the threshold voltage. Furthermore, by thinning the fifth nitride semiconductor layer, it is possible to suppress an unnecessary increase in the threshold voltage.

[0018] A semiconductor device according to a third aspect of the present disclosure includes a first nitride semiconductor layer, a second nitride semiconductor layer provided above the first nitride semiconductor layer and having a larger band gap than the first nitride semiconductor layer, a p-type third nitride semiconductor layer provided above the second nitride semiconductor layer, a source electrode and a drain electrode provided so as to sandwich the third nitride semiconductor layer, a fourth nitride semiconductor layer provided above the third nitride semiconductor layer and having a larger band gap than the third nitride semiconductor layer and containing Al, a fifth nitride semiconductor layer provided above the fourth nitride semiconductor layer and not containing Al, a gate electrode provided above the fifth nitride semiconductor layer, and at least a portion of the fifth nitride semiconductor layer has a thickness of less than 3 nm.

[0019] As a result, as in the first aspect, since the fifth nitride semiconductor layer not containing Al is provided above the fourth nitride semiconductor layer containing Al, oxidation of the upper surface of the fourth nitride semiconductor layer can be suppressed. This stabilizes the Schottky characteristics and the threshold voltage. Furthermore, since the fourth nitride semiconductor layer containing Al has a larger band gap than the third nitride semiconductor layer, the gate leakage current can be reduced. Thus, the semiconductor device according to this aspect can reduce the gate leakage current and suppress variations in the threshold voltage.

[0020] Furthermore, when a Schottky junction is formed between a fourth nitride semiconductor layer having a wide band gap and a gate electrode, 2DEG is not generated near the interface between the first nitride semiconductor layer and the second nitride semiconductor layer unless a large positive bias is applied to the gate electrode, which means that a normally-off transistor having a large threshold voltage can be realized.

[0021] A semiconductor device according to a fourth aspect of the present disclosure is a semiconductor device according to any one of the first to third aspects, wherein the fifth nitride semiconductor layer includes, in a cross section parallel to each of the gate length direction and the thickness direction, an inner region and an outer region located outward in the gate length direction from the inner region, and the semiconductor device includes an insulating film provided between an upper surface of the outer region and the gate electrode, and the gate electrode is in contact with an upper surface of the inner region.

[0022] This allows the gate length to be effectively shortened, enabling a steep gate operation, which in turn allows for faster switching operations, for example.

[0023] A semiconductor device according to a fifth aspect of the present disclosure is the semiconductor device according to the fourth aspect, wherein the thickness of the inner region is thinner than the thickness of the outer region.

[0024] This makes it possible to suppress an unnecessary increase in threshold voltage by thinning the inner region that is in contact with the gate electrode, and furthermore, because the outer region is thick, it is possible to further suppress oxidation of the top surface of the fourth nitride semiconductor layer directly below the outer region.

[0025] A semiconductor device according to a sixth aspect of the present disclosure is the semiconductor device according to the fifth aspect, wherein the difference in thickness between the outer region and the inner region is 1 nm or more.

[0026] This makes it possible to suppress an unnecessary increase in threshold voltage and also to suppress oxidation of the upper surface of the fourth nitride semiconductor layer.

[0027] A semiconductor device according to a seventh aspect of the present disclosure is a semiconductor device according to any one of the fourth to sixth aspects, wherein the length of the outer region in the gate length direction is 0.1 μm or more.

[0028] This allows the gate current during ON operation to flow mainly through the inner region and to be less likely to flow through the side regions where the gate current may be disabled, thereby suppressing variations in the Schottky characteristics.

[0029] A semiconductor device according to an eighth aspect of the present disclosure is a semiconductor device according to any one of the fourth to seventh aspects, wherein the hydrogen concentration in the inner region is higher than the p-type impurity concentration in the inner region.

[0030] In some cases, p-type impurities from the third nitride semiconductor layer diffuse into the fifth nitride semiconductor layer via the fourth nitride semiconductor layer. According to this aspect, the charge resulting from the p-type impurities can be neutralized by hydrogen. This improves the Schottky characteristics with the gate electrode, enabling the realization of a normally-off transistor with a large threshold voltage.

[0031] A semiconductor device according to a ninth aspect of the present disclosure is a semiconductor device according to any one of the fourth to eighth aspects, comprising an n-type sixth nitride semiconductor layer provided between an upper surface of the outer region and the insulating film.

[0032] This allows the n-type impurity to neutralize the charge resulting from the p-type impurity diffused into the fifth nitride semiconductor layer, thereby improving the Schottky characteristics with the gate electrode and realizing a normally-off transistor having a large threshold voltage.

[0033] A semiconductor device according to a tenth aspect of the present disclosure is the semiconductor device according to the ninth aspect, wherein the boundary between the inner region and the outer region is flush with a portion of the side surface of the sixth nitride semiconductor layer.

[0034] This prevents the n-type sixth nitride semiconductor layer from being provided on the inner region, thereby suppressing deterioration of the Schottky characteristics.

[0035] A semiconductor device according to an eleventh aspect of the present disclosure is the semiconductor device according to any one of the first to tenth aspects, wherein the third nitride semiconductor layer contains GaN as a main component.

[0036] This allows for a higher activation rate of the p-type dopant compared to mixed crystals such as AlGaN, making it easier to maintain normally-off characteristics.

[0037] A semiconductor device according to a twelfth aspect of the present disclosure is the semiconductor device according to any one of the first to eleventh aspects, wherein the fourth nitride semiconductor layer contains AlGaN as a main component.

[0038] This increases the resistance component between the gate electrode and the 2DEG, thereby reducing the gate leakage current.

[0039] A semiconductor device according to a thirteenth aspect of the present disclosure is the semiconductor device according to any one of the first to twelfth aspects, wherein the fifth nitride semiconductor layer contains GaN as a main component.

[0040] This makes it possible to suppress oxidation of the upper surface of the fourth nitride semiconductor layer, thereby stabilizing the threshold voltage.

[0041] A semiconductor device according to a fourteenth aspect of the present disclosure is a semiconductor device according to any one of the first to thirteenth aspects, further comprising a seventh nitride semiconductor layer provided between the third nitride semiconductor layer and the fourth nitride semiconductor layer, the seventh nitride semiconductor layer having a band gap larger than that of the fourth nitride semiconductor layer.

[0042] This allows the seventh nitride semiconductor layer to function as a band barrier layer between the third nitride semiconductor layer and the fourth nitride semiconductor layer, further increasing the resistance component between the gate electrode and the 2DEG, thereby reducing the gate leakage current.

[0043] A semiconductor device according to a fifteenth aspect of the present disclosure is the semiconductor device according to the fourteenth aspect, wherein the seventh nitride semiconductor layer has a thickness of less than 3 nm.

[0044] This can prevent crystal defects from occurring in the upper layers due to lattice mismatch between the third nitride semiconductor layer and the seventh nitride semiconductor layer, thereby preventing deterioration of the Schottky characteristics between the gate electrode and the fourth nitride semiconductor layer.

[0045] A semiconductor device according to a sixteenth aspect of the present disclosure is a semiconductor device according to any one of the first to fifteenth aspects, comprising a p-type eighth nitride semiconductor layer provided so as to be embedded in the second nitride semiconductor layer at a position overlapping the third nitride semiconductor layer in a planar view, and an upper surface of the eighth nitride semiconductor layer is flush with an upper surface of the second nitride semiconductor layer.

[0046] This allows the thickness of the third nitride semiconductor layer to be reduced in the portion located directly below the gate electrode, making it possible to adjust the threshold voltage while maintaining low resistance without affecting the concentration of the 2DEG between the gate and drain and between the gate and source.

[0047] A method for manufacturing a semiconductor device according to a seventeenth aspect of the present disclosure includes: a first step of forming, in this order, a first nitride semiconductor layer and a second nitride semiconductor layer having a larger band gap than the first nitride semiconductor layer; a second step of forming, in this order above the second nitride semiconductor layer, a p-type third nitride semiconductor layer, a fourth nitride semiconductor layer having a larger band gap than the third nitride semiconductor layer and containing Al, and an i-type fifth nitride semiconductor layer not containing Al; a third step of forming a source electrode and a drain electrode to sandwich the third nitride semiconductor layer; and a fourth step of forming a gate electrode above the fifth nitride semiconductor layer.

[0048] As a result, since the fifth nitride semiconductor layer not containing Al is provided above the fourth nitride semiconductor layer containing Al, oxidation of the upper surface of the fourth nitride semiconductor layer can be suppressed. This stabilizes the Schottky characteristics and the threshold voltage. Furthermore, since the fourth nitride semiconductor layer containing Al has a larger band gap than the third nitride semiconductor layer, the gate leakage current can be reduced. Thus, according to this aspect, a semiconductor device can be manufactured in which the gate leakage current is reduced and the variation in threshold voltage is suppressed.

[0049] Furthermore, when a Schottky junction is formed between the fourth nitride semiconductor layer having a wide band gap and the gate electrode, 2DEG does not occur unless a large positive bias is applied to the gate electrode, which means that a normally-off transistor having a large threshold voltage can be manufactured.

[0050] A method for manufacturing a semiconductor device according to an eighteenth aspect of the present disclosure includes: a first step of forming, in this order, a first nitride semiconductor layer and a second nitride semiconductor layer having a larger band gap than the first nitride semiconductor layer; a second step of forming, in this order above the second nitride semiconductor layer, a p-type third nitride semiconductor layer, a fourth nitride semiconductor layer having a larger band gap than the third nitride semiconductor layer and containing Al, and a fifth nitride semiconductor layer not containing Al; a third step of forming a source electrode and a drain electrode to sandwich the third nitride semiconductor layer; and a fourth step of forming a gate electrode above the fifth nitride semiconductor layer, wherein at least a portion of the fifth nitride semiconductor layer has a thickness of less than 3 nm.

[0051] As a result, as in the seventeenth aspect, since the fifth nitride semiconductor layer not containing Al is provided above the fourth nitride semiconductor layer containing Al, oxidation of the upper surface of the fourth nitride semiconductor layer can be suppressed. This stabilizes the Schottky characteristics and the threshold voltage. Furthermore, since the fourth nitride semiconductor layer containing Al has a larger band gap than the third nitride semiconductor layer, the gate leakage current can be reduced. Thus, according to this aspect, a semiconductor device can be manufactured in which the gate leakage current is reduced and the variation in threshold voltage is suppressed.

[0052] Furthermore, when a Schottky junction is formed between the fourth nitride semiconductor layer having a wide band gap and the gate electrode, 2DEG does not occur unless a large positive bias is applied to the gate electrode, which means that a normally-off transistor having a large threshold voltage can be manufactured.

[0053] A method for manufacturing a semiconductor device according to a 19th aspect of the present disclosure is a method for manufacturing a semiconductor device according to the 17th or 18th aspect, wherein the fifth nitride semiconductor layer includes, in a cross section parallel to each of the gate length direction and the thickness direction, an inner region and an outer region located outward of the inner region in the gate length direction, and the method for manufacturing a semiconductor device includes a fifth step of forming a first insulating film covering an upper surface of the outer region, and in the fourth step, forming the gate electrode so as to be in contact with an upper surface of the inner region.

[0054] This allows the gate length to be effectively shortened, enabling a steep gate operation, which in turn allows for faster switching operations, for example.

[0055] A method for manufacturing a semiconductor device according to a twentieth aspect of the present disclosure is a method for manufacturing a semiconductor device according to the nineteenth aspect, and includes a sixth step of etching using the first insulating film as a mask to make the thickness of the inner region thinner than the thickness of the outer region.

[0056] This makes it possible to suppress an unnecessary increase in threshold voltage by thinning the inner region that is in contact with the gate electrode, and furthermore, because the outer region is thick, it is possible to further suppress oxidation of the top surface of the fourth nitride semiconductor layer directly below the outer region.

[0057] A semiconductor device manufacturing method according to a twenty-first aspect of the present disclosure is the semiconductor device manufacturing method according to the twentieth aspect, in which the etching is dry etching using a gas containing hydrogen gas.

[0058] As a result, hydrogen penetrates into the inner region, neutralizing the charge caused by the p-type impurities diffused from the third nitride semiconductor layer. This improves the Schottky characteristics with the gate electrode, and 2DEG does not occur unless a large positive bias is applied to the gate electrode. In other words, a normally-off transistor with a large threshold voltage can be realized.

[0059] A semiconductor device manufacturing method according to a 22nd aspect of the present disclosure is a semiconductor device manufacturing method according to the 20th or 21st aspect, wherein in the sixth step, etching is performed until the thickness of the inner region is less than 3 nm.

[0060] This makes it possible to suppress oxidation of the upper surface of the fourth nitride semiconductor layer and stabilize the threshold voltage. Furthermore, by thinning the fifth nitride semiconductor layer, it is possible to suppress an unnecessary increase in the threshold voltage.

[0061] A semiconductor device manufacturing method according to a 23rd aspect of the present disclosure is a semiconductor device manufacturing method according to any one of the 19th to 22nd aspects, and includes a seventh step of forming a second insulating film having an opening after the first step and before the second step, and in the second step, the third nitride semiconductor layer, the fourth nitride semiconductor layer, and the fifth nitride semiconductor layer are formed within the opening.

[0062] This allows the second nitride semiconductor layer and the second insulating film to be formed continuously, thereby preventing the upper surface of the second nitride semiconductor layer from being oxidized, and making it difficult for impurity levels to be formed in the upper surface of the second nitride semiconductor layer, thereby increasing the lateral breakdown voltage.

[0063] A semiconductor device manufacturing method according to a 24th aspect of the present disclosure is a semiconductor device manufacturing method according to any one of the 17th to 22nd aspects, wherein in the second step, a stacked film of nitride semiconductors is formed by performing crystal growth continuously from the first step, and the formed stacked film is patterned to form the third nitride semiconductor layer, the fourth nitride semiconductor layer, and the fifth nitride semiconductor layer.

[0064] This allows the second nitride semiconductor layer and the third nitride semiconductor layer to be formed continuously, making it difficult for impurity levels to be formed at the interface, thereby stabilizing the threshold voltage and reducing the gate leakage current.

[0065] A semiconductor device manufacturing method according to a twenty-fifth aspect of the present disclosure is the semiconductor device manufacturing method according to the twenty-fourth aspect, wherein the patterning of the stacked film comprises etching using the gate electrode as a mask.

[0066] This allows the gate electrode, the third nitride semiconductor layer, and the fourth nitride semiconductor layer to be formed simultaneously. The gate length can be shortened, enabling steep gate operation. Furthermore, the parasitic resistance of the transistor can be reduced, resulting in a reduced on-resistance.

[0067] A semiconductor device manufacturing method according to a 26th aspect of the present disclosure is a semiconductor device manufacturing method according to any one of the 17th to 25th aspects, wherein in the second step, an n-type sixth nitride semiconductor layer is formed above the fifth nitride semiconductor layer.

[0068] This allows the n-type impurity to neutralize the charge resulting from the p-type impurity diffused into the fifth nitride semiconductor layer, thereby improving the Schottky characteristics with the gate electrode and realizing a normally-off transistor having a large threshold voltage.

[0069] A method for manufacturing a semiconductor device according to a 27th aspect of the present disclosure is a method for manufacturing a semiconductor device according to any one of the 17th to 26th aspects, wherein in the second step, a seventh nitride semiconductor layer having a band gap larger than that of the fourth nitride semiconductor layer is formed between the third nitride semiconductor layer and the fourth nitride semiconductor layer.

[0070] This allows the seventh nitride semiconductor layer to function as a band barrier layer between the third nitride semiconductor layer and the fourth nitride semiconductor layer, further increasing the resistance component between the gate electrode and the 2DEG, thereby reducing the gate leakage current.

[0071] Hereinafter, the embodiments will be specifically described with reference to the drawings.

[0072] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component placement and connection configurations, steps, and step order shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, among the components in the following embodiments, components not described in the independent claims are described as optional components.

[0073] Furthermore, each figure is a schematic diagram and is not necessarily an exact illustration. Therefore, for example, the scales of the figures do not necessarily match. Furthermore, in each figure, substantially the same components are given the same reference numerals, and redundant explanations are omitted or simplified.

[0074] Furthermore, in this specification, terms indicating the relationship between elements, such as parallel and perpendicular, terms indicating the shape of elements, and numerical ranges are not expressions that only express a strict meaning, but are expressions that also include a substantially equivalent range, for example, a difference of about a few percent.

[0075] In addition, in this specification, the terms "upper" and "lower" do not refer to the upper direction (vertically upper) and lower direction (vertically lower) in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in a stacked structure. Furthermore, the terms "upper" and "lower" are used not only when two components are arranged with a gap between them and another component is present between them, but also when two components are arranged in close contact with each other and the two components are in contact. In this specification, the direction in which the gate electrode is provided relative to the substrate is considered to be "upper." Furthermore, in this specification, "plan view" refers to a view from a direction perpendicular to the top surface of the substrate, unless otherwise specified.

[0076] In this specification, a nitride semiconductor refers to a group III nitride semiconductor containing one or more group III elements and nitrogen. Examples of group III elements include aluminum (Al), gallium (Ga), and indium (In). Examples of group III nitride semiconductors include GaN, AlN, InN, AlGaN, InGaN, and AlInGaN. A group III nitride semiconductor may contain one or more elements other than group III elements, such as silicon (Si), phosphorus (P), and magnesium (Mg). In the following description, unless otherwise specified, the term "AlInGaN" means that the group III nitride semiconductor contains all of Al, In, Ga, and N. The same applies to other designations such as AlGaN and GaN.

[0077] In this specification, n-type and p-type refer to the conductivity type of a semiconductor, and are conductivity types of opposite polarity. The i-type typically refers to a so-called undoped state in which no n-type or p-type dopants are added. The i-type semiconductor layer may be doped with n-type or p-type dopants, provided that the n-type or p-type dopants are not activated. The i-type semiconductor layer may be doped with impurities other than n-type or p-type dopants.

[0078] In this specification, the term "major component" refers to the component with the highest content among all components constituting a member. For example, a component with a content of 50% or more is a major component. A component may be a material, an element, or a compound.

[0079] First Embodiment First, a semiconductor device according to a first embodiment will be described.

[0080] FIG. 1 is a cross-sectional view of a semiconductor device 1 according to this embodiment. Specifically, FIG. 1 shows a cross section parallel to each of the gate length direction and the thickness direction. The gate length direction is the left-right direction in FIG. 1, and is the direction in which the source electrode 32, the gate electrode 30, and the drain electrode 34 are aligned. The gate length direction is sometimes called the channel length direction. The thickness direction is the up-down direction in FIG. 1, and is the direction perpendicular to the main surface of the substrate 10. The thickness direction is sometimes called the stacking direction.

[0081] 1 is a normally-off type high electron mobility transistor (HEMT) that includes a substrate 10, a buffer layer 12, a channel layer 14, a barrier layer 16, a p-type semiconductor layer 18, an Al-containing layer 20, an Al-free layer 22, a gate electrode 30, a source electrode 32, a drain electrode 34, and an insulating film 40.

[0082] The substrate 10 is a support substrate that supports the main structure of the HEMT. The substrate 10 is, for example, a Si substrate, but may also be an SOI (Silicon on Insulator) substrate. Alternatively, the substrate 10 may be a substrate containing SiC, sapphire, diamond, GaN, AlN, or the like as a main component.

[0083] The buffer layer 12 is a nitride semiconductor layer containing a nitride semiconductor as a main component. The buffer layer 12 is provided to reduce the lattice mismatch between the substrate 10 and the channel layer 14. For example, the buffer layer 12 has a superlattice structure in which multiple AlN films and AlGaN films are alternately stacked, but this is not limited thereto. Another layer, such as a back barrier layer, may be provided between the buffer layer 12 and the channel layer 14. The back barrier layer is, for example, a layer with a larger band gap than the channel layer 14, and is a nitride semiconductor layer containing i-type AlGaN as a main component, but is not limited thereto. The buffer layer 12 and the substrate 10 may not be provided.

[0084] The channel layer 14 is an example of a first nitride semiconductor layer and may also be called an electron transit layer. The channel layer 14 contains i-type GaN as a main component, but is not limited to this. The channel layer 14 may contain, for example, i-type InGaN, AlGaN, InAlGaN, or the like as a main component.

[0085] The barrier layer 16 is an example of a second nitride semiconductor layer, and may also be called an electron supply layer. The barrier layer 16 is provided above the channel layer 14 and has a larger band gap than the channel layer 14. The barrier layer 16 contains i-type AlGaN as a main component, but is not limited to this. The barrier layer 16 may also contain, for example, i-type GaN, InAlGaN, or the like as a main component.

[0086] The barrier layer 16 is in contact with the upper surface of the channel layer 14, forming a heterojunction. Electrons generated by piezoelectric polarization and spontaneous polarization are accumulated along the interface between the barrier layer 16 and the channel layer 14, generating a 2DEG on the channel layer 14 side of the interface. By controlling the generation and disappearance of the 2DEG by the potential applied to the gate electrode 30, the semiconductor device 1 can be operated as a transistor.

[0087] It is only necessary that 2DEG is generated in the channel layer 14, and the barrier layer 16 and the channel layer 14 do not need to be in contact with each other. For example, a nitride semiconductor layer such as AlN may be provided between the barrier layer 16 and the channel layer 14.

[0088] The p-type semiconductor layer 18 is an example of a p-type third nitride semiconductor layer. The p-type semiconductor layer 18 is provided above the barrier layer 16. For example, the p-type semiconductor layer 18 is provided in contact with the upper surface 16a of the barrier layer 16. The p-type semiconductor layer 18 contains p-type GaN as a main component. Compared to mixed crystals such as AlGaN, the activation rate of the p-type dopant is higher, making it easier to maintain normally-off characteristics. The p-type dopant is, for example, Mg. The p-type semiconductor layer 18 may also contain p-type AlGaN, InGaN, InAlGaN, or the like as a main component.

[0089] The p-type semiconductor layer 18 is provided between and spaced apart from the source electrode 32 and the drain electrode 34. As shown in FIG. 1 , the side surface of the p-type semiconductor layer 18 faces the source electrode 32 or the drain electrode 34, but is not in contact with either the source electrode 32 or the drain electrode 34.

[0090] The Al-containing layer 20 is an example of a fourth nitride semiconductor layer containing Al. The Al-containing layer 20 is provided above the p-type semiconductor layer 18 and has a larger band gap than the p-type semiconductor layer 18. For example, the Al-containing layer 20 is provided in contact with the upper surface of the p-type semiconductor layer 18. The Al-containing layer 20 contains i-type AlGaN as a main component. This increases the resistance component between the gate electrode 30 and the 2DEG, thereby reducing the gate leakage current. The Al-containing layer 20 may contain i-type GaN, InGaN, InAlGaN, or the like as a main component. The conductivity type of the Al-containing layer 20 is i-type, but may also be p-type or n-type.

[0091] The Al-free layer 22 is an example of a fifth nitride semiconductor layer that does not contain Al. The Al-free layer 22 is provided above the Al-containing layer 20. For example, the Al-free layer 22 is provided in contact with the upper surface of the Al-containing layer 20. For example, the Al-free layer 22 contains i-type GaN as a main component. This can suppress oxidation of the upper surface of the Al-containing layer 20 and stabilize the threshold voltage. The Al-free layer 22 may contain i-type InGaN, InN, or the like as a main component. The conductivity type of the Al-free layer 22 is i-type, but may also be p-type or n-type.

[0092] The Al-free layer 22 includes an inner region 23 and an outer region 24 in a cross section (cross section shown in FIG. 1 ) parallel to both the gate length direction and the thickness direction. The outer region 24 is located outward of the inner region 23 in the gate length direction. The outer region 24 is provided on both the source electrode 32 side and the drain electrode 34 side of the inner region 23. In this embodiment, the thickness of the inner region 23 is the same as the thickness of the outer region 24.

[0093] The gate electrode 30 is provided above the Al-free layer 22. For example, the gate electrode 30 contacts and covers the upper surface of the Al-free layer 22. Specifically, the gate electrode 30 contacts the upper surface 23 a of the inner region 23 of the Al-free layer 22 through an opening 41 provided in the insulating film 40.

[0094] The gate electrode 30 contains, as a main component, a conductive material such as a metal element, a metal alloy, or a metal nitride. For example, the gate electrode 30 has a single-layer structure of a conductive film containing Ti or TiN as a main component. Alternatively, the gate electrode 30 may have a stacked structure of multiple conductive films. For example, the gate electrode 30 may include a conductive film containing Al, W, or WSi as a main component.

[0095] The source electrode 32 and the drain electrode 34 are provided to sandwich the p-type semiconductor layer 18. Specifically, the source electrode 32 and the drain electrode 34 sandwich the p-type semiconductor layer 18, the Al-containing layer 20, the Al-free layer 22, and the gate electrode 30 therebetween.

[0096] In this embodiment, the source electrode 32 and the drain electrode 34 are provided in contact with the upper surface 16a of the barrier layer 16. Both the source electrode 32 and the drain electrode 34 are electrically connected to the 2DEG.

[0097] The source electrode 32 and the drain electrode 34 contain, as a main component, a conductive material that forms an ohmic contact with the n-type nitride semiconductor. For example, the source electrode 32 and the drain electrode 34 have a stacked structure of a conductive film containing Ti as a main component, a conductive film containing Al as a main component, and a conductive film containing Ti as a main component. The source electrode 32 and the drain electrode 34 may also have a single-layer structure of a conductive film. The conductive film may be a metal film containing a metal element as a main component, a metal film containing a metal alloy as a main component, or a conductive metal nitride film. The source electrode 32 and the drain electrode 34 may contain the same material as a main component, or may contain different materials as main components.

[0098] At least one of the source electrode 32 and the drain electrode 34 may be in contact with the channel layer 14. For example, a source opening and a drain opening may be provided that penetrate the barrier layer 16 and reach the channel layer 14, and the source electrode 32 may be provided so as to cover the bottom and side surfaces of the source opening, and the drain electrode 34 may be provided so as to cover the bottom and side surfaces of the drain opening.

[0099] The insulating film 40 is an example of a first insulating film, and is provided between the upper surface 24 a of the outer region 24 of the Al-free layer 22 and the gate electrode 30. Due to the provision of the insulating film 40, the gate electrode 30 is not in contact with the upper surface 24 a of the outer region 24.

[0100] In this embodiment, the insulating film 40 covers not only the upper surface 24a of the outer region 24, but also the side surfaces of the Al-free layer 22, the Al-containing layer 20, and the p-type semiconductor layer 18, and the upper surface 16a of the barrier layer 16. For example, the insulating film 40 covers and contacts the upper surface 16a of the barrier layer 16 between the gate electrode 30 and the source electrode 32 and between the gate electrode 30 and the drain electrode 34 in a plan view.

[0101] The insulating film 40 has openings 41, 42, and 43. The opening 41 is provided at a position overlapping the inner region 23 of the Al-free layer 22 in plan view. The opening 41 is provided to expose the upper surface 23 a of the inner region 23 and bring the upper surface 23 a into contact with the gate electrode 30.

[0102] The opening 42 is provided to expose the upper surface 16 a of the barrier layer 16 and bring the upper surface 16 a into contact with the source electrode 32. The opening 43 is provided to expose the upper surface 16 a of the barrier layer 16 and bring the upper surface 16 a into contact with the drain electrode 34. In this embodiment, the source electrode 32 and the drain electrode 34 cover the ends of the openings 42 and 43, respectively, but this is not limiting. The insulating film 40 does not necessarily have to be in contact with the source electrode 32 or the drain electrode 34.

[0103] The insulating film 40 contains, for example, SiN as a main component, but is not limited to this. ２ , SiON, Al ２ O ３ The insulating film 40 may contain, as a main component, a single layer structure or a laminate structure of a plurality of insulating films. The insulating film 40 is formed by plasma CVD (Chemical Vapor Deposition) or the like.

[0104] The insulating film 40 can increase the lateral breakdown voltage of the semiconductor device 1. Specifically, the breakdown voltage between the gate and the drain can be increased.

[0105] As described above, in the semiconductor device 1 according to this embodiment, the Al-containing layer 20 is provided between the p-type semiconductor layer 18 and the gate electrode 30. Since the band gap of the Al-containing layer 20 is larger than the band gap of the p-type semiconductor layer 18, the electrical resistance between the gate electrode 30 and the p-type semiconductor layer 18 increases. This makes it possible to reduce the gate leakage current.

[0106] Furthermore, since the Al-free layer 22 is provided above the Al-containing layer 20, it is possible to suppress oxidation of the upper surface of the Al-containing layer 20. As a result, the Schottky characteristics are stabilized, and the threshold voltage can be stabilized.

[0107] Furthermore, when the Al-containing layer 20 having a large band gap is connected to the gate electrode 30 by a Schottky junction, 2DEG is not generated near the interface between the channel layer 14 and the barrier layer 16 unless a large positive bias is applied to the gate electrode 30. In other words, the semiconductor device 1 can be operated as a normally-off transistor having a large threshold voltage.

[0108] The dimensions of the main components of the semiconductor device 1 can be, for example, as follows:

[0109] The thickness of the channel layer 14 is, for example, 100 nm or more and 400 nm or less, for example, 200 nm. The thickness of the barrier layer 16 is, for example, 10 nm or more and 80 nm or less, for example, 30 nm. The thickness of the p-type semiconductor layer 18 is, for example, 50 nm or more and 200 nm or less, for example, 100 nm. The thickness of the Al-containing layer 20 is, for example, 5 nm or more and 30 nm or less, for example, 20 nm. The thickness of the Al-free layer 22 is, for example, 0.5 nm or more and less than 3 nm, for example, 2 nm. For example, the Al-containing layer 20 is thinner than the p-type semiconductor layer 18 and thicker than the Al-free layer 22. When the thickness of the Al-free layer 22 is less than 3 nm, an unnecessary increase in threshold voltage can be suppressed.

[0110] The length in the gate length direction of each of the p-type semiconductor layer 18, the Al-containing layer 20, and the Al-free layer 22 is, for example, 1 μm or more and 2 μm or less. The length in the gate length direction of each of the p-type semiconductor layer 18, the Al-containing layer 20, and the Al-free layer 22 is equal to one another, for example, 1.6 μm. In the p-type semiconductor layer 18, the concentration of the p-type dopant is 1×10 １９ cm －３ That's it, 2 x 10 ２０ cm －３ As an example, １９ cm －３The concentration of the p-type dopant can be measured by, for example, secondary ion mass spectrometry (SIMS).

[0111] The length L of the outer region 24 of the Al-free layer 22 on the source electrode 32 side (left side) in the gate length direction ２ The length L of the outer region 24 of the Al-free layer 22 on the drain electrode 34 side (right side) in the gate length direction is, for example, 0.1 μm or more and 0.3 μm or less, for example, 0.2 μm. ２ The length L of the outer region 24 is, for example, 0.1 μm or more and 0.3 μm or less, for example, 0.2 μm. ２ By making the length L of the outer region 24 on the left and right of the inner region 23, it is possible to separate the region through which the gate current mainly flows during ON operation (specifically, the inner region 23) from the side surface of the gate structure. Since there is a possibility that the gate current will be invalid if it flows through the side surface of the gate structure, by separating the inner region 23 from the side surface of the gate structure, it is possible to suppress variations in the Schottky characteristics. ２ The outer region 24 can be regarded as a region covered with the insulating film 40 in a plan view of the substrate 10.

[0112] The inner region 23 can be regarded as a region not covered with the insulating film 40 in a plan view of the substrate 10, i.e., a region exposed to the opening 41 of the insulating film 40. The length L of the inner region 23 in the gate length direction １ The length L of the inner region 23 in the gate length direction is, for example, 0.4 μm or more and 1.8 μm or less, for example, 1.2 μm. １ corresponds to the gate length of the semiconductor device 1. The gate length is shorter than the length of the gate electrode 30 in the gate length direction, allowing for a steep gate operation.

[0113] The thickness of the gate electrode 30 is, for example, 200 nm or more and 500 nm or less, and is 400 nm as an example. Note that FIG. 1 shows an example in which the upper surface of the gate electrode 30 is flush and the lower surface has a step, and the thickness of the gate electrode 30 varies depending on the position. In this case, the thickness of the gate electrode 30 is represented by the distance between the upper surface of the gate electrode 30 and the upper surface (upper surface 23a) of the Al-free layer 22. Note that the thickness of the gate electrode 30 is substantially uniform, and the upper surface may have a step (recess) corresponding to the step on the lower surface. The length L in the gate length direction of the gate electrode 30 Ｇ is, for example, 1 μm or more and 2 μm or less, and is 1.6 μm as an example.

[0114] The thickness of the insulating film 40 is, for example, 100 nm or more and 300 nm or less, and is, for example, 140 nm.

[0115] As shown in FIG. 1, the distance L between the source electrode 32 and the p-type semiconductor layer 18 ＧＳ The distance L between the drain electrode 34 and the p-type semiconductor layer 18 is, for example, 1 μm or more and 3 μm or less, for example, 2 μm. ＧＤ is, for example, 7 μm or more and 13 μm or less, and is 10 μm as an example. ＧＳ corresponds to the so-called gate-source distance, and the distance L ＧＤ corresponds to the so-called gate-drain distance. ＧＤ By increasing the length of L, the breakdown voltage can be increased. ＧＳ and L ＧＤ This shows an example where L is the same as L. ＧＳ Is, L ＧＤ It may be shorter than

[0116] [Manufacturing Method] Next, a manufacturing method of the semiconductor device 1 according to this embodiment will be described.

[0117] The method for manufacturing the semiconductor device 1 includes a first step and a second step for sequentially forming a plurality of nitride semiconductor layers, a third step for forming a source electrode 32 and a drain electrode 34, a fourth step for forming a gate electrode 30, and a fifth step for forming an insulating film 40. In this embodiment, the first step, the second step, the fifth step, the third step, and the fourth step are performed in this order. Each step will be specifically described below with reference to FIGS. 2A to 2D. FIGS. 2A to 2D are cross-sectional views for describing each step of the method for manufacturing the semiconductor device 1 according to this embodiment.

[0118] First, as shown in FIG. 2A , in the first step, a channel layer 14 and a barrier layer 16 are formed in this order. Furthermore, in the second step, a p-type semiconductor layer 18, an Al-containing layer 20, and an Al-free layer 22 are formed in this order. In the second step according to this embodiment, a nitride semiconductor layer is formed by continuing crystal growth from the first step. The layer is a layer including the p-type semiconductor layer 18, the Al-containing layer 20, and the Al-free layer 22 before being patterned into a predetermined shape. Specifically, a nitride semiconductor film is formed on the upper surface of the substrate 10 by epitaxial growth, thereby forming the buffer layer 12, the channel layer 14, the barrier layer 16, the p-type semiconductor layer 18, the Al-containing layer 20, and the Al-free layer 22 in this order. The composition and thickness of each layer can be controlled by adjusting the gas introduced, dopant, growth temperature, growth time, and the like during the epitaxial growth.

[0119] 2B , in a second step, the formed stacked film is patterned to form a p-type semiconductor layer 18, an Al-containing layer 20, and an Al-free layer 22 each having a predetermined shape. For example, by photolithography and dry etching, portions of the Al-free layer 22, the Al-containing layer 20, and the p-type semiconductor layer 18 located outside the gate region are selectively removed. In the region outside the gate region, the upper surface 16 a of the barrier layer 16 is exposed.

[0120] 2C , in a fifth step, an insulating film 40 is formed. For example, the insulating film 40 is formed by depositing a SiN film by plasma CVD so as to cover the upper surface 16 a of the barrier layer 16 and the upper surface 22 a of the Al-free layer 22.

[0121] Next, as shown in FIG. 2D , in a third step, the source electrode 32 and the drain electrode 34 are formed to sandwich the p-type semiconductor layer 18 therebetween. Specifically, first, openings 42 and 43 are formed in the insulating film 40. For example, by photolithography and dry etching, regions of the insulating film 40 where the source electrode 32 and the drain electrode 34 are to be formed are removed to form the openings 42 and 43. Thereafter, for example, a conductive film is formed over the entire surface by sputtering or vapor deposition, and then the conductive film is patterned into a predetermined shape by photolithography and dry etching to form the source electrode 32 and the drain electrode 34. The patterning may be performed by a lift-off method. Alternatively, the source electrode 32 and the drain electrode 34 may be formed in different steps.

[0122] Next, in the fourth step, a gate electrode 30 is formed above the Al-free layer 22. Specifically, first, an opening 41 is formed in the insulating film 40. For example, the opening 41 is formed by removing a portion of the insulating film 40 above the inner region 23 of the Al-free layer 22 by photolithography and dry etching. The portion of the Al-free layer 22 exposed in the opening 41 is the inner region 23. The upper surface 23a of the inner region 23 is exposed in the opening 41. Thereafter, a conductive film is formed over the entire surface by, for example, sputtering or vapor deposition, and then the conductive film is patterned into a predetermined shape by photolithography and dry etching to form the gate electrode 30. The patterning may be performed by a lift-off method. As a result, the gate electrode 30 contacts the upper surface 23a of the inner region 23 through the opening 41. The portion of the Al-free layer 22 covered by the insulating film 40 is the outer region 24. The upper surface 24a of the outer region 24 is covered by the insulating film 40 and does not contact the gate electrode 30.

[0123] Through the above steps, the semiconductor device 1 shown in FIG. 1 can be manufactured.

[0124] Generally, the substrate 10 undergoing manufacturing is transported between apparatuses between the crystal growth process and the etching process, and the substrate 10 is exposed to the atmosphere during this transport. In the manufacturing method of the semiconductor device 1 according to this embodiment, as described with reference to FIG. 2A , the Al-containing layer 20 and the Al-free layer 22 are continuously formed. Even if the substrate 10 is exposed to the atmosphere for etching after the formation of the Al-free layer 22, the upper surface of the Al-containing layer 20 is not exposed to the atmosphere because it is covered with the Al-free layer 22. Therefore, oxidation of the upper surface of the Al-containing layer 20 is suppressed, and variations in the Schottky characteristics can be suppressed.

[0125] The method for manufacturing the semiconductor device 1 is not limited to the above example. The fourth step of forming the gate electrode 30 may be performed before the third step of forming the source electrode 32 and the drain electrode 34. Furthermore, the openings 41, 42, and 43 may be formed in the same step.

[0126] (Embodiment 2) Next, a description will be given of embodiment 2. The following description will focus on the differences from embodiment 1, and the description of commonalities will be omitted or simplified.

[0127] [Configuration] Fig. 3 is a cross-sectional view of the semiconductor device 100 according to the present embodiment. Fig. 4 is an enlarged cross-sectional view of the vicinity of the gate structure of the semiconductor device 100 according to the present embodiment. As shown in Figs. 3 and 4, the semiconductor device 100 includes an Al-free layer 122 instead of the Al-free layer 22, as compared to the semiconductor device 1 according to the first embodiment.

[0128] The Al-free layer 122 is an example of a fifth nitride semiconductor layer that does not contain Al, and has a different cross-sectional shape compared to the Al-free layer 22. Specifically, the Al-free layer 22 has a uniform thickness, whereas the Al-free layer 122 includes portions with different thicknesses. Note that the conductivity type of the Al-free layer 122 is i-type, but it may also be p-type or n-type.

[0129] 3 and 4, the Al-free layer 122 includes an inner region 123 and an outer region 124. The thickness T １ is the thickness T of the outer region 124 ２ Specifically, the lower surfaces of the inner region 123 and the outer region 124 are flush with each other, and a step is formed on the upper surface. More specifically, the upper surface 123 a of the inner region 123 is located lower (closer to the substrate 10) than the upper surface 124 a of the outer region 124.

[0130] This makes it possible to suppress an unnecessary increase in the threshold voltage by thinning the inner region 123 that is in contact with the gate electrode 30. Furthermore, since the outer region 124 is thick, oxidation of the upper surface of the Al-containing layer 20 directly below the outer region 124 can be further suppressed.

[0131] For example, the thickness T of the inner region 123 １ is 0.5 nm or more and less than 3 nm, and is 2 nm as an example. ２ and the thickness T of the inner region 123 １ The difference between the thickness T ２ and thickness T １ By increasing the difference between them, it is possible to suppress an unnecessary increase in the threshold voltage and also suppress oxidation of the upper surface of the Al-containing layer 20 .

[0132] Furthermore, in this embodiment, the hydrogen concentration in the inner region 123 is higher than the p-type impurity concentration in the inner region 123. P-type impurities (p-type dopants) may diffuse from the p-type semiconductor layer 18 into the Al-free layer 122 via the Al-containing layer 20. Because the hydrogen concentration in the inner region 123 is high, the hydrogen can neutralize the charge caused by the p-type impurities. This improves the Schottky characteristics with the gate electrode 30, making it possible to realize a normally-off transistor having a large threshold voltage.

[0133] Next, a method for manufacturing the semiconductor device 100 according to this embodiment will be described.

[0134] The method for manufacturing the semiconductor device 100 includes a first step and a second step for sequentially forming a plurality of nitride semiconductor layers, a third step for forming a source electrode 32 and a drain electrode 34, a fourth step for forming a gate electrode 30, a fifth step for forming an insulating film 40, and a sixth step for etching the Al-free layer 122. In this embodiment, the first step, the second step, the fifth step, the third step, the sixth step, and the fourth step are performed in this order. The first step, the second step, the fifth step, and the third step are the same as those described with reference to FIGS. 2A to 2D . Below, the sixth step and the subsequent steps will be specifically described with reference to FIGS. 5A and 5B . FIGS. 5A and 5B are cross-sectional views for describing the respective steps of the method for manufacturing the semiconductor device 100 according to this embodiment.

[0135] 2A to 2C, after the source electrode 32 and the drain electrode 34 are formed, an opening 41 is formed in the insulating film 40 as shown in Fig. 5A. For example, the opening 41 is formed by removing a portion of the insulating film 40 above the inner region 123 of the Al-free layer 122 by photolithography and dry etching, thereby exposing a portion of the upper surface 122a of the Al-free layer 122.

[0136] 5B , in a sixth step, etching is performed using the insulating film 40 with the openings 41 formed therein as a mask, thereby making the thickness of the inner region 123 thinner than the thickness of the outer region 124. For example, etching is performed until the thickness of the inner region 123 becomes less than 3 nm.

[0137] The etching is dry etching using a gas containing hydrogen gas. The Al-free layer 122 contains undoped GaN as a main component, but a p-type dopant (e.g., Mg) contained in the p-type semiconductor layer 18 may diffuse into the Al-free layer 122 via the Al-containing layer 20. If a p-type dopant is contained in the Al-free layer 122, the Schottky characteristics between the Al-free layer 122 and the gate electrode 30 may be degraded. In contrast, dry etching using a gas containing hydrogen gas allows hydrogen to penetrate into the Al-free layer 122 and neutralize the charge caused by the p-type dopant. This improves the Schottky characteristics between the Al-free layer 122 and the gate electrode 30.

[0138] Dry etching is performed using, for example, an ICP (Inductively Coupled Plasma) dry etching apparatus. As gas raw materials, for example, chlorine gas at 10 sccm to 30 sccm and hydrogen gas at 1 sccm to 10 sccm can be used. As an example, chlorine (Cl ２ ) gas and 2 sccm of hydrogen (H ２ ) gas can be used. The pressure is 0.5 Pa or more and 5 Pa or less, for example, 2 Pa. As for the plasma output, a power of 50 W or more and 200 W or less is supplied to the ICP upper electrode, and a power of 5 W or more and 20 W or less is supplied to the ICP lower electrode. For example, a power of 100 W is supplied to the ICP upper electrode, and a power of 10 W is supplied to the ICP lower electrode.

[0139] The dry etching apparatus may be a CCP (Capacitively Coupled Plasma) dry etching apparatus or an ECR (Electron Cyclotron Resonance) dry etching apparatus. ４ , BCl ３ , CCl ４ Alternatively, a chlorine-based gas (gas containing chlorine atoms) such as NH 4 may be used instead of hydrogen gas. ３ , HCl, HBr, CH ２ F ２ , CHF ３, C.H. ４ , SiH ４ Alternatively, a hydrogen-based gas (gas containing hydrogen atoms) such as chlorine-based gas or hydrogen-based gas may be used. The chlorine-based gas and the hydrogen-based gas may each be a mixed gas of two or more types. Alternatively, an inert gas such as Ar or He may be used.

[0140] After thinning the inner region 123 by etching, the fourth step is to form the gate electrode 30 above the Al-free layer 122. For example, a conductive film is formed over the entire surface by sputtering or vapor deposition, and then the conductive film is patterned into a predetermined shape by photolithography and dry etching to form the gate electrode 30. The patterning may be performed by a lift-off method. As a result, the gate electrode 30 contacts the upper surface 23 a of the inner region 23 through the opening 41.

[0141] 1 can be manufactured through the above steps. The manufacturing method of the semiconductor device 100 is not limited to the above example. The third step of forming the source electrode 32 and the drain electrode 34 may be performed after the fourth step of forming the gate electrode 30.

[0142] Third Embodiment Next, a third embodiment will be described. The following description will focus on the differences from the second embodiment, and the description of the commonalities will be omitted or simplified.

[0143] 6 is a cross-sectional view of a semiconductor device 200 according to the present embodiment. As shown in Fig. 6, the semiconductor device 200 further includes an n-type semiconductor layer 226 compared to the semiconductor device 100 according to the second embodiment.

[0144] The n-type semiconductor layer 226 is an example of an n-type sixth nitride semiconductor layer, and is provided between the upper surface 124a of the outer region 124 of the Al-free layer 122 and the insulating film 40. For example, the n-type semiconductor layer 226 is provided in contact with both the upper surface 124a of the outer region 124 and the lower surface of the insulating film 40.

[0145] The n-type semiconductor layer 226 contains, for example, n-type GaN as a main component. For example, the n-type semiconductor layer 226 contains an n-type dopant such as Si. The concentration of the n-type dopant is 1.0×10 １９ cm －３ That's it, 5.0 x 10 １９ cm －３ For example, 3.0 × 10 １９ cm －３ The n-type semiconductor layer 226 may contain n-type InGaN, InN, AlGaN, AlInGaN, etc. as a main component. The thickness of the n-type semiconductor layer 226 is, for example, 1 nm or more and 10 nm or less, and is, for example, 3 nm.

[0146] The provision of the n-type semiconductor layer 226 makes it possible to neutralize charges resulting from p-type dopants that have diffused from the p-type semiconductor layer 18 into the Al-free layer 122. This makes it possible to improve the Schottky characteristics between the Al-free layer 122 and the gate electrode 30. The improvement in the Schottky characteristics makes it possible to realize a normally-off transistor having a large threshold voltage.

[0147] In this embodiment, the n-type semiconductor layer 226 is not in contact with the inner region 123 of the Al-free layer 122. The boundary between the inner region 123 and the outer region 124 of the Al-free layer 122 is flush with a portion of the side surface of the n-type semiconductor layer 226. The n-type semiconductor layer 226 is provided so as not to overlap (be exposed to) the opening 41 of the insulating film 40 in a plan view of the substrate 10. The gate electrode 30 is in contact with the upper surface 123a of the inner region 123. This suppresses ohmic contact between the gate electrode 30 and the n-type semiconductor layer 226 and improves Schottky characteristics. Therefore, a normally-off transistor having a large threshold voltage can be realized.

[0148] [Manufacturing Method] Next, a manufacturing method of the semiconductor device 200 according to this embodiment will be described.

[0149] The method for manufacturing the semiconductor device 200 includes a first step and a second step for sequentially forming a plurality of nitride semiconductor layers, a third step for forming a source electrode 32 and a drain electrode 34, a fourth step for forming a gate electrode 30, a fifth step for forming an insulating film 40, and a sixth step for etching the Al-free layer 122. In this embodiment, the first step, the second step, the fifth step, the third step, the sixth step, and the fourth step are performed in this order. Each step will be specifically described below with reference to FIGS. 7A to 7E. FIGS. 7A to 7E are cross-sectional views for describing each step of the method for manufacturing the semiconductor device 200 according to this embodiment.

[0150] First, as shown in FIG. 7A , in the first step, the channel layer 14 and the barrier layer 16 are formed in this order. Furthermore, in the second step, the p-type semiconductor layer 18, the Al-containing layer 20, the Al-free layer 122, and the n-type semiconductor layer 226 are formed in this order. In the second step according to this embodiment, crystal growth is performed continuously from the first step to form a nitride semiconductor laminate film. The laminate film is a laminate film including the p-type semiconductor layer 18, the Al-containing layer 20, the Al-free layer 122, and the n-type semiconductor layer 226 before being patterned into a predetermined shape. Specifically, the buffer layer 12, the channel layer 14, the barrier layer 16, the p-type semiconductor layer 18, the Al-containing layer 20, the Al-free layer 122, and the n-type semiconductor layer 226 are formed in this order by epitaxially growing a nitride semiconductor film on the upper surface of the substrate 10. The composition and thickness of each layer can be controlled by adjusting the gas introduced, dopant, growth temperature, growth time, etc. during epitaxial growth.

[0151] 7B , in a second step, the formed stacked film is patterned to form a predetermined shape of the p-type semiconductor layer 18, the Al-containing layer 20, the Al-free layer 122, and the n-type semiconductor layer 226. For example, by photolithography and dry etching, portions of the n-type semiconductor layer 226, the Al-free layer 22, the Al-containing layer 20, and the p-type semiconductor layer 18 located outside the gate region are selectively removed. In the region outside the gate region, the upper surface 16a of the barrier layer 16 is exposed.

[0152] 7C , in a fifth step, an insulating film 40 is formed. For example, the insulating film 40 is formed by depositing a SiN film by plasma CVD so as to cover the upper surface 16 a of the barrier layer 16 and the upper surface 226 a of the n-type semiconductor layer 226. Furthermore, in a third step, the source electrode 32 and the drain electrode 34 are formed so as to sandwich the p-type semiconductor layer 18 therebetween. Specifically, first, openings 42 and 43 are formed in the insulating film 40, and then the source electrode 32 and the drain electrode 34 are formed. The methods for forming the openings 42 and 43 and the source electrode 32 and the drain electrode 34 are the same as those in the first embodiment.

[0153] 7D , an opening 41 is formed in the insulating film 40. For example, the opening 41 is formed by removing a portion of the insulating film 40 above the inner region 123 of the Al-free layer 122 by photolithography and dry etching, thereby exposing a portion of the upper surface 226 a of the n-type semiconductor layer 226.

[0154] 7E, etching is performed using the insulating film 40 with the openings 41 as a mask to remove the portion of the n-type semiconductor layer 226 exposed in the openings 41. Further, etching is performed continuously to make the thickness of the inner region 123 thinner than the thickness of the outer region 124 (sixth step). For example, etching is performed until the thickness of the inner region 123 is less than 3 nm. The etching can be performed in the same manner as the etching for thinning the inner region 123 in the second embodiment.

[0155] After the inner region 123 is thinned by etching, in the fourth step, the gate electrode 30 is formed above the Al-free layer 122. The gate electrode 30 can be formed by the same method as in the first embodiment.

[0156] Through the above steps, the semiconductor device 200 shown in FIG. 6 can be manufactured.

[0157] In the manufacturing method of the semiconductor device 200 according to this embodiment, by successively removing the n-type semiconductor layer 226 and thinning the inner region 123 of the Al-free layer 122, it is possible to make a portion of the side surface of the n-type semiconductor layer 226 (the side surface on the opening 41 side) flush with the interface between the inner region 123 and the outer region 124. This allows for so-called self-alignment, which simplifies the etching process. Furthermore, since the n-type semiconductor layer 226 is less likely to be interposed between the gate electrode 30 and the inner region 123, the Schottky characteristics can be improved. Therefore, a normally-off transistor with a large threshold voltage can be realized.

[0158] The method for manufacturing the semiconductor device 200 is not limited to the above-described example. The third step of forming the source electrode 32 and the drain electrode 34 may be performed after the fourth step of forming the gate electrode 30. Furthermore, the removal of the n-type semiconductor layer 226 and the thinning of the inner region 123 may be performed stepwise in separate steps.

[0159] Furthermore, the semiconductor device 200 according to the present embodiment may include the Al-free layer 22 according to the first embodiment, instead of the Al-free layer 122. That is, the thickness of the Al-free layer 22 may be uniform, and the sixth step may not be performed after etching the n-type semiconductor layer 226.

[0160] (Fourth Embodiment) Next, a description will be given of a fourth embodiment. The following description will focus on the differences from the first embodiment, and the description of the commonalities will be omitted or simplified.

[0161] 8 is a cross-sectional view of a semiconductor device 300 according to this embodiment. As shown in Fig. 8, the semiconductor device 300 further includes a band barrier layer 328 compared to the semiconductor device 1 according to the first embodiment.

[0162] The band barrier layer 328 is an example of a seventh nitride semiconductor layer, and has a band gap larger than that of the Al-containing layer 20. The band barrier layer 328 is provided between the p-type semiconductor layer 18 and the Al-containing layer 20. For example, the band barrier layer 328 is provided in contact with each of the upper surface of the p-type semiconductor layer 18 and the lower surface of the Al-containing layer 20.

[0163] The band barrier layer 328 contains, for example, i-type AlN as a main component, but is not limited to this. The band barrier layer 328 may contain AlGaN, AlInGaN, or the like as a main component.

[0164] The thickness of the band barrier layer 328 is thinner than both the thickness of the p-type semiconductor layer 18 and the thickness of the Al-containing layer 20. For example, the thickness of the band barrier layer 328 is 0.5 nm or more and less than 3 nm, e.g., 2 nm. When AlN is crystal-grown on GaN, the critical thickness of AlN is approximately 3 nm. By setting the thickness of the band barrier layer 328 to be less than the critical thickness, it is possible to suppress the occurrence of crystal defects in the upper layers (the Al-containing layer 20 and the Al-free layer 22). This makes it possible to suppress the deterioration of the Schottky characteristics between the gate electrode 30 and the Al-containing layer 20.

[0165] In the semiconductor device 300 according to this embodiment, the band barrier layer 328 is provided, which can further increase the resistance component between the gate electrode 30 and the 2DEG, thereby reducing the gate leakage current.

[0166] [Manufacturing Method] Next, a manufacturing method of the semiconductor device 300 according to this embodiment will be described.

[0167] The method for manufacturing the semiconductor device 300 includes a first step and a second step for sequentially forming a plurality of nitride semiconductor layers, a third step for forming a source electrode 32 and a drain electrode 34, a fourth step for forming a gate electrode 30, and a fifth step for forming an insulating film 40. In this embodiment, the first step, the second step, the fifth step, the third step, and the fourth step are performed in this order. Each step will be specifically described below with reference to FIGS. 9A to 9D. FIGS. 9A to 9D are cross-sectional views for describing each step of the method for manufacturing the semiconductor device 300 according to this embodiment.

[0168] 9A , in the first step, the channel layer 14 and the barrier layer 16 are formed in this order. Furthermore, in the second step, the p-type semiconductor layer 18, the band barrier layer 328, the Al-containing layer 20, and the Al-free layer 22 are formed in this order. In the second step according to this embodiment, crystal growth is performed continuously from the first step to form a nitride semiconductor laminate film. This laminate film includes the p-type semiconductor layer 18, the band barrier layer 328, the Al-containing layer 20, and the Al-free layer 22 before being patterned into a predetermined shape. Specifically, a nitride semiconductor film is formed on the upper surface of the substrate 10 by epitaxial growth, thereby forming the buffer layer 12, the channel layer 14, the barrier layer 16, the p-type semiconductor layer 18, the band barrier layer 328, the Al-containing layer 20, and the Al-free layer 22 in this order. The composition and thickness of each layer can be controlled by adjusting the gas introduced, dopant, growth temperature, growth time, etc. during epitaxial growth.

[0169] 9B , in a second step, the formed stacked film is patterned to form a p-type semiconductor layer 18, a band barrier layer 328, an Al-containing layer 20, and an Al-free layer 22 each having a predetermined shape. For example, by photolithography and dry etching, portions of the Al-free layer 22, the Al-containing layer 20, the band barrier layer 328, and the p-type semiconductor layer 18 located outside the gate region are selectively removed. In the region outside the gate region, the upper surface 16 a of the barrier layer 16 is exposed.

[0170] 9C , in a fifth step, an insulating film 40 is formed. For example, the insulating film 40 is formed by depositing a SiN film by plasma CVD so as to cover the upper surface 16 a of the barrier layer 16 and the upper surface 22 a of the Al-free layer 22. Furthermore, in a third step, the source electrode 32 and the drain electrode 34 are formed so as to sandwich the p-type semiconductor layer 18 therebetween. Specifically, first, openings 42 and 43 are formed in the insulating film 40, and then the source electrode 32 and the drain electrode 34 are formed. The methods for forming the openings 42 and 43 and the source electrode 32 and the drain electrode 34 are the same as those in the first embodiment.

[0171] 9D , an opening 41 is formed in the insulating film 40. For example, a portion of the insulating film 40 above the inner region 23 of the Al-free layer 22 is removed by photolithography and dry etching to form the opening 41 and expose a portion of the upper surface 22 a of the Al-free layer 22.

[0172] Next, in a fourth step, the gate electrode 30 is formed above the Al-free layer 22. The gate electrode 30 can be formed by the same method as in the first embodiment.

[0173] The semiconductor device 300 shown in FIG. 8 can be manufactured through the above steps. The manufacturing method for the semiconductor device 300 is not limited to the above example. The third step of forming the source electrode 32 and the drain electrode 34 may be performed after the fourth step of forming the gate electrode 30. The semiconductor device 300 according to this embodiment may include the Al-free layer 122 according to the second embodiment instead of the Al-free layer 22. After the opening 41 is formed in the insulating film 40, a sixth step of reducing the thickness of the inner region 123 of the Al-free layer 122 may be performed. The semiconductor device 300 may also include the n-type semiconductor layer 226 according to the third embodiment.

[0174] (Embodiment 5) Next, a description will be given of embodiment 5. The following description will focus on the differences from embodiment 1, and the description of commonalities will be omitted or simplified.

[0175] 10 is a cross-sectional view of a semiconductor device 400 according to the present embodiment. As shown in Fig. 10, the semiconductor device 400 further includes an insulating film 440 compared to the semiconductor device 1 according to the first embodiment.

[0176] The insulating film 440 is an example of a second insulating film, and covers the upper surface 16a of the barrier layer 16. The insulating film 440 is provided between the upper surface 16a of the barrier layer 16 and the insulating film 40. For example, the insulating film 440 is in contact with both the upper surface 16a and the lower surface of the insulating film 40.

[0177] An opening 441 is provided in the insulating film 440. The opening 441 is an opening for forming a gate structure. The length of the opening 441 in the gate length direction is the same as the length of the p-type semiconductor layer 18 in the gate length direction. The insulating film 440 also has openings 442 and 443. The opening 442, like the opening 42 provided in the insulating film 40, is provided to bring the source electrode 32 into contact with the upper surface 16 a of the barrier layer 16. The opening 443, like the opening 43 provided in the insulating film 40, is provided to bring the drain electrode 34 into contact with the upper surface 16 a of the barrier layer 16.

[0178] The insulating film 440 contains, for example, SiN as a main component, and is formed continuously from the crystal growth of the nitride semiconductor.

[0179] [Manufacturing Method] Next, a manufacturing method of the semiconductor device 400 according to this embodiment will be described.

[0180] The method for manufacturing the semiconductor device 400 includes a first step and a second step for sequentially forming a plurality of nitride semiconductor layers, a third step for forming the source electrode 32 and the drain electrode 34, a fourth step for forming the gate electrode 30, a fifth step for forming the insulating film 40, and a seventh step for forming the insulating film 440. In this embodiment, the first step, the seventh step, the second step, the fifth step, the third step, and the fourth step are performed in this order. Each step will be specifically described below with reference to FIGS. 11A to 11F. FIGS. 11A to 11F are cross-sectional views for describing each step of the method for manufacturing the semiconductor device 400 according to this embodiment.

[0181] First, as shown in FIG. 11A , in the first step, the channel layer 14 and the barrier layer 16 are formed in this order. Furthermore, in the seventh step, an insulating film 440 is formed. The insulating film 440 is formed continuously from the formation of the barrier layer 16. That is, the channel layer 14, the barrier layer 16, and the insulating film 440 are formed in this order in the same growth furnace without being exposed to the atmosphere. Specifically, the buffer layer 12, the channel layer 14, the barrier layer 16, and the insulating film 440 are formed in this order on the upper surface of the substrate 10 by epitaxial crystal growth. The composition and thickness of each layer can be controlled by adjusting the introduced gas, dopant, growth temperature, growth time, etc. during the epitaxial growth.

[0182] 11B , an opening 441 is formed in the gate region of the insulating film 440. For example, a portion of the insulating film 440 located in the gate region is removed by photolithography and dry etching to form the opening 441. In the opening 441, the upper surface 16 a of the barrier layer 16 is exposed.

[0183] 11C , in the second step, the p-type semiconductor layer 18, the Al-containing layer 20, and the Al-free layer 22 are formed in this order. In the second step according to this embodiment, selective crystal growth is performed in the opening 441 of the insulating film 440, thereby forming the p-type semiconductor layer 18, the Al-containing layer 20, and the Al-free layer 22 in this order. Note that the composition and thickness of each layer can be controlled by adjusting the gas introduced, the dopant, the growth temperature, the growth time, and the like during the epitaxial growth.

[0184] 11D , in a fifth step, the insulating film 40 is formed. For example, the insulating film 40 is formed by depositing a SiN film by plasma CVD so as to cover the upper surface of the insulating film 440 and the upper surface 22 a of the Al-free layer 22.

[0185] 11E , in a third step, the source electrode 32 and the drain electrode 34 are formed to sandwich the p-type semiconductor layer 18 therebetween. Specifically, first, openings 42 and 43 are formed in the insulating film 40, and openings 442 and 443 are formed in the insulating film 440. For example, by photolithography and dry etching, regions of the insulating films 40 and 440 where the source electrode 32 and the drain electrode 34 will be formed are removed to form the openings 42 and 442, and the openings 43 and 443. Thereafter, for example, a conductive film is formed over the entire surface by sputtering or vapor deposition, and then the conductive film is patterned into a predetermined shape by photolithography and dry etching to form the source electrode 32 and the drain electrode 34. The patterning may be performed by a lift-off method. Alternatively, the source electrode 32 and the drain electrode 34 may be formed in different steps.

[0186] 11F , an opening 41 is formed in the insulating film 40. For example, a portion of the insulating film 40 above the inner region 23 of the Al-free layer 22 is removed by photolithography and dry etching to form the opening 41 and expose a portion of the upper surface 22 a of the Al-free layer 22.

[0187] Next, in a fourth step, the gate electrode 30 is formed above the Al-free layer 22. The gate electrode 30 can be formed by the same method as in the first embodiment.

[0188] Through the above steps, the semiconductor device 400 shown in FIG. 10 can be manufactured. In this embodiment, the barrier layer 16 and the insulating film 440 are formed continuously, so that the upper surface 16 a of the barrier layer 16 is not exposed to the atmosphere. This makes it possible to suppress oxidation of the upper surface 16 a of the barrier layer 16. Since impurity levels are less likely to be formed on the upper surface 16 a of the barrier layer 16, the lateral breakdown voltage can be increased.

[0189] The manufacturing method of the semiconductor device 400 is not limited to the above-described example. The third step of forming the source electrode 32 and the drain electrode 34 may be performed after the fourth step of forming the gate electrode 30. The semiconductor device 400 according to this embodiment may include the Al-free layer 122 according to the second embodiment instead of the Al-free layer 22. After the opening 41 is formed in the insulating film 40, a sixth step of reducing the thickness of the inner region 123 of the Al-free layer 122 may be performed. The semiconductor device 400 may also include the n-type semiconductor layer 226 according to the third embodiment. The semiconductor device 400 may also include the band barrier layer 328 according to the fourth embodiment.

[0190] Next, a modification of the sixth embodiment will be described.

[0191] 12 is a cross-sectional view of a semiconductor device 401 according to this modification. The semiconductor device 401 shown in FIG. 12 differs from the semiconductor device 100 according to the sixth embodiment in that it includes a p-type semiconductor layer 418.

[0192] The p-type semiconductor layer 418 is provided so as to be embedded in the barrier layer 16 at a position overlapping the p-type semiconductor layer 18 in a plan view. An upper surface 418a of the p-type semiconductor layer 418 is flush with an upper surface 16a of the barrier layer 16. For example, the upper surface 418a of the p-type semiconductor layer 418 is in contact with the lower surface of the p-type semiconductor layer 18. In a plan view of the substrate 10, the outline of the p-type semiconductor layer 418 is substantially the same as the outline of the p-type semiconductor layer 18.

[0193] The p-type semiconductor layer 418 has the same base semiconductor as the barrier layer 16 and contains the same type of p-type dopant as the p-type dopant contained in the p-type semiconductor layer 18. Specifically, the p-type semiconductor layer 418 is formed by diffusing the p-type dopant contained in the p-type semiconductor layer 18 into the surface layer portion of the barrier layer 16. The diffusion of the p-type dopant is performed, for example, by heat treatment or annealing treatment during epitaxial growth. As an example, the temperature of the heat treatment or annealing treatment is 900° C. or higher. By adjusting the temperature or treatment time, the diffusion distance of the p-type dopant can be adjusted, and the thickness of the p-type semiconductor layer 418 can be adjusted.

[0194] By providing the p-type semiconductor layer 418, the thickness of the barrier layer 16 is partially reduced. Specifically, the portion of the barrier layer 16 located directly below the gate electrode 30 is thinner than the portions located between the gate and drain and between the gate and source. This maintains a high concentration of 2DEG between the gate and drain and between the gate and source, thereby reducing the on-resistance. On the other hand, by reducing the thickness of the portion located directly below the gate electrode 30, the threshold voltage of the transistor can be adjusted.

[0195] (Embodiment 6) Next, a description will be given of embodiment 6. The following description will focus on the differences from embodiment 2, and the description of commonalities will be omitted or simplified.

[0196] 13 is a cross-sectional view of a semiconductor device 500 according to the present embodiment. As shown in FIG. 13, the semiconductor device 500 includes a gate electrode 530 and a gate wiring 530G instead of the gate electrode 30, as compared with the semiconductor device 100 according to the second embodiment.

[0197] The gate electrode 530 is provided above the Al-free layer 122. Specifically, the gate electrode 530 is provided between the outer region 124 of the Al-free layer 122 and the insulating film 40. For example, the gate electrode 530 is in contact with both the upper surface 124a of the outer region 124 and the lower surface of the insulating film 40. The gate electrode 530 contains a conductive material as a main component. For example, the gate electrode 530 is formed using the same material as the gate electrode 30 according to the first embodiment.

[0198] In this embodiment, the gate electrode 530 is not in contact with the inner region 123 of the Al-free layer 122. The boundary between the inner region 123 and the outer region 124 of the Al-free layer 122 is flush with part of the side surface (the side surface on the opening 41 side) of the gate electrode 530. The gate electrode 530 is provided so as not to overlap (be exposed to) the opening 41 of the insulating film 40 in a plan view of the substrate 10.

[0199] Furthermore, a portion of the side surface of the gate electrode 530 (the side surface on the source electrode 32 side and the drain electrode 34 side) is flush with each side surface (side surface of the gate structure) of the Al-free layer 122, the Al-containing layer 20, and the p-type semiconductor layer 18. For example, the length of the gate electrode 530 in the gate length direction (including the length of the opening 41) is the same as the length of the p-type semiconductor layer 18 in the gate length direction. This allows the effective gate length to be shortened, enabling steep gate operation. Furthermore, the parasitic resistance of the transistor can be reduced, thereby reducing the on-resistance.

[0200] The gate wiring 530G is provided above the Al-free layer 122. Specifically, the gate wiring 530G contacts and covers the upper surface 123a of the inner region 123 of the Al-free layer 122. More specifically, the gate wiring 530G contacts the upper surface 123a of the inner region 123 of the Al-free layer 122 through an opening 41 provided in the insulating film 40. The gate wiring 530G is electrically connected to the gate electrode 530. The gate wiring 530G and the gate electrode 530 may be collectively considered as the gate electrode. The gate wiring 530G may also be a gate pad.

[0201] The gate wiring 530G contains a conductive material as a main component, for example, the gate wiring 530G is formed using the same material as the gate electrode 30 according to the first embodiment.

[0202] [Manufacturing Method] Next, a manufacturing method of the semiconductor device 500 according to this embodiment will be described.

[0203] The method for manufacturing the semiconductor device 500 includes a first step and a second step for sequentially forming a plurality of nitride semiconductor layers, a third step for forming a source electrode 32 and a drain electrode 34, a fourth step for forming a gate electrode 30, a fifth step for forming an insulating film 40, and a sixth step for etching the Al-free layer 122. In this embodiment, the first step, the second step, the fourth step, the fifth step, the third step, and the sixth step are performed in this order. Each step will be specifically described below with reference to FIGS. 14A to 14E. FIGS. 14A to 14E are cross-sectional views for describing each step of the method for manufacturing the semiconductor device 200 according to this embodiment.

[0204] First, as shown in FIG. 14A , in the first step, the channel layer 14 and the barrier layer 16 are formed in this order. Furthermore, in the second step, the p-type semiconductor layer 18, the Al-containing layer 20, and the Al-free layer 122 are formed in this order. Furthermore, in the fourth step, the gate electrode 530 is formed. In the second step according to this embodiment, crystal growth is performed continuously from the first step to form a nitride semiconductor laminate film. The laminate film is a laminate film including the p-type semiconductor layer 18, the Al-containing layer 20, and the Al-free layer 122 before being patterned into a predetermined shape. Specifically, a nitride semiconductor film is formed on the upper surface of the substrate 10 by epitaxial growth, thereby forming the buffer layer 12, the channel layer 14, the barrier layer 16, the p-type semiconductor layer 18, the Al-containing layer 20, and the Al-free layer 122 in this order. The composition and thickness of each layer can be controlled by adjusting the gas introduced, dopant, growth temperature, growth time, etc. during the epitaxial growth. Then, the gate electrode 530 before being patterned into a predetermined shape is formed so as to cover the upper surface of the Al-free layer 122. For example, a conductive film is formed as the gate electrode 530 on the entire surface by sputtering or vapor deposition.

[0205] 14B , in a second step, the formed nitride semiconductor stacked film and the gate electrode 530 are patterned to form the p-type semiconductor layer 18, the Al-containing layer 20, and the Al-free layer 122, each having a predetermined shape, and the gate electrode 530. For example, by photolithography and dry etching, portions of the gate electrode 530, the Al-free layer 122, the Al-containing layer 20, and the p-type semiconductor layer 18 located outside the gate region are selectively removed. In the region outside the gate region, the upper surface 16 a of the barrier layer 16 is exposed.

[0206] 14C , in a fifth step, the insulating film 40 is formed. For example, the insulating film 40 is formed by depositing a SiN film by plasma CVD so as to cover the upper surface 16 a of the barrier layer 16 and the upper surface 530 a of the gate electrode 530.

[0207] 14D , in a third step, the source electrode 32 and the drain electrode 34 are formed to sandwich the p-type semiconductor layer 18. Specifically, first, openings 42 and 43 are formed in the insulating film 40, and then the source electrode 32 and the drain electrode 34 are formed. The methods for forming the openings 42 and 43 and the source electrode 32 and the drain electrode 34 are the same as those in the first embodiment.

[0208] Next, as shown in FIG. 14E , an opening 41 is formed in the insulating film 40. For example, by photolithography and dry etching, a portion of the insulating film 40 above the inner region 123 of the Al-free layer 122 is removed to form the opening 41, thereby exposing a portion of the upper surface 530a of the gate electrode 530. Further, etching is performed using the insulating film 40 with the opening 41 as a mask to remove the portion of the gate electrode 530 exposed in the opening 41. Further, etching is continued to make the thickness of the inner region 123 thinner than the thickness of the outer region 124 (sixth step). For example, etching is performed until the thickness of the inner region 123 is less than 3 nm. The etching can be performed in the same manner as the etching for thinning the inner region 123 in the second embodiment.

[0209] Next, the gate wiring 530G is formed above the Al-free layer 22. For example, a conductive film is formed over the entire surface by sputtering or vapor deposition, and then the conductive film is patterned into a predetermined shape by photolithography and dry etching, thereby forming the gate wiring 530G. The patterning may be performed by a lift-off method. As a result, the gate wiring 530G contacts the upper surface 123a of the inner region 123 through the opening 41. The gate wiring 530G may also be formed by plating.

[0210] 13 can be manufactured through the above steps. In the method for manufacturing the semiconductor device 500 according to this embodiment, the gate electrode 530, the Al-free layer 122, the Al-containing layer 20, and the p-type semiconductor layer 18 can be patterned all at once. This allows the gate length to be shortened, enabling a steep gate operation.

[0211] The manufacturing method of the semiconductor device 500 is not limited to the above-described example. The third step of forming the source electrode 32 and the drain electrode 34 may be performed after the step of forming the gate wiring 530G. The semiconductor device 500 according to this embodiment may include the Al-free layer 22 according to the first embodiment instead of the Al-free layer 122. That is, the sixth step of reducing the thickness of the inner region 123 of the Al-free layer 122 may not be performed. The semiconductor device 500 may also include the n-type semiconductor layer 226 according to the third embodiment. The semiconductor device 500 may also include the band barrier layer 328 according to the fourth embodiment. The semiconductor device 500 may also include the insulating film 440 according to the fifth embodiment.

[0212] While the semiconductor device and its manufacturing method according to one or more aspects have been described above based on the embodiments, the present disclosure is not limited to these embodiments. As long as they do not deviate from the gist of the present disclosure, various modifications that a person skilled in the art can make to the present embodiments and configurations constructed by combining components of different embodiments are also included within the scope of the present disclosure.

[0213] For example, the semiconductor device according to each of the above embodiments may not include the insulating film 40. Furthermore, for example, the method for manufacturing the semiconductor device according to each of the above embodiments may not include the fifth step of forming the insulating film 40.

[0214] Furthermore, for example, in each embodiment, an example has been shown in which the side surfaces of the p-type semiconductor layer 18, the Al-containing layer 20, the Al-free layer 22 or 122, the n-type semiconductor layer 226, and the band barrier layer 328 (each side surface of the gate structure) are flush and perpendicular to the main surface of the substrate 10, but this is not limiting. Each side surface of the gate structure may be inclined obliquely with respect to the main surface of the substrate 10, or may be formed in a stepped pattern.

[0215] Furthermore, for example, in each embodiment, when the conductivity type of the Al-free layer 22 or 122 is i-type, the conductivity type of the Al-containing layer 20 may be p-type. Alternatively, when the conductivity type of the Al-free layer 22 or 122 is i-type, the conductivity type of the Al-containing layer 20 may be n-type. Alternatively, the conductivity type of the Al-free layer 22 or 122 may be p-type. Furthermore, when the conductivity type of the Al-free layer 22 or 122 is p-type, the conductivity type of the Al-containing layer 20 may be i-type, p-type, or n-type. Furthermore, the conductivity type of the Al-free layer 22 or 122 may be n-type. Furthermore, when the conductivity type of the Al-free layer 22 or 122 is n-type, the conductivity type of the Al-containing layer 20 may be i-type, p-type, or n-type. Furthermore, both the Al-free layer 22 or 122 and the Al-containing layer 20 may be undoped.

[0216] Furthermore, various modifications, substitutions, additions, omissions, etc. can be made to each of the above-described embodiments within the scope of the claims or their equivalents.

[0217] The present disclosure can be used, for example, in a power amplifier for high-output or high-frequency applications, a wireless communication base station or terminal device in which the power amplifier is used, or a wireless power supply device that transmits power using microwaves.

[0218] 1, 100, 200, 300, 400, 401, 500 semiconductor device 10 substrate 12 buffer layer 14 channel layer 16 barrier layer 16a, 22a, 23a, 24a, 122a, 123a, 124a, 226a, 418a, 530a upper surface 18, 418 p-type semiconductor layer 20 Al-containing layer 22, 122 Al-free layer 23, 123 inner region 24, 124 outer region 30, 530 gate electrode 32 source electrode 34 drain electrode 40, 440 insulating film 41, 42, 43, 441, 442, 443 opening 226 n-type semiconductor layer 328 band barrier layer 530G gate wiring

Claims

1. A semiconductor device comprising: a first nitride semiconductor layer; a second nitride semiconductor layer provided above the first nitride semiconductor layer and having a larger band gap than the first nitride semiconductor layer; a p-type third nitride semiconductor layer provided above the second nitride semiconductor layer; a source electrode and a drain electrode provided so as to sandwich the third nitride semiconductor layer; an i-type fourth nitride semiconductor layer provided above the third nitride semiconductor layer and having a larger band gap than the third nitride semiconductor layer and containing Al; an i-type fifth nitride semiconductor layer provided above the fourth nitride semiconductor layer and not containing Al; and a gate electrode provided above the fifth nitride semiconductor layer.

2. The semiconductor device according to claim 1, wherein the thickness of at least a portion of said fifth nitride semiconductor layer is less than 3 nm.

3. A semiconductor device comprising: a first nitride semiconductor layer; a second nitride semiconductor layer provided above the first nitride semiconductor layer and having a larger band gap than the first nitride semiconductor layer; a p-type third nitride semiconductor layer provided above the second nitride semiconductor layer; a source electrode and a drain electrode provided so as to sandwich the third nitride semiconductor layer; a fourth nitride semiconductor layer provided above the third nitride semiconductor layer and having a larger band gap than the third nitride semiconductor layer and containing Al; a fifth nitride semiconductor layer provided above the fourth nitride semiconductor layer and not containing Al; and a gate electrode provided above the fifth nitride semiconductor layer, 4. The semiconductor device according to any one of claims 1 to 3, wherein the fifth nitride semiconductor layer includes, in a cross section parallel to both the gate length direction and the thickness direction, an inner region and an outer region located outward of the inner region in the gate length direction, the semiconductor device comprising an insulating film provided between an upper surface of the outer region and the gate electrode, and the gate electrode being in contact with an upper surface of the inner region.

5. The semiconductor device according to claim 4, wherein the thickness of the inner region is thinner than the thickness of the outer region.

6. The semiconductor device according to claim 5, wherein the difference in thickness between the outer region and the inner region is 1 nm or more.

7. The semiconductor device according to any one of claims 4 to 6, wherein the length of said outer region in the gate length direction is 0.1 μm or more.

8. The semiconductor device according to any one of claims 4 to 7, wherein the hydrogen concentration in the inner region is higher than the p-type impurity concentration in the inner region.

9. The semiconductor device according to any one of claims 4 to 8, further comprising an n-type sixth nitride semiconductor layer provided between the upper surface of said outer region and said insulating film.

10. The semiconductor device according to claim 9, wherein the boundary between the inner region and the outer region is flush with a part of a side surface of the sixth nitride semiconductor layer.

11. The semiconductor device according to any one of claims 1 to 10, wherein the third nitride semiconductor layer contains GaN as a main component.

12. The semiconductor device according to any one of claims 1 to 11, wherein the fourth nitride semiconductor layer contains AlGaN as a main component.

13. The semiconductor device according to any one of claims 1 to 12, wherein the fifth nitride semiconductor layer contains GaN as a main component.

14. The semiconductor device according to any one of claims 1 to 13, further comprising a seventh nitride semiconductor layer provided between the third nitride semiconductor layer and the fourth nitride semiconductor layer, the seventh nitride semiconductor layer having a band gap larger than that of the fourth nitride semiconductor layer.

15. The semiconductor device according to claim 14, wherein the seventh nitride semiconductor layer has a thickness of less than 3 nm.

16. The semiconductor device according to any one of claims 1 to 15, further comprising a p-type eighth nitride semiconductor layer provided so as to be embedded in the second nitride semiconductor layer at a position overlapping the third nitride semiconductor layer in a planar view, and an upper surface of the eighth nitride semiconductor layer is flush with an upper surface of the second nitride semiconductor layer.

17. A method for manufacturing a semiconductor device, comprising: a first step of forming, in this order, a first nitride semiconductor layer and a second nitride semiconductor layer having a larger band gap than the first nitride semiconductor layer; a second step of forming, in this order above the second nitride semiconductor layer, a p-type third nitride semiconductor layer, an i-type fourth nitride semiconductor layer having a larger band gap than the third nitride semiconductor layer and containing Al, and an i-type fifth nitride semiconductor layer not containing Al; a third step of forming a source electrode and a drain electrode to sandwich the third nitride semiconductor layer; and a fourth step of forming a gate electrode above the fifth nitride semiconductor layer.

18. A method for manufacturing a semiconductor device, comprising: a first step of forming, in this order, a first nitride semiconductor layer and a second nitride semiconductor layer having a larger band gap than the first nitride semiconductor layer; a second step of forming, in this order above the second nitride semiconductor layer, a p-type third nitride semiconductor layer, a fourth nitride semiconductor layer having a larger band gap than the third nitride semiconductor layer and containing Al, and a fifth nitride semiconductor layer not containing Al; a third step of forming a source electrode and a drain electrode to sandwich the third nitride semiconductor layer therebetween; and a fourth step of forming a gate electrode above the fifth nitride semiconductor layer, wherein at least a portion of the fifth nitride semiconductor layer has a thickness of less than 3 nm.

19. A method for manufacturing a semiconductor device according to claim 17 or 18, wherein the fifth nitride semiconductor layer includes, in a cross section parallel to both the gate length direction and the thickness direction, an inner region and an outer region located outward of the inner region in the gate length direction, and the method for manufacturing a semiconductor device includes a fifth step of forming a first insulating film covering an upper surface of the outer region, and in the fourth step, the gate electrode is formed so as to be in contact with an upper surface of the inner region.

20. The method for manufacturing a semiconductor device according to claim 19, further comprising a sixth step of etching the inner region using the first insulating film as a mask to make the thickness of the inner region thinner than the thickness of the outer region.

21. The method for manufacturing a semiconductor device according to claim 20, wherein the etching is dry etching using a gas containing hydrogen gas.

22. The method for manufacturing a semiconductor device according to claim 20 or 21, wherein in the sixth step, etching is performed until the thickness of the inner region becomes less than 3 nm.

23. A method for manufacturing a semiconductor device according to any one of claims 19 to 22, comprising a seventh step of forming a second insulating film having an opening after the first step and before the second step, wherein in the second step, the third nitride semiconductor layer, the fourth nitride semiconductor layer and the fifth nitride semiconductor layer are formed within the opening.

24. A method for manufacturing a semiconductor device according to any one of claims 17 to 22, wherein in the second step, a laminated film of nitride semiconductors is formed by performing crystal growth continuously from the first step, and the formed laminated film is patterned to form the third nitride semiconductor layer, the fourth nitride semiconductor layer, and the fifth nitride semiconductor layer.

25. The method for manufacturing a semiconductor device according to claim 24, wherein the patterning of the laminated film is performed by etching using the gate electrode as a mask.

26. The method for manufacturing a semiconductor device according to any one of claims 17 to 25, wherein in the second step, an n-type sixth nitride semiconductor layer is formed above the fifth nitride semiconductor layer.

27. A method for manufacturing a semiconductor device according to any one of claims 17 to 26, wherein in the second step, a seventh nitride semiconductor layer having a band gap larger than that of the fourth nitride semiconductor layer is formed between the third nitride semiconductor layer and the fourth nitride semiconductor layer.

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