Integrated circuit for DC-DC converter, DC-DC converter, and control method therefor

Abstract

This integrated circuit (20) for a DC-DC converter comprises: a high-side switching element (14); a low-side switching element (15); a control circuit (10) that controls the high-side switching element (14) and the low-side switching element (15) such that the output voltage of an inductor (L1) is constant; a p-type semiconductor substrate (21) that includes an n-well region (22) and a p-well region (23); and an electric potential control circuit (30). The low-side switching element (15) is a transistor that includes an n-type impurity region provided in the p-well region (23) as a source or a drain. If both the high-side switching element (14) and the low-side switching element (15) are non-conductive, the electric potential control circuit (30) supplies a first electric potential to the n-well region (22), and if one of the high-side switching element (14) and the low-side switching element (15) is conducting, the electric potential control circuit (30) supplies a second electric potential higher than the first electric potential to the n-well region (22).

Description

Integrated circuit for DC-DC converter, DC-DC converter and control method thereof

[0001] The present disclosure relates to an integrated circuit for a DC-DC converter, a DC-DC converter, and a control method thereof.

[0002] Patent Documents 1 and 2 disclose a DC-DC converter and a switching regulator including a transistor formed on a substrate having a triple-well structure.

[0003] JP 2005-203470 A JP 2002-233137 A

[0004] The above-mentioned conventional technology has room for improvement in terms of achieving both suppression of power loss and reduction of noise.

[0005] Therefore, the present disclosure provides an integrated circuit for a DC-DC converter, a DC-DC converter, and a control method thereof that can suppress power loss and reduce noise at the same time.

[0006] an integrated circuit for a DC-DC converter according to one aspect of the present disclosure, the integrated circuit comprising: a high-side switching element connected between a first terminal and a second terminal; a low-side switching element connected between the second terminal and a third terminal to which a potential lower than the potential supplied to the first terminal is supplied; a control circuit that controls the conduction and non-conduction of the high-side switching element and the low-side switching element so that an output voltage of an inductive load connected to the second terminal is constant; a p-type semiconductor substrate including a first n-type region and a p-type region provided within the first n-type region; and a potential control circuit that controls the potential supplied to the first n-type region, the low-side switching element being a transistor including a second n-type region provided within the p-type region as a source or a drain, the potential control circuit supplying a first potential to the first n-type region when both the high-side switching element and the low-side switching element are non-conductive, and supplying a second potential higher than the first potential to the first n-type region when one of the high-side switching element and the low-side switching element is conductive.

[0007] A DC-DC converter according to one aspect of the present disclosure includes an integrated circuit for a DC-DC converter according to the above aspect, an output terminal, the inductive load connected in series between the second terminal and the output terminal, and a capacitive element connected in series between the output terminal and the third terminal.

[0008] a control circuit that controls the conduction and non-conduction of the high-side switching element and the low-side switching element so that an output voltage of an inductive load connected to the second terminal is constant; and a p-type semiconductor substrate that includes a first n-type region and a p-type region provided within the first n-type region, wherein the low-side switching element is a transistor that includes a second n-type region provided within the p-type region as a source or a drain, and the control method of the DC-DC converter includes the steps of: supplying a first potential to the first n-type region when both the high-side switching element and the low-side switching element are non-conductive; and supplying a second potential to the first n-type region when one of the high-side switching element and the low-side switching element is conductive.

[0009] Furthermore, one aspect of the present disclosure can be realized as a program that causes a computer to execute the control method, or as a computer-readable non-transitory recording medium storing the program.

[0010] According to the present disclosure, it is possible to suppress power loss and reduce noise at the same time.

[0011] Fig. 1 is a circuit diagram of a DC-DC converter according to an embodiment. Fig. 2 is a cross-sectional view of an integrated circuit for a DC-DC converter according to an embodiment. Fig. 3 is a diagram showing the configuration of a potential control circuit provided in the DC-DC converter according to an embodiment. Fig. 4 is a timing chart for explaining the operation of the DC-DC converter according to an embodiment. Fig. 5 is a flowchart showing a control method for the DC-DC converter according to an embodiment.

[0012] Hereinafter, the embodiments will be specifically described with reference to the drawings.

[0013] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component placement and connection configurations, steps, and step order shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, among the components in the following embodiments, components not described in the independent claims are described as optional components.

[0014] Furthermore, each figure is a schematic diagram and is not necessarily an exact illustration. Therefore, for example, the scales of the figures do not necessarily match. Furthermore, in each figure, substantially the same components are given the same reference numerals, and redundant explanations are omitted or simplified.

[0015] Furthermore, in this specification, ordinal numbers such as "first" and "second" do not refer to the number or order of components unless otherwise specified, but are used for the purpose of avoiding confusion and distinguishing between components of the same type.

[0016] (Embodiment) [Circuit Configuration] First, the circuit configuration of a DC-DC converter according to an embodiment will be described with reference to Fig. 1. Fig. 1 is a circuit diagram of a DC-DC converter 1 according to this embodiment.

[0017] The DC-DC converter 1 converts a DC input voltage Vcc into a desired DC voltage (output voltage Vo) and outputs it from an external output terminal 19. As shown in Fig. 1, the DC-DC converter 1 includes a DC-DC converter integrated circuit 20, a reference power supply Vr, an inductor L1, a capacitor C1, and the external output terminal 19. The DC-DC converter integrated circuit 20 includes a control circuit 10, a high-side switching element 14, a low-side switching element 15, a power supply line 16, a ground line 17, an output terminal 18, and a potential control circuit 30.

[0018] The control circuit 10 controls the conduction (ON) and non-conduction (OFF) of the high-side switching element 14 and the low-side switching element 15 so that the output voltage Vo of the inductor L1 is constant. Specifically, the control circuit 10 includes a comparator 11, a pulse generating circuit 12, and a timing adjustment circuit 13. The control circuit 10 supplies control voltages V3H and V3L, which are generated based on the pulse signal generated by the pulse generating circuit 12, to the high-side switching element 14 and the low-side switching element 15, respectively.

[0019] The comparator 11 compares the two input voltages and outputs the comparison result. Specifically, the comparator 11 includes an inverting input terminal (-), a non-inverting input terminal (+), and an output terminal. A reference voltage Vref supplied from a reference power supply Vr is input to the inverting input terminal. The output voltage of the inductor L1, i.e., the output voltage Vo of the DC-DC converter 1, is input to the non-inverting input terminal. The output voltage Vo is fed back to the DC-DC converter 1.

[0020] The comparator 11 compares the reference voltage Vref with the output voltage Vo, and outputs an output signal having a voltage (level) V1 that varies based on the comparison result. For example, the voltage V1 of the output signal is high when Vo>Vref, and is low when Vo<Vref.

[0021] The pulse generating circuit 12 generates a pulse voltage based on the comparison result by the comparator 11. Specifically, the pulse generating circuit 12 detects the falling edge of the voltage V1 of the output signal from the comparator 11. The pulse generating circuit 12 outputs a pulse signal having a voltage V2 (pulse voltage) that is maintained at a low level for a certain period TL after the falling edge of the voltage V1.

[0022] The timing adjustment circuit 13 generates control voltages V3H and V3L based on the pulse voltage so that the period during which both the high-side switching element 14 and the low-side switching element 15 are non-conductive (i.e., the simultaneous-off period) is a predetermined period. The simultaneous-off period is set to prevent the high-side switching element 14 and the low-side switching element 15 from simultaneously conducting when they are switched on. If the high-side switching element 14 and the low-side switching element 15 were to simultaneously turn on, a through current would flow from the power supply line 16 to the ground line 17, which could increase power loss and damage the switching elements. Note that if the simultaneous-off period is too long, power loss would increase due to the nature of the DC-DC converter 1. For this reason, the simultaneous-off period is designed to be sufficiently shorter than the period TL.

[0023] The high-side switching element 14 is connected between the power supply line 16 and the output terminal 18. The high-side switching element 14 is a p-type MOS (Metal Oxide Semiconductor) transistor. The source of the high-side switching element 14 is connected to the power supply line 16, and the drain is connected to the output terminal 18. The gate, which is the control terminal of the high-side switching element 14, is connected to the control circuit 10 (specifically, the timing adjustment circuit 13), and a control signal having a control voltage V3H is input thereto. The high-side switching element 14 is conductive (ON) when the control voltage V3H is at a low level, and is non-conductive (OFF) when the control voltage V3H is at a high level.

[0024] The low-side switching element 15 is connected between the ground line 17 and the output terminal 18. The low-side switching element 15 is an n-type MOS transistor. The source of the low-side switching element 15 is connected to the ground line 17, and the drain is connected to the output terminal 18. The gate, which is the control terminal of the low-side switching element 15, is connected to the control circuit 10 (specifically, the timing adjustment circuit 13), and a control signal having a control voltage V3L is input thereto. The low-side switching element 15 is conductive (ON) when the control voltage V3L is at a high level, and is non-conductive (OFF) when the control voltage V3L is at a low level.

[0025] The high-side switching element 14 and the low-side switching element 15 form a so-called CMOS inverter. The high-side switching element 14 and the low-side switching element 15 alternately switch between conductive and non-conductive states. The timing adjustment circuit 13 adjusts the switching timing so that the high-side switching element 14 and the low-side switching element 15 are not turned on at the same time. This prevents the power supply line 16 and the ground line 17 from becoming conductive and resulting in increased power loss.

[0026] The power supply line 16 is an example of a first terminal to which a DC input voltage Vcc is supplied. The ground line 17 is an example of a second terminal to which a potential lower than the potential supplied to the power supply line 16 is supplied. Specifically, the ground line 17 is supplied with a ground potential, i.e., 0 V. The output terminal 18 is an example of a third terminal to which the CMOS inverter outputs power.

[0027] The reference power supply Vr is a voltage source that generates a reference voltage Vref.

[0028] The inductor L1 is an example of an inductive load connected in series between the output terminal 18 and the external output terminal 19. The inductor L1 is a discrete component such as a chip inductor, and is provided separately from the DC-DC converter integrated circuit 20, but is not limited to this. The inductor L1 may also be an inductor formed using wiring within the DC-DC converter integrated circuit 20.

[0029] The capacitor C1 is an example of a capacitance element connected in series between the output terminal 18 and the ground line. The capacitor C1 is a discrete component such as a chip capacitor, and is provided separately from the DC-DC converter integrated circuit 20, but is not limited to this. The capacitor C1 may be a capacitor formed using wiring within the DC-DC converter integrated circuit 20. Alternatively, the capacitor C1 may be a capacitor formed using a diffusion element within the DC-DC converter integrated circuit 20.

[0030] In the DC-DC converter 1 according to this embodiment, the comparator 11, pulse generating circuit 12, and timing adjustment circuit 13 included in the control circuit 10 are each configured by a combination of circuit elements such as transistors, diodes, capacitors, and resistors. These circuit elements, as well as the high-side switching element 14 and low-side switching element 15, are formed within a DC-DC converter integrated circuit 20. The configuration of the main parts of the DC-DC converter integrated circuit 20 will be described below with reference to FIG. 2.

[0031] [Cross-sectional configuration] Fig. 2 is a cross-sectional view of the DC-DC converter integrated circuit 20 according to this embodiment. Specifically, Fig. 2 schematically shows a portion of the DC-DC converter integrated circuit 20 where the low-side switching element 15 and another transistor 25 are formed.

[0032] The low-side switching element 15 is an n-type MOS transistor including a gate electrode 15g, a gate insulating film 15i, an n-type drain region 15d, and an n-type source region 15s.

[0033] The other transistor 25 is an n-type MOS transistor including a gate electrode 25 g, a gate insulating film 25 i, an n-type drain region 25 d, and an n-type source region 25 s. The other transistor 25 is a transistor other than the low-side switching element 15. For example, the other transistor 25 is a transistor included in a component other than the low-side switching element 15 among the components included in the DC-DC converter 1. Specifically, the other transistor 25 is a transistor included in the comparator 11, the pulse generating circuit 12, or the timing adjustment circuit 13.

[0034] Alternatively, the other transistor 25 may be a transistor included in a logic circuit provided in the periphery of a component other than the DC-DC converter 1. In other words, the other transistor 25 does not have to be a component included in the DC-DC converter 1, and the DC-DC converter integrated circuit 20 may integrate components other than the DC-DC converter 1. In this case, Figure 2 shows not only a cross section of the DC-DC converter 1, but also cross sections of other peripheral elements.

[0035] 2, the DC-DC converter integrated circuit 20 includes a p-type semiconductor substrate 21. The p-type semiconductor substrate 21 is, for example, a p-type Si (silicon) substrate. The p-type semiconductor substrate 21 may be an SOI (silicon on insulator) substrate having a p-type Si layer. The p-type semiconductor substrate 21 may also be a GaAs substrate or the like.

[0036] 2, the p-type semiconductor substrate 21 has a triple-well structure. Specifically, as shown in FIG. 2, the p-type semiconductor substrate 21 includes an n-well region 22, a p-well region 23, an n-type drain region 15d, and an n-type source region 15s.

[0037] The n-well region 22 is an example of a first n-type region, and is formed by implanting n-type impurities such as P (phosphorus). The n-well region 22 is also called a deep n-well region. The n-type impurities are implanted by, for example, ion implantation, but the method for forming the n-well region 22 is not particularly limited.

[0038] The p-well region 23 is an example of a p-type region, and is provided within the n-well region 22. The p-well region 23 is separated from a main portion of the p-type semiconductor substrate 21 by the n-well region 22. The main portion is a portion of the p-type semiconductor substrate 21 that is not surrounded by the n-well region 22 and is a portion different from the p-well region 23. The p-well region 23 is located closer to the upper surface (front surface) of the p-type semiconductor substrate 21 than the n-well region 22.

[0039] 2, "upward" refers to the direction in which gate electrodes 15g and 25g are disposed relative to p-type semiconductor substrate 21. The upper surface of p-type semiconductor substrate 21 is the surface on which contact regions 21p, 22n, and 23p, drain regions 15d and 25d, and source regions 15s and 25s are provided. The upper surface is also called the front surface.

[0040] The low-side switching element 15 is formed using a triple-well structure of a p-type semiconductor substrate 21. Specifically, the low-side switching element 15 includes an n-type region provided in a p-well region 23 as a source or drain. More specifically, the drain region 15d and the source region 15s of the low-side switching element 15 are each an example of a second n-type region and are provided in the p-well region 23. The drain region 15d and the source region 15s are each formed by implanting n-type impurities such as P (phosphorus) into predetermined regions in the surface layer of the p-well region 23. The implantation of the n-type impurities is performed by, for example, ion implantation, but the method for forming the drain region 15d and the source region 15s is not particularly limited.

[0041] The other transistor 25 is formed by utilizing the twin-well structure of the p-type semiconductor substrate 21. Specifically, the other transistor 25 includes an n-type region provided in the main portion of the p-type semiconductor substrate 21 as a source or drain. A drain region 25d and a source region 25s of the other transistor 25 are each provided in the main portion of the p-type semiconductor substrate 21. The drain region 25d and the source region 25s are each formed by implanting n-type impurities such as P (phosphorus) into predetermined regions in the surface layer portion of the p-type semiconductor substrate 21. The implantation of the n-type impurities is performed by, for example, ion implantation, but the method of forming the drain region 25d and the source region 25s is not particularly limited.

[0042] The contact region 21p is a p-type region for supplying a predetermined potential to the p-type semiconductor substrate 21. The ground line 17 is connected to the contact region 21p, and a ground potential (0 V) is supplied to the contact region 21p. For example, the contact region 21p has a higher p-type impurity concentration than the main portion of the p-type semiconductor substrate 21. This allows the contact resistance with the ground line 17 to be reduced.

[0043] The contact region 23p is a p-type region for supplying a predetermined potential to the p-well region 23. The ground line 17 is connected to the contact region 23p, and a ground potential (0 V) is supplied to the contact region 23p. For example, the contact region 23p has a higher p-type impurity concentration than the p-well region 23. This allows the contact resistance with the ground line 17 to be reduced.

[0044] The contact region 22n is an n-type region for supplying a predetermined potential V10 to the n-well region 22. The potential control circuit 30 shown in FIG. 1 is connected to the contact region 22n, and the potential V10 is supplied to the contact region 22n. For example, the contact region 22n has a higher n-type impurity concentration than the n-well region 22. This allows the contact resistance with the potential control circuit 30 to be reduced.

[0045] The contact regions 21p, 22n, and 23p are formed by adding p-type impurities or n-type impurities by ion implantation, etc. The contact regions 21p, 22n, and 23p do not necessarily have to be provided.

[0046] In the DC-DC converter integrated circuit 20 according to this embodiment, the potential V10 supplied to the n-well region 22 is changed by a potential control circuit 30. The potential control circuit 30 is a circuit that controls the potential V10 supplied to the n-well region 22. Specifically, when both the high-side switching element 14 and the low-side switching element 15 are non-conductive, the potential control circuit 30 supplies a first potential to the n-well region 22. The first potential is, for example, a potential supplied to the ground line 17, specifically, a ground potential (0 V). Furthermore, when one of the high-side switching element 14 and the low-side switching element 15 is conductive, the potential control circuit 30 supplies a second potential higher than the first potential to the n-well region 22. The second potential is, for example, a potential supplied to the power supply line 16, specifically, a DC input voltage Vcc.

[0047] 3 is a diagram showing the configuration of the potential control circuit 30 provided in the DC-DC converter 1 according to this embodiment. As shown in FIG. 3, the potential control circuit 30 includes an XOR circuit 31 and a selector 32.

[0048] The XOR circuit 31 is a circuit that outputs the exclusive OR of two inputs. Control voltages V3H and V3L are supplied to the XOR circuit 31. The XOR circuit 31 outputs a control signal, the signal level of which changes depending on the combination of the voltage levels of the control voltages V3H and V3L, to the selector 32. The control signal can take two signal levels: high level (1) and low level (0).

[0049] The selector 32 selects and outputs one of two inputs based on a control signal supplied from the XOR circuit 31. The output terminal of the selector 32 is connected to the contact region 22n of the n-well region 22 shown in FIG. 2. The potential supplied to the power supply line 16, specifically, the DC input voltage Vcc, is input to the first input terminal (0) of the selector 32. The potential supplied to the ground line 17, specifically, 0V, is input to the second input terminal (1) of the selector 32. When the control signal from the XOR circuit 31 is low level (0), the selector 32 outputs the DC input voltage Vcc, and the DC input voltage Vcc is applied to the n-well region 22 via the contact region 22n as the potential V10. When the control signal from the XOR circuit 31 is high level (1), the selector 32 outputs 0V, and 0V (ground potential) is applied to the n-well region 22 via the contact region 22n as the potential V10.

[0050] The following Table 1 summarizes the operation of the potential control circuit 30.

[0051]

[0052] The circuit configuration of the potential control circuit 30 shown in FIG. 3 is merely an example. Any circuit configuration may be used as long as it can supply 0 V (first potential) during the simultaneous-off period and Vcc (second potential) during periods other than the simultaneous-off period. Furthermore, the potential control circuit 30 may be capable of supplying potentials other than 0 V and Vcc as the first and second potentials. For example, the potential control circuit 30 may be capable of supplying a potential greater than 0 V generated based on the DC input voltage Vcc to the n-well region 22 as the first or second potential. The potential control circuit 30 may also generate a potential other than 0 V or Vcc and supply it to the n-well region 22.

[0053] [Operation] Next, the operation of the DC-DC converter 1 will be described with reference to Fig. 4. Fig. 4 is a timing chart for explaining the operation of the DC-DC converter 1 according to this embodiment.

[0054] Vo, V1, V2, V3H, V3L, and V4 shown in Figure 4 respectively represent fluctuations in potential (voltage) at various points on the circuit shown in Figure 1. Specifically, Vo represents the output voltage of inductor L1, i.e., the fluctuations in the voltage at external output terminal 19. V1 represents the fluctuations in the voltage level of the output signal from comparator 11. V2 represents the fluctuations in the voltage level (pulse voltage) of the pulse signal from pulse generating circuit 12. V3H represents the fluctuations in the control voltage input to the control terminal (gate electrode) of high-side switching element 14. V3L represents the fluctuations in the control voltage input to the control terminal (gate electrode 15g) of low-side switching element 15. V4 represents the fluctuations in the voltage at output terminal 18 (input voltage to inductor L1).

[0055] IL represents the current flowing through the inductor L1. The magnitude of the current flowing in the direction from the output terminal 18 to the external output terminal 19 is represented by a positive value, and the magnitude of the current flowing in the opposite direction is represented by a negative value. The DC-DC converter 1 according to this embodiment operates so that the magnitude of the current IL is maintained at or above 0. The DC-DC converter 1 also operates so that the output voltage Vo is constant. Specifically, the output voltage Vo is fed back to the comparator 11.

[0056] The voltage V1 of the output signal from the comparator 11 varies depending on the comparison result between the output voltage Vo and the reference voltage Vref. As shown in Figure 4, at time t1, the voltage changes from Vo > Vref to Vo < Vref, and the voltage V1 changes from high to low. From time t1 to time t3, Vo < Vref is maintained, and the voltage V1 is also maintained at low. At time t3, Vo > Vref, and the voltage V1 changes from low to high, and is maintained at high until Vo < Vref again.

[0057] Voltage V2 of the pulse signal from pulse generating circuit 12 is maintained at a low level for a certain period TL after voltage V1 falls. For example, as shown in Figure 4, voltage V2 switches from a high level to a low level at time t1, remains at a low level for period TL, and then switches to a high level at time t4 (= t1 + TL). After time t4, voltage V2 is maintained at a high level until time t6 when voltage V1 falls again.

[0058] The control voltages V3H and V3L are controlled by the timing adjustment circuit 13 based on the voltage V2. For example, at time t1 when the voltage V2 switches from high to low, the control voltage V3L switches from high to low. As a result, the low-side switching element 15 switches from conductive (ON) to non-conductive (OFF) at time t1.

[0059] In contrast, control voltage V3H does not change at time t1, but switches from high to low at time t2 after the lapse of period Td1. As a result, high-side switching element 14 switches from non-conductive (off) to conductive (on) at time t2. That is, during period Td1, a period in which high-side switching element 14 and low-side switching element 15 are simultaneously non-conductive, i.e., a simultaneous off period, is provided.

[0060] Thereafter, at time t4 when voltage V2 switches from low to high, control voltage V3H switches from low to high, causing high-side switching element 14 to switch from conductive (ON) to non-conductive (OFF) at time t4.

[0061] In contrast, control voltage V3L does not change at time t4, but switches from low to high at time t5 after the lapse of period Td2. As a result, low-side switching element 15 switches from non-conductive (off) to conductive (on) at time t5. That is, during period Td2, a period is provided in which low-side switching element 15 and high-side switching element 14 are simultaneously non-conductive, i.e., a simultaneous off period is provided.

[0062] 4 shows an example in which the period Td1 is longer than the period Td2, but this is not limiting. The period Td1 may be the same length as the period Td2, or may be shorter than the period Td2. By providing a simultaneous off period, it is possible to suppress a through current from flowing between the power supply line 16 and the ground line 17.

[0063] The voltage V4 at the output terminal 18 and the output voltage Vo vary depending on the conduction and non-conduction of the high-side switching element 14 and the low-side switching element 15. Specifically, as shown in Fig. 4, immediately before time t1, the high-side switching element 14 is non-conductive and the low-side switching element 15 is conductive, so that the output terminal 18 is short-circuited to the ground line 17. Therefore, immediately before time t1, the voltage V4 is 0 V.

[0064] During the period from time t1 to time t2, both the high-side switching element 14 and the low-side switching element 15 are non-conductive. In the DC-DC converter 1 according to this embodiment, in order to maintain the current IL flowing through the inductor L1 at a positive value, the voltage V4 at the output terminal 18 becomes a negative value (e.g., −0.7 V) that is lower than the ground potential (0 V) of the ground line 17 by the forward voltage of the parasitic diode D2, and the current IL flows from the ground line 17 to the output terminal 18. Note that, as shown in FIG. 2 , a parasitic pn diode D2 is formed between the ground line 17 and the output terminal 18, extending from the contact region 23 p to the drain region 15 d, and a current flows from the ground line 17 to the output terminal 18 via this parasitic pn diode D2. Because the current IL decreases from time t1 to time t2, the voltage V4 increases.

[0065] At time t2, the high-side switching element 14 switches from non-conducting to conducting, causing the output terminal 18 to be short-circuited to the power supply line 16. Therefore, at time t2, the voltage V4 becomes the DC input voltage Vcc supplied to the power supply line 16. The output voltage Vo becomes a voltage in which fluctuations in the voltage V4 have been smoothed by the inductor L1 and the capacitor C1. Specifically, at time t2, the voltage V4 rises to the DC input voltage Vcc, causing the output voltage Vo to change from decreasing to increasing. From time t2 to time t4, the output voltage Vo rises at a constant rate.

[0066] At time t4, the high-side switching element 14 switches from conductive to non-conductive, and the period until time t5 becomes a simultaneous off period. As a result, the voltage V4 at the output terminal 18 becomes a negative value (e.g., −0.7 V), just as it did during the period from time t1 to time t2, and a current IL flows from the ground line 17 to the inductor L1 via the output terminal 18. At time t5, the low-side switching element 15 switches from non-conductive to conductive, and the output terminal 18 is short-circuited to the ground line 17. As a result, after time t5, the voltage V4 becomes the ground potential (0 V) supplied to the ground line 17. The output voltage Vo changes from increasing to decreasing at time t4, decreasing at a constant rate.

[0067] At time t6, the output voltage Vo falls below the reference voltage Vref. That is, the state at time t6 is the same as that at time t1. Thereafter, the same processing as that performed during the period from time t1 to time t6 is repeated, and the DC-DC converter 1 operates so as to maintain the output voltage Vo constant.

[0068] [Operational Effects] Next, operational effects of the DC-DC converter integrated circuit 20 will be described in comparison with the prior art.

[0069] In the DC-DC converter integrated circuit 20, an n-type region and a p-type region are included in the p-type semiconductor substrate 21, and therefore, parasitic diodes and parasitic transistors are formed due to the p-n junctions. Specifically, as shown in FIG. 2, parasitic diodes D0, D1, and D2, and parasitic transistors Q10 and Q99 are formed.

[0070] The parasitic diode D0 is a pn diode formed by the p-well region 23 and the n-well region 22. The parasitic diode D1 is a pn diode formed by (a main portion of) the p-type semiconductor substrate 21 and the n-well region 22. The parasitic diode D2 is a pn diode formed by the p-well region 23 (p-type contact region 23p) and the n-type drain region 15d. The parasitic transistor Q10 is a parasitic bipolar transistor having an npn structure with the n-type drain region 15d, the p-well region 23, and the n-well region 22 (n-type contact region 22n). The parasitic transistor Q99 is a parasitic bipolar transistor having an npn structure with the n-type source region 25s (or the n-type drain region 25d), the p-type semiconductor substrate 21, and the n-well region 22 (n-type contact region 22n).

[0071] Parasitic diodes and parasitic transistors can be factors that cause malfunction of the DC-DC converter 1. If the n-well region 22 is not provided, the number of parasitic diodes and parasitic transistors can be reduced. For example, parasitic diodes D0 and D1 are not generated. Furthermore, the parasitic transistor Q10 is not generated. Instead, the parasitic transistor Q99 is formed by utilizing the drain region 15d instead of the n-well region 22. That is, the parasitic transistor Q99 is formed by the n-type drain region 15d, the p-type semiconductor substrate 21, and the n-type source region 25s (or the n-type drain region 25d). As a result, the following problems arise.

[0072] If the n-well region 22 were not provided and the low-side switching element 15 were provided in the p-type semiconductor substrate 21 like the other transistors 25, the low-side switching element 15 would be more susceptible to the effects of noise generated in the p-type semiconductor substrate 21. In particular, when the low-side switching element 15 is conductive, noise components in the p-type semiconductor substrate 21 are generated in the drain region 15d (output terminal 18), causing noise to be generated in the voltage V4 of the output terminal 18.

[0073] Furthermore, the parasitic transistor Q99 including the drain region 15d may cause the other transistor 25 to malfunction. Specifically, during the simultaneous off period, as shown in FIG. 4, the voltage V4 becomes negative, and a current flows from the ground line 17 to the drain region 15d via the parasitic diode D2. At this time, because the parasitic transistor Q99 includes the drain region 15d, a current may flow from the other transistor 25 to the drain region 15d via the parasitic transistor Q99. The current flowing through the other transistor 25 may cause the other transistor 25 to malfunction.

[0074] As described above, if the n-well region 22 is not provided, two problems will occur: (a) noise will be generated in the voltage V4 of the output terminal 18, and (b) malfunction of the other transistor 25. The n-well region 22 is provided to solve these two problems.

[0075] By providing the n-well region 22, the low-side switching element 15 is separated from the main portion of the p-type semiconductor substrate 21. Specifically, as shown in FIG. 2, by providing the n-well region 22, parasitic diodes D0 and D1 are connected in series in the opposite directions between the drain region 15d and the p-type semiconductor substrate 21. Therefore, noise (unwanted charge) generated in the p-type semiconductor substrate 21 is less likely to flow into the p-well region 23. Therefore, noise generated in the p-type semiconductor substrate 21 is less likely to affect the voltage V4 via the drain region 15d.

[0076] Furthermore, the provision of the n-well region 22 creates a parasitic transistor Q10. During the simultaneous off period, a current may flow to the drain region 15d via the parasitic transistor Q10, but the parasitic transistor Q10 is not directly connected to the other transistor 25. Therefore, even if a current flows via the parasitic transistor Q10, the possibility of causing the other transistor 25 to malfunction is sufficiently low.

[0077] However, simply providing the n-well region 22 poses a problem of high power loss in the DC-DC converter 1. For example, to suppress the noise (a) described above, it is desirable to supply a high potential V10 to the n-well region 22. This is because a high potential V10 allows a large reverse voltage to be applied to each of the parasitic diodes D0 and D1, thereby reducing their respective junction capacitances. However, if the voltage V4 becomes negative during the simultaneous off period, a high potential V10 causes current to flow from the contact region 22n, which has a higher potential than the contact region 23p, to the drain region 15d via the transistor Q10, resulting in high power loss. To reduce power loss, it is necessary to lower the potential V10, but lowering the potential V10 does not sufficiently suppress noise.

[0078] Thus, there is a problem that simply providing the n-well region 22 does not achieve both suppression of power loss and reduction of noise.

[0079] In contrast to this, the DC-DC converter integrated circuit 20 according to this embodiment is provided with a potential control circuit 30 that controls the potential V10. Specifically, the potential control circuit 30 changes the potential V10 in accordance with the states of the high-side switching element 14 and the low-side switching element 15, as shown in FIG.

[0080] FIG. 5 is a flowchart showing a control method for the DC-DC converter 1 according to this embodiment. The control method shown in FIG. 5 is mainly performed by the potential control circuit 30. Specifically, the potential control circuit 30 determines the states of the high-side switching element 14 and the low-side switching element 15 (S10). If both the high-side switching element 14 and the low-side switching element 15 are non-conductive ("simultaneous OFF" in S10), the potential control circuit 30 supplies a first potential to the n-well region 22 (S12). Here, the first potential is the potential supplied to the source of the low-side switching element 15, specifically, ground potential (0 V). If one of the high-side switching element 14 and the low-side switching element 15 is conductive ("one is ON" in S10), the potential control circuit 30 supplies a second potential higher than the first potential to the n-well region 22 (S12). Here, the second potential is the potential supplied to the source of the high-side switching element 14, specifically, the DC input voltage Vcc. Thereafter, the process returns to step S10 and the above processing is repeated while the DC-DC converter 1 is in operation.

[0081] In this manner, during the simultaneous off period, a low first potential is supplied to the n-well region 22, thereby suppressing power loss due to the current flowing through the parasitic transistor Q10. There are two paths for the current flowing to the drain region 15d, namely, the parasitic diode D2 and the parasitic transistor Q10, which may further reduce power loss.

[0082] Furthermore, a high second potential is supplied to the n-well region 22 outside the simultaneous-off period, thereby reducing the junction capacitance of the parasitic diodes D0 and D1 and reducing noise. By setting the second potential to the DC input voltage Vcc, the highest potential input to the DC-DC converter 1 can be utilized, thereby enhancing the noise reduction effect. Furthermore, since a dedicated circuit for generating the second potential is not required, this contributes to simplifying and miniaturizing the circuit configuration. Furthermore, since the parasitic transistor Q10 does not conduct outside the simultaneous-off period, there is virtually no impact of power loss due to the parasitic transistor Q10.

[0083] During the simultaneous off period, the first potential is low, so noise may affect voltage V4. However, because the simultaneous off period is sufficiently shorter than the on period, the effect is suppressed. The effect of noise on voltage V4 is attenuated by a low-pass filter formed by inductor L1 and capacitor C1. However, because the period of 0 V is shorter than when potential V10 is always fixed at 0 V, the attenuation effect of the low-pass filter can be more effectively achieved.

[0084] [Summary] The following describes the features of the present disclosure described based on the above embodiment.

[0085] a p-type semiconductor substrate including a first n-type region and a p-type region provided within the first n-type region; and a potential control circuit that controls the potential supplied to the first n-type region, wherein the low-side switching element is a transistor including a second n-type region provided within the p-type region as a source or a drain, and the potential control circuit supplies a first potential to the first n-type region when both the high-side switching element and the low-side switching element are non-conductive, and supplies a second potential higher than the first potential to the first n-type region when one of the high-side switching element and the low-side switching element is conductive.

[0086] This makes it possible to suppress power loss and reduce noise at the same time.

[0087] A DC-DC converter integrated circuit according to a second aspect of the present disclosure is the DC-DC converter integrated circuit according to the first aspect, wherein the first potential is a potential supplied to the third terminal.

[0088] This can enhance the effect of suppressing power loss.

[0089] A third aspect of the present disclosure provides an integrated circuit for a DC-DC converter according to the first or second aspect, wherein the second potential is a potential supplied to the first terminal.

[0090] This can enhance the noise reduction effect.

[0091] An integrated circuit for a DC-DC converter according to a fourth aspect of the present disclosure is the integrated circuit for a DC-DC converter according to any one of the first to third aspects, wherein the control circuit includes a comparator that compares the output voltage of the inductive load with a reference voltage, and a pulse generation circuit that generates a pulse voltage based on the comparison result by the comparator, and supplies a first control voltage and a second control voltage based on the pulse voltage to the high-side switching element and the low-side switching element, respectively.

[0092] This allows the output voltage feedback system to be realized with a simple circuit configuration, which prevents the circuit from becoming too complicated and contributes to the miniaturization of integrated circuits for DC-DC converters.

[0093] An integrated circuit for a DC-DC converter according to a fifth aspect of the present disclosure is the integrated circuit for a DC-DC converter according to the fourth aspect, wherein the control circuit further includes a timing adjustment circuit that generates the first control voltage and the second control voltage based on the pulse voltage so that the period during which both the high-side switching element and the low-side switching element are non-conductive is a predetermined period.

[0094] This makes it possible to set a simultaneous off period of a desired length, thereby suppressing the occurrence of through current and reducing power loss.

[0095] An integrated circuit for a DC-DC converter according to a sixth aspect of the present disclosure is the integrated circuit for a DC-DC converter according to the fourth aspect, wherein the potential control circuit switches between the first potential and the second potential based on the first control voltage and the second control voltage.

[0096] This makes it possible to realize potential switching with a simple circuit configuration, which prevents the circuit from becoming too complicated and contributes to the miniaturization of integrated circuits for DC-DC converters.

[0097] A DC-DC converter according to a seventh aspect of the present disclosure includes an integrated circuit for a DC-DC converter according to any one of the first to sixth aspects, an output terminal, the inductive load connected in series between the second terminal and the output terminal, and a capacitive element connected in series between the output terminal and the third terminal.

[0098] This makes it possible to suppress power loss and reduce noise at the same time.

[0099] a control circuit that controls the conduction and non-conduction of the high-side switching element and the low-side switching element so that an output voltage of an inductive load connected to the second terminal is constant; and a p-type semiconductor substrate that includes a first n-type region and a p-type region provided within the first n-type region, wherein the low-side switching element is a transistor that includes a second n-type region provided within the p-type region as a source or a drain, and the control method of the DC-DC converter includes the steps of: supplying a first potential to the first n-type region when both the high-side switching element and the low-side switching element are non-conductive; and supplying a second potential higher than the first potential to the first n-type region when one of the high-side switching element and the low-side switching element is conductive.

[0100] This makes it possible to suppress power loss and reduce noise at the same time.

[0101] (Other Embodiments) While the integrated circuit for a DC-DC converter, the DC-DC converter, and the control method thereof according to one or more aspects have been described above based on the embodiments, the present disclosure is not limited to these embodiments. As long as they do not deviate from the gist of the present disclosure, various modifications that would occur to a person skilled in the art to the present embodiments and forms constructed by combining the components of different embodiments are also included within the scope of the present disclosure.

[0102] For example, the high-side switching element 14 may be an n-type MOS transistor, the same as the low-side switching element 15. The timing of conduction and non-conduction can be controlled by adjusting the control voltage input to each switching element. Furthermore, the high-side switching element 14 and the low-side switching element 15 may be field-effect transistors other than MOS transistors.

[0103] Furthermore, for example, some of the circuit elements that make up the control circuit 10 may be configured separately from the DC-DC converter integrated circuit 20 .

[0104] Furthermore, for example, although an example has been shown in which the potential control circuit 30 is configured with a dedicated circuit, the function of the potential control circuit 30 may be realized by executing a software program.

[0105] Furthermore, the general or specific aspects of the present disclosure may be realized as a system, an apparatus, a method, an integrated circuit, or a computer program. Alternatively, the general or specific aspects may be realized as a computer-readable non-transitory recording medium such as an optical disk, a HDD, or a semiconductor memory on which the computer program is stored. Alternatively, the general or specific aspects of the present disclosure may be realized as any combination of a system, an apparatus, a method, an integrated circuit, a computer program, and a recording medium.

[0106] Furthermore, various modifications, substitutions, additions, omissions, etc. can be made to the above-described embodiments within the scope of the claims or their equivalents.

[0107] The present disclosure can be used in DC-DC converters, power supply circuits including DC-DC converters, and electrical appliances.

[0108] 1 DC-DC converter 10 Control circuit 11 Comparator 12 Pulse generation circuit 13 Timing adjustment circuit 14 High-side switching element 15 Low-side switching element 15g, 25g Gate electrode 15i, 25i Gate insulating film 15s, 25s Source region 15d, 25d Drain region 16 Power supply line 17 Ground line 18 Output terminal 19 External output terminal 20 Integrated circuit for DC-DC converter 21 P-type semiconductor substrate 21p, 22n, 23p Contact region 22 N-well region 23 P-well region 25 Other transistors 30 Potential control circuit 31 XOR circuit 32 Selector

Claims

1. An integrated circuit for a DC-DC converter comprising: a high-side switching element connected between a first terminal and a second terminal; a low-side switching element connected between the second terminal and a third terminal to which a potential lower than the potential supplied to the first terminal is supplied; a control circuit that controls the conduction and non-conduction of the high-side switching element and the low-side switching element so that the output voltage of an inductive load connected to the second terminal remains constant; a p-type semiconductor substrate including a first n-type region and a p-type region provided within the first n-type region; and a potential control circuit that controls the potential supplied to the first n-type region, wherein the low-side switching element is a transistor including a second n-type region provided within the p-type region as a source or drain, and the potential control circuit supplies a first potential to the first n-type region when both the high-side switching element and the low-side switching element are non-conductive, and supplies a second potential higher than the first potential to the first n-type region when one of the high-side switching element and the low-side switching element is conductive.

2. The integrated circuit for a DC-DC converter according to claim 1, wherein the first potential is a potential supplied to the third terminal.

3. The integrated circuit for a DC-DC converter according to claim 1, wherein the second potential is a potential supplied to the first terminal.

4. The integrated circuit for a DC-DC converter according to claim 1, wherein the control circuit includes: a comparator that compares the output voltage of the inductive load with a reference voltage; and a pulse generation circuit that generates a pulse voltage based on the comparison result by the comparator, and supplies a first control voltage and a second control voltage based on the pulse voltage to the high-side switching element and the low-side switching element, respectively.

5. The DC-DC converter integrated circuit according to claim 4, wherein the control circuit further includes a timing adjustment circuit that generates the first control voltage and the second control voltage based on the pulse voltage so that the period during which both the high-side switching element and the low-side switching element are non-conductive is a predetermined period.

6. The integrated circuit for a DC-DC converter according to claim 4, wherein the potential control circuit switches between the first potential and the second potential based on the first control voltage and the second control voltage.

7. A DC-DC converter comprising: an integrated circuit for a DC-DC converter according to any one of claims 1 to 6; an output terminal; the inductive load connected in series between the second terminal and the output terminal; and a capacitive element connected in series between the output terminal and the third terminal.

8. A control method for a DC-DC converter, the DC-DC converter comprising: a high-side switching element connected between a first terminal and a second terminal; a low-side switching element connected between the second terminal and a third terminal to which a potential lower than the potential supplied to the first terminal is supplied; a control circuit that controls the conduction and non-conduction of the high-side switching element and the low-side switching element so that the output voltage of an inductive load connected to the second terminal remains constant; and a p-type semiconductor substrate including a first n-type region and a p-type region provided in the first n-type region, the low-side switching element being a transistor including a second n-type region provided in the p-type region as a source or drain, the control method for the DC-DC converter comprising: when both the high-side switching element and the low-side switching element are non-conductive, supplying a first potential to the first n-type region; and when one of the high-side switching element and the low-side switching element is conductive, supplying a second potential higher than the first potential to the first n-type region. A method for controlling a DC-DC converter.

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