D / a converter

Abstract

A resistor (R+) converts the total current of a plurality of current source units 3 into an analog output voltage. Each current source unit 3 receives first to fourth overlap clocks (Φ1-Φ4) having phases sequentially shifted by 90°, and first to fourth digital inputs (Di1-Di4) that are among the digital inputs corresponding to the current source unit 3 and that are synchronized respectively with the first to fourth overlap clocks (Φ1-Φ4). Each current source unit 3 has first to fourth switch parts (SW1-SW4) connected in parallel to each other, and a current source (I0) connected in series to the first to fourth switch parts (SW1-SW4). The first switch part (SW1) outputs a current from the current source (I0) in response to the first digital input (Di1) in a period in which the first and second overlap clocks (Φ1, Φ2) overlap. The same applies to the switch parts (SW2-SW4).

Description

D / A converter

[0001] The present disclosure relates to digital-to-analog converters.

[0002] Current-output D / A converters (hereinafter abbreviated as DACs) are the fastest conversion type DACs in practical use. They pass the current of a current-source cell through a resistor, convert it into an analog voltage, and output it. Current-source cells are broadly classified into two types: a unary configuration with multiple current-source units with the same current value, and a binary configuration with multiple current-source units weighted by a current value ratio that is a power of two. In a unary configuration, the number of current-source units that output a current is controlled according to a digital input. In a binary configuration, a current-source unit that outputs a current is selected according to the digital input. This controls the current value of the current-source cell according to the digital input, and an analog voltage corresponding to the digital input is output.

[0003] Each bit of the digital input has a binary weight (a power of 2). The D / A converter outputs an analog voltage with a magnitude corresponding to that weight. In the case of 8 bits, the weight ratio from the least significant bit to the most significant bit is 1, 2, 4, ... 64, 128. In the case of a binary configuration in which this is set as the current amount of multiple current source units, the current amount of the least significant to most significant current source cells is I ０ = 1I, I １ = 2I, I ２ = 4I, ...I ７ = 128I. However, problems arise when the digits change, for example, from 127 (01111111) to 128 (10000000). ０ +I １ +I ２ +I ３ +I ４ +I ５ +I ６ At 128, a current of I ７ Since the current source units that pass current are completely interchanged between 127 and 128, if there is an error in the amount of current in each current source unit and this error is biased toward the positive or negative side and superimposed, a large error (differential nonlinearity error) will occur.

[0004] On the other hand, in the unary configuration, a current of 127I flows at 127, and a current of 127I + 1I flows at 128. Therefore, errors are not superimposed, and only the error of the added 1I remains, suppressing errors. For this reason, the unary configuration is advantageous in terms of accuracy. However, a logic circuit must perform a decoding process (also known as binary-unary conversion or binary-thermometer conversion) to convert the binary code input to the unary current-source cell into a thermometer code. This binary-unary conversion requires multiple logic stages as the number of binary digits increases, resulting in longer processing times for the logic circuit. This delay also delays the switching of the switches within the current-source cell, slowing down the conversion speed. For this reason, considering the trade-off between accuracy and speed, a segment configuration is often used, with the upper side configured as a unary configuration and the lower side configured as a binary configuration.

[0005] A current source unit has a current source that supplies a constant current value and a switch that controls whether to output the current (see, for example, Non-Patent Document 1). The operation of a current source unit is broadly divided into single-ended operation and differential operation. In single-ended operation, two switches are used to switch whether the current of the current source cell is output or discarded as dummy. In differential operation, two switches are used to switch whether the current of the current source cell is output as a positive output or a negative output.

[0006] A quad switching current source cell has also been proposed, in which two pairs of these two switches are connected to one current source (see, for example, Non-Patent Document 2). While one of the two sets is operating, the other performs decoding processing of the next input data, alternately extracting output. This makes the delay of the logic circuit invisible, enabling faster conversion speeds.

[0007] After a digital signal is input to a sub-DAC, the output voltage gradually transitions and settles to a final value, requiring a certain transition time. Therefore, it has been proposed to provide two sets of sub-DACs with quad-switching current source cells, operate these sub-DACs alternately (time interleaved operation), and selectively extract the output using a multiplexer (see, for example, Non-Patent Document 3). A total of four sets of switches are switched with a 90° phase difference. Each set does not output a voltage during the transition period in the first half of its operation, and instead extracts a voltage that has settled to its final value in the second half of its operation. This shortens the transition time of the sub-DAC's output voltage, thereby enabling a conversion speed twice as fast as that of a single sub-DAC.

[0008] A. van den Bosch, et al., "A 10-bit 1-GSample / s Nyquist current-steering CMOS D / A converter," IEEE JSSC, Mar. 2001.B. Schafferer, et al., "A 3V CMOS 400mW 14b 1.4GS / s DAC for Multi-Carrier Applications," IEEE ISSCC2004.E. Olieman, et al., "An Interleaved Full Nyquist High-Speed ​​DAC Technique," IEEE JSSC, Mar. 2015.

[0009] The Quad Switching DAC in Non-Patent Document 2 could only double its conversion speed. To further increase the speed, Non-Patent Document 3 uses a multiplexer to time-interleave two sets of sub-DACs. However, because the two sets of sub-DACs each use a separate current source, any errors in the current values ​​of these current sources will cause an offset, causing the analog output voltage to deviate from the ideal value for the digital input. Furthermore, a gain error will occur, causing the output voltage range to deviate from the ideal value.

[0010] Furthermore, in Non-Patent Document 3, a multiplexer that selectively extracts the output of the sub-DAC is located outside the sub-DAC. Therefore, the magnitude of the current flowing through the multiplexer changes depending on the digital input. Because the drain voltage-current characteristics of a transistor are not linear, a nonlinear error occurs in which the voltage drop caused by the multiplexer's transistors does not linearly correspond to changes in the digital input. Therefore, the analog output voltage deviates from the ideal value for the digital input.

[0011] Furthermore, the DAC in Non-Patent Document 3 performs RZ (Return-to-Zero) operation, in which the output current of one of the two sub-DACs flows to Dummy, which means that half of the current of the current source cell is wasted, which is disadvantageous in terms of power efficiency.

[0012] The present disclosure has been made to solve the above-mentioned problems, and its purpose is to obtain a D / A converter that can prevent offset, gain error, and nonlinearity error and improve power efficiency.

[0013] A D / A converter according to the present disclosure includes a current source cell having a plurality of current source units connected in parallel to each other and outputting a current in response to a digital input, and a resistor for converting a total current of the plurality of current source units into an analog output voltage, wherein each current source unit receives first to fourth overlap clocks whose phases are sequentially shifted by 90°, and first to fourth digital inputs which are portions of the digital input corresponding to each current source unit that are synchronized with the first to fourth overlap clocks, and each current source unit has first to fourth switch sections connected in parallel to each other and current sources connected in series to the first to fourth switch sections, the second switch unit outputs the current of the current source in response to the second digital input during a period when the first and second overlapping clocks overlap, the second switch unit outputs the current of the current source in response to the second digital input during a period when the second and third overlapping clocks overlap, the third switch unit outputs the current of the current source in response to the third digital input during a period when the third and fourth overlapping clocks overlap, and the fourth switch unit outputs the current of the current source in response to the fourth digital input during a period when the fourth and first overlapping clocks overlap.

[0014] In the present disclosure, the first to fourth switch units use a common current source, which prevents offset and gain errors. Furthermore, the first to fourth switch units that switch operation are located within a current source unit, and the magnitude of the current flowing through the first to fourth switch units does not depend on the digital input, so no nonlinearity errors occur. Furthermore, NRZ operation is performed, which improves power efficiency.

[0015] 1 is a circuit diagram showing a D / A converter according to a first embodiment; 2 is a circuit diagram showing a current source unit according to a first embodiment; 3 is a timing chart showing an operation of the current source unit according to the first embodiment; 4 is a circuit diagram showing a current source unit according to a second embodiment; and 5 is a timing chart showing an operation of the current source unit according to the second embodiment.

[0016] A D / A converter according to an embodiment will be described with reference to the drawings. The same or corresponding components are designated by the same reference numerals, and repeated description may be omitted.

[0017] 1 is a circuit diagram showing a D / A converter according to a first embodiment. A logic circuit 1 receives a digital input D ０ ~D ｎ is processed and input to the current source cell 2. A four-phase overlap clock Φ １ ~Φ ４ are also input to the current source cell 2. The overlapping clocks with adjacent numbers, for example, the overlapping clock Φ １ , Φ ２ The overlap clock Φ is shifted in phase by 90° and overlaps by 1 / 4 period. １ ~Φ ４ is generated by a four-phase clock generator disclosed in Japanese Patent No. 4152969, for example.

[0018] The current source cell 2 has a plurality of current source units 3 connected in parallel to each other. The plurality of current source units 3 each output a current in response to a corresponding digital input. Resistors R+ and R- are connected between the current source cell 2 and the power supply. The resistor R+ divides the total current of the plurality of current source units 3 into an analog output voltage V ｏｕｔ The current source units 3 operate differentially, and the resistor R- converts the total current of the inverted outputs of the multiple current source units 3 into the analog output voltage V ｏｕｔ Convert to -.

[0019] The current source unit 3 includes a switch section SW connected in parallel. １ ~SW ４ and switch section SW １ ~SW ４ A current source I connected in series with ０ The current source cell 2 has a digital input D ０ ~D ｎ Upper side D ｋ＋１ ~D ｎ The current source unit 3 corresponding to the digital input D ０ ~D ｎ Lower side D ０~D ｋ For example, in an 8-bit DAC, the unary configuration of the upper 5 bits is made up of 31 current source units 3 that supply the same current, and the binary configuration of the lower 3 bits is made up of current sources I with current ratios of 1, 2, and 4. ０ The current source I of the multiple current source units 3 in the unary configuration ０ The current values ​​of the current sources I of the binary current source units 3 are the same. ０ The current values ​​of the binary code D are weighted by a current value ratio of a power of 2. The logic circuit 1 is configured as a current source unit 3 having a unary configuration. ｋ＋１ ~D ｎ A decoding process is performed to convert the signal into a thermometer code.

[0020] 2 is a circuit diagram showing a current source unit according to the first embodiment. ０ consists of two transistors controlled by voltages Vb and Vbcas, respectively, and supplies a constant current. ０ The drain of the switch SW １ ~SW ４ is connected.

[0021] Digital Input D ｉ１ ~D ｉ４ is the digital input D corresponding to the i-th current source unit 3 ｉ Among the overlapping clocks Φ １ ~Φ ４ This is the part that synchronizes with each of the digital inputs D ｉ１ ~D ｉ４ are input to the current source unit 3 in sequence with a phase difference of 90 degrees. ｉ to digital input D ｉ１ ~D ｉ４ Generate.

[0022] Switch section SW １ are transistors Q connected in series with each other. １１ ~Q １３ and a transistor Q connected in series with each other. １１ ´~Q１３ The transistor Q １１ ~Q １３ and transistor Q １１ ´~Q １３ ' are connected in parallel with each other. ２ are transistors Q connected in series with each other. ２１ ~Q ２３ and a transistor Q connected in series with each other. ２１ ´~Q ２３ The switch section SW ３ are transistors Q connected in series with each other. ３１ ~Q ３３ and a transistor Q connected in series with each other. ３１ ´~Q ３３ The switch section SW ４ are transistors Q connected in series with each other. ４１ ~Q ４３ and a transistor Q connected in series with each other. ４１ ´~Q ４３ ´ and.

[0023] Transistor Q １１ ~Q １３ are overlapping clocks Φ １ , overlapping clock Φ ２ , digital input D ｉ１ The transistor Q ２１ ~Q ２３ are overlapping clocks Φ ２ , overlapping clock Φ ３ , digital input D ｉ２ The transistor Q ３１ ~Q ３３ are overlapping clocks Φ ３ , overlapping clock Φ ４ , digital input D ｉ３ The transistor Q ４１ ~Q ４３ are overlapping clocks Φ ４ , overlapping clock Φ １ , digital input D ｉ４ is controlled by.

[0024] 3 is a timing chart showing the operation of the current source unit according to the first embodiment. ｉ１ After the overlap clock Φ １ becomes "1" and the transistor Q １１ Then, the overlap clock Φ ２ becomes "1" and the transistor Q １２ Overlap clock Φ １ , Φ ２ During the period when both of the digital inputs D ｉ１ Depending on the transistor Q １３ is turned on and off, and the switch SW １ is the current source I ０ The current source I ０ The current of the digital input D ｉ１ If is "1", then I ｏｕｔ If it is "0", it will be "+" ｏｕｔ -. That is, digital input D ｉ１ By this, the current source I ０ The current from ｏｕｔ + and I ｏｕｔ -, and the overlap clock Φ １ , Φ ２ The timing at which the current flows is controlled by

[0025] Then, the overlap clock Φ １ When becomes "0", the transistor Q １１ is turned off, and the switch SW １ The current output from D ｉ２ becomes "1" and the switch SW ２ The same operation is performed in D ｉ３ becomes "1" and the switch SW ３ The same operation is performed in D ｉ４ becomes "1" and the switch SW ４ The same operation is performed in

[0026] Switch section SW １ is the overlapping clock Φ １ , Φ ２During the overlapping period, the digital input D ｉ１ The current source I ０ The switch SW outputs a current of ２ is the overlapping clock Φ ２ , Φ ３ During the overlapping period, the digital input D ｉ２ The current source I ０ The switch SW outputs a current of ３ is the overlapping clock Φ ３ , Φ ４ During the overlapping period, the digital input D ｉ３ The current source I ０ The switch SW outputs a current of ４ is the overlapping clock Φ ４ , Φ １ During the overlapping period, the digital input D ｉ４ The current source I ０ It outputs a current of

[0027] In this way, the four-phase clock with a phase difference of 90° controls the switch SW in the current source unit 3. １ ~SW ４ This allows the current source I ０ The current from the switch SW １ ~SW ４ Since one of these operates and outputs, it becomes a non-return-to-zero (NRZ) operation.

[0028] As described above, in this embodiment, the switch section SW １ ~SW ４ is a common current source I ０ Since the switch SW1 is used, offset and gain errors can be prevented. １ ~SW ４ is in the current source unit 3, and the switch section SW １ ~SW ４ Since the magnitude of the current flowing through the current source unit 3 does not depend on the digital input, no nonlinearity error occurs. Furthermore, since the current source unit 3 performs NRZ operation, power efficiency can be improved.

[0029] The logic circuit 1 is realized by a processing circuit such as a CPU that executes a program stored in a memory, a system LSI, etc. Furthermore, a plurality of processing circuits may cooperate to execute the above functions.

[0030] Second Embodiment Fig. 4 is a circuit diagram showing a current source unit according to a second embodiment. １ is AND circuit A １ , A １ ' and a transistor Q connected in series with each other １４ , Q １５ and a transistor Q connected in series with each other. １４ ´,Q １５ The switch section SW ２ is AND circuit A ２ , A ２ ' and a transistor Q connected in series with each other ２４ , Q ２５ and a transistor Q connected in series with each other. ２４ ´,Q ２５ The switch section SW ３ is AND circuit A ３ , A ３ ' and a transistor Q connected in series with each other ３４ , Q ３５ and a transistor Q connected in series with each other. ３４ ´,Q ３５ The switch section SW ４ is AND circuit A ４ , A ４ ' and a transistor Q connected in series with each other ４４ , Q ４５ and a transistor Q connected in series with each other. ４４ ´,Q ４５ ´ and.

[0031] Overlap Clock Φ １ and digital input D ｉ１ are basically the same timing. １ is the overlap clock Φ １ and digital input D ｉ１ AND operation is performed on the transistor Q １ is AND circuit A１ Output D ｉ１ Transistor Q １５ is the overlap clock Φ ２ Controlled by AND circuit A １ ´ is the overlap clock Φ １ and digital input D ｉ１ - AND operation. Transistor Q １ ' is AND circuit A １ The output of the transistor Q １５ ´ is the overlap clock Φ ２ is controlled by.

[0032] AND circuit A ２ is the overlap clock Φ ２ and digital input D ｉ２ AND operation is performed on the transistor Q ２４ is AND circuit A ２ Output D ｉ２ Transistor Q ２５ is the overlap clock Φ ３ Controlled by AND circuit A ２ ´ is the overlap clock Φ ２ and digital input D ｉ２ - AND operation. Transistor Q ２４ ' is AND circuit A ２ The output of the transistor Q ２５ ´ is the overlap clock Φ ３ is controlled by.

[0033] AND circuit A ３ is the overlap clock Φ ３ and digital input D ｉ３ AND operation is performed on the transistor Q ３４ is AND circuit A ３ Output D ｉ３ Transistor Q ３５ is the overlap clock Φ ４ Controlled by AND circuit A ３ ´ is the overlap clock Φ ３ and digital input D ｉ３ - AND operation. Transistor Q ３４' is AND circuit A ３ The output of the transistor Q ３５ ´ is the overlap clock Φ ４ is controlled by.

[0034] AND circuit A ４ is the overlap clock Φ ４ and digital input D ｉ４ AND operation is performed on the transistor Q ４４ is AND circuit A ４ Output D ｉ４ Transistor Q ４５ is the overlap clock Φ １ Controlled by AND circuit A ４ ´ is the overlap clock Φ ４ and digital input D ｉ４ - AND operation. Transistor Q ４４ ' is AND circuit A ４ The output of the transistor Q ４５ ´ is the overlap clock Φ １ is controlled by.

[0035] 5 is a timing chart showing the operation of the current source unit according to the second embodiment. As in the first embodiment, the switch SW1 in the current source unit 3 is driven by a four-phase clock having a phase difference of 90°. １ ~SW ４ The switch SW operates in a time interleaved manner. １ is the overlapping clock Φ １ , Φ ２ During the overlapping period, the digital input D ｉ１ The current source I ０ The switch SW outputs a current of ２ is the overlapping clock Φ ２ , Φ ３ During the overlapping period, the digital input D ｉ２ The current source I ０ The switch SW outputs a current of ３ is the overlapping clock Φ ３ , Φ ４ During the overlapping period, the digital input D ｉ３The current source I ０ The switch SW outputs a current of ４ is the overlapping clock Φ ４ , Φ １ During the overlapping period, the digital input D ｉ４ The current source I ０ This provides the same effect as in the first embodiment.

[0036] Furthermore, in this embodiment, each switch unit SW １ ~SW ４ In this embodiment, the number of transistor stages is one less than that in the first embodiment. This makes it possible to expand the output voltage range by one transistor stage.

[0037] In addition, the overlap clock Φ １ , Φ ２ and the transistor Q １１ , Q １２ It is also possible to reduce the number of transistor stages to one. In this case, the number of transistor stages is reduced by one. However, as the operating speed increases, the pulse width during the "1" period after the AND process narrows, so the speed limit becomes lower than when the AND process is not performed.

[0038] 1 Logic circuit, 2 Current source cell, 3 Current source unit, A １ ~A ４ AND circuit, D ０ ~D ｎ , D ｉ１ ~D ｉ４ Digital input, I ０ Current source, Q １１ ~Q ４５ Transistor, R+, R- Resistor, SW １ ~SW ４ Switch section, Φ １ ~Φ ４ Overlapping Clocks

Claims

1. A current source cell comprising: a current source cell having a plurality of current source units connected in parallel to each other, each outputting a current in response to a digital input; and a resistor for converting the total current of the plurality of current source units into an analog output voltage, wherein each current source unit receives first to fourth overlapping clocks whose phases are sequentially shifted by 90°, and first to fourth digital inputs which are portions of the digital input corresponding to each current source unit that are synchronized with the first to fourth overlapping clocks, each current source unit having first to fourth switch sections connected in parallel to each other and a current source connected in series to the first to fourth switch sections, wherein the first switch section outputs a current from the current source in response to the first digital input during a period when the first and second overlapping clocks overlap, the second switch section outputs a current from the current source in response to the second digital input during a period when the second and third overlapping clocks overlap, and the third switch section outputs a current from the current source in response to the third digital input during a period when the third and fourth overlapping clocks overlap, the fourth switch section outputs the current of the current source in response to the fourth digital input during a period in which the fourth and first overlapping clocks overlap.

2. The D / A converter according to claim 1, further comprising a logic circuit that generates the first to fourth digital inputs from the digital inputs corresponding to each current source unit.

3. A D / A converter as claimed in claim 1 or 2, characterized in that: the first switch section has first to third transistors connected in series with each other, and the first to third transistors are controlled by the first overlapping clock, the second overlapping clock, and the first digital input, respectively; the second switch section has fourth to sixth transistors connected in series with each other, and the fourth to sixth transistors are controlled by the second overlapping clock, the third overlapping clock, and the second digital input, respectively; the third switch section has seventh to ninth transistors connected in series with each other, and the seventh to ninth transistors are controlled by the third overlapping clock, the fourth overlapping clock, and the third digital input, respectively; and the fourth switch section has tenth to twelfth transistors connected in series with each other, and the tenth to twelfth transistors are controlled by the fourth overlapping clock, the first overlapping clock, and the fourth digital input, respectively.

4. The first switch section has a first AND circuit and first and second transistors connected in series with each other, the first AND circuit performs an AND operation on the first overlapping clock and the first digital input, the first and second transistors being controlled by the output of the first AND circuit and the second overlapping clock, respectively; the second switch section has a second AND circuit and third and fourth transistors connected in series with each other, the second AND circuit performs an AND operation on the second overlapping clock and the second digital input, the third and fourth transistors being controlled by the output of the second AND circuit and the third overlapping clock, respectively; 3. The D / A converter according to claim 1, wherein the third switch section has a third AND circuit and fifth and sixth transistors connected in series with each other, the third AND circuit performs an AND operation on the third overlapping clock and the third digital input, the fifth and sixth transistors being controlled by the output of the third AND circuit and the fourth overlapping clock, respectively; and the fourth switch section has a fourth AND circuit and seventh and eighth transistors connected in series with each other, the fourth AND circuit performs an AND operation on the fourth overlapping clock and the fourth digital input, the seventh and eighth transistors being controlled by the output of the fourth AND circuit and the first overlapping clock, respectively.

5. The D / A converter according to claim 1 or 2, characterized in that the current source cells are configured as segments in which the current source units corresponding to the upper side of the digital input are configured as unary and the current source units corresponding to the lower side of the digital input are configured as binary, the current values ​​of the current sources of the plurality of current source units in the unary configuration are the same, and the current values ​​of the current sources of the plurality of current source units in the binary configuration are weighted by a current value ratio that is a power of 2.

6. A D / A converter according to claim 1 or 2, wherein said current source unit operates differentially.

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