Analog simulation of circuit designs with temporal parallelism and time-variant reduction

Abstract

A computing system (101) implementing a design verification system (300) to alter (401) a circuit design (301) describing an electronic system into a simplified representation of the circuit design (313), and also implement an analog simulator (340) to perform (402) a simulation of the simplified representation of the circuit design. The design verification system can identify (403) circuit activity (317) corresponding to the electronic system in different temporal windows during the simulation of the simplified representation of the circuit design, perform (404) a topological analysis of the circuit design based, at least in part, on the identified circuit activity in the different temporal windows. The design verification system can modify (405) the circuit design into a plurality of circuit design subsets corresponding to the different temporal windows based, at least in part, on the topological analysis.

Description

ANALOG SIMULATION OF CIRCUIT DESIGNS WITH TEMPORAL PARALLELISM AND TIME-VARIANT REDUCTIONTECHNICAL FIELD

[0001] This application is generally related to electronic design automation and, more specifically, to analog simulation of circuit designs with temporal parallelism and time-variant reduction.BACKGROUND

[0001] Designing and fabricating electronic systems typically involves many steps, known as a “design flow.” The particular steps of a design flow often are dependent upon the type of electronic system to be manufactured, its complexity, the design team, and the fabricator or foundry that will manufacture the electronic system from a design. One step of the design flow for the development of integrated circuits often includes performing analog simulation of circuit designs describing the integrated circuits. These circuit design can often be specified using a transistor-level netlist, for example, in Simulation Program with Integrated Circuit Emphasis (SPICE), Eldo-SPICE, Spectre, or the like. The transistor-level netlist for the integrated circuit can correspond to a post-layout representation of the integrated circuit and, in some embodiments, include various parasitic resistances and capacitances.

[0002] As the complexity of integrated circuits has increased, performing analog simulations of their corresponding circuit designs has become expensive in terms of processing and memory resource utilization and the time to accomplish the simulation typically renders it impractical. Many integrated circuit developers, instead, implement various speed-ups in the analog simulation process to reduce resource consumption and overall throughput of their analog simulations, but these speed-ups come with a trade-off, namely, a reduction in the accuracy of the simulation results.SUMMARY

[0003] This application discloses a computing system implementing a design verification system to alter a circuit design describing an electronic system into a simplified representation of the circuit design, and also implement an analog simulator to perform a simulation of the simplified representation of the circuit design. The design verification system can identify circuit activity corresponding to the electronic system in different temporal windows during the simulation of the simplified representation of the circuit design, perform a topological analysis of the circuit design based, at least in part, on the identified circuit activity in the different temporal windows. The design verification system can modify the circuit design into a plurality of circuit design subsets corresponding to the different temporal windows based, at least in part, on the topological analysis. The analog simulator can simulate the circuit design subsets to generate operational measurements of the electronic system described by the circuit design. Embodiments of will be described below in greater detail.DESCRIPTION OF THE DRAWINGS

[0004] Figures 1 and 2 illustrate an example of a computer system of the type that may be used to implement various embodiments.

[0005] Figure 3 illustrates an example design verification system 300 for performing analog simulation with temporal parallelism and time-variant reduction that may be implemented according to various embodiments.

[0006] Figure 4 illustrates a flowchart showing an example implementation of analog simulation with temporal parallelism and time-variant reduction according to various examples.DETAILED DESCRIPTIONIllustrative Operating Environment

[0007] Various examples may be implemented through the execution of software instructions by a computing device 101 , such as a programmable computer. Accordingly, Figure 1 shows an illustrative example of a computing device 101. As seen in this figure, the computing device 101 includes a computing unit 103 with a processor unit 105 and a system memory 107. The processor unit 105 may be any type of programmable electronic device for executing softwareinstructions, but will conventionally be a microprocessor. The system memory 107 may include both a read-only memory (ROM) 109 and a random access memory (RAM) 111. As will be appreciated by those of ordinary skill in the art, both the read-only memory (ROM) 109 and the random access memory (RAM) 111 may store software instructions for execution by the processor unit 105.

[0008] The processor unit 105 and the system memory 107 are connected, either directly or indirectly, through a bus 113 or alternate communication structure, to one or more peripheral devices 115-123. For example, the processor unit 105 or the system memory 107 may be directly or indirectly connected to one or more additional memory storage devices, such as a hard disk drive 117, which can be magnetic and / or removable, a removable optical disk drive 119, and / or a flash memory card. The processor unit 105 and the system memory 107 also may be directly or indirectly connected to one or more input devices 121 and one or more output devices 123. The input devices 121 may include, for example, a keyboard, a pointing device (such as a mouse, touchpad, stylus, trackball, or joystick), a scanner, a camera, and a microphone. The output devices 123 may include, for example, a monitor display, a printer and speakers. With various examples of the computing device 101 , one or more of the peripheral devices 115-123 may be internally housed with the computing unit 103. Alternately, one or more of the peripheral devices 115-123 may be external to the housing for the computing unit 103 and connected to the bus 113 through, for example, a Universal Serial Bus (USB) connection.

[0009] With some implementations, the computing unit 103 may be directly or indirectly connected to a network interface 115 for communicating with other devices making up a network. The network interface 115 can translate data and control signals from the computing unit 103 into network messages according to one or more communication protocols, such as the transmission control protocol (TCP) and the Internet protocol (IP). Also, the network interface 115 may employ any suitable connection agent (or combination of agents) for connecting to a network, including, for example, a wireless transceiver, a modem, or an Ethernet connection. Such network interfaces and protocols are well known in the art, and thus will not be discussed here in more detail.

[0010] It should be appreciated that the computing device 101 is illustrated as an example only, and it not intended to be limiting. Various embodiments may be implemented using one ormore computing devices that include the components of the computing device 101 illustrated in Figure 1 , which include only a subset of the components illustrated in Figure 1 , or which include an alternate combination of components, including components that are not shown in Figure 1. For example, various embodiments may be implemented using a multi-processor computer, a plurality of single and / or multiprocessor computers arranged into a network, or some combination of both.

[0011] With some implementations, the processor unit 105 can have more than one processor core. Accordingly, Figure 2 illustrates an example of a multi-core processor unit 105 that may be employed with various embodiments. As seen in this figure, the processor unit 105 includes a plurality of processor cores 201 A and 201 B. Each processor core 201 A and 201 B includes a computing engine 203A and 203B, respectively, and a memory cache 205A and 205B, respectively. As known to those of ordinary skill in the art, a computing engine 203A and 203B can include logic devices for performing various computing functions, such as fetching software instructions and then performing the actions specified in the fetched instructions. These actions may include, for example, adding, subtracting, multiplying, and comparing numbers, performing logical operations such as AND, OR, NOR and XOR, and retrieving data. Each computing engine 203A and 203B may then use its corresponding memory cache 205A and 205B, respectively, to quickly store and retrieve data and / or instructions for execution.

[0012] Each processor core 201A and 201 B is connected to an interconnect 207. The particular construction of the interconnect 207 may vary depending upon the architecture of the processor unit 105. With some processor cores 201 A and 201 B, such as the Cell microprocessor created by Sony Corporation, Toshiba Corporation and IBM Corporation, the interconnect 207 may be implemented as an interconnect bus. With other processor units 201A and 201 B, however, such as the Opteron™ and Athlon™ dual-core processors available from Advanced Micro Devices of Sunnyvale, California, the interconnect 207 may be implemented as a system request interface device. In any case, the processor cores 201 A and 201 B communicate through the interconnect 207 with an input / output interface 209 and a memory controller 210. The input / output interface 209 provides a communication interface to the bus 113. Similarly, the memory controller 210 controls the exchange of information to the system memory 107. With some implementations, the processor unit 105 may include additional components, such as a high-level cache memory accessible shared by the processor cores201 A and 201 B. It also should be appreciated that the description of the computer network illustrated in Figure 1 and Figure 2 is provided as an example only, and is not intended to suggest any limitation as to the scope of use or functionality of alternate embodiments.Analog Simulation with Temporal Parallelism and Time-Variant Reduction

[0013] Figure 3 illustrates an example design verification system 300 for performing analog simulation with temporal parallelism and time-variant reduction that may be implemented according to various embodiments. Figure 4 illustrates a flowchart showing an example implementation of analog simulation with temporal parallelism and time-variant reduction according to various examples. Referring to Figures 3 and 4, the design verification system 300 can receive a circuit design 301 describing an integrated circuit using a transistor-level netlist specified, for example, in Simulation Program with Integrated Circuit Emphasis (SPICE), Eldo- SPICE, Spectre, or the like. The transistor-level netlist for the integrated circuit can correspond to a post-layout representation of the integrated circuit and, in some embodiments, include various parasitic resistances and capacitances.

[0014] The design verification system 300, for example, implemented in the computing device 101 of Figure 1 , can receive a test bench 302 capable of defining test stimulus, for example, clock signals, activation signals, power signals, control signals, data signals, or the like, that, when grouped, may form test bench transactions capable of prompting operation of the circuit design 301 in an analog verification environment. The test bench 302 also can include one or more measurement commands to identify the electrical activity within an analog simulation of the circuit design 301 to measure and record.

[0015] The design verification tool 300 can include an analog simulator 340 to implement the analog verification environment capable of simulating the circuit design 301 and the test bench 302. The analog simulator 340 can simulate operations performed by the circuit design 301 in response to the test stimulus generated by the test bench 302, for example, using a continuous time matrix-based differential equation solvers. The design verification tool 300 can implement a multi-stage process for performing the analog simulation, which can speed-up the overall simulation time, while maintaining accuracy, by employing temporal parallelism and time-variant reduction in the analog simulation environment. Embodiments of the temporal parallelism andtime-variant reduction utilized by the design verification tool 300 will be described below in greater detail.

[0016] The analog simulator 340 can generate simulation results, for example, including waveform data corresponding to operation of the circuit design 301 in the analog verification environment. The design verification system 300 can generate verification results 303 from the simulation results and output the waveform data as a waveform database 304. The design verification system 300 (or a tool external to the design verification tool 300) can perform a functional verification of the circuit design 301 , for example, by comparing the verification results 303 and / or the waveform database 304 with an expected output from the circuit design 301 in response the test stimulus generated by the test bench 302.

[0017] The design verification tool 300 can include a design activity system 310 to work with the analog simulator 340 to identify temporal window-based circuit activity 317 corresponding to different temporal windows during the analog simulation when various subsets of the circuit design 301 have become active. The design activity system 310 can provide low resolution settings 311 to the analog simulator 340, which can configure the analog simulator 340 to perform an analog simulation with high throughput and low accuracy. In some embodiments, the design activity system 310 can utilize the measurement commands in the test bench 302 when generating the low resolution settings 311.

[0018] The design activity system 310 can include a design reduction system 312 that, in a block 401 of Figure 4, can alter the circuit design 301 to create a simplified representation of the circuit design or a simplified design 313. In some embodiments, the design reduction system 312 can generate the simplified design 313 by identifying and removing parasitic capacitance and parasitic resistances from the circuit design 301. The design activity system 310 can provide the simplified design 313 and the test bench 302 to the analog simulator 340, which in a block 402 of Figure 4 can allow the analog simulator 340 to perform a low resolution simulation of the simplified representation of the circuit design and generate low resolution simulation results 315. Although the analog simulator 340 and design activity system 310 are shown as working together to simulate a simplified design 313, in some embodiments, the circuit design 301 can be simulated directly by the analog simulator 340 with the low resolution setting 311.

[0019] The design activity system 310 can include an activity detection system 314 to analyze the low resolution simulation results 315 based, at least in part, on the electrical activity to be measured in the measurement commands of the test bench 302. The activity detection system 314, in a block 403 of Figure 4, can identify circuit activity corresponding to portions of the electronic system that were active within different temporal windows of the low resolution simulation. In some embodiments, the activity detection system 314 can detect circuit activity and inactivity from the low resolution simulation results 315 and define discrete temporal windows when the circuit activity occurred or between when there was circuit inactivity during the analog simulation. The activity detection system 314 can generate temporal window-based circuit activity 317, which identifies the time periods in the analog simulation when different portions of the simplified design 313 had circuit activity.

[0020] The design verification tool 300 can include a design topology analysis system 320 that, in a block 404 of Figure 4, can perform a topological analysis of the simplified representation of the circuit design based on the identified circuit activity, which correlates the temporal windowbased circuit activity 317 to the different active portions of the simplified design 313. The design topology analysis system 320 can include a topological graph system 322 to analyze the topological structure of the simplified design 313 and cast the simplified design 313 into a numerical graph based on the topological structure of the simplified design 313. In some embodiments, the numerical graph can represent the circuitry and signal connectivity of the simplified design 313 in a mathematical form. The design topology analysis system 320 can perform signal tracing in the numerical graph to correlate the signals associated with circuit activity to the physical structure of the circuitry in the simplified design 313.

[0021] The design topology analysis system 320 can include a temporal window-based graph modification system 324 to utilize the temporal window-based circuit activity 317 to modify the numerical graph of the simplified design 313 into a plurality of subgraphs 321 , for example, one subgraph for each temporal window identified in the low resolution analog simulation. In some embodiments, the temporal window-based graph modification system 324 can identify active circuitry within one of the temporal windows and eliminate non-active circuitry from the numerical graph of the simplified design 313 to generate a subgraph. The process can be repeated for each temporal window identified in the temporal window-based circuit activity 317,which can allow the temporal window-based graph modification system 324 to create the plurality of subgraphs 321 .

[0022] The design verification tool 300 can include a parallel simulation system 330 to utilize the subgraphs 321 to identify subsets of the circuit design 301 active during different temporal windows and work with the analog simulator 340 to perform high resolution simulation of the design subsets 333 in parallel. The parallel simulation system 330 can then aggregate high resolution simulation results 335 of these parallel simulations with the low resolution results 315 to generate the verification results 303 and the waveform database 304.

[0023] The parallel simulation system 330 can include a design partitioning system 332 that, in a block 405 of Figure 4, can modify the circuit design 301 into one or more circuit design subsets corresponding to the different temporal windows based on the topological analysis. In some embodiments, the design partitioning system 332 can correlate circuitry in the circuit design 301 to the numerical representations of circuitry in the subgraphs 321 and modify the circuit design 301 to remove circuitry not represented or present in the subgraphs 321. As a result, the design partitioning system 332 can create multiple design subsets 333, which can each correspond to portions of the circuit design 301 determined to have active circuitry within different temporal windows of an analog simulation of the circuit design 301 with the test bench 302.

[0024] The parallel simulation system 330 can provide high resolution settings 331 to the analog simulator 340, which can configure the analog simulator 340 to perform an analog simulation with high-level of accuracy. In some embodiments, the design activity system 310 can utilize the measurement commands in the test bench 302 to generate the high resolution settings 331. The parallel simulation system 330, in a block 406 of Figure 4, can work with the analog simulator 340 to perform high resolution simulations of the circuit design subsets 333 in parallel. In some embodiments, the parallel simulation system 330 can provide the analog simulator 340 with the design subsets 333, the test bench 302, and the temporal windows in the analog simulation that correspond to the design subsets 333. The analog simulator 340 can perform simulations of the design subsets 333 in their corresponding temporal window in parallel, and generate high resolution simulation results 335 of the different design subsets 333. By performing high resolution analog simulation over a limited duration of the overall simulationtime, i.e., over the period of the temporal windows, and performing them in parallel, the parallel simulation system 330 can receive high resolution simulation results 335 when the circuitry in the circuit design 301 has been determined to be active and reduce the overall simulation time of the circuit design 301 .

[0025] The parallel simulation system 330 can include a result aggregation system 334 to generate the verification results 303 and the waveform database 304 from the low resolution simulation results 315 and the high resolution simulation results 335. In some embodiments, such as in a block 407 of Figure 4, the result aggregation system 334 can output results from at least the high resolution simulations as verification results for simulating the circuit design. The result aggregation system 334 also can utilize the low resolution simulation results 315 as a base for the verification results 303 and the waveform database 304, and then supplant the low resolution simulation results 315 with the high resolution simulation results 335 in the temporal windows for active circuitry identified by the design activity system 310. The result aggregation system 334 can output the verification results 303 and the waveform database 304 for use in downstream verification, characterization, and / or validation processes.

[0026] The system and apparatus described above may use dedicated processor systems, micro controllers, programmable logic devices, microprocessors, or any combination thereof, to perform some or all of the operations described herein. Some of the operations described above may be implemented in software and other operations may be implemented in hardware. Any of the operations, processes, and / or methods described herein may be performed by an apparatus, a device, and / or a system substantially similar to those as described herein and with reference to the illustrated figures.

[0027] The processing device may execute instructions or "code" stored in memory. The memory may store data as well. The processing device may include, but may not be limited to, an analog processor, a digital processor, a microprocessor, a multi-core processor, a processor array, a network processor, or the like. The processing device may be part of an integrated control system or system manager, or may be provided as a portable electronic device configured to interface with a networked system either locally or remotely via wireless transmission.

[0028] The processor memory may be integrated together with the processing device, for example RAM or FLASH memory disposed within an integrated circuit microprocessor or the like. In other examples, the memory may comprise an independent device, such as an external disk drive, a storage array, a portable FLASH key fob, or the like. The memory and processing device may be operatively coupled together, or in communication with each other, for example by an I / O port, a network connection, or the like, and the processing device may read a file stored on the memory. Associated memory may be "read only" by design (ROM) by virtue of permission settings, or not. Other examples of memory may include, but may not be limited to, WORM, EPROM, EEPROM, FLASH, or the like, which may be implemented in solid state semiconductor devices. Other memories may comprise moving parts, such as a known rotating disk drive. All such memories may be "machine-readable" and may be readable by a processing device.

[0029] Operating instructions or commands may be implemented or embodied in tangible forms of stored computer software (also known as "computer program" or "code"). Programs, or code, may be stored in a digital memory and may be read by the processing device. “Computer- readable storage medium" (or alternatively, "machine-readable storage medium") may include all of the foregoing types of memory, as well as new technologies of the future, as long as the memory may be capable of storing digital information in the nature of a computer program or other data, at least temporarily, and as long at the stored information may be "read" by an appropriate processing device. The term "computer-readable" may not be limited to the historical usage of "computer" to imply a complete mainframe, mini-computer, desktop or even laptop computer. Rather, "computer-readable" may comprise storage medium that may be readable by a processor, a processing device, or any computing system. Such media may be any available media that may be locally and / or remotely accessible by a computer or a processor, and may include volatile and non-volatile media, and removable and non-removable media, or any combination thereof.

[0030] A program stored in a computer-readable storage medium may comprise a computer program product. For example, a storage medium may be used as a convenient means to store or transport a computer program. For the sake of convenience, the operations may be described as various interconnected or coupled functional blocks or diagrams. However, theremay be cases where these functional blocks or diagrams may be equivalently aggregated into a single logic device, program or operation with unclear boundaries.Conclusion

[0031] While the application describes specific examples of carrying out embodiments of the invention, those skilled in the art will appreciate that there are numerous variations and permutations of the above described systems and techniques that fall within the spirit and scope of the invention as set forth in the appended claims. For example, while specific terminology has been employed above to refer to design processes, it should be appreciated that various examples of the invention may be implemented using any desired combination of electronic design automation processes.

[0032] One of skill in the art will also recognize that the concepts taught herein can be tailored to a particular application in many other ways. In particular, those skilled in the art will recognize that the illustrated examples are but one of many alternative implementations that will become apparent upon reading this disclosure.

[0033] Although the specification may refer to “an”, “one”, “another”, or “some” example(s) in several locations, this does not necessarily mean that each such reference is to the same example(s), or that the feature only applies to a single example.

Claims

CLAIMS1. A method comprising: performing, by a computing system with an analog simulator, a simulation of a circuit design describing an electronic system; identifying, by the computing system, circuit activity corresponding to the electronic system in different temporal windows during the simulation of the circuit design; performing, by the computing system, a topological analysis of the circuit design based, at least in part, on the identified circuit activity in the different temporal windows; modifying, by the computing system, the circuit design into a plurality of circuit design subsets corresponding to the different temporal windows based, at least in part, on the topological analysis; and simulating, by the computing system with the analog simulator, the circuit design subsets to generate operational measurements of the electronic system described by the circuit design.

2. The method of claim 1 , further comprising generating, by the computing system, a verification result file configured to include at least one of the operational measurements of the electronic system described by the circuit design or waveform data generated during the simulation of the circuit design subsets inserted into the different temporal windows associated with waveform data generated during the simulation of the circuit design.

3. The method of claim 1 , further comprising altering, by the computing system, the circuit design into a simplified representation of the circuit design by removing one or more resistive or capacitive circuit elements from the circuit design, wherein the performing the simulation of the circuit design includes simulating the simplified representation of the circuit design.

4. The method of claim 3, wherein the simulation of the simplified representation of the circuit design corresponds to a low resolution simulation of the circuit design, and wherein the simulating of the circuit design subsets corresponds to a high resolution simulation of the circuit design.

5. The method of claim 3, wherein performing the topological analysis of the circuit design further comprises generating a numerical graph representation of the circuit design from the simplified representation of the circuit design, and generating one or more sub-graphs by deleting one or more portions of the numerical graph representation of the circuit design not corresponding to the identified circuit activity in the different temporal windows.

6. The method of claim 5, wherein modifying the circuit design into the plurality of circuit design subsets further comprises identifying circuit elements in the circuit design that correspond to the sub-graphs and, for each of the sub-graphs, removing circuitry from the circuit design not corresponding to the identified circuit elements to generate the circuit design subsets.

7. The method of claim 1 , wherein the simulating of the circuit design subsets is performed in parallel by the analog simulator.

8. A system comprising: a memory system configured to store computer-executable instructions; and a computing system, in response to execution of the computer-executable instructions, is configured to: implement an analog simulator to perform a simulation of a circuit design describing an electronic system; identify circuit activity corresponding to the electronic system in different temporal windows during the simulation of the circuit design; perform a topological analysis of the circuit design based, at least in part, on the identified circuit activity in the different temporal windows; modify the circuit design into a plurality of circuit design subsets corresponding to the different temporal windows based, at least in part, on the topological analysis; and simulate, with the analog simulator, the circuit design subsets to generate operational measurements of the electronic system described by the circuit design.

9. The system of claim 8, wherein the computing system, in response to execution of the computer-executable instructions, is further configured to generate a verification result fileconfigured to include at least one of the operational measurements of the electronic system described by the circuit design or waveform data generated during the simulation of the circuit design subsets inserted into the different temporal windows associated with waveform data generated during the simulation of the circuit design.

10. The system of claim 8, wherein the computing system, in response to execution of the computer-executable instructions, is further configured to alter the circuit design into a simplified representation of the circuit design by removing one or more resistive or capacitive circuit elements from the circuit design, wherein the performing the simulation of the circuit design includes simulating the simplified representation of the circuit design.11 . The system of claim 10, wherein the simulation of the simplified representation of the circuit design corresponds to a low resolution simulation of the circuit design, and wherein the simulating of the circuit design subsets corresponds to a high resolution simulation of the circuit design.

12. The system of claim 10, wherein the computing system, in response to execution of the computer-executable instructions, is further configured to perform the topological analysis of the circuit design by generating a numerical graph representation of the circuit design from the simplified representation of the circuit design, and generating one or more sub-graphs by deleting one or more portions of the numerical graph representation of the circuit design not corresponding to the identified circuit activity in the different temporal windows.

13. The system of claim 12, wherein the computing system, in response to execution of the computer-executable instructions, is further configured to modify the circuit design into a plurality of circuit design subsets by identifying circuit elements in the circuit design that correspond to the sub-graphs and, for each of the sub-graphs, removing circuitry from the circuit design not corresponding to the identified circuit elements to generate the circuit design subsets.

14. An apparatus comprising at least one computer-readable memory device storing instructions configured to cause one or more processing devices in a computing system to perform operations comprising: performing an analog simulation of a circuit design describing an electronic system; identifying circuit activity corresponding to the electronic system in different temporal windows during the simulation of the circuit design; performing a topological analysis of the circuit design based, at least in part, on the identified circuit activity in the different temporal windows; modifying the circuit design into a plurality of circuit design subsets corresponding to the different temporal windows based, at least in part, on the topological analysis; and analog simulating the circuit design subsets to generate operational measurements of the electronic system described by the circuit design.

15. The apparatus of claim 14, wherein the instructions are configured to cause one or more processing devices to perform operations further comprising generating a verification result file configured to include at least one of the operational measurements of the electronic system described by the circuit design or waveform data generated during the analog simulation of the circuit design subsets inserted into the different temporal windows associated with waveform data generated during the simulation of the circuit design.

16. The apparatus of claim 14, wherein the instructions are configured to cause one or more processing devices to perform operations further comprising altering the circuit design into a simplified representation of the circuit design by removing one or more resistive or capacitive circuit elements from the circuit design, wherein the performing the simulation of the circuit design includes analog simulating the simplified representation of the circuit design.

17. The apparatus of claim 16, wherein the analog simulation of the simplified representation of the circuit design corresponds to a low resolution simulation of the circuit design, and wherein the analog simulating of the circuit design subsets corresponds to a high resolution simulation of the circuit design.

18. The apparatus of claim 16, wherein the instructions are configured to cause one or more processing devices to perform operations further comprising performing the topological analysis of the circuit design by generating a numerical graph representation of the circuit design from the simplified representation of the circuit design, and generating one or more subgraphs by deleting one or more portions of the numerical graph representation of the circuit design not corresponding to the identified circuit activity in the different temporal windows.

19. The apparatus of claim 18, wherein the instructions are configured to cause one or more processing devices to perform operations further comprising modifying the circuit design into the plurality of circuit design subsets by identifying circuit elements in the circuit design that correspond to the sub-graphs and, for each of the sub-graphs, removing circuitry from the circuit design not corresponding to the identified circuit elements to generate the circuit design subsets.

20. The apparatus of claim 14, wherein the instructions are configured to cause one or more processing devices to perform operations further comprising analog simulating the circuit design subsets in parallel by an analog simulator.

Images