Semiconductor structure, semiconductor device, and method for preparing semiconductor structure

Abstract

The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure, a semiconductor device, and a method for preparing a semiconductor structure. The semiconductor structure comprises: a substrate, a plurality of active columns arranged at intervals in a first direction and a second direction being formed in the substrate, the plurality of active columns all extending in a third direction, and the first direction intersecting the second direction and being perpendicular to the third direction; and capacitor contact structures, each of which covers a top surface of an active column and is connected to a capacitor structure. A top surface of each capacitor contact structure is non-planar, and the projection area of the capacitor contact structure on a plane perpendicular to the third direction is larger than the projection area of the active column on the plane perpendicular to the third direction.

Description

Semiconductor structure, semiconductor device, and method for preparing semiconductor structure

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on the Chinese patent application with application number 202410389625.5 and application date April 1, 2024, and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby introduced into this application as a reference. Technical Field

[0003] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure, a semiconductor device, and a method for preparing the semiconductor structure. Background Art

[0004] Dynamic Random Access Memory (DRAM) is a volatile memory that consists of multiple memory cells. Each memory cell mainly includes a transistor and a capacitor structure, and the memory cells are electrically connected to each other through word lines (WL) and bit lines (BL).

[0005] With the advancement of semiconductor technology, a new architecture has been proposed, replacing horizontal transistors with vertical transistors (Vertical Channel Transistors). This type of DRAM features vertically extending active pillars on the substrate, a wraparound gate around the active pillars, and buried bit lines and word lines.

[0006] However, DRAM with vertical transistors still faces many problems, and electrical issues have become a technical issue that needs to be solved urgently.

[0007] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field.

[0008] Summary of the Invention

[0009] The present disclosure provides a semiconductor structure, a semiconductor device, and a method for manufacturing the semiconductor structure. The semiconductor structure can reduce the contact resistance between the capacitor structure and the active pillar, thereby improving the transmission rate of DRAM.

[0010] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by practice of the present disclosure.

[0011] According to one aspect of the present disclosure, a semiconductor structure is provided, comprising: a substrate, in which a plurality of active pillars are formed and arranged at intervals along a first direction and a second direction, wherein the plurality of active pillars extend along a third direction; the first direction intersects the second direction and is perpendicular to the third direction;

[0012] A capacitor contact structure, the capacitor contact structure covers the top surface of the active pillar and is used to connect the capacitor structure;

[0013] The top surface of the capacitor contact structure is non-planar, and a projected area of ​​the capacitor contact structure on a plane perpendicular to the third direction is larger than a projected area of ​​the active pillar on a plane perpendicular to the third direction.

[0014] In one embodiment, the top surface of the capacitor contact structure is an arc-shaped surface, and the first contact surface of the active pillar in contact with the capacitor contact structure is an arc-shaped surface protruding toward the capacitor contact structure.

[0015] In one embodiment, a centerline of the active pillar substantially overlaps a centerline of the capacitor contact structure.

[0016] In one embodiment, a first isolation structure is formed between active pillars adjacent to each other along the first direction, and a first gap exists in the first isolation structure.

[0017] In one embodiment, a first contact surface where at least a portion of the active pillars are in contact with the capacitor contact structure is higher than a top surface of the first isolation structure.

[0018] In one embodiment, a gate structure is further formed in the substrate, the gate structure surrounds a portion of the active pillar, adjacent gate structures along the second direction are in contact and connected, and adjacent gate structures along the first direction are insulated from each other;

[0019] A bit line structure is also formed in the substrate. The bit line structure is located on a side of the substrate away from the extension direction of the active pillar. The bit line structure extends along a first direction, and adjacent bit line structures along a second direction are insulated from each other.

[0020] In one embodiment, the semiconductor structure further includes: an insulating layer, the insulating layer covering the top surface of the first isolation structure; and adjacent capacitor contact structures along the first direction and the second direction are isolated by the insulating layer.

[0021] The capacitor structure is located on the capacitor contact structure; the second contact surface between the capacitor structure and the capacitor contact structure is an arc surface.

[0022] According to another aspect of the present disclosure, a semiconductor device is provided, which is obtained by bonding the above-mentioned semiconductor structure to a target wafer.

[0023] According to another aspect of the present disclosure, a method for preparing the above-mentioned semiconductor structure is provided, comprising:

[0024] Providing a substrate, forming a plurality of initial active pillars in the substrate that are spaced apart along a first direction and a second direction, wherein the plurality of initial active pillars all extend along a third direction; the first direction intersects the second direction and is perpendicular to the third direction;

[0025] generating an epitaxial structure on a top surface of the initial active pillar by epitaxial growth;

[0026] depositing a metal layer to cover the epitaxial structure;

[0027] Performing a thermal annealing step to react and obtain a capacitor contact structure, with the unreacted initial active pillar and the epitaxial structure serving as the active pillar of the semiconductor structure;

[0028] The top surface of the capacitor contact structure is non-planar, and a projected area of ​​the capacitor contact structure on a plane perpendicular to the third direction is larger than a projected area of ​​the active pillar on a plane perpendicular to the third direction.

[0029] In one embodiment, the top surface of the epitaxial structure is non-planar, and a projected area of ​​the epitaxial structure on a plane perpendicular to the third direction is larger than a projected area of ​​the initial active pillar on a plane perpendicular to the third direction.

[0030] In one embodiment, the top surface of the capacitor contact structure and the top surface of the epitaxial structure are arc-shaped surfaces, and the first contact surface of the active pillar contacting the capacitor contact structure is an arc-shaped surface protruding toward the capacitor contact structure.

[0031] In one embodiment, the preparation method further includes forming a first isolation structure between active pillars adjacent to each other along a first direction, and forming a first gap in the first isolation structure.

[0032] In one embodiment, the bottom surface of the epitaxial structure is flush with the top surface of the first isolation structure, and the first contact surface of at least a portion of the active pillars in contact with the capacitor contact structure is higher than the top surface of the first isolation structure.

[0033] In one embodiment, the preparation method further comprises: removing the unreacted metal layer after performing the thermal annealing step.

[0034] In one embodiment, the metal layer is made of Co or Ti, and the epitaxial structure is made of single crystal silicon.

[0035] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0037] FIG1 shows a top perspective view of a substrate of a semiconductor structure provided by an embodiment of the present disclosure;

[0038] FIG2 shows a cross-sectional view of the semiconductor structure at point aa corresponding to FIG1 according to an embodiment of the present disclosure;

[0039] FIG3 shows a cross-sectional view of the semiconductor structure taken at position cc of FIG1 according to an embodiment of the present disclosure.

[0040] FIG4 shows a schematic structural diagram of a semiconductor device provided by an embodiment of the present disclosure;

[0041] FIG5 is a flowchart showing the steps of a method for preparing a semiconductor structure according to an embodiment of the present disclosure;

[0042] 6 , 8 , 10 , 12 , 14 , and 16 sequentially illustrate cross-sectional views at point aa during the preparation process of the semiconductor structure according to an embodiment of the present disclosure;

[0043] 7 , 9 , 11 , 13 , 15 , and 17 sequentially show cross-sectional views at point cc during the preparation process of the semiconductor structure provided by an embodiment of the present disclosure corresponding to FIG. 1 . DETAILED DESCRIPTION

[0044] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present disclosure. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0045] As the size of transistor units integrated on the substrate of semiconductor devices gradually decreases, 4F transistors with vertical channels are gradually proposed. 2 (F represents the minimum feature size) vertical transistor structure, compared to the planar 6F 2 Architecture transistor, 4F 2 The area of ​​the vertical transistor unit of the architecture can be reduced by about 30%.

[0046] However, in existing semiconductor structures with vertical transistors, the contact resistance between the active pillars of the vertical transistors and the capacitor structure is relatively high, which limits the transmission rate of the vertical transistors and affects the performance of the semiconductor structure.

[0047] In view of this, the embodiments of the present disclosure provide a semiconductor structure, a semiconductor device, and a method for preparing a semiconductor structure. The semiconductor structure sets a capacitor contact structure between the active column and the capacitor structure, reduces the line width effect during the formation of the capacitor contact structure, increases the contact area between the capacitor contact structure and the active column, and increases the contact area between the capacitor structure and the capacitor contact structure, thereby reducing the resistance between the capacitor structure and the active column, thereby improving the transmission rate of the vertical transistor and improving the performance of the semiconductor structure.

[0048] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0049] 1 is a top perspective view of a substrate of a semiconductor structure provided by an embodiment of the present disclosure; FIG. 2 is a cross-sectional view corresponding to point aa of the semiconductor structure in FIG. 1 ; and FIG. 3 is a cross-sectional view corresponding to point cc of the semiconductor structure in FIG. 1 .

[0050] 1 , in one embodiment, a semiconductor structure 100 may include:

[0051] A substrate 110 is formed with a plurality of active pillars 120 arranged in a first direction and a second direction, wherein the plurality of active pillars 120 extend along a third direction; the first direction intersects the second direction and is perpendicular to the third direction;

[0052] Continuing with FIG. 1 , illustratively, the first direction and the second direction may be perpendicular to each other, the first direction being, for example, the Y direction in FIG. 1 , the second direction being, for example, the X direction in FIG. 1 , and the third direction being, for example, the Z direction in FIG. 1 , which is the thickness direction of the substrate 110. In other embodiments, the first and second directions may not be perpendicular, for example, the angle between the first and second directions may be an acute angle. The material of the substrate 110 may be, for example, single crystal silicon, polycrystalline silicon, amorphous silicon, or silicon on insulator (SOI). In addition, the material of the substrate 110 may include, but is not limited to, silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride compounds, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. The active pillars 120 in the substrate 110 are arranged in an array and extend in the thickness direction of the substrate 110, i.e., the Z direction. The cross-section of the active pillars 120 can be circular, square, or elliptical, etc., to improve the integration of the semiconductor structure 100, but is not limited to this. The active pillars 120 are used to form a channel region (not shown), a source region (not shown), and a drain region (not shown) of a vertical transistor.

[0053] 2 , a capacitor contact structure 170 is shown. The capacitor contact structure 170 covers the top surface of the active pillar 120 and is used to connect to the capacitor structure 190. The top surface 172 of the capacitor contact structure 170 is non-planar, and the projected area of ​​the capacitor contact structure 170 on a plane perpendicular to the third direction is larger than the projected area of ​​the active pillar 120 on a plane perpendicular to the third direction. The material of the capacitor contact structure 170 can be CoSi2 or TiSi2, both of which have excellent thermal stability and excellent electrical conductivity compared to other metal silicides. The projected area of ​​the lower electrode (not shown) of the capacitor structure 190 on a plane perpendicular to the third direction is smaller than the projected area of ​​the capacitor contact structure 170 on a plane perpendicular to the third direction, that is, the capacitor structure 190 can be completely located on the capacitor contact structure 170. The non-planar top surface 172 of the capacitor contact structure 170 maximizes the contact area between the capacitor contact structure 170 and the capacitor structure 190, thereby reducing the resistance between the capacitor contact structure 170 and the capacitor structure 190. The ratio of the projected area of ​​the capacitor contact structure 170 on the plane perpendicular to the third direction to the projected area of ​​the active column 120 on the plane perpendicular to the third direction is 1.2-2.0. The ratio cannot be too small, otherwise the lower electrode of the capacitor structure 190 cannot be completely located on the capacitor contact structure 170, thereby affecting the performance of the semiconductor structure 100, such as electrical performance; the ratio cannot be too large, otherwise the capacitor contact structures 170 will be connected to each other, causing a short circuit.

[0054] Continuing with FIG. 2 , in one embodiment, the top surface 172 of the capacitor contact structure 170 is an arcuate surface. This arcuate surface is easy to manufacture in the production process, which can reduce the process difficulty and manufacturing costs. The first contact surface 171 where the active pillar 120 contacts the capacitor contact structure 170 is an arcuate surface that protrudes toward the capacitor contact structure. The active pillar 120 protrudes toward the capacitor contact structure 170, increasing the contact area between the active pillar 120 and the capacitor contact structure 170, reducing the resistance between the active pillar 120 and the capacitor contact structure 170, and thereby reducing the resistance between the active pillar 120 and the capacitor structure 190.

[0055] 2, in one embodiment, the center line 173 of the active pillar 120 substantially overlaps with the center line 174 of the capacitor contact structure 170. The center line 173 of the active pillar 120 and the center line 174 of the capacitor contact structure 170 can completely overlap, or they can substantially overlap, which means there is a process error. In other words, the center line 173 of the active pillar 120 and the center line 174 of the capacitor contact structure 170 substantially overlap to ensure that the capacitor structure 190 is located directly above the active pillar 120, that is, a 4F 2 (F represents the minimum feature size) vertical transistor structure, compared to the planar 6F 2 Architecture transistor, 4F 2 The area of ​​the vertical transistor unit of the architecture can be reduced by about 30%.

[0056] Continuing with FIG. 2 , in one embodiment, a first isolation structure 162 is formed between adjacent active pillars 120 along a first direction, i.e., the Y direction. The first isolation structure 162 also includes a first gap 160. Referring to FIG. 3 , a second isolation structure 152 is formed between adjacent active pillars 120 along a second direction, i.e., the X direction. The top surface of the first isolation structure 162 is higher than the top surface of the second isolation structure 152. The first isolation structure material may be silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, a photoresist material, or a porous material. In this embodiment, the first isolation structure 162 is made of low-density silicon nitride to reduce stress on the active pillars 120 caused by the first isolation structure 162. The second isolation structure 152 may be made of one or more of silicon oxide, silicon nitride, silicon oxynitride, FSG (fluorine-doped silicon dioxide), BSG (boron-doped silicon dioxide), PSG (phosphorus-doped silicon dioxide), or BPSG (boron-phosphorus-doped silicon dioxide). The first isolation structure 162 and the second isolation structure 152 may be made of different materials. The first gap 160 in the first isolation structure 162 may improve the isolation effect of the first isolation structure 162 and enhance the insulation performance of the first isolation structure 162.

[0057] 2 , in one embodiment, a first contact surface 171 where at least a portion of the active pillars 120 are in contact with the capacitor contact structure 170 is higher than the top surface of the first isolation structure 162 , and a top surface 172 of the capacitor contact structure 170 is higher than the top surface of the first isolation structure 162 . In this way, the capacitor contact structure 170 can reduce the influence of the line width effect during the formation process and reduce the resistance of the capacitor contact structure itself.

[0058] As shown in FIG2 , in one embodiment, a gate structure 130 is further formed in the substrate 110. The gate structure 130 surrounds a portion of the active pillar 120, that is, the gate structure 130 surrounds the channel region of the active pillar 120. Referring to FIG1 , adjacent gate structures 130 along the second direction, i.e., the X direction, are in contact and connected to form a word line, and adjacent gate structures 130 along the first direction, i.e., the Y direction, are insulated from each other. Continuing with FIG3 , the gate structure 130 is located directly above the second isolation structure 152. A gate oxide layer 151 is further provided between the gate structure 130 and the active pillar 120. The gate oxide layer 151 may be an annular structure, i.e., the gate oxide layer 151 surrounds the entire outer wall of the channel region of the active pillar 120. Alternatively, the gate oxide layer 151 may be a semi-annular structure, i.e., the gate oxide layer 151 surrounds a portion of the outer wall of the channel region of the active pillar 120, while another portion of the outer wall of the channel region is exposed outside the gate oxide layer 151. The gate oxide layer 151 can be made of one or more of silicon oxide, FSG (fluorine-doped silicon dioxide), BSG (boron-doped silicon dioxide), PSG (phosphorus-doped silicon dioxide), or BPSG (boron-phosphorus-doped silicon dioxide). A third isolation structure 153 is formed between adjacent active pillars 120 along the second direction, i.e., the X direction. The third isolation structure 153 is directly above the gate structure 130. The material of the third isolation structure 153 can be silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, a photoresist material, or a porous material. In this embodiment, the third isolation structure 153 and the first isolation structure 162 are made of the same material, i.e., silicon nitride. As shown in FIG1 , a bitline structure 140 is also formed within the substrate 110. The bitline structure 140 is located on a side of the substrate 110 that is away from the active pillars 120. The bitline structure 140 extends along the first direction, i.e., the Y direction, and adjacent bitline structures 140 along the second direction, i.e., the X direction, are insulated from each other. As shown in FIG3 , the bitline structure 140 is electrically connected to the active pillar 120. Furthermore, the bitline structure 140 is connected to a first pad located on the side of the substrate 110 that faces away from the active pillar 120 via a via structure (not shown), facilitating subsequent bonding steps. A second gap 161 is provided between adjacent bitline structures 140 and within the second isolation structure 152. This gap 161 improves the isolation performance of the second isolation structure 152 and prevents electrical leakage from the bitline structure 140.

[0059] 3 , in one embodiment, the semiconductor structure 100 further includes: an insulating layer 180, the insulating layer 180 covering the top surface of the first isolation structure 162; and the capacitor contact structures 170 adjacent along the first direction, i.e., the Y direction, and the second direction, i.e., the X direction, are isolated by the insulating layer 180. At the same time, the insulating layer 180 also covers the top surface of the third isolation structure 153 and the top surface of the capacitor contact structure 170. Thus, during the subsequent preparation process of the capacitor structure 190, the insulating layer 180 can serve as a support layer for the capacitor structure 190, thereby improving the stability of the capacitor structure 190. The material of the insulating layer 180 can be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride. In this embodiment, the material of the insulating layer 180 can be the same as that of the third isolation structure 153 and / or the first isolation structure 162. This improves the bonding performance between the layers and avoids delamination in subsequent steps, thereby affecting the performance of the semiconductor structure 100.

[0060] Continuing with FIG. 2 , capacitor structure 190 is located on capacitor contact structure 170; the second contact surface between capacitor structure 190 and capacitor contact structure 170 is an arcuate surface. In other words, the second contact surface between capacitor structure 190 and capacitor contact structure 170 is actually a portion of top surface 172 of the capacitor contact structure. Thus, the second contact surface between capacitor structure 190 and capacitor contact structure 170 is an arcuate surface, which increases the contact area between capacitor structure 190 and capacitor contact structure 170 and reduces the resistance between capacitor structure 190 and capacitor contact structure 170. Furthermore, because capacitor contact structure 170 has a sufficiently large cross-section, capacitor structure 190 can be completely located on capacitor contact structure 170, avoiding the problem of damage to third isolation structure 153 when etching to obtain capacitor structure 190 due to capacitor contact structure 170 being too small, thereby improving the stability and electrical performance of capacitor structure 190.

[0061] Based on the above embodiments, the present disclosure further provides a semiconductor device, which is described in detail below.

[0062] FIG4 shows a schematic structural diagram of a semiconductor device provided by an embodiment of the present disclosure;

[0063] As shown in Figure 4, in one embodiment, a semiconductor device 300 is obtained by bonding the above-mentioned semiconductor structure 100 to the target wafer 200. The semiconductor device 300 can be a memory device or a non-memory device. The memory device can include, for example, a dynamic random access memory (DRAM), a static random access memory (SRAM), a flash memory, an electrically erasable programmable read-only memory (EEPROM), a phase change random access memory (PRAM), or a magnetoresistive random access memory (MRAM). The non-memory device can be a logic device (such as a microprocessor, a digital signal processor, or a microcontroller) or a device similar thereto. The target wafer 200 has CMOS transistors, etc., for example, the target wafer 200 contains semiconductor devices 300 such as peripheral region transistors in a DRAM, etc. The semiconductor structure 100 and the target wafer 200 may be bonded by bump bonding, fusion bonding, hybrid bonding, etc. The semiconductor structure 100 and the target wafer 200 may also be bonded by chip to chip bonding or wafer on wafer bonding.

[0064] In one embodiment, the semiconductor structure 100 and the target wafer 200 can be bonded using a hybrid bonding method. As shown in FIG4 , the semiconductor structure 100 leads internal electrical signals to a first pad 101 through a through-hole structure (via) (not shown), and the target wafer 200 leads internal electrical signals to a second pad 201 through a through-hole structure (via) (not shown). The first pad 101 is isolated by a first dielectric layer 102, and the second pad 201 is isolated by a second dielectric layer 202. During an annealing process, hybrid bonding between the semiconductor structure 100 and the target wafer 200 is achieved. The first pad 101 and the second pad 201 can be made of the same material, such as metal. For example, the metal can be copper, gold, or aluminum. The first dielectric layer 102 and the second dielectric layer 202 can be made of the same material, such as insulating material. For example, the insulating material can be silicon nitride Si3N4, silicon dioxide SiO2, silicon carbonitride SiCN, silicon oxynitride SiON, hafnium oxide HfO, or zirconium oxide ZrO.

[0065] On the basis of the above embodiments, the present disclosure further provides a method for preparing a semiconductor structure (hereinafter referred to as a preparation method), which is used to prepare the above semiconductor structure 100. The preparation method is described in detail below.

[0066] FIG5 is a flowchart of the steps of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure; FIG6, FIG8, FIG10, FIG12, FIG14, and FIG16 are cross-sectional views corresponding to the position aa during the fabrication process of the semiconductor structure of FIG1; and FIG7, FIG8, FIG11, FIG13, FIG15, and FIG17 are cross-sectional views corresponding to the position cc during the fabrication process of the semiconductor structure of FIG1. ​​In other words, FIG6 and FIG7, FIG8 and FIG9, FIG10 and FIG11, FIG12 and FIG13, FIG14 and FIG15, and FIG16 and FIG17 are cross-sectional views of the same structure from different perspectives.

[0067] 5 , the method for preparing a semiconductor structure includes:

[0068] S100: Provide a substrate 110, and form a plurality of initial active pillars 121 in the substrate 110, spaced apart along a first direction and a second direction. The plurality of initial active pillars 121 extend along a third direction. The first direction intersects with the second direction and is perpendicular to the third direction. For example, the first direction and the second direction may be perpendicular to each other, the first direction being, for example, the Y direction in FIG. 1 , the second direction being, for example, the X direction in FIG. 1 , and the third direction being, for example, the Z direction in FIG. 1 , i.e., the thickness direction of the substrate 110. In other embodiments, the first and second directions may not be perpendicular, for example, the angle between the first and second directions may be an acute angle.

[0069] As shown in FIG6 , the material of substrate 110 can be, for example, single crystal silicon, polycrystalline silicon, amorphous silicon, or silicon on insulator (SOI). Alternatively, the material of substrate 110 can include, but is not limited to, silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride compounds, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Initial active pillars 121 within substrate 110 are arranged in an array and extend in the thickness direction of substrate 110, i.e., the Z-direction. The cross-section of initial active pillars 121 can be circular, square, or elliptical to improve the integration density of semiconductor structure 100, but is not limited to these.

[0070] Continuing with FIG. 6 , in one embodiment, first isolation structures 162 are formed between adjacent initial active pillars 121 along a first direction, i.e., the Y direction. First isolation structures 162 also have first gaps 160. Referring to FIG. 7 , second isolation structures 152 are formed between adjacent initial active pillars 121 along a second direction, i.e., the X direction. The top surface of the first isolation structure 162 is higher than the top surface of the second isolation structure 152. The first isolation structure material may be silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, a photoresist material, or a porous material. In this embodiment, the first isolation structure 162 is made of low-density silicon nitride to reduce stress on the initial active pillars 121 from the first isolation structure 162. The second isolation structure 152 may be made of one or more of silicon oxide, silicon nitride, silicon oxynitride, FSG (fluorine-doped silicon dioxide), BSG (boron-doped silicon dioxide), PSG (phosphorus-doped silicon dioxide), or BPSG (boron-phosphorus-doped silicon dioxide). The first isolation structure 162 and the second isolation structure 152 may be made of different materials. The first gap 160 in the first isolation structure 162 may improve the isolation effect of the first isolation structure 162 and enhance the insulation performance of the first isolation structure 162.

[0071] 6 , in one embodiment, a gate structure 130 is further formed in the substrate 110. The gate structure 130 surrounds a portion of the initial active pillar 121. Adjacent gate structures 130 along the second direction, i.e., the X direction, are in contact with each other to form a word line. Adjacent gate structures 130 along the first direction, i.e., the Y direction, are insulated from each other. Continuing with FIG7 , the gate structure 130 is located directly above the second isolation structure 152. A gate oxide layer 151 is further provided between the gate structure 130 and the initial active pillar 121. The gate oxide layer 151 may be a ring-shaped structure. The gate oxide layer 151 can be made of one or more of silicon oxide, FSG (fluorine-doped silicon dioxide), BSG (boron-doped silicon dioxide), PSG (phosphorus-doped silicon dioxide), or BPSG (boron-phosphorus-doped silicon dioxide). A third isolation structure 153 is formed between adjacent initial active pillars 121 along the second direction, i.e., the X direction. The third isolation structure 153 is directly above the gate structure 130. The material of the third isolation structure 153 can be silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, a photoresist material, or a porous material. In this embodiment, the third isolation structure 153 and the first isolation structure 162 are made of the same material, i.e., silicon nitride.

[0072] S200 , forming an epitaxial structure 122 on the top surface of the initial active pillar 121 by epitaxial growth;

[0073] 8-9 , an epitaxial structure 122 is generated on the top surface of the initial active column 121. The epitaxial structure 122 may be single crystal silicon. The specific preparation steps are as follows: using epitaxial equipment, at a certain temperature, such as above 500 degrees Celsius, and a certain pressure, such as less than 10 Torr, silane and hydrogen chloride gas are introduced to gradually generate an epitaxial structure 122 on the top surface of the initial active column 121. The epitaxial structure has a mushroom head shape.

[0074] Continuing with reference to FIG8 , in one embodiment, the top surface of the epitaxial structure 122 is non-planar, and the projected area of ​​the epitaxial structure 122 on a plane perpendicular to the third direction is larger than the projected area of ​​the initial active column 121 on a plane perpendicular to the third direction. This can benefit the electrical performance of the capacitor contact structure 170 obtained after subsequent reactions.

[0075] 8 , in one embodiment, the top surface of the epitaxial structure 122 is an arc-shaped surface, and the bottom surface of the epitaxial structure 122 is flush with the top surface of the first isolation structure 162 .

[0076] S300 , depositing a metal layer 123 to cover the epitaxial structure 122 ;

[0077] 10-11 , a metal layer 123 is deposited on the epitaxial structure 122 . The metal layer 123 may be made of Co or Ti, both of which have excellent thermal stability.

[0078] Compared with the prior art method of etching back the first isolation structure 162 and then depositing the metal layer 123, the present disclosure first generates the epitaxial structure 122 on the top surface of the initial active column 121 through epitaxial growth, thereby avoiding the damage to the first gap 160 caused by etching back the first isolation structure 162 in the prior art, and further avoiding the deposition of impurities in the first gap 160 in subsequent steps, thereby improving the performance stability of the semiconductor structure 100.

[0079] S400, performing a thermal annealing step to react and obtain a capacitor contact structure 170, wherein the unreacted initial active pillar 121 and the epitaxial structure 122 serve as the active pillar 120 of the semiconductor structure; wherein the top surface of the capacitor contact structure 170 is non-planar, and the projected area of ​​the capacitor contact structure 170 on a plane perpendicular to the third direction is larger than the projected area of ​​the active pillar 120 on a plane perpendicular to the third direction.

[0080] 14-15 , a thermal annealing step is performed. At a first temperature, metal layer 123 reacts with epitaxial structure 122 and initial active pillar 121 to form capacitor contact structure 170. This thermal annealing step is the first annealing step. For example, metal layer 123 is made of Co or Ti, and epitaxial structure 122 and initial active pillar 121 are both made of single crystal silicon. The two react to form capacitor contact structure 170. CoSi2 or TiSi2 can be used, both of which have excellent thermal stability and excellent electrical conductivity. The unreacted initial active pillar 121 and the epitaxial structure 122 serve as the active pillar 120 of the semiconductor structure 100; in the prior art, the silicon that reacts with the metal layer is sandwiched between the first isolation structure, and the silicon sandwiched between the first isolation structure during the thermal annealing step will have a serious line width effect, that is, the resistance of the obtained metal silicide is too high, while the metal layer 123 disclosed in the present invention mainly reacts with the epitaxial structure 122, and the epitaxial structure 122 is not sandwiched between the first isolation structure 162, thereby largely avoiding the line width effect, and the resistance of the obtained metal silicide is reduced.

[0081] Continuing with reference to FIG14 , the top surface 172 of the capacitor contact structure 170 is non-planar, so that the contact surface between the capacitor contact structure 170 and the capacitor structure 190 is as large as possible, thereby reducing the resistance between the capacitor contact structure 170 and the capacitor structure 190. The projected area of ​​the capacitor contact structure 170 on a plane perpendicular to the third direction is larger than the projected area of ​​the active pillar 120 on a plane perpendicular to the third direction. The ratio of the projected area of ​​the capacitor contact structure 170 on a plane perpendicular to the third direction to the projected area of ​​the active pillar 120 on a plane perpendicular to the third direction is 1.2-2.0. The ratio cannot be too small, otherwise the lower electrode of the capacitor structure 190 cannot be completely seated on the capacitor contact structure 170. The ratio cannot be too large, otherwise the capacitor contact structures 170 will be connected to each other, causing a short circuit.

[0082] Continuing with FIG. 14 , in one embodiment, the top surface 172 of the capacitor contact structure 170 is an arcuate surface. This arcuate surface is easy to manufacture during the production process, which can reduce the process difficulty and manufacturing costs. The first contact surface 171 where the active pillar 120 contacts the capacitor contact structure 170 is an arcuate surface that protrudes toward the capacitor contact structure. The active pillar 120 protrudes toward the capacitor contact structure 170, increasing the contact area between the active pillar 120 and the capacitor contact structure 170 and reducing the resistance between the active pillar 120 and the capacitor contact structure 170.

[0083] Continuing to refer to FIG14 , in one embodiment, the first contact surface 171 where at least a portion of the active pillars 120 contact the capacitor contact structure 170 is higher than the top surface of the first isolation structure 162 , which is an inevitable result of the manufacturing method disclosed herein.

[0084] In one embodiment, the method for fabricating the semiconductor structure 100 includes: removing the unreacted metal layer 123 after performing a thermal annealing step.

[0085] 12-13 , the unreacted metal layer 123 is removed by pickling with, for example, sulfuric acid, to prevent the capacitor contact structures 170 from contacting each other, thereby preventing the capacitor contact structures 170 from short-circuiting.

[0086] In one embodiment, the method for fabricating the semiconductor structure 100 includes: after removing the unreacted metal layer 123, performing a second thermal annealing step. Specifically, the second thermal annealing step is performed at a second temperature, wherein the second temperature is greater than the first temperature of the first thermal annealing step. The two thermal annealing steps can further reduce the resistance of the capacitor contact structure 170.

[0087] In one embodiment, the method for preparing a semiconductor structure further includes: depositing an insulating layer 180 and preparing a capacitor structure 190 .

[0088] 16 , the insulating layer 180 covers the top surface of the first isolation structure 162; the capacitor contact structures 170 adjacent along the first direction, i.e., the Y direction, and the second direction, i.e., the X direction, are isolated by the insulating layer 180. At the same time, as shown in FIG17 , the insulating layer 180 also covers the top surface of the third isolation structure 153 and the top surface of the capacitor contact structure 170. In this way, in the subsequent preparation process of the capacitor structure 190, the insulating layer 180 can serve as a support layer for the capacitor structure 190, thereby improving the stability of the capacitor structure 190. The material of the insulating layer 180 can be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride. In this embodiment, the material of the insulating layer 180 can be the same as the material of the third isolation structure 153 and / or the first isolation structure 162. In this way, the bonding performance between the layers is improved, and delamination in subsequent steps is avoided, thereby affecting the performance of the semiconductor structure 100.

[0089] As shown in FIG16 , a capacitor structure 190 is fabricated on the capacitor contact structure 170; the second contact surface between the capacitor structure 190 and the capacitor contact structure 170 is an arcuate surface. That is, the second contact surface between the capacitor structure 190 and the capacitor contact structure 170 is actually a portion of the top surface 172 of the capacitor contact structure. Thus, the second contact surface between the capacitor structure 190 and the capacitor contact structure 170 is an arcuate surface, which increases the contact area between the capacitor structure 190 and the capacitor contact structure 170 and reduces the resistance between the capacitor structure 190 and the capacitor contact structure 170. Furthermore, because the capacitor contact structure 170 has a sufficiently large cross-section, the capacitor structure 190 can be completely seated on the capacitor contact structure 170, avoiding the problem of damage to the third isolation structure 153 when etching the capacitor structure 190 due to the capacitor contact structure 170 being too small, thereby improving the stability and electrical performance of the capacitor structure 190.

[0090] In one embodiment, the method for fabricating a semiconductor structure further includes: fabricating a bit line structure 140 , and fabricating a second gap 161 .

[0091] As shown in Figures 2-3, substrate 110 is thinned to expose active pillars 120, and bitline structures 140 are deposited. Bitline structures 140 extend along a first direction, i.e., the Y direction, and adjacent bitline structures 140 are insulated from each other along a second direction, i.e., the X direction. Bitline structures 140 are electrically connected to active pillars 120, thereby forming through-hole structures (vias) (not shown) and first pads on the side of substrate 110 facing away from the direction in which active pillars 120 extend. Electrical signals are routed to the first pads through the through-hole structures (vias) (not shown), facilitating subsequent bonding steps. Furthermore, second gaps 161 are formed between adjacent bitline structures 140 and within second isolation structures 152. Second gaps 161 improve the isolation performance of second isolation structures 152 and prevent leakage from bitline structures 140.

[0092] The above-mentioned method for preparing the semiconductor structure simplifies the existing process, reduces the line width effect during the formation of the capacitor contact structure, avoids the generation of metal residual defects, and thus avoids the destruction of the first gap. It also increases the contact area between the capacitor contact structure and the active column, and increases the contact area between the capacitor structure and the capacitor contact structure, thereby reducing the resistance between the capacitor structure and the active column, improving the transmission rate of the vertical transistor, and thus improving the performance of the semiconductor structure.

[0093] In the description of the present disclosure, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0094] In the description of the present disclosure, it should be understood that the terms "including" and "having" and any variations thereof used herein are intended to cover non-exclusive inclusions. For example, a process, method, system, product or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products or apparatuses.

[0095] Unless otherwise expressly specified or limited, the terms "mounted," "connected," "connected," "fixed," etc. should be interpreted broadly. For example, they may refer to fixed connections, removable connections, or integration. They may refer to direct connections or indirect connections through an intermediary, and they may involve internal connections between two components or interactions between two components. Those skilled in the art will understand the specific meanings of these terms in the present invention based on the specific circumstances. Furthermore, the terms "first," "second," etc., etc., are used for descriptive purposes only and should not be construed to indicate or imply relative importance or implicitly specify the quantity of the technical features indicated.

[0096] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A semiconductor structure (100), include: A substrate (110), wherein a plurality of active pillars (120) are formed in the substrate (110) and are arranged at intervals along a first direction and a second direction, and the plurality of active pillars (120) all extend along a third direction; the first direction intersects with the second direction and are both perpendicular to the third direction; a capacitor contact structure (170), the capacitor contact structure (170) covering the top surface of the active pillar (120) and used for connecting to the capacitor structure (190); The top surface of the capacitor contact structure (170) is non-planar, and the projected area of ​​the capacitor contact structure (170) on a plane perpendicular to the third direction is larger than the projected area of ​​the active column (120) on a plane perpendicular to the third direction.

2. The semiconductor structure according to claim 1, wherein The top surface of the capacitor contact structure (170) is an arc-shaped surface, and the first contact surface (171) of the active column (120) in contact with the capacitor contact structure (170) is an arc-shaped surface protruding toward the capacitor contact structure (170).

3. The semiconductor structure according to claim 1, wherein The center line (173) of the active pillar (120) substantially overlaps with the center line (174) of the capacitor contact structure (170).

4. The semiconductor structure according to claim 1, wherein A first isolation structure (162) is formed between the active pillars (120) adjacent to each other along the first direction, and a first gap (160) is also present in the first isolation structure (162).

5. The semiconductor structure according to claim 4, wherein A first contact surface (171) where at least a portion of the active pillar (120) contacts the capacitor contact structure (170) is higher than a top surface of the first isolation structure (162). The semiconductor structure according to claim 1 , wherein: A gate structure (130) is also formed in the substrate (110), and the gate structure (130) surrounds a portion of the active pillar (120). The gate structures (130) adjacent to each other along the second direction are in contact with each other, and the gate structures (130) adjacent to each other along the first direction are insulated from each other. A bit line structure (140) is also formed in the substrate (110), and the bit line structure (140) is located on a side of the substrate (110) away from the extension direction of the active pillar (120). The bit line structure (140) extends along the first direction, and the bit line structures (140) adjacent to each other along the second direction are insulated from each other.

7. The semiconductor structure according to claim 1, wherein The semiconductor structure further comprises: An insulating layer (180), the insulating layer (180) covers the top surface of the first isolation structure (162); the capacitor contact structures (170) adjacent to each other along the first direction and the second direction are isolated by the insulating layer (180). A capacitor structure (190) is located on the capacitor contact structure (170); a second contact surface of the capacitor structure (190) in contact with the capacitor contact structure (170) is an arc-shaped surface.

8. A semiconductor device (300), wherein: The semiconductor structure (100) according to any one of claims 1 to 7 is bonded to a target wafer (200) to obtain the semiconductor structure (100).

9. A method for preparing a semiconductor structure, wherein: The preparation method comprises: A substrate (110) is provided, and a plurality of initial active pillars (121) are formed in the substrate (110) and are arranged at intervals along a first direction and a second direction, wherein the plurality of initial active pillars (121) all extend along a third direction; the first direction intersects with the second direction and is perpendicular to the third direction; generating an epitaxial structure (122) on the top surface of the initial active pillar (121) by epitaxial growth; depositing a metal layer (123) to cover the epitaxial structure (122); Performing a thermal annealing step to react and obtain a capacitor contact structure (170), wherein the unreacted initial active pillar (121) and the epitaxial structure (122) serve as the active pillar (120) of the semiconductor structure; The top surface of the capacitor contact structure (170) is non-planar, and the projected area of ​​the capacitor contact structure (170) on a plane perpendicular to the third direction is larger than the projected area of ​​the active column (120) on a plane perpendicular to the third direction.

10. The preparation method according to claim 9, wherein The top surface of the epitaxial structure (122) is non-planar, and the projection area of ​​the epitaxial structure (122) on a plane perpendicular to the third direction is larger than the projection area of ​​the initial active column (121) on a plane perpendicular to the third direction.

11. The preparation method according to claim 10, wherein The top surface of the capacitor contact structure (170) and the top surface of the epitaxial structure (122) are arc-shaped surfaces, and the first contact surface (171) of the active column (120) in contact with the capacitor contact structure (170) is an arc-shaped surface protruding toward the capacitor contact structure (170).

12. The preparation method according to claim 9, wherein The preparation method further comprises forming a first isolation structure (162) between the active pillars (120) adjacent to each other along the first direction, and forming a first gap (160) in the first isolation structure (162).

13. The preparation method according to claim 12, wherein The bottom surface of the epitaxial structure (122) is flush with the top surface of the first isolation structure (162), and the first contact surface (171) where at least part of the active pillar (120) contacts the capacitor contact structure (170) is higher than the top surface of the first isolation structure (162).

14. The preparation method according to claim 9, wherein The preparation method further comprises: after performing the thermal annealing step, removing the unreacted metal layer (123).

15. The preparation method according to claim 9, wherein The material of the metal layer (123) is Co or Ti, and the material of the epitaxial structure (122) is single crystal silicon.

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