Distributed computing system, pcie apparatus, and method for generating interconnection topological structure information

Abstract

A distributed computing system, a PCIe apparatus and a method for generating interconnection topological structure information. The distributed computing system comprises a plurality of PCIe apparatuses and a main control apparatus, the plurality of PCIe apparatuses respectively comprise a plurality of ports, and the main control apparatus is used for establishing point-to-point links between the plurality of ports of the plurality of PCIe apparatuses. A first portion of the plurality of ports operates in a root port mode, and a second portion of the plurality of ports operates in an endpoint mode. The first portion of the plurality of ports and the second portion of the plurality of ports are located in different PCIe apparatuses. The main control apparatus respectively inputs corresponding root port apparatus identification codes and corresponding root port identification codes into the first portion of the plurality of ports, and the first portion of the plurality of ports respectively outputs the corresponding root port apparatus identification codes and the corresponding root port identification codes to the second portion of the plurality of ports. The main control apparatus obtains information of a plurality of link pairs by means of reading the second portion of the plurality of ports, so as to generate interconnection topological structure information.

Description

Distributed computing system, PCIe device, and method for generating interconnection topology information

[0001] This application claims priority to Chinese Patent Application No. 202410383242.7 filed on April 1, 2024, and the contents of the above-mentioned Chinese patent application disclosure are hereby incorporated by reference in their entirety as a part of this application. Technical Field

[0002] The present disclosure relates to a distributed computing system, a PCIe device, and a method for generating interconnection topology information. Background Art

[0003] Multiple computing devices in a distributed computing system are typically interconnected using daughterboards or universal base boards (UBBs). It's worth noting that different daughterboards or UBBs correspond to different interconnection topologies, so the host controller must adapt the configuration based on the actual physical connection method to generate information about the multi-card interconnection topology. However, due to the existence of multiple daughterboards or UBBs, traditional distributed computing systems often require extensive manual adaptation.

[0004] In addition, when interconnection settings between multiple computing devices are temporarily changed, such as link speed or link bandwidth, traditional distributed computing systems often require a long time to implement because they use complex adaptation methods to generate a multi-card interconnection topology. Summary of the Invention

[0005] The present disclosure is directed to a distributed computing system, a PCIe device, and a method for generating interconnection topology information, which can effectively generate interconnection topology information.

[0006] According to an embodiment of the present disclosure, a distributed computing system includes multiple PCIe devices and a master control device. Each of the multiple PCIe devices includes multiple ports. The master control device is coupled to the multiple PCIe devices and is configured to establish point-to-point links between the multiple ports of the multiple PCIe devices. A first portion of the multiple ports operates in root port mode, and a second portion of the multiple ports operates in terminal mode. The master control device inputs corresponding root port device identifiers and corresponding root port identifiers into the first portions of the multiple ports, respectively, and the first portions of the multiple ports output the corresponding root port device identifiers and corresponding root port identifiers to the second portions of the multiple ports. The first portion of the multiple ports and the second portion of the multiple ports are located in different PCIe devices. The master control device obtains multiple link pair information by reading the second portions of the multiple ports to generate interconnection topology information. Each of the multiple link pair information includes the corresponding root port device identifier, the corresponding root port identifier, the corresponding terminal device identifier, and the corresponding terminal port identifier.

[0007] In the above embodiment, the plurality of PCIe devices respectively include a plurality of root port circuits and a plurality of end port circuits corresponding to the plurality of ports. At least one of the plurality of root port circuits is configured to store the corresponding root port device identifier and the corresponding root port identifier, and at least one of the plurality of end port circuits is configured to store the corresponding end device identifier and the corresponding end port identifier.

[0008] In the above embodiment, the plurality of root port circuits each include a first register and a flip-flop, wherein the first register is configured to store the corresponding root port device identifier and the corresponding root port identifier, and the flip-flop is configured to determine whether to output the corresponding root port device identifier and the corresponding root port identifier.

[0009] In the above embodiment, each of the plurality of terminal port circuits includes a second register configured to store the corresponding root port device identifier and the corresponding root port identifier.

[0010] In the above embodiment, in response to the master control device determining that the first portion of the plurality of ports operates in the root port mode, the master control device writes the corresponding root port device identification code and the corresponding root port identification code to the first register of the corresponding port, and triggers the corresponding port to write the corresponding root port device identification code and the corresponding root port identification code to the second register of the peer port.

[0011] In the above embodiment, in response to the main control device determining that the second part of the plurality of ports operates in terminal mode, the main control device records the current terminal device identification code and the current terminal port identification code into the initial list.

[0012] In the above embodiment, the main control device sequentially reads the second registers of the plurality of corresponding ports according to the initial list to obtain a plurality of link pair information and generate interconnection topology information.

[0013] In the above embodiment, the master device updates the values ​​of the first registers of the ports of the PCIe devices to the corresponding device identification codes and port identification codes. The master device initializes point-to-point link settings between the PCIe devices and performs link training.

[0014] In the above embodiment, the master control device enumerates the plurality of PCIe devices to obtain the plurality of addresses of the plurality of PCIe devices, and the master control device uses the data of the plurality of addresses as the low-order bit data of the device identification code.

[0015] In the above embodiment, the high-order bits of the device identification code include the master device address of the master device.

[0016] According to an embodiment of the present disclosure, a PCIe device of the present disclosure includes multiple ports, multiple root port circuits, and multiple terminal port circuits. The root port circuit is coupled to the multiple ports. The terminal port circuit is coupled to the multiple ports. In response to at least one of the multiple ports operating in root port mode, at least one of the multiple ports receives a root port device identifier and a root port identifier corresponding to the PCIe device provided by a master control device, and stores the root port device identifier and the corresponding root port identifier corresponding to the PCIe device in at least one of the multiple root port circuits. In response to at least one of the multiple ports operating in terminal port mode, at least one of the multiple ports receives a root port device identifier and a root port identifier corresponding to another PCIe device, and stores the root port device identifier and the corresponding root port identifier corresponding to the other PCIe device in at least one of the multiple terminal port circuits.

[0017] According to an embodiment of the present disclosure, the method for generating interconnection topology information includes the following steps: establishing point-to-point links between multiple ports of multiple PCIe devices; inputting corresponding root port device identifiers and corresponding root port identifiers into first parts of the multiple ports, respectively, wherein the first parts of the multiple ports operate in root port mode; outputting the corresponding root port device identifiers and the corresponding root port identifiers to second parts of the multiple ports through the first parts of the multiple ports, respectively, wherein the second parts of the multiple ports operate in terminal mode, and the first parts of the multiple ports and the second parts of the multiple ports are located in different PCIe devices; and reading the second parts of the multiple ports to obtain multiple link pair information to generate the interconnection topology information; wherein each of the multiple link pair information includes the corresponding root port device identifier, the corresponding root port identifier, the corresponding terminal device identifier, and the corresponding terminal port identifier.

[0018] In the above embodiment, the plurality of PCIe devices respectively include a plurality of root port circuits and a plurality of terminal port circuits corresponding to the plurality of ports;

[0019] In the above embodiment, at least one of the plurality of root port circuits is used to store the corresponding root port device identifier and the corresponding root port identifier, and at least one of the plurality of end port circuits is used to store the corresponding end device identifier and the corresponding end port identifier.

[0020] In the above embodiment, the plurality of root port circuits each include a first register and a flip-flop, wherein the first register is configured to store the corresponding root port device identifier and the corresponding root port identifier, and the flip-flop is configured to determine whether to output the corresponding root port device identifier and the corresponding root port identifier.

[0021] In the above embodiment, each of the plurality of terminal port circuits includes a second register configured to store the corresponding root port device identifier and the corresponding root port identifier.

[0022] In the above embodiment, the step of inputting the corresponding root port device identifier and the corresponding root port identifier into the first portion of the plurality of ports includes: in response to the first portion of the plurality of ports operating in the root port mode, writing the corresponding root port device identifier and the corresponding root port identifier into the first register of the corresponding port. The step of outputting the corresponding root port device identifier and the corresponding root port identifier to the second portion of the plurality of ports through the first portion of the plurality of ports includes: triggering the corresponding port to write the corresponding root port device identifier and the corresponding root port identifier into the second register of the peer port.

[0023] In the above embodiment, the method for generating interconnection topology information further includes the following steps: in response to the main control device determining that the second part of the plurality of ports operates in terminal mode, recording the current terminal device identification code and the current terminal port identification code into the initial list.

[0024] In the above embodiment, the step of generating the interconnection topology information includes: sequentially reading the second registers of a plurality of corresponding ports according to the initial list to obtain a plurality of link pair information, and generating the interconnection topology information.

[0025] In the above embodiment, the master device is coupled to the plurality of PCIe devices and is configured to establish point-to-point links between the plurality of ports of the plurality of PCIe devices.

[0026] In the above embodiment, the method for generating interconnection topology information also includes: updating the values ​​of the first registers of the multiple ports of the multiple PCIe devices to corresponding device identification codes and corresponding port identification codes; and initializing the point-to-point link settings between the multiple PCIe devices and performing link training.

[0027] In the above embodiment, the method for generating interconnection topology information further includes: enumerating the multiple PCIe devices to obtain multiple addresses of the multiple PCIe devices, and the master control device uses the data of the multiple addresses as the low-bit data of the device identification code; wherein the master control device is coupled to the multiple PCIe devices and is used to establish a point-to-point link between the multiple ports of the multiple PCIe devices.

[0028] Based on the above, the distributed computing system, PCIe device, and method for generating interconnection topology information disclosed herein can efficiently generate interconnection topology information between multiple ports of multiple PCIe devices.

[0029] The present disclosure will be understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that, for ease of understanding and for the sake of simplicity, the various figures in this disclosure depict only a portion of the display device, and certain components in the figures are not drawn to scale. Furthermore, the number and dimensions of components in the figures are for illustrative purposes only and are not intended to limit the scope of this disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] FIG1 is a schematic diagram of a distributed computing system according to an embodiment of the present disclosure;

[0031] FIG2 is a flow chart of generating interconnection topology information according to an embodiment of the present disclosure;

[0032] FIG3 is a schematic diagram of a distributed computing system according to an embodiment of the present disclosure;

[0033] FIG4 is a flow chart of generating interconnection topology information according to an embodiment of the present disclosure;

[0034] FIG5 is a flow chart of generating interconnection topology information according to an embodiment of the present disclosure; and

[0035] FIG6 is a schematic diagram of a distributed computing system according to an embodiment of the present disclosure.

[0036] Explanation of the accompanying drawings: 100, 600: distributed computing system; 110, 310, 611, 612: master control device; 121, 122, 621, 622: PCIe switch; 131-138, 331, 332, 631-638: PCIe device; 310, 330: root port circuit; 320, 340: terminal port circuit; 311, 331: first register; 312, 332: trigger; 321, 341: second register; P1-P7: port; EP: terminal port; S210-S240, S401-S412, S501-S506: steps. DETAILED DESCRIPTION

[0037] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0038] Throughout the specification and claims of this disclosure, certain terms are used to refer to specific components. Those skilled in the art will appreciate that electronic device manufacturers may refer to the same component by different names. This document is not intended to distinguish between components that have the same function but different names. In the following description and claims, terms such as "comprise" and "include" are open-ended and should be interpreted as meaning "including, but not limited to..."

[0039] FIG1 is a schematic diagram of a distributed computing system according to an embodiment of the present disclosure. The distributed computing system 100 includes a master control device 110, a PCIe (Peripheral Component Interconnect Express) switch 121, a PCIe switch 122, and a plurality of PCIe devices 131 to 138. In this embodiment, each of the PCIe devices 131 to 138 includes an end port EP and a plurality of ports P1 to P7. Each of the PCIe devices 131 to 138 can be coupled to the PCIe switch 121 or the PCIe switch 122 via the end port EP. Each of the PCIe devices 131 to 138 can be coupled to other PCIe devices via ports P1 to P7. In this embodiment, the PCIe devices 131 to 134 share a PCIe switch 121, and the PCIe devices 135 to 138 share a PCIe switch 122.

[0040] In one embodiment, the main control device 110 may be, for example, a central processing unit (CPU) and may be mounted on a motherboard. The PCIe devices 131-138 may be, for example, display chip cards or artificial intelligence accelerator cards, and other related computing chip cards, and may be mounted on the PCIe switches 121 and 122 of the motherboard. The PCIe devices 131-138 may include, for example, a graphics processing unit (GPU), a general-purpose graphics processing unit (GPGPU), a field programmable gate array (FPGA), a neural network processor (NPU), or an application-specific integrated circuit (ASIC) chip, but the present disclosure is not limited thereto.

[0041] In this embodiment, the host control device 110 may obtain interconnection topology information of the point-to-point links between the PCIe devices 131 - 138 , and may implement data transfer operations between the PCIe devices 131 - 138 according to the interconnection topology information.

[0042] FIG2 is a flowchart of generating interconnection topology information according to an embodiment of the present disclosure. Referring to FIG1 and FIG2 , in this embodiment, each port (P1 to P7) of the PCIe devices 131 to 138 can operate in root port mode or end point mode. It should be noted that a port operating in root port mode can write or read data to a port operating in end point mode. In this embodiment, the distributed computing system 100 can perform operations such as the following steps S210 to S240. In step S210, the master control device 110 can establish a point-to-point link between multiple ports (P1 to P7) of the PCIe devices 131 to 138. In step S220, the master control device 110 can input the corresponding root port device identifier (i.e., the current address of the PCIe device) and the corresponding root port identifier (i.e., the current port identifier of this port) into the first part of the multiple ports, wherein the first part of the multiple ports operates in root port mode.

[0043] In this embodiment, the master control device 110 can enumerate the PCIe devices 131-138 to obtain multiple addresses of the PCIe devices 131-138. The addresses can be data of the bus (Bus: 8 bits), device (Device: 5 bits), and function (Function: 3 bits). The master control device 110 can use the data of the multiple addresses as the data of the low-order bits (e.g., [15:0]) of the device identification codes of the individual PCIe devices 131-138. In addition, in the application scenario of multi-machine interconnection, the data of the high-order bits (e.g., [23:16]) of the device identification code can include the data of the master device address of the master control device 110. In this embodiment, the master control device 110 can input the above-mentioned device identification code and port identification code into the first part of the multiple ports operating in the root port mode as the corresponding root port device identification code and the corresponding root port identification code.

[0044] In step S230, the first portion of the plurality of ports respectively outputs the corresponding root port device identifier and the corresponding root port identifier to the second portion of the plurality of ports, wherein the second portion of the plurality of ports operates in terminal mode. In this embodiment, the master control device 110 may enable the first portion of the plurality of ports operating in root port mode to initiate a write operation (i.e., write data to a peer port) to output the corresponding root port device identifier and the corresponding root port identifier to a peer port, wherein the peer port is the second portion of the plurality of ports operating in terminal mode. The first portion of the plurality of ports and the second portion of the plurality of ports are located on different PCIe devices.

[0045] In step S240, the master control device 110 can obtain a plurality of link pair information by reading the second portion of the plurality of ports to generate the interconnection topology information. In this embodiment, each of the plurality of link pair information includes the corresponding root port device identifier, the corresponding root port identifier, the corresponding terminal device identifier (i.e., the current address of the PCIe device of the port operating in terminal mode), and the corresponding terminal port identifier (i.e., the port identifier of the port operating in terminal mode). Therefore, the master control device 110 can effectively generate the interconnection topology information based on the plurality of link pair information.

[0046] FIG3 is a schematic diagram of a distributed computing system according to an embodiment of the present disclosure. Referring to FIG3 , two PCIe devices are used as an example. In this embodiment, a master control device 310 is coupled to a first PCIe device 331 and a second PCIe device 332 via a PCIe switch (not shown). The first PCIe device 331 may include a port, a root port circuit 310, and a terminal port circuit 320. The second PCIe device 332 may include a port, a root port circuit 331, and a terminal port circuit 340. A port of the first PCIe device 331 is coupled to a port of the second PCIe device 332. In this embodiment, the root port circuit 310 includes a first register 311 and a trigger 312. The first register 311 is coupled to the trigger 312. The terminal port circuit 320 includes a second register 321. The root port circuit 330 includes a first register 331 and a trigger 332. The first register 331 is coupled to the trigger 332. The terminal port circuit 340 includes a second register 341.

[0047] In this embodiment, the first registers 311 and 331 may be used to store the corresponding root port device identifier and the corresponding root port identifier, and the triggers 312 and 332 may be used to determine whether to output the corresponding root port device identifier and the corresponding root port identifier. In this embodiment, the second registers 321 and 341 may be used to store the corresponding root port device identifier and the corresponding root port identifier.

[0048] Specifically, the master control device 310 may use the address of the first PCIe device 331 as the device ID of the first PCIe device 331, and may use the address of the second PCIe device 332 as the device ID of the second PCIe device 332. The master control device 310 may write the device ID and port ID of the first PCIe device 331 into the first register 311 (as the root port device ID and root port ID of the first PCIe device 331), and write the device ID and port ID of the second PCIe device 332 into the first register 331 (as the terminal device ID and terminal port ID of the second PCIe device 332). When the port of the first PCIe device 331 operates in root port mode and the port of the second PCIe device 332 operates in terminal mode, the first PCIe device 331 can output the device ID and port ID of the first PCIe device 331 stored in the first register 311 to the port of the second PCIe device 332 via the trigger 312 for storage in the second register 341. In this way, the master device 310 can read the port of the second PCIe device 332 operating in terminal mode and the second register 341 of the second PCIe device 332 to obtain link pair information. The link pair information includes the terminal device ID and terminal port ID of the second PCIe device 332, and the root port device ID and root port ID of the first PCIe device 331. The master device 310 can generate interconnection topology information based on this link pair information.

[0049] Therefore, referring again to FIG1 , the PCIe devices 131-138 in FIG1 may have multiple ports, and each of the multiple ports includes multiple root port circuits and multiple end port circuits corresponding to the multiple ports. Furthermore, at least one of the multiple root port circuits may be configured to store the corresponding root port device identifier and the corresponding root port identifier, and at least one of the multiple end port circuits may be configured to store the corresponding end device identifier and the corresponding end port identifier.

[0050] FIG4 is a flowchart of generating interconnection topology information according to an embodiment of the present disclosure. Referring to FIG1 and FIG4 , the distributed computing system 100 may also perform the following operations, S401 through S412. In step S401, the master control device 110 may enumerate multiple PCIe devices 131 through 138 to obtain multiple addresses of the PCIe devices 131 through 138. The master control device 110 may use these multiple addresses as device identification codes for the individual PCIe devices 131 through 138.

[0051] In step S402, the master control device 110 may initialize the point-to-point link settings between the PCIe devices 131 to 138. In step S403, the master control device 110 may sequentially check the status of each point-to-point link between the PCIe devices 131 to 138. In step S404, the master control device 110 may determine whether a link has been formed on the current port. If not, in step S405, the master control device 110 may check the status of other point-to-point links, or check the port of the next PCIe device. If so, in step S406, the master control device 110 may determine whether this port is operating in root port mode. If not, in step S407, in response to the master control device 110 determining that the current port is operating in terminal mode, the master control device 110 may record the current terminal device identification code and the current terminal port identification code to the initial list, and execute step S409. If so, in step S408, in response to the master control device 110 determining that the current port is operating in the root port mode, the master control device 110 may write the current root port device identifier and the current root port identifier into the first register of the corresponding port, and trigger the corresponding port to write the current root port device identifier and the current root port identifier into the second register of the opposite port.

[0052] In step S409, the master control device 110 determines whether all point-to-point links have been checked. If not, step S403 is re-executed. If so, in step S410, the system may wait for a predetermined time, such as 200 nanoseconds (ns). In step S411, the master control device 110 sequentially reads the second registers of multiple corresponding ports according to the initial list. The initial list may record the corresponding root port device identifiers and corresponding root port identifiers stored in the second registers of all ports operating in terminal mode. Therefore, in step S412, the master control device 110 can effectively obtain information about multiple link pairs to generate interconnection topology information.

[0053] FIG5 is a flowchart of generating interconnection topology information according to an embodiment of the present disclosure. Referring to FIG1 and FIG5 , the distributed computing system 100 may also perform the following operations, S501 through S506. In step S501, the master control device 110 may enumerate multiple PCIe devices 131 through 138 to obtain multiple addresses of the PCIe devices 131 through 138. The master control device 110 may use these multiple addresses as device identification codes for the individual PCIe devices 131 through 138.

[0054] In step S502, the master control device 110 may update the values ​​of the first registers of the multiple ports of all PCIe devices 131-138 to the corresponding device identification codes and port identification codes. In step S503, the master control device 110 may initialize the point-to-point link settings between the PCIe devices 131-138 and perform link training. In step S504, the master control device 110 may determine whether all end-to-end links have completed training. If not, after a delay, the judgment result of step S504 is executed again. If so, in step S505, the master control device 110 may trigger the corresponding port to write the current root port device identification code and the current root port identification code to the second register of the opposite port. In step S506, the master control device 110 may read the values ​​of the second registers of all ports to obtain multiple link pair information and generate interconnection topology information. It is worth noting that if the data read by the master control device 110 from the second register is the reset default value (0), the master control device 110 will discard the link pair information.

[0055] FIG6 is a schematic diagram of a distributed computing system according to an embodiment of the present disclosure. Referring to FIG6 , the distributed computing system 600 according to this embodiment is used to implement a multi-machine multi-card interconnection system. The distributed computing system 600 includes a master control device 611, a master control device 612, a PCIe switch 621, a PCIe switch 622, and a plurality of PCIe devices 631 to 638. In this embodiment, each of the PCIe devices 631 to 638 includes a terminal port EP and a plurality of ports P1 to P4. Each of the PCIe devices 631 to 634 can be coupled to the PCIe switch 621 via the terminal port EP. Each of the PCIe devices 635 to 638 can be coupled to the PCIe switch 622 via the terminal port EP. Each of the PCIe devices 631 to 638 can be coupled to other PCIe devices via ports P1 to P3. In this embodiment, PCIe devices 631-634 share a PCIe switch 621, and PCIe devices 635-638 share a PCIe switch 622. PCIe switch 621 is coupled to host device 611. Switch 622 is coupled to host device 612. Host device 611 and host device 612 can communicate with each other.

[0056] In this embodiment, PCIe devices 631-634 can perform point-to-point data transmission via multiple point-to-point links, and PCIe devices 635-638 can also perform point-to-point data transmission via another multiple point-to-point links. The master control device 611 and the master control device 612 can each apply the method for generating interconnection topology information described in the embodiments of Figures 1 to 5 to generate interconnection topology information between PCIe devices 631-634 and between PCIe devices 635-638, respectively.

[0057] In summary, the distributed computing system, PCIe device, and method for generating interconnection topology information disclosed herein are designed to operate in root port mode and terminal mode at both ends of a point-to-point link, wherein the port operating in root port mode can access the port operating in terminal mode through read and write operations to read or write data from the configuration space or memory space in the corresponding PCIe device. The present disclosure can add registers and triggers to the port operating in root port mode, and use them to write the location information of the port operating in root port mode into the configuration space or memory space of the opposite end. The port operating in terminal mode can also add registers to save location information. In this way, the master control device can read the corresponding registers of the ports operating in terminal mode in all PCIe devices, thereby obtaining information about each PCIe link pair, and thus can quickly and efficiently generate interconnection topology information.

[0058] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A distributed computing system comprising: a plurality of PCIe devices, each comprising a plurality of ports; as well as a master control device coupled to the plurality of PCIe devices and configured to establish a point-to-point link between the plurality of ports of the plurality of PCIe devices; wherein a first portion of the plurality of ports operates in a root port mode, and a second portion of the plurality of ports operates in a terminal mode, and the first portion of the plurality of ports and the second portion of the plurality of ports are located in different PCIe devices; wherein the master device inputs the corresponding root port device identification code and the corresponding root port identification code into the first parts of the plurality of ports, respectively, and the first parts of the plurality of ports output the corresponding root port device identification code and the corresponding root port identification code into the second parts of the plurality of ports, respectively; The main control device obtains a plurality of link pair information by reading the second part of the plurality of ports to generate interconnection topology information; Each of the plurality of link pair information includes the corresponding root port device identifier, the corresponding root port identifier, the corresponding terminal device identifier, and the corresponding terminal port identifier.

2. The distributed computing system according to claim 1, wherein: The plurality of PCIe devices respectively include a plurality of root port circuits and a plurality of terminal port circuits corresponding to the plurality of ports; At least one of the plurality of root port circuits is used to store the corresponding root port device identifier and the corresponding root port identifier, and at least one of the plurality of end port circuits is used to store the corresponding end device identifier and the corresponding end port identifier.

3. The distributed computing system according to claim 2, wherein: The plurality of root port circuits respectively include a first register and a trigger; The first register is used to store the corresponding root port device identifier and the corresponding root port identifier, and the trigger is used to determine whether to output the corresponding root port device identifier and the corresponding root port identifier.

4. The distributed computing system according to claim 3, wherein: The plurality of terminal port circuits respectively include a second register; The second register is used to store the corresponding root port device identification code and the corresponding root port identification code.

5. The distributed computing system according to claim 4, wherein: In response to the master control device determining that the first portion of the plurality of ports operates in the root port mode, the master control device writes the corresponding root port device identifier and the corresponding root port identifier into the first register of the corresponding port, and triggers the corresponding port to write the corresponding root port device identifier and the corresponding root port identifier into the second register of the opposite port.

6. The distributed computing system according to claim 4, wherein: In response to the main control device determining that the second portion of the plurality of ports operates in terminal mode, the main control device records a current terminal device identification code and a current terminal port identification code into an initial list.

7. The distributed computing system according to claim 6, wherein: The main control device sequentially reads the second registers of a plurality of corresponding ports according to the initial list to obtain a plurality of link pair information and generate interconnection topology information.

8. The distributed computing system according to any one of claims 4 to 7, wherein: The master control device updates the values ​​of the first registers of the plurality of ports of the plurality of PCIe devices to the corresponding device identification codes and the corresponding port identification codes; The master control device initializes point-to-point link settings between the multiple PCIe devices and performs link training.

9. The distributed computing system according to any one of claims 1 to 8, wherein: The master control device enumerates the plurality of PCIe devices to obtain a plurality of addresses of the plurality of PCIe devices, and the master control device uses data of the plurality of addresses as data of low-order bits of a device identification code.

10. The distributed computing system according to claim 9, wherein: The high-order bit data of the device identification code includes the master device address data of the master device.

11. A PCIe device, comprising: Multiple ports; a plurality of root port circuits coupled to the plurality of ports; as well as a plurality of terminal port circuits coupled to the plurality of ports; wherein, in response to at least one of the plurality of ports operating in the root port mode, at least one of the plurality of ports receives a root port device identification code and a root port identification code corresponding to the PCIe device provided by the host control device, and stores the root port device identification code and the root port identification code corresponding to the PCIe device in a corresponding at least one of the plurality of root port circuits; In response to at least one of the plurality of ports operating in terminal mode, at least one of the plurality of ports receives a root port device identifier and a root port identifier corresponding to another PCIe device, and stores the root port device identifier and the root port identifier corresponding to the other PCIe device in at least one of the plurality of terminal port circuits.

12. A method for generating interconnection topology information, comprising: Establishing a point-to-point link between multiple ports of multiple PCIe devices; inputting corresponding root port device identifiers and corresponding root port identifiers into a first portion of the plurality of ports, respectively, wherein the first portion of the plurality of ports operates in a root port mode; outputting, through the first portion of the plurality of ports, the corresponding root port device identifiers and the corresponding root port identifiers to a second portion of the plurality of ports, respectively, wherein the second portion of the plurality of ports operates in a terminal mode and the first portion of the plurality of ports and the second portion of the plurality of ports are located in different PCIe devices; as well as Reading the second part of the plurality of ports to obtain a plurality of link pair information to generate the interconnection topology information; Each of the plurality of link pair information includes the corresponding root port device identifier, the corresponding root port identifier, the corresponding terminal device identifier, and the corresponding terminal port identifier.

13. The method for generating interconnection topology information according to claim 12, wherein: The plurality of PCIe devices respectively include a plurality of root port circuits and a plurality of terminal port circuits corresponding to the plurality of ports; At least one of the plurality of root port circuits is used to store the corresponding root port device identifier and the corresponding root port identifier, and at least one of the plurality of end port circuits is used to store the corresponding end device identifier and the corresponding end port identifier.

14. The method for generating interconnection topology information according to claim 13, wherein: The plurality of root port circuits respectively include a first register and a trigger; The first register is used to store the corresponding root port device identifier and the corresponding root port identifier, and the trigger is used to determine whether to output the corresponding root port device identifier and the corresponding root port identifier.

15. The method for generating interconnection topology information according to claim 14, wherein: The plurality of terminal port circuits respectively include a second register; The second register is used to store the corresponding root port device identification code and the corresponding root port identification code.

16. The method for generating interconnection topology information according to claim 15, wherein: The step of inputting the corresponding root port device identification code and the corresponding root port identification code into the first part of the plurality of ports respectively comprises: In response to the first portion of the plurality of ports operating in the root port mode, writing the corresponding root port device identifier and the corresponding root port identifier into the first register of the corresponding port; The step of outputting the corresponding root port device identification code and the corresponding root port identification code to the second parts of the plurality of ports through the first parts of the plurality of ports comprises: The corresponding port is triggered to write the corresponding root port device identifier and the corresponding root port identifier into the second register of the opposite port.

17. The method for generating interconnection topology information according to claim 15, further comprising: In response to the main control device determining that the second part of the plurality of ports operates in terminal mode, recording a current terminal device identification code and a current terminal port identification code into an initial list; The main control device is coupled to the multiple PCIe devices and is used to establish point-to-point links between the multiple ports of the multiple PCIe devices.

18. The method for generating interconnection topology information according to claim 17, wherein: The step of generating the interconnection topology information includes: The second registers of a plurality of corresponding ports are sequentially read according to the initial list to obtain a plurality of link pair information and generate interconnection topology information.

19. The method for generating interconnection topology information according to any one of claims 14 to 18, further comprising: Updating the values ​​of the first registers of the ports of the PCIe devices to the corresponding device identification codes and the corresponding port identification codes; as well as Initialize point-to-point link setup between the plurality of PCIe devices and perform link training.

20. The method for generating interconnection topology information according to claim 12, further comprising: enumerating the plurality of PCIe devices to obtain a plurality of addresses of the plurality of PCIe devices, and the master control device uses data of the plurality of addresses as data of low-order bits of a device identification code; The master control device is coupled to the multiple PCIe devices and is configured to establish a point-to-point link between the multiple ports of the multiple PCIe devices.

Images