Semiconductor device and preparation method, and packaging structure and electronic device

Abstract

The embodiments of the present application relate to the technical field of semiconductors. Provided are a semiconductor device and a preparation method, and a packaging structure and an electronic device, which are used for improving the reliability of a semiconductor device while suppressing the short-channel effect of the semiconductor device. The semiconductor device comprises: a first electrode and a second electrode that are arranged on the top of a substrate, and a first gate arranged between the first electrode and the second electrode, wherein the substrate includes a fin structure extending in a direction towards the top of the substrate, and the top of the fin structure is flush with the top of the substrate. The semiconductor device further comprises: a third electrode arranged on the top of the fin structure, a fourth electrode arranged on a side wall of the fin structure, and a second gate, wherein the second gate is located between the third electrode and the fourth electrode.

Description

Semiconductor device and manufacturing method, packaging structure, and electronic equipment

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on March 30, 2024, with application number 202410391211.6 and application name “Semiconductor devices and preparation methods, packaging structures, and electronic devices”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a semiconductor device and a preparation method, a packaging structure, and an electronic device. Background Art

[0003] Semiconductor devices are used in a variety of electronic devices, such as personal computers, cell phones, digital cameras, and other electronic devices. As the performance of these devices improves, the size of these devices continues to decrease. However, achieving this scaling while maintaining adjustable channel length remains a major challenge. Summary of the Invention

[0004] The embodiments of the present application provide a semiconductor device and its preparation method, packaging structure, and electronic device, which can realize a planar device integrated with a vertical transistor, wherein the width and channel length of the planar device can be flexibly adjusted. To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0005] In a first aspect, a semiconductor device is provided. The semiconductor device includes: a first electrode and a second electrode disposed on a top of a substrate, and a first gate disposed between the first electrode and the second electrode; the substrate includes a fin structure extending toward the top of the substrate, with the top of the fin structure flush with the top of the substrate; the semiconductor device also includes: a fourth electrode disposed on the top of the fin structure, a third electrode disposed on the bottom of the fin structure, and a second gate, with the second gate located between the third electrode and the fourth electrode.

[0006] The first electrode, the second electrode, and the first gate located between the first electrode and the second electrode in the semiconductor device provided by the present application constitute a first device. The first device can be a planar field effect transistor, and the fin structure, the third electrode, the fourth electrode, and the second gate constitute a second device. The second device can be a vertical field effect transistor, that is, a planar field effect transistor and a vertical field effect transistor are arranged on the same substrate. The channel of the first device is located on the surface of the substrate between the first electrode and the second electrode, so that the length of the channel can be adjusted by adjusting the distance between the first electrode and the second electrode, and the width of the first device is flexibly adjustable. At the same time, the top of the fin structure is flush with the top of the substrate, that is, the distance from the channel of the first device to the bottom of the substrate is the same as the distance from the top of the fin structure of the second device to the bottom of the substrate. The first device uses the unetched substrate surface as the channel, and the process error is small, which can improve the reliability of the semiconductor device. The roughness of the substrate surface is low, which can improve the performance of the semiconductor device.

[0007] In one possible embodiment, the first electrode, the second electrode, and the fourth electrode are made of the same material. Since the first electrode, the second electrode, and the fourth electrode are made of the same material, they can be formed simultaneously in the same epitaxial growth process. This not only further saves costs and reduces process complexity, but also improves device mobility and thus enhances semiconductor device performance.

[0008] In one possible embodiment, the first gate and the second gate are made of the same material. Since the first gate and the second gate are made of the same material, the first gate and the second gate can be formed simultaneously in the same process, which not only further saves costs and reduces process complexity, but also improves device reliability.

[0009] In one possible embodiment, a dielectric layer is embedded in the substrate, and the first electrode, second electrode, and first gate are disposed on one side of the dielectric layer; the fin structure is disposed on the other side of the dielectric layer. Thus, by providing the dielectric layer in the substrate, electrical interference or crosstalk between multiple devices is prevented.

[0010] In one possible embodiment, the semiconductor device includes a first isolation layer, which is disposed on a sidewall of the fin structure and between the third electrode and the second gate. Thus, the third electrode and the second gate are insulated by the first isolation layer.

[0011] In one possible embodiment, the semiconductor device includes a second isolation layer, which is disposed on a sidewall of the fin structure and located on a side of the second gate away from the substrate, thereby insulating the fourth electrode from the second gate via the second isolation layer.

[0012] In a second aspect, a method for fabricating a semiconductor device is provided. The method comprises: forming a fin structure on a substrate, extending toward the top of the substrate, with the top of the fin structure flush with the top of the substrate; forming a third electrode at the bottom of the fin structure; forming a first electrode and a second electrode on the top of the substrate; forming a fourth electrode on the top of the fin structure; forming a first gate between the first electrode and the second electrode; and forming a second gate on a sidewall of the fin structure, with the second gate located on a side of the third electrode away from the substrate.

[0013] In one possible embodiment, the preparation method further includes: forming a first groove on the substrate, wherein the first electrode, the second electrode and the first gate are located on one side of the first groove, and the fin structure is located on the other side of the first groove; and depositing a dielectric material in the first groove to form a dielectric layer.

[0014] In one possible implementation, forming a first electrode and a second electrode on a substrate, and forming a fourth electrode on top of a fin structure includes: forming the first electrode and the second electrode on the substrate, and forming the fourth electrode on top of the fin structure through a same process.

[0015] In one possible embodiment, forming a first electrode and a second electrode on a substrate and forming a fourth electrode on top of a fin structure by the same process includes: forming a patterned hard mask layer on a first region of the substrate; using the hard mask layer as a mask to form a plurality of second grooves in the first region of the substrate; forming the first electrode and the second electrode in the plurality of second grooves, and simultaneously forming a fourth electrode on the fin structure.

[0016] In one possible embodiment, before forming the first electrode and the second electrode, forming the first gate includes: forming a first dummy gate on the substrate; correspondingly, after forming the first electrode and the second electrode, forming the first gate also includes: removing the first dummy gate; and forming the first gate on the substrate.

[0017] In a possible implementation, after forming the third electrode, the preparation method further includes: forming a first isolation layer on the sidewall of the fin structure, where the first isolation layer is located on the third electrode.

[0018] In one possible embodiment, before forming the third electrode and the fourth electrode, forming the second gate includes: forming a second dummy gate on the first isolation layer; correspondingly, after forming the first electrode and the second electrode, forming the second gate also includes: removing the second dummy gate; and forming the second gate on the sidewall of the fin structure.

[0019] In a possible implementation, after forming the second dummy gate on the sidewall of the fin structure, the preparation method further includes: forming a second isolation layer on the second dummy gate.

[0020] In a third aspect, a chip packaging structure is provided, which includes a packaging substrate and the semiconductor device according to the first aspect and any possible embodiment thereof; the semiconductor device is electrically connected to the packaging substrate.

[0021] In a fourth aspect, an electronic device is provided. The electronic device includes a printed circuit board and the chip packaging structure provided in the third aspect; the chip packaging structure is electrically connected to the printed circuit board. The technical effects of any possible implementation of the second to fourth aspects can be referenced to the technical effects of the different implementations of the first aspect described above and are not further elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] FIG1 is a schematic structural diagram of a semiconductor device provided in an embodiment of the present application;

[0023] FIG2 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present application;

[0024] 3 to 16 are schematic structural diagrams of semiconductor devices at various stages of the manufacturing process provided by embodiments of the present application;

[0025] FIG17 is a schematic structural diagram of a chip packaging structure provided in an embodiment of the present application;

[0026] FIG18 is a schematic structural diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0027] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0028] In the following, the terms "first," "second," etc., are used for descriptive convenience only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature specified as "first," "second," etc. may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0029] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0030] In order to adapt to the rapid development of technologies such as graphics computing, neural network (NN), artificial intelligence (AI), cloud computing, and high-performance computing cluster (HPCC), semiconductor devices are required to have high performance, high reliability, high integration, and miniaturization.

[0031] The embodiment of the present application also provides a semiconductor device. Referring to the structural schematic diagram of the semiconductor device shown in FIG4 , wherein FIG1 (2) is a cross-sectional schematic diagram of FIG1 (1) at AA', and FIG1 (3) is a cross-sectional schematic diagram of FIG1 (1) at BB'. The semiconductor device includes: a substrate 10; a first electrode 21 and a second electrode 22 arranged on the top of the substrate 10, and a first gate 46 arranged between the first electrode 21 and the second electrode 22; the substrate 10 includes a fin structure 40 extending toward the top of the substrate 10, and the top of the fin structure 40 is flush with the top of the substrate 10; the semiconductor device also includes: a fourth electrode 24 arranged on the top of the fin structure 40, a third electrode 23 arranged at the bottom of the fin structure 40, and a second gate 47, and the second gate 47 is located between the third electrode 23 and the fourth electrode 24.

[0032] Exemplarily, the first electrode 21 can be a source electrode, and the corresponding second electrode 22 is a drain electrode; the first electrode 21 can also be a drain electrode, and the corresponding second electrode 22 is a source electrode; the third electrode 23 can be a source electrode, and the corresponding fourth electrode 24 is a drain electrode; the third electrode 23 can also be a drain electrode, and the corresponding fourth electrode 24 is a source electrode.

[0033] In a specific embodiment, as shown in Figure 2, the process of preparing the above-mentioned semiconductor device includes: S110: forming a fin structure 40 on the substrate 10 extending toward the top of the substrate 10, and the top of the fin structure 40 is flush with the top of the substrate 10; S120: forming a third electrode 23 at the bottom of the fin structure 40; S130: forming a first electrode 21 and a second electrode 22 on the top of the substrate 10; S140: forming a fourth electrode 24 on the top of the fin structure 40; S150: forming a first gate 46 between the first electrode 21 and the second electrode 22, and the distance from the bottom of the first gate 46 to the bottom of the substrate 10 is the same as the distance from the top of the fin structure 40 to the bottom of the substrate 10; S160: forming a second gate 47 on the sidewall of the fin structure 40, and the second gate 47 is located on the side of the third electrode 23 away from the substrate 10.

[0034] The first electrode 21, the second electrode 22 and the first gate 46 located between the first electrode 21 and the second electrode 22 in the semiconductor device provided by the present application constitute a first device, the first device can be a planar field effect transistor, the fin structure 40, the third electrode 23, the fourth electrode 24 and the second gate 47 constitute a second device, the second device can be a vertical field effect transistor (VFET), that is, a planar field effect and a vertical field effect transistor are provided on the same substrate 10. Among them, the channel of the first device is located on the surface of the substrate 10 between the first electrode 21 and the second electrode 22, so that the length of the channel can be adjusted by adjusting the distance between the first electrode 21 and the second electrode 23, and the width of the first device is flexibly adjustable. Therefore, it can be applied to analog devices or IO (Input / Output) input / output interfaces, and has broad application prospects. At the same time, the top of the fin structure 40 is flush with the top of the substrate 10, that is, the distance h1 from the channel of the first device to the bottom of the substrate 10 is the same as the distance h2 from the top of the fin structure 40 of the second device to the bottom of the substrate 10. The first device uses the unetched surface of the substrate 10 as the channel, and the process error is small, which can improve the reliability of the semiconductor device. The roughness of the surface of the substrate 10 is low, which can improve the performance of the semiconductor device.

[0035] In an optional embodiment, the manufacturing process of the semiconductor device and the device structure formed during the manufacturing process are described in detail below.

[0036] S100 : forming a dielectric layer 50 on the substrate 10 .

[0037] For example, the material of substrate 10 can be made of silicon or other semiconductor materials. Alternatively or additionally, substrate 10 can include one or more combinations of silicon, germanium, and III-V semiconductors. In some embodiments, substrate 10 is made of a compound semiconductor, such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. In some embodiments, substrate 10 is made of an alloy or a multi-component compound, such as silicon germanium, silicon germanium carbide, gallium arsenide phosphide, or gallium indium phosphide.

[0038] As shown in FIG3 , a first groove is formed on the substrate 10 by a patterning process, and a dielectric material is filled in the first groove to form a dielectric layer 50 embedded in the substrate 10. For example, the dielectric layer 50 can be made of silicon oxide, silicon nitride, silicon oxynitride, or other dielectric materials. The dielectric layer 50 is deposited by a chemical vapor deposition (CVD) process, a spin-on-glass process, or other applicable processes. In some optional examples, after forming the dielectric layer 50, a chemical mechanical polishing (CMP) process is performed to planarize the dielectric layer 50.

[0039] For ease of explanation, the dielectric layer 50 can be considered to divide the substrate 10 into a first region 104 and a second region 105. The first region 104 of the substrate 10 is used to form a first device, and the second region 105 of the substrate 10 is used to form a second device. It is understood that the dielectric layer 50 can also be referred to as a shallow trench isolation (STI) structure, which is used to prevent electrical interference or crosstalk between multiple devices.

[0040] It should be noted that when multiple first devices are formed on substrate 10, dielectric layer 50 disposed in first region 104 of substrate 10 includes a first portion and a second portion, and the first portion of dielectric layer 50 extends in a different direction than the second portion of dielectric layer 50. For example, the first portion of dielectric layer 50 extends along the x-direction, and the second portion of dielectric layer 50 extends along the y-direction, where the x-direction is the direction in which the first and second devices are arranged, and the y-direction is perpendicular to the x-direction. When multiple second devices are formed on substrate 10, dielectric layer 50 disposed in second region 105 of substrate 10 extends only along the x-direction.

[0041] S101: A first barrier layer 51 is formed on a substrate 10. For example, as shown in FIG4 , FIG4 (b) is a schematic cross-sectional view of FIG4 (i) at AA′, and FIG4 (c) is a schematic cross-sectional view of FIG4 (i) at BB′. The first barrier layer 51 covers a first region 104 of the substrate 10 to protect the underlying substrate 10 from being etched during subsequent processes.

[0042] S110 : forming a fin structure 40 on the substrate 10 and extending toward the top of the substrate 10 , wherein the top of the fin structure 40 is flush with the top of the substrate 10 .

[0043] 4, the substrate 10 is etched by a dry etching process to form a fin structure 40 on the second region 105 of the substrate 10. The dry etching process includes using a fluorine-based etchant gas, such as SF6, C x F y , NF3, or a combination thereof. The etching process may be a time-controlled process, and the fin structure 40 reaches a predetermined height by controlling the etching process time. It should be noted that the number of fin structures 40 can be adjusted according to actual applications and is not limited to one fin structure 40.

[0044] S120 : forming a third electrode 23 on the bottom of the fin structure 40 .

[0045] For example, refer to the structural schematic diagram of the semiconductor device shown in Figure 5, wherein (2) in Figure 5 is a cross-sectional schematic diagram of (1) in Figure 5 at AA', and (3) in Figure 5 is a cross-sectional schematic diagram of (1) in Figure 5 at BB'. When forming the third electrode 23, a pit can be formed in advance on the second region 105 of the substrate 10. The pit can be in a "Σ" shape, a "U" shape, or other shapes. The first electrode material is then filled in the pit by an epitaxial process to form the third electrode 23. The third electrode 23 surrounds the bottom of the fin structure 40, and the upper part of the fin structure 40 protrudes from the third electrode 23. In other words, part of the fin structure 40 is embedded in the third electrode 23. Alternatively, when forming the third electrode 23, an ion doping material can be implanted into the fin structure 40 by an implantation process to form the third electrode 23 at the bottom of the fin structure 40. The first electrode material may include a combination of one or more of the following materials: silicon germanium (SiGe), germanium (Ge), indium arsenide (InAs), indium gallium arsenide (InGaAs), indium antimonide (InSb), gallium arsenide (GaAs), gallium antimonide (GaSb), indium aluminum phosphide (InAlP), indium phosphide (InP). Exemplarily, when the second device is an N-type semiconductor device and the third electrode 23 is formed by an implantation process, the ion doping material is a P-type ion doping material, and the P-type ion doping material may be at least one of boron (B), aluminum (Al), gallium (Ga), indium (In), or a combination thereof. When the second device is a P-type semiconductor device and the third electrode 23 is formed by an implantation process, the ion doping material is an N-type ion doping material, and the N-type ion doping material may be phosphorus (P), As, PH x + and / or P2H x + At least one of (x=1, 2, 3, ...) or a combination thereof.

[0046] S121 : forming a first isolation layer 32 on the third electrode 23 .

[0047] In a specific example, refer to the structural schematic diagram of the semiconductor device shown in Figure 6, wherein Figure 6 (ii) is a cross-sectional schematic diagram of Figure 6 (i) at AA', and Figure 6 (iii) is a cross-sectional schematic diagram of Figure 6 (i) at BB'. A first isolation layer 32 covers the third electrode 23, and the first isolation layer 32 is made of silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), or other low dielectric constant (low-k) dielectric materials. The first isolation layer 32 is used to insulate the third electrode 23 from the second gate 47 formed subsequently.

[0048] S122 : forming a second dummy gate 61 on the first isolation layer 32 .

[0049] Taking into account that heat treatment will be performed during the subsequent formation of the first electrode 21, the second electrode 22 and the fourth electrode 24, high temperature will affect the performance of the first gate 46, thereby reducing the reliability of the device. Refer to the structural schematic diagram of the semiconductor device shown in Figure 7, wherein (2) in Figure 7 is a cross-sectional schematic diagram of (1) in Figure 7 at AA', and (3) in Figure 7 is a cross-sectional schematic diagram of (1) in Figure 7 at BB'. In this embodiment, the semiconductor device first forms a second dummy gate 61, and after the first electrode 21, the second electrode 22 and the fourth electrode 24 are formed, the second dummy gate 61 is removed, and then the second gate 47 is formed, thereby improving the reliability of the semiconductor device. In some optional embodiments, the second dummy gate is made of a conductive or non-conductive material. In some embodiments, the second dummy gate 61 is made of polysilicon. The second dummy gate 61 is formed by a deposition process, and is formed on the first isolation layer 32 by a method such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma chemical vapor deposition (HDPCVD), metal organic chemical vapor deposition (MOCVD), or plasma enhanced chemical vapor deposition (PECVD).

[0050] S123 : forming a second isolation layer 33 on the second dummy gate 61 .

[0051] In a specific example, as shown in FIG7 , a second isolation layer 33 covers the second dummy gate 61. The second isolation layer 33 is made of silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), or other low-k dielectric materials. The second isolation layer 33 is used to insulate the subsequently formed second gate 47 from the fourth electrode 24.

[0052] S124: remove the first barrier layer 51 covering the first region 104 of the substrate 10 and form a second barrier layer 52. Exemplarily, the second barrier layer 52 covers the second isolation layer 33 and the top of the fin structure 40 to protect the underlying structure from being etched during subsequent processes.

[0053] S125 : forming a first dummy gate 60 on the substrate 10 .

[0054] In some optional examples, refer to the structural schematic diagram of the semiconductor device shown in Figure 8, wherein (ii) in Figure 8 is a cross-sectional schematic diagram of (i) in Figure 8 at AA', and (iii) in Figure 8 is a cross-sectional schematic diagram of (i) in Figure 8 at BB'. A first dummy gate 60 is formed on the first region 104 of the substrate 10, and a third isolation layer is formed on the sidewall of the first dummy gate 60. The third isolation layer is made of silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG) or other low dielectric constant (low-k) dielectric materials. The third isolation layer is used to insulate the first gate 46 formed subsequently from the first electrode 21 and the second electrode 22.

[0055] S130 : forming a first electrode 21 and a second electrode 22 on the top of the substrate 10 .

[0056] In a specific embodiment, the forming of the first electrode 21 and the second electrode 22 on the substrate 10 further includes:

[0057] S131 : forming a patterned hard mask layer 65 on the first region 104 of the substrate 10 .

[0058] For example, refer to the structural schematic diagram of the semiconductor device shown in Figure 9, wherein (2) in Figure 9 is a cross-sectional schematic diagram of (1) in Figure 9 at AA', and (3) in Figure 9 is a cross-sectional schematic diagram of (1) in Figure 9 at BB'. After forming the first dummy gate 60, the second barrier layer 52 is removed, and a hard mask layer 65 is uniformly conformally grown on the substrate 10, and then a photoresist layer is formed on the hard mask layer 65. The photoresist layer is patterned by a patterning process. Finally, the hard mask layer 65 is patterned by using the patterned photoresist layer as a mask, thereby obtaining a patterned hard mask layer 65. The patterned hard mask layer 65 exposes a portion of the substrate 10. Optionally, the patterning process includes a photolithography process and an etching process. The photolithography process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, developing the photoresist, rinsing, and drying (e.g., hard baking). The etching process includes a dry etching process or a wet etching process.

[0059] S132: Using the patterned hard mask layer 65 as a mask, a plurality of second grooves 12 are formed in the first region 104 of the substrate 10. The plurality of second grooves 12 are used for the subsequent selective growth of the first electrode 21 and the second electrode 22. For example, as shown in FIG9 , two second grooves 12 are formed in the first region 104 of the substrate 10, one of which is used to form the first electrode 21, and the other is used to form the second electrode 22.

[0060] S133 : performing secondary patterning on the patterned hard mask layer 65 , so that the secondary patterned hard mask layer 65 exposes the top of the fin structure 40 .

[0061] S134 : forming first electrodes 21 and second electrodes 22 in the plurality of second grooves 12 .

[0062] Referring to the schematic structural diagram of the semiconductor device shown in FIG10 , FIG10 ( b ) is a schematic cross-sectional view of FIG10 ( a ) at AA′, and FIG10 ( c ) is a schematic cross-sectional view of FIG10 ( a ) at BB′. The first electrode 21 and the second electrode 22 are formed by growing a strained material in the second groove 12 through an epitaxial (EPI) process. The epitaxial process may include a selective epitaxial growth (SEG) process, a CVD deposition technique (e.g., vapor phase epitaxy (VPE) and / or ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy, or other suitable EPI processes.

[0063] S140 : forming a fourth electrode 24 on the top of the fin structure 40 .

[0064] To further save costs, the first electrode 21, the second electrode 22, and the fourth electrode 24 can be formed simultaneously in the same epitaxial process. This not only reduces the complexity of the process, but also improves the mobility of the first device to improve the performance of the semiconductor device.

[0065] After the first electrode 21, the second electrode 22, and the fourth electrode 24 are formed, ion doping in the first electrode 21, the second electrode 22, and the fourth electrode 24 is activated by heat treatment. The heat treatment may be furnace annealing or rapid thermal annealing, wherein the annealing is performed at a temperature ranging from about 800° C. to about 1100° C. for a duration of about 1 second to about 10 seconds.

[0066] In some optional embodiments, after forming the first electrode 21 , the second electrode 22 and the fourth electrode 24 , the photoresist layer may be dissolved with a stripping solution to remove the photoresist layer, or the photoresist layer may be stripped with a stripping device.

[0067] It can be understood that the embodiments of the present application are described using the example that the first device and the second device are both N-type semiconductor devices or both P-type semiconductor devices. When different types of first devices and second devices are formed on the same substrate 10, the above steps S131-S140 can be referred to so that the first device and the second device, which are both N-type semiconductor devices, form the first electrode 21, the second electrode 22 and the fourth electrode 24 in the same process, and the first device and the second device, which are both P-type semiconductor devices, form the first electrode 21, the second electrode 22 and the fourth electrode 24 in the same process.

[0068] S141: forming an insulating layer 66 covering the first electrode 21, the first dummy gate 60, the second electrode 22, the second isolation layer 33, and the fourth electrode 24. In some optional embodiments, as shown in FIG11, FIG11 (ii) is a schematic cross-sectional view of FIG11 (i) at AA', and FIG11 (iii) is a schematic cross-sectional view of FIG11 (i) at BB'. After forming the insulating layer 66, it is necessary to planarize the insulating layer 66 by a chemical mechanical polishing (CMP) process until the surface of the first dummy gate 60 is exposed.

[0069] S142 : forming a through hole 67 penetrating the insulating layer 66 and the second isolation layer 33 to expose the surface of the second dummy gate 61 , and removing the first dummy gate 60 and the second dummy gate 61 .

[0070] For example, as shown in FIG12, FIG12 (ii) is a schematic cross-sectional view of FIG12 (i) at AA', and FIG12 (iii) is a schematic cross-sectional view of FIG12 (i) at BB'. A through hole 67 can be formed through the insulating layer 66 and the second isolation layer 33 to expose the surface of the second dummy gate 61, and then the first dummy gate 60 and the second dummy gate 61 are removed by wet etching. As a result, a cavity is formed between the first isolation layer 32 and the second isolation layer 33, and the cavity is connected to the via 67. The cavity formed between the first isolation layer 32 and the second isolation layer 33 provides space for the subsequent formation of the second gate 47. In some optional examples, considering that a gate oxide layer is easily generated between the second dummy gate 61 and the fin structure 40, an anti-reflective coating (BARC) can be formed on the first region 104 of the substrate 10. The BARC covers the insulating layer 66 and fills between the third isolation layers. The anti-reflective coating (BARC) is used to protect the underlying layers from being etched. Then, through photolithography and wet etching processes, only the gate oxide layer on the surface of the fin structure 40 is removed. Finally, the anti-reflective coating is removed.

[0071] S150 : forming a first gate electrode 46 between the first electrode 21 and the second electrode 22 .

[0072] In some optional embodiments, the first gate 46 is made of a metal material. The metal material may include an N work function metal or a P work function metal. The N work function metal includes tungsten (W), copper (Cu), titanium (Ti), silver (Ag), aluminum (Al), titanium aluminum alloy (TiAl), titanium aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium (Zr), or a combination thereof. The P work function metal includes titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), ruthenium (Ru), or a combination thereof.

[0073] S160 : forming a second gate 47 on the sidewall of the fin structure 40 . The second gate 47 is located on a side of the third electrode 23 away from the substrate 10 .

[0074] In a specific example, forming the second gate 47 further includes:

[0075] S161: Depositing gate metal material in the cavity and via 67 to form a second gate metal layer 48. The formed semiconductor device is shown in FIG13 , wherein FIG13 ( 2 ) is a schematic cross-sectional view of FIG13 ( 1 ) at AA′, and FIG13 ( 3 ) is a schematic cross-sectional view of FIG13 ( 1 ) at BB′.

[0076] S162 : forming a third barrier layer 53 , where the third barrier layer 53 covers the first region 104 of the substrate 10 .

[0077] S163 : forming a trench 68 penetrating the insulating layer 66 , the second isolation layer 33 , the second gate metal layer 48 , the first isolation layer 32 and the third electrode 23 , wherein the trench 68 extends into the substrate 10 .

[0078] The resulting semiconductor device is shown in FIG14 , wherein FIG14 ( 2 ) is a schematic cross-sectional view of FIG14 ( 1 ) taken at AA′, and FIG14 ( 3 ) is a schematic cross-sectional view of FIG14 ( 1 ) taken at BB′. The unetched second gate metal layer 48 forms a second gate 47 disposed on the sidewall of the fin structure 40.

[0079] To further save costs, the first gate 46 and the second gate 47 can be formed simultaneously in the same process, which not only reduces process complexity but also improves semiconductor device performance. Furthermore, reducing the thermal process that the first gate 46 and the second gate 47 undergo can effectively improve the reliability of the semiconductor device.

[0080] It can be understood that when the first gate 46 and the second gate 47 are formed simultaneously, the materials of the first gate 46 and the second gate 47 are the same; when the first gate 46 and the second gate 47 are formed sequentially, the materials of the first gate 46 and the second gate 47 can be the same or different, and the embodiments of the present application do not limit this.

[0081] S164: Remove the third barrier layer 53, and deposit a dielectric material in the trench 68 to form an interlayer dielectric layer 55 covering the insulating layer 66. The structure of the formed semiconductor device is shown in FIG15 , where FIG15 (a) and FIG15 (b) are cross-sectional schematic diagrams of the semiconductor device in different directions.

[0082] In this embodiment, the interlayer dielectric layer 55 can be a multilayer structure made of a variety of dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, tetraethyl orthosilicate (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric materials and / or other applicable dielectric materials. Examples of low-k dielectric materials include, but are not limited to, fluorinated silicate glass (FSG), carbon-doped silicon oxide, fluorinated amorphous carbon, parylene, bisbenzocyclobutene (BCB), or polyimide. The interlayer dielectric layer 55 can be formed by flowable chemical vapor deposition (FCVD), chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating, or other applicable processes.

[0083] Then, according to some optional embodiments, a polishing process is performed on the interlayer dielectric layer 55. In some optional embodiments, the interlayer dielectric layer 55 is planarized by a chemical mechanical polishing (CMP) process.

[0084] S170 : forming at least one conductive structure 70 penetrating the interlayer dielectric layer 55 in the interlayer dielectric layer 55 .

[0085] Refer to the structural schematic diagram of the semiconductor device shown in Figure 16, wherein Figure 16 (1) and Figure 16 (2) are cross-sectional schematic diagrams of the semiconductor device in different directions. The conductive structure 70 can be multiple. One of the conductive structures 70 can be a gate electrode, that is, the gate electrode penetrates the interlayer dielectric layer 55 and contacts the first gate 46. Alternatively, one of the conductive structures 70 can also penetrate the interlayer dielectric layer 55 and the insulating layer 66 to contact the first electrode 21; or one of the conductive structures 70 can also penetrate the interlayer dielectric layer 55 and the insulating layer 66 to contact the second electrode 22; or one of the conductive structures 70 can also penetrate the interlayer dielectric layer 55 and the insulating layer 66 to contact the fourth electrode 24.

[0086] The embodiment of the present application further provides a chip packaging structure 300. As shown in FIG17 , the chip packaging structure 300 includes a semiconductor device 100 and a packaging substrate 200, and the semiconductor device 100 is electrically connected to the packaging substrate 200.

[0087] In some embodiments, the chip packaging structure 300 may further include micro bumps (micro bumps, ubumps) 210, and the packaging substrate may be electrically connected to the semiconductor device 100 via a plurality of micro bumps 210. In addition, in some embodiments, as shown in FIG17 , the electronic device may further include a connector 220; the packaging substrate 200 in the chip packaging structure is connected to other electronic devices via the connector 220, for example, electrically connected to a printed circuit board. In this way, communication between the semiconductor device 100 and other electronic devices can be achieved. Here, the connector 220 may be a solder ball or a micro bump.

[0088] The semiconductor device according to the embodiment of the present application can be applied to various electronic devices. For example, by integrating a plurality of such semiconductor devices and other devices (for example, other forms of transistors, etc.), electrically connected to a printed circuit board, and thereby constructing an electronic device. Therefore, the embodiment of the present application also provides an electronic device, as shown in Figure 18, the electronic device may include a chip packaging structure 300 and a printed circuit board (PCB) 400 provided in the above embodiment. The electronic device may include a CMOS image sensor, a NAND flash memory, a high-bandwidth memory, a mobile phone, a tablet computer (pad), a television, an intelligent wearable product (for example, a smart watch, a smart bracelet), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device and other electronic products. The embodiment of the present application does not place any special restrictions on the specific form of the above-mentioned electronic device.

[0089] The above are only specific embodiments of the present application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A semiconductor device, characterized in that: include: substrate; A first electrode and a second electrode are provided on top of the substrate, and a first gate is provided between the first electrode and the second electrode; The substrate includes a fin structure extending toward the top of the substrate, and the top of the fin structure is flush with the top of the substrate; The semiconductor device further includes a fourth electrode disposed on the top of the fin structure, a third electrode disposed on the bottom of the fin structure, and a second gate located between the third electrode and the fourth electrode.

2. The semiconductor device according to claim 1, wherein The first electrode, the second electrode and the fourth electrode are made of the same material.

3. The semiconductor device according to claim 1 or 2, wherein: The first gate and the second gate are made of the same material.

4. The semiconductor device according to any one of claims 1 to 3, wherein: A dielectric layer is embedded in the substrate, and the first electrode, the second electrode and the first gate are arranged on one side of the dielectric layer; The fin structure is disposed on the other side of the dielectric layer.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that: The semiconductor device includes a first isolation layer, which is disposed on a sidewall of the fin structure and located between the third electrode and the second gate.

6. The semiconductor device according to any one of claims 1 to 5, wherein: The semiconductor device includes a second isolation layer, which is arranged on a sidewall of the fin structure and located on a side of the second gate away from the substrate.

7. A method for preparing a semiconductor device, characterized in that: include: forming a fin structure on a substrate and extending toward a top of the substrate, wherein a top of the fin structure is flush with a top of the substrate; forming a third electrode at the bottom of the fin structure; forming a first electrode and a second electrode on top of the substrate; forming a fourth electrode on top of the fin structure; forming a first gate electrode between the first electrode and the second electrode; A second gate is formed on a sidewall of the fin structure, and the second gate is located on a side of the third electrode away from the substrate.

8. The method according to claim 7, characterized in that The preparation method further comprises: forming a first groove on the substrate, wherein the first electrode, the second electrode, and the first gate are located on one side of the first groove, and the fin structure is located on the other side of the first groove; A dielectric material is deposited in the first groove to form a dielectric layer.

9. The method according to claim 7 or 8, characterized in that forming a first electrode and a second electrode on the top of the substrate, and forming a fourth electrode on the top of the fin structure; comprising: A first electrode and a second electrode are formed on the substrate through a same process, and a fourth electrode is formed on top of the fin structure.

10. The method according to claim 9, characterized in that Forming a first electrode and a second electrode on the substrate by a same process, and forming a fourth electrode on top of the fin structure includes: forming a patterned hard mask layer on a first region of the substrate; forming a plurality of second grooves in a first region of the substrate using the hard mask layer as a mask; A first electrode and a second electrode are formed in the plurality of second grooves, and a fourth electrode is formed on the fin structure.

11. The method according to any one of claims 7 to 10, characterized in that Before forming the first electrode and the second electrode, forming the first gate includes: forming a first dummy gate on the substrate; Accordingly, after forming the first electrode and the second electrode, forming the first gate further includes: removing the first dummy gate; A first gate is formed on the substrate.

12. The method according to any one of claims 7 to 11, characterized in that After forming the third electrode, the preparation method further includes: A first isolation layer is formed on the sidewall of the fin structure, wherein the first isolation layer is located on the third electrode.

13. The method according to claim 12, characterized in that Before forming the third electrode and the fourth electrode, forming the second gate includes: forming a second dummy gate on the first isolation layer; Accordingly, after forming the first electrode and the second electrode, forming the second gate further includes: removing the second dummy gate; A second gate is formed on the sidewall of the fin structure.

14. The method according to claim 13, characterized in that After forming a second dummy gate on the sidewall of the fin structure, the preparation method further includes: A second isolation layer is formed on the second dummy gate.

15. A chip packaging structure, characterized in that: The invention comprises a packaging substrate and a semiconductor device according to any one of claims 1 to 6; the semiconductor device is electrically connected to the packaging substrate.

16. An electronic device, characterized in that: The device comprises a printed circuit board and a chip packaging structure as claimed in claim 15; the chip packaging structure is electrically connected to the printed circuit board.

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