Coding method, decoding method, and communication apparatus

Abstract

The present application provides a coding method, a decoding method, and a communication apparatus. In the method, a check matrix used for coding first information comprises a plurality of submatrices, and each submatrix is a zero matrix or a non-zero matrix having both row and column weights of 1. Therefore, each submatrix is an orthogonal matrix, such that parallel decoding and low decoding complexity can be achieved, and the communication delay is reduced, thereby improving the communication efficiency.

Description

Coding method, decoding method and communication device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of the People's Republic of China on April 3, 2024, with application number 202410404643.6 and invention name "A coding method, a decoding method and a communication device", the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of wireless communication technology, and in particular to an encoding method, a decoding method, and a communication device. Background Art

[0004] Low-density parity check (LDPC) codes are a channel coding scheme that closely approximates the Shannon line, offering high performance and low complexity. They have been selected by the 3rd Generation Partnership Project (3GPP) as the coding and decoding scheme for data channels in fifth-generation (5G) communications. The mainstream LDPC codes feature a quasi-cyclic (QC) structure, which uses a shift within each block to mitigate undesirable structures such as short cycles and improve code length.

[0005] How to use LDPC codes to encode and decode information to improve communication efficiency remains to be solved. Summary of the Invention

[0006] The embodiments of the present application provide an encoding method, a decoding method, and a communication device to improve communication efficiency.

[0007] In the first aspect, an embodiment of the present application provides a coding method, which can be executed by a first device or a module (such as a chip) in the first device. The method includes: determining a first matrix according to a base matrix, a lifting size, and a translation value corresponding to the base matrix; wherein the base matrix includes a first element, and the first element is an element in the base matrix whose value is greater than 1; each zero element in the base matrix corresponds to a zero matrix in the first matrix, and each non-zero element in the base matrix corresponds to a non-zero matrix in the first matrix; by cyclically shifting the elements of at least one non-zero matrix in the first matrix, a check matrix is ​​obtained; wherein the at least one non-zero matrix corresponds to at least one of the first elements in the base matrix, the check matrix includes multiple block matrices, at least one block matrix in the multiple block matrices corresponds one-to-one to the at least one non-zero matrix, and the at least one block matrix is ​​composed of multiple sub-matrices, and the sub-matrix is ​​a zero matrix, or a non-zero matrix with both row weight and column weight being 1; encoding the first information according to the check matrix to obtain the second information.

[0008] In the above scheme, the check matrix used to encode the first information includes multiple sub-matrices, each sub-matrix is ​​a zero matrix or a non-zero matrix with both row weight and column weight being 1. Therefore, each sub-matrix is ​​an orthogonal matrix, which can realize parallel decoding with low decoding complexity, reduce communication delay, and thus improve communication efficiency.

[0009] In the second aspect, an embodiment of the present application provides a decoding method, which can be performed by a second device or a module (such as a chip) in the second device. The method includes: obtaining third information; determining a first matrix according to a base matrix, a lifting size, and a translation value corresponding to the base matrix; wherein the base matrix includes a first element, and the first element is an element in the base matrix whose value is greater than 1; wherein each zero element in the base matrix corresponds to a zero matrix in the first matrix, and each non-zero element in the base matrix corresponds to a non-zero matrix in the first matrix; by cyclically shifting the elements of at least one non-zero matrix in the first matrix, a check matrix is ​​obtained; wherein the at least one non-zero matrix corresponds to at least one first element in the base matrix, the check matrix includes multiple block matrices, at least one block matrix in the multiple block matrices corresponds one-to-one to the at least one non-zero matrix, and the at least one block matrix is ​​composed of multiple sub-matrices, and the sub-matrix is ​​a zero matrix, or a non-zero matrix with both row weight and column weight 1; decoding the third information according to the check matrix to obtain the first information.

[0010] In the above scheme, the check matrix used to decode the third information includes multiple sub-matrices, each sub-matrix is ​​a zero matrix or a non-zero matrix with both row weight and column weight being 1. Therefore, each sub-matrix is ​​an orthogonal matrix, which can realize parallel decoding with low decoding complexity, reduce communication delay, and thus improve communication efficiency.

[0011] Based on the first aspect or the second aspect, any one or more of the following implementation methods may be provided:

[0012] In a possible implementation method, the multiple block matrices include a first block matrix, the first block matrix is ​​composed of l1*l1 sub-matrices, and the value of the first element corresponding to the first block matrix is ​​less than or equal to l1.

[0013] The above solution can realize the promotion of the first element of the basis matrix (ie, the element with a value greater than 1) into mutually orthogonal sub-units to achieve parallel decoding.

[0014] In a possible implementation method, the block matrices in the check matrix corresponding to each element in the same row of the base matrix are composed of l2*l2 sub-matrices.

[0015] The above solution can avoid elements in the same row corresponding to block matrices of different sizes, so that the parallel decoding unit is divided regularly for the check equation, the memory storage structure of the entire check equation is simple, and the hardware complexity is low.

[0016] In a possible implementation method, l2 is the maximum value of the values ​​of the elements in the same row.

[0017] The above solution achieves the technical effect of parallel block decoding without memory conflicts at the lowest cost, while maximizing the degree of parallelism.

[0018] In a possible implementation method, the element in the i-th row and j1-th column of the base matrix corresponds to the block matrix in the check matrix. The element in the i-th row and j2-th column of the base matrix corresponds to the size of the block matrix in the check matrix. sub-matrices; where j1≠j2, or Wherein x is an integer greater than 1.

[0019] In the above scheme, the entire verification equation memory storage structure is simple, the hardware complexity is low, and a larger design space can be achieved, with a better code structure.

[0020] In one possible implementation method, the base matrix includes a first submatrix region, the values ​​of the elements in the first submatrix region are all t, and each block matrix corresponding to the first submatrix region in the check matrix is ​​composed of l3*l3 submatrices, and t=l3.

[0021] The above solution has the most unified hardware form and does not need to distinguish specific positions. The cyclic shift method of each position is exactly the same, and the protocol description is the most concise.

[0022] In one possible implementation method, the code rate of the first sub-matrix area is greater than or equal to the code rate threshold; or, the number of rows in the first sub-matrix area is greater than or equal to the row number threshold; or, the first sub-matrix area corresponds to a high code rate information column; or, the first sub-matrix area corresponds to a high code rate core check.

[0023] In one possible implementation method, the elements of the at least one non-zero matrix do not include a first type of 1, the first type of 1 corresponds to a translation value, and the translation value is A non-negative integer multiple of or A non-negative integer multiple of Zc′=Zc+l-mod(Zc,l);

[0024] Here, Zc represents the lifting size, the block matrix corresponding to the first type 1 is composed of l*l sub-matrices, and mod represents a modulo operation.

[0025] The above solution can reduce the number of cyclic shifts, thereby improving encoding or decoding efficiency.

[0026] In a possible implementation method, the elements of the at least one non-zero matrix do not include a second type of 1, the second type of 1 corresponds to l translation values, and the l translation values ​​are or The remainders obtained after modulo are the same; Zc′=Zc+l-mod(Zc,l);

[0027] Here, Zc represents the lifting size, the block matrix corresponding to the second type 1 is composed of l*l sub-matrices, and mod represents a modulo operation.

[0028] The above solution can reduce the number of cyclic shifts, thereby improving encoding or decoding efficiency.

[0029] In one possible implementation method, the check matrix is ​​obtained by cyclically shifting the elements of at least one non-zero matrix in the first matrix, including: cyclically shifting the elements of the at least one non-zero matrix to the left or right according to the translation amount corresponding to the elements of the at least one non-zero matrix to obtain the check matrix; wherein the translation amount is related to the lifting size and the number of sub-matrices contained in the block matrix corresponding to the elements of the at least one non-zero matrix.

[0030] In one possible implementation method, the translation amount is any one of the following:

[0031] or Zc′=Zc+l-mod(Zc,l);

[0032] Wherein, Zc represents the lifting size, the block matrix corresponding to the elements of the at least one non-zero matrix is ​​composed of l*l sub-matrices, and mod represents a modulo operation.

[0033] In one possible implementation method, the at least one block matrix includes a second block matrix, the second block matrix is ​​composed of l*l sub-matrices, the second block matrix corresponds to the second matrix, the size of the second matrix is ​​l*l, and the elements in the second matrix correspond one-to-one to the sub-matrices in the second block matrix; if the value of the element in the second matrix is ​​0, then the corresponding sub-matrix in the second block matrix is ​​a zero matrix; or, if the value of the element in the second matrix is ​​1, then the corresponding sub-matrix in the second block matrix is ​​a non-zero matrix. In one possible implementation method, the mod(i+s k -1,l) columns have values ​​of 1, i=1,2,…,l, and k=1,2,…,t; where s1,s2,…,s t The t translation values ​​are determined by t translation values, the l, and the lifting size, where the t translation values ​​are translation values ​​of the first element in the base matrix corresponding to the second block matrix.

[0034] In one possible implementation method, or, Wherein, Zc is the lifting size, Y k represents the kth translation value among the t translation values, Indicates rounding down. Indicates rounding up.

[0035] In one possible implementation method, the second matrix is ​​composed of N sub-matrices, each of the N sub-matrices is a zero matrix, or a matrix obtained by adding t cyclic shift matrices, where t is the value of the first element in the base matrix corresponding to the second block matrix.

[0036] In a possible implementation method, the non-zero matrix with both row weight and column weight of 1 is a cyclic shift matrix.

[0037] In a third aspect, an embodiment of the present application provides a communication device, which may be a first device or a module (such as a chip) in the first device. The device has the function of implementing any implementation method of the first aspect described above. The function may be implemented by hardware or by hardware executing corresponding software implementations. The hardware or software includes one or more modules corresponding to the above functions.

[0038] In a fourth aspect, an embodiment of the present application provides a communication device, which may be a second device or a module (such as a chip) in the second device. The device has the function of implementing any implementation method of the second aspect described above. The function may be implemented by hardware or by hardware executing corresponding software implementation. The hardware or software includes one or more modules corresponding to the above functions.

[0039] In a fifth aspect, an embodiment of the present application provides a communication device, comprising a unit or means for executing each step of any implementation method of the above-mentioned first aspect to the second aspect.

[0040] In a sixth aspect, an embodiment of the present application provides a communication device, comprising a processor and an interface circuit, wherein the processor is configured to communicate with other devices via the interface circuit and execute any of the implementation methods of the first to second aspects above. The processor comprises one or more.

[0041] Optionally, the communication device may further include a memory for storing computer instructions, the memory being coupled to a processor, and the processor executing the computer instructions stored in the memory so that the device executes any implementation method of the first to second aspects above.

[0042] In the seventh aspect, an embodiment of the present application also provides a computer program product, which includes a computer program or instructions. When the computer program or instructions are run by a communication device, any implementation method of the above-mentioned first to second aspects is executed.

[0043] In an eighth aspect, an embodiment of the present application further provides a computer-readable storage medium, wherein instructions are stored in the computer-readable storage medium, which, when executed on a communication device, enables any implementation method of the above-mentioned first to second aspects to be executed.

[0044] In the ninth aspect, the present application provides a chip (or chip system), which includes a processor, the processor is coupled to a memory, and the memory stores a computer program; the processor is used to call part or all of the computer program in the memory, so that any implementation method of the above-mentioned first aspect to the second aspect is executed.

[0045] In a tenth aspect, the present application provides a communication system comprising a first device for executing any implementation method of the above-mentioned first aspect, and a second device for executing any implementation method of the above-mentioned second aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] FIG1( a ) is a schematic diagram of the architecture of a communication system used in an embodiment of the present application;

[0047] Figure 1(b) shows a schematic diagram of a network device;

[0048] FIG2 is a schematic diagram of a 4*4 cyclic shift matrix;

[0049] FIG3 is an example diagram of a basis matrix in a unilateral QC-LDPC code;

[0050] FIG4 is an example diagram of a check matrix;

[0051] FIG5 is an example diagram of a basis matrix in a multi-edge QC-LDPC code;

[0052] FIG6 is a schematic diagram of a flow chart of an encoding method provided in an embodiment of the present application;

[0053] FIG7 is a diagram illustrating an example of a process for generating a check matrix according to an embodiment of the present application;

[0054] FIG8 is an example diagram of some elements of a check matrix;

[0055] FIG9 is an example diagram showing the relationship between the block matrix A and the matrix B;

[0056] FIG10 is an example diagram showing the relationship between the block matrix A and the matrix B;

[0057] FIG11 is an example diagram of a method for dividing a base matrix into regions;

[0058] FIG12 is a schematic diagram of a flowchart of a decoding method provided in an embodiment of the present application;

[0059] FIG13 is a diagram showing a comparison of simulation results of the embodiment of the present application and a unilateral QC-LDCP code;

[0060] FIG14 is a diagram showing a comparison of simulation results of the embodiment of the present application and a multi-edge QC-LDCP code;

[0061] FIG15 is a schematic diagram of the structure of a communication device provided in an embodiment of the present application;

[0062] FIG16 is a schematic diagram of the structure of a communication device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0063] Figure 1(a) is a schematic diagram of the architecture of the communication system used in the embodiment of the present application. The communication system 1000 shown in Figure 1(a) includes a wireless access network 100 and a core network 200. Optionally, the communication system 800 also includes the Internet 300. The wireless access network 100 may include at least one network device (such as 110a and 110b in Figure 1(a)), and may also include at least one terminal device (such as 120a-120j in Figure 1(a)). The terminal device is connected to the network device wirelessly, and the network device is connected to the core network wirelessly or wired. The core network device and the network device can be independent and different physical devices, or the functions of the core network device and the logical functions of the network device can be integrated into the same physical device, or the functions of some core network devices and some network devices can be integrated into one physical device. Terminal devices and terminal devices, as well as network devices and network devices, can be connected to each other by wire or wirelessly. FIG1( a ) is only a schematic diagram. The communication system may further include other network devices, such as wireless relay devices and wireless backhaul devices, which are not shown in FIG1( a ).

[0064] A network device is an access device that a terminal device uses to access a communication system via a wired or wireless method. A network device may be a base station, an evolved NodeB (eNodeB), a transmission reception point (TRP), a next generation NodeB (gNB) in a fifth generation (5G) mobile communication system, a next generation base station in a sixth generation (6G) mobile communication system, a base station in a future mobile communication system, or an access node in a WiFi system; it may also be a module or unit that performs some of the functions of a base station, for example, a centralized unit (CU), a distributed unit (DU), or a radio unit (RU). A network device may be a macro base station (such as 110a in FIG1(a)), a micro base station or an indoor station (such as 110b in FIG1(a)), a relay node or a donor node, etc. The embodiments of the present application do not limit the specific technology and specific device form adopted by the network device.

[0065] A terminal device is a device with wireless transceiver capabilities that can send signals to or receive signals from a network device. Terminal devices include but are not limited to terminal devices, terminals, user equipment (UE), mobile stations, mobile terminals, etc. Terminal devices can be widely used in various scenarios, such as device-to-device (D2D), vehicle-to-everything (V2X) communication, machine-type communication (MTC), Internet of Things (IoT), virtual reality, augmented reality, industrial control, autonomous driving, telemedicine, smart grid, smart furniture, smart office, smart wearable, smart transportation, smart city, etc. The terminal device can specifically be a mobile phone, tablet computer, computer with wireless transceiver capabilities, wearable device, vehicle, aircraft, ship, robot, robotic arm, smart home device, etc. The embodiments of this application do not limit the specific technology and specific device form adopted by the terminal device.

[0066] Network devices and terminal devices can be fixed or mobile. They can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; they can also be deployed on water; they can also be deployed on aircraft, balloons, and artificial satellites. The embodiments of this application do not limit the application scenarios of network devices and terminal devices.

[0067] The roles of network devices and terminal devices can be relative. For example, the helicopter or drone 120i in Figure 1(a) can be configured as a mobile network device. For terminal devices 120j that access the wireless access network 100 via 120i, terminal device 120i is a network device. However, for network device 110a, 120i is a terminal device, meaning that communication between 110a and 120i occurs via a wireless air interface protocol. Of course, communication between 110a and 120i can also occur via an interface protocol between network devices. In this case, relative to 110a, 120i is also a network device. Therefore, both network devices and terminal devices can be collectively referred to as communication devices. 110a and 110b in Figure 1(a) can be referred to as communication devices with network device functionality, and 120a-120j in Figure 1(a) can be referred to as communication devices with terminal device functionality.

[0068] Network devices and terminal devices, network devices and network devices, and terminal devices and terminal devices can communicate through authorized spectrum, unauthorized spectrum, or both; can communicate through spectrum below 6 gigahertz (GHz), spectrum above 6 GHz, or spectrum below 6 GHz and spectrum above 6 GHz simultaneously. The embodiments of the present application do not limit the spectrum resources used for wireless communications.

[0069] In the embodiments of the present application, the functions of the network device may also be performed by a module (such as a chip) in the network device, or by a control subsystem that includes the network device functions. The control subsystem that includes the network device functions here may be a control center in the above-mentioned application scenarios such as smart grid, industrial control, smart transportation, and smart city. The functions of the terminal device may also be performed by a module (such as a chip or modem) in the terminal device, or by a device that includes the terminal device functions.

[0070] Figure 1(b) shows a schematic diagram of a network device. As shown in Figure 1(b), the network device includes one or more CUs, one or more DUs, and one or more RUs. For clarity, Figure 1(b) shows only one CU, DU, and RU. The CU is connected to the core network and one or more DUs. Optionally, the CU may have some of the core network's functionality. The CU may include a CU-control plane (CP) and a CU-user plane (UP).

[0071] The CU and DU can be configured according to the protocol layer functions of the wireless network they implement: for example, the CU is configured to implement the functions of the packet data convergence protocol (PDCP) layer and the protocol layers above it (such as the radio resource control (RRC) layer and / or the service data adaptation protocol (SDAP) layer, etc.); the DU is configured to implement the functions of the protocol layers below the PDCP layer (such as the radio link control (RLC) layer, the medium access control (MAC) layer, and / or the physical (PHY) layer, etc.). For another example, the CU is configured to implement the functions of the protocol layers above the PDCP layer (such as the RRC layer and / or the SDAP layer), and the DU is configured to implement the functions of the PDCP layer and the protocol layers below it (such as the RLC layer, the MAC layer, and / or the PHY layer, etc.).

[0072] The above configuration of CU and DU is only an example, and the functions of CU and DU can also be configured as needed. For example, the CU or DU can be configured to have the functions of more protocol layers, or the CU or DU can be configured to have partial processing functions of the protocol layer. For example, some functions of the RLC layer and the functions of the protocol layers above the RLC layer are set in the CU, and the remaining functions of the RLC layer and the functions of the protocol layers below the RLC layer are set in the DU. For another example, the functions of the CU or DU can be divided according to the service type or other system requirements, such as by delay, and the functions whose processing time needs to meet the smaller delay requirement are set in the DU, and the functions that do not need to meet the delay requirement are set in the CU.

[0073] The DU and RU can work together to implement the functions of the PHY layer. A DU can be connected to one or more RUs. The functions of the DU and RU can be configured in various ways according to the design. For example, the DU is configured to implement the baseband function, and the RU is configured to implement the mid-RF function. For another example, the DU is configured to implement the high-layer functions in the PHY layer, and the RU is configured to implement the low-layer functions in the PHY layer or to implement the low-layer functions and the RF functions. The high-layer functions in the physical layer may include a part of the functions of the physical layer, which is closer to the MAC layer, and the low-layer functions in the physical layer may include another part of the functions of the physical layer, which is closer to the mid-RF side.

[0074] The CU and DU may be set separately, or may be included in the same network element, such as a baseband unit (BBU). The RU may be included in a radio frequency device or a radio frequency unit, such as a remote radio unit (RRU), an active antenna unit (AAU) or a remote radio head (RRH). In different systems, CU, DU or RU may also have different names, but those skilled in the art can understand their meanings. For example, in an open radio access network (ORAN) system, CU may also be referred to as O-CU (open CU), DU may also be referred to as O-DU, and RU may also be referred to as O-RU. Any of the CU (or CU-CP, CU-UP), DU and RU in this application may be implemented by a software module, a hardware module, or a combination of a software module and a hardware module.

[0075] To facilitate understanding of the content of this application, the nouns or terms involved in the embodiments of this application are explained below.

[0076] 1. Single-sided QC-LDPC Code

[0077] A single-sided QC-LDPC code can be represented using a base matrix. The elements in the base matrix are either 0 or 1. Element 1 in the base matrix is ​​expanded into a Zc*Zc cyclic shift matrix, and element 0 in the base matrix is ​​expanded into a Zc*Zc zero matrix. After the expansion is completed, a check matrix is ​​obtained, which can be used for encoding or decoding. Among them, Zc can be called an expansion factor, lifting factor, expansion value, expansion coefficient, lifting size, etc. The base matrix can be represented as H BG , where BG is the abbreviation of base graph.

[0078] For example, if the element in the i-th row and j-th column of the basis matrix is ​​1, it corresponds to a shifting value (SV), which can be expressed by P i,j represents the shift value corresponding to row i and column j. A shift value can be used to calculate the corresponding number of cyclic shifts.

[0079] Taking Zc=4 as an example, the matrices obtained by cyclically shifting the 4*4 unit matrix to the right by 1, 2, 3, and 0 times respectively are shown in FIG2 , that is, the cyclic shift times are 1, 2, 3, and 0 respectively.

[0080] The following is an example of a base matrix in a single-sided QC-LDPC code. The base matrix is ​​a 3*3 matrix, and it is assumed that Zc=4 and P 0,0 The corresponding number of rightward circular shifts is 1, P 0,1 The corresponding number of right circular shifts is 2, P 1,0 The corresponding number of right circular shifts is 3, P 1,2 The corresponding number of right circular shifts is 3, P 2,2 The corresponding number of rightward cyclic shifts is 1, and after expanding the base matrix, a check matrix as shown in FIG4 can be obtained.

[0081] Currently, the 3GPP 212 protocol defines various values ​​of the boost size (Zc) as shown in Table 1.

[0082] Table 1

[0083] See Table 1, the value of the lifting size Zc can be Where j represents the jth row in Table 1, j = 0, 1, 2, 3, 4, 5, 6, 7, and a0, a1, a2, a3, a4, a5, a6, a7 are 2, 3, 5, 7, 9, 11, 13, 15 respectively. k j The value of traverses 0~max(k j ), among which max(k0), max(k1), max(k2), max(k3), max(k4), max(k5), max(k6), and max(k7) are 7, 7, 6, 5, 5, 5, 4, and 4 respectively.

[0084] For example, if j=0, then a0=2, k0 traverses from 0 to 7, so the value of Zc can be 2*2 0 , 2*2 1 , 2*2 2 , 2*2 3 , 2*2 4 , 2*2 5 , 2*2 6 , 2*2 7 , that is, 2, 4, 8, 16, 32, 64, 128, and 256. The case where j is 1 to 7 is similar and will not be described in detail.

[0085] The protocol also stipulates that each row of Zc in Table 1 corresponds to a set of SVs. When constructing the check matrix, the size of Zc is first determined, and then a set of SVs corresponding to Zc is determined. Then, the check matrix is ​​constructed based on Zc and SVs.

[0086] Table 2 below is a partial example of a set of SVs defined in the 3GPP 212 protocol.

[0087] Table 2

[0088] Table 2 shows the basis matrix H BG The translation value SV corresponding to each element with a value of 1 in the 0th row of i,j The set index i in Table 2 LS This is the set index i in Table 1 LS . And, the basis matrix H BG The cyclic shift value corresponding to each element with a value of 1 in the 0th row of Zc can be obtained by taking the modulus of Zc using the translation value corresponding to the element.

[0089] It should be noted that Table 2 only shows the translation values ​​corresponding to the elements in row 0, and actually also includes the translation values ​​corresponding to the elements in other rows (eg, row 1, row 2, etc.).

[0090] Refer to Table 2, when the value of Zc is 2, 4, 8, 16, 32, 64, 128 or 256, then i LS = 0, basis matrix H BG The SVs corresponding to the elements with values ​​of 1 in the 0th row of are 250, 69, 226, 159, 100, 10, 59, 229, 110, 191, 9, 195, 23, 190, 35, 239, 31, 1, 0. Assuming Zc = 4, the basis matrix H BG The cyclic shift numbers corresponding to the elements with value 1 in the 0th row of are 250mod4, 69mod4, 226mod4, 159mod4, 100mod4, 10mod4, 59mod4, 229mod4, 110mod4, 191mod4, 9mod4, 195mod4, 23mod4, 190mod4, 35mod4, 239mod4, 31mod4, 1mod4, 0mod4, which are 2, 1, 2, 3, 0, 2, 3, 1, 2, 3, 1, 3, 3, 2, 3, 3, 3, 1, 0. That is to say, the 4*4 unit matrix is ​​cyclically shifted 2, 1, 2, 3, 0, 2, 3, 1, 2, 3, 1, 3, 3, 2, 3, 3, 3, 1, 0 times respectively, and the basis matrix H is obtained. BG The size of the matrix corresponding to each element with a value of 1 in the 0th row is 4*4. BG Each element in the 0th row with a value of 0 is updated to a zero matrix of size 4*4.

[0091] Similarly, for other values ​​of Zc, there are corresponding translation values ​​and cyclic shift times, see Table 2 for details.

[0092] Similarly, for the basis matrix H BG The corresponding Zc*Zc matrices of the rows other than the 0th row are determined by a similar method.

[0093] In the embodiment of the present application, the lifting and shifting operation of the unilateral LDPC code is described as follows: for a given lifting size Zc, from the base matrix H BG Lift to the check matrix H, specifically, the basis matrix H BG t in i,j (where t i,j =1) will be replaced by a Zc×Zc matrix I(P i,j ), where I(P i,j ) is the identity matrix I of Zc×Zc cyclic shift P i,j times (either left or right cyclic shift is acceptable) or cyclic shift P i,j mod Zc matrix, P i,j is the translation value corresponding to row i and column j; the basis matrix H BG The 0 in will be replaced by a Zc×Zc all-zero matrix. It can be seen that the purpose of lifting is to transform the basis matrix H BG To become a larger check matrix H, the purpose of translation is to transform each H BG The identity matrix corresponding to the non-zero elements of is cyclically shifted into a predefined matrix.

[0094] The decoding threshold and decoding complexity of single-sided QC-LDPC codes are mainly determined by the basis matrix. The degree distribution supported by a small-scale basis matrix is ​​relatively restricted, the decoding threshold cannot be optimized, and performance is severely impaired under extremely high bit rates. Large-scale basis matrices, without the introduction of orthogonality, have low parallelism and complex hardware implementation.

[0095] 2. Multi-edge QC-LDPC codes

[0096] In multi-edge QC-LDPC codes, the elements of the basis matrix can be 0, 1, or integers greater than 1. That is, the elements of the basis matrix can be 0, 1, 2, 3, and so on. When an element in the basis matrix is ​​x and x is greater than 1, it means that the element is expanded to the sum of x cyclic shift matrices of size Zc*Zc. When an element in the basis matrix is ​​1, it means that the element is expanded to a cyclic shift matrix of size Zc*Zc. When an element in the basis matrix is ​​0, it means that the element is expanded to a zero matrix of size Zc*Zc.

[0097] Figure 5 is an example diagram of the basis matrix in a multi-edge QC-LDPC code. In this example, the values ​​of five elements in the basis matrix are all greater than 1, and the values ​​are 3, 2, 2, 2, 2. For example, the element in row 1 and column 0 is circled in the figure. This element is 2, indicating that this element can be promoted to the sum of two cyclic shift matrices of size Zc*Zc. Taking Zc=4 as an example, the figure shows that this element is promoted to the sum of cyclic shift matrix 1 and cyclic shift matrix 2. Similar promotion is performed for other elements with values ​​greater than 1. For elements 0 and 1 in the basis matrix, the promotion method is referred to as the promotion method for single-edge QC-LDPC codes.

[0098] In the embodiment of the present application, the total number of elements in the basis matrix whose values ​​are greater than 1 is called the number of multiple edges. For example, in the basis matrix of Figure 5, there are 5 elements whose values ​​are greater than 1, so the number of multiple edges is equal to 5.

[0099] In the embodiment of the present application, the values ​​of the elements in the basis matrix that are greater than 1 are referred to as the multiplicity of the heavy edge. For example, the multiplicity of the element in row 0 and column 0 in FIG5 is 3, the multiplicity of the element in row 0 and column 1 is 2, and so on. Moreover, there is at least one maximum value among all the multiplicities, which is referred to as the maximum multiplicity of the heavy edge. For example, the maximum multiplicity of the heavy edge in FIG5 is 3.

[0100] In the embodiment of the present application, the lifting and shifting operation of the multi-edge QC-LDCP code is described as follows: for a given lifting size Zc, from the basis matrix H BG Lift to the check matrix H, specifically, the basis matrix H BG t in i,j (where t i,j ≥1) will be replaced by a Zc×Zc matrix Where I(P i,j,k ) is the identity matrix I of Zc×Zc cyclic shift P i,j,k times (either left or right circular shift is acceptable), P i,j,k is the kth translation value corresponding to the i-th row and j-th column, P i,j,k Two different, where 1≤k≤t i,j ; Basis matrix H BG The 0 in will be replaced by a Zc×Zc zero matrix. It can be seen that the purpose of lifting is to transform the basis matrix H BG To become a larger check matrix H, the purpose of translation is to transform each H BG At least one identity matrix corresponding to the non-zero elements of is cyclically shifted into a predefined matrix.

[0101] Table 3 below gives a partial example of a set of SVs.

[0102] Table 3

[0103] Refer to Table 3, taking the 0th row of the basis matrix as an example, the 0th, 1st, 5th, and 8th columns of the 0th row all correspond to 3 translation values, indicating that the multiplicity of the heavy edges is 3. Taking the element of the 0th row and 0th column as an example, when the value of the lifting size Zc corresponds to the set index i LS When is 0, the three translation values ​​corresponding to this element are 211, 165, and 111, respectively. This means that the element in row 0, column 0 is lifted to the sum of three cyclic shift matrices of size Zc*Zc, each derived based on the translation values ​​211, 165, and 111. The meanings of the other rows of the basis matrix are similar and will not be repeated here.

[0104] Due to the presence of multiple edges, multi-edge QC-LDPC codes have a larger column weight than single-edge QC-LDPC codes of the same size. Column weight refers to the number of non-zero elements in a column of the parity check matrix. Therefore, multi-edge QC-LDPC codes have a larger degree distribution design space than single-edge QC-LDPC codes, resulting in a better decoding threshold.

[0105] However, due to the correlation within the QC units (i.e., the ZC*ZC matrix) in the multi-edge QC-LDPC code, parallel reading, calculation, and storage are impossible, resulting in high latency, low hardware utilization, and uneven hardware utilization.

[0106] In summary, both single-edge QC-LDPC codes and multi-edge QC-LDPC codes in the prior art have corresponding defects. To solve this problem, this application provides corresponding embodiments, which are described in detail below.

[0107] Figure 6 is a schematic flow chart of an encoding method provided in an embodiment of the present application. The method is executed by a first device or a module (e.g., a chip) of the first device. The following description uses the first device executing the method as an example. The first device may be a terminal device, a network device, or another type of device. The specific type of the first device is not limited in the embodiment of the present application.

[0108] The method comprises the following steps:

[0109] Step 601: The first device determines a first matrix according to a base matrix, a lifting size, and a translation value corresponding to the base matrix.

[0110] Among them, the base matrix is ​​a multi-edge QC-LDPC code. Each zero element in the base matrix corresponds to a zero matrix in the first matrix, and the size of the zero matrix is ​​Zc*Zc, where Zc is the lifting size. Each non-zero element in the base matrix corresponds to a non-zero matrix in the first matrix, and the size of the non-zero matrix is ​​also Zc*Zc. When the non-zero element in the base matrix is ​​x and x is greater than 1, the size of the non-zero matrix in the first matrix corresponding to the non-zero element is Zc*Zc, and the non-zero matrix is ​​the sum of x cyclic shift matrices of size Zc*Zc. In this application, elements in the base matrix with a value greater than 1 are referred to as first elements. When the value of a non-zero element in the base matrix is ​​1, the size of the non-zero matrix in the first matrix corresponding to the non-zero element is Zc*Zc, and the non-zero matrix is ​​a cyclic shift matrix of size Zc*Zc. Among them, when the value of the non-zero element in the basis matrix is ​​1, it corresponds to one translation value; when the value of the non-zero element in the basis matrix is ​​x and x is greater than 1, it corresponds to x translation values.

[0111] Step 601 is the aforementioned process of generating a check matrix using a base matrix of a multi-edge QC-LDPC code, wherein FIG5 is an example of the process.

[0112] In one implementation method, the first device may determine a base matrix based on a target code length and / or a target code rate, and then determine a lifting size Zc based on the target code length and the base matrix.

[0113] For ease of explanation, the following uses H BG Represents the basis matrix, using H ME Represents the first matrix.

[0114] In step 602, the first device obtains a check matrix by cyclically shifting elements of at least one non-zero matrix in the first matrix.

[0115] The check matrix includes multiple block matrices, each of which corresponds to a non-zero matrix or a zero matrix in the first matrix. The size of the block matrix is ​​Zc*Zc, and each block matrix is ​​composed of multiple sub-matrices, each of which is a zero matrix or a non-zero matrix with both row and column weights of 1. A sub-matrix with a row weight of 1 means that only one element in each row is 1, and all other elements are 0. A sub-matrix with a column weight of 1 means that only one element in each column is 1, and all other elements are 0.

[0116] Exemplarily, for each submatrix in the block matrix, if the submatrix is ​​a non-zero matrix with both row weight and column weight being 1, the submatrix may be a cyclic shift matrix.

[0117] In this step, the elements of at least one non-zero matrix in the first matrix that is cyclically shifted are aligned with the base matrix H. BGIt corresponds to at least one first element (ie, an element with a value greater than 1) in , and corresponds to at least one block matrix in the check matrix.

[0118] For ease of explanation, H is used below to represent a check matrix, and A is used to represent a block matrix.

[0119] FIG7 is an example diagram of the process of generating a check matrix. The first device first generates a check matrix according to H BG Generate H ME , then according to H ME Generate H. In the example of Figure 7, H ME Each square in represents a matrix of size Zc*Zc. And, H ME in and H BG The square corresponding to the element 0 is the zero matrix, H ME Zhong and H BG The square corresponding to element 1 (i.e., the element with value 1) is a cyclic shift matrix, H ME The corresponding H BG The square corresponding to the element x (that is, the element with value x and x greater than 1) is the sum of x cyclic shift matrices.

[0120] Furthermore, the first device H ME Move some or all of the elements 1 in to obtain H. In Figure 7, each circle in H represents a block matrix A of size Zc*Zc. Each block matrix A consists of multiple sub-matrices, and each sub-matrix is ​​a zero matrix, or a non-zero matrix with both row weight and column weight 1.

[0121] The block matrix in the check matrix H and the first matrix H ME The matrices of size Zc*Zc in the . For example, the first matrix H ME The element 1 of a part of the Zc*Zc matrix in is moved to obtain the corresponding block matrix in the check matrix H.

[0122] FIG8 is an example diagram of some elements of the check matrix. This example is for H in FIG7 BG An example of the change process of the first row elements of . And assuming Zc=6, then H BG Each element in the first row corresponds to the first matrix H ME It should be noted that only the elements with a value of 1 are marked in FIG8 , and the values ​​of the unmarked elements are all 0. For the first matrix H ME Each 6*6 matrix in the 6*6 matrix is ​​shifted by some of the elements 1 (see the figure for illustration), thereby obtaining the check matrix H, which corresponds to H BGThere are five block matrices with the first row element, namely block matrices A1 to A5. Block matrices A1 to A5 are composed of four sub-matrices, each of which is 3*3 in size, and each sub-matrix is ​​a non-zero matrix with both row and column weights of 1.

[0123] FIG8 shows only the H in FIG7 BG The change process of the first row elements of H in Figure 7 BG The change process of the elements in the second and third rows is similar and will not be described in detail.

[0124] Some features of the check matrix H obtained after the operation of step 602 are described below.

[0125] First, about H BG Each non-zero element of (assuming the multiplicity of the edge is t, that is, the value of the non-zero element is t) corresponds to a block matrix A of the check matrix H, where A is divided into l*l sub-matrices (t≤l), where each A i,j There are only two cases, either a zero matrix or a matrix with both row and column weights 1, and each A i,j The scale is (where Zc is an integer multiple of l) or (where Zc is not an integer multiple of l and Zc′ is an integer multiple of l). Here, Zc′=Zc+l-mod(Zc,l). mod represents a modulo operation. The meaning of Zc′ is explained here in a unified manner and will not be repeated here.

[0126] In one possible implementation method, at least one block matrix in the check matrix H includes a second block matrix (hereinafter also referred to as matrix A), the second block matrix is ​​composed of l*l sub-matrices, the second block matrix corresponds to the second matrix (hereinafter also referred to as matrix B), the size of the second matrix is ​​l*l, and the elements in the second matrix correspond one-to-one to the sub-matrices in the second block matrix; if the value of the element in the second matrix is ​​0, then the corresponding sub-matrix in the second block matrix is ​​a zero matrix; or, if the value of the element in the second matrix is ​​1, then the corresponding sub-matrix in the second block matrix is ​​a non-zero matrix. The relationship between the block matrix A and the matrix B is described in detail below. If the value of the i row and j column of the matrix B is 1, it means that A in the block matrix A i,j is a non-zero matrix, and the value of row i and column j of matrix B is 0, which means that A in the block matrix A i,j is a zero matrix.

[0127] The matrix B can be considered as being generated by "lifting", but it is not limited to the quasi-cyclic lifting method. The "lifting" here can be represented by t permutations, that is, the i-th permutation The connection relationship of matrix B is j rows and The columns are connected, and any j-th position of the permutation of i1 and i2 satisfies In one implementation method, the above permutations are all cyclic, that is, p j =(j+s)mod l, s is a value between 0 and l-1. In this implementation, the matrix B = I(p1,…,p t ), where I(p1,…,p t )=I(p1)+…+I(p t ), where I(p k ) is the identity matrix of Zc*Zc I cyclic shift p k The matrix of the second (left or right), p k are not equal to each other, where 1≤k≤t.

[0128] Figure 9 is an example diagram of the relationship between the block matrix A and the matrix B. In Figure 9, the values ​​of the unmarked elements in each matrix are all 0. BG An element with a value greater than 1 (for example, the element has a value of 2, that is, the multiplicity of the heavy edge t=2), the element is expanded to a 12*12 non-zero matrix, that is, Zc=12. After cyclic shift, the non-zero matrix changes into a block matrix A shown in the figure, and l=4. Therefore, the block matrix A includes 4*4 (that is, 16) sub-matrices. And each sub-matrix is ​​a zero matrix or a non-zero matrix. When the sub-matrix is ​​a non-zero matrix, the row weight and column weight of the sub-matrix are both 1, that is, only one element in each row is 1, and the rest are 0, and only one element in each column is 1, and the rest are 0. The size of each sub-matrix is ​​3*3. Furthermore, for each block matrix A, there is a corresponding matrix B, where if a sub-matrix in the block matrix A is a zero matrix, the sub-matrix corresponds to the element 0 at the same position in the matrix B, and if a sub-matrix in the block matrix A is a non-zero matrix, the sub-matrix corresponds to the element 1 at the same position in the matrix B. Therefore, the matrix B is a matrix of size l*l, and its elements are either 0 or 1. The row weight and column weight of the matrix B are both t, which is the same as the basis matrix H. BG The corresponding elements have the same value.

[0129] As an implementation method, the matrix B is the result of adding t circular shift matrices of size l*l. The positions of the values ​​1 in the matrix B can be represented as follows: for the matrix B, use B(a, b) to represent the element in the ath row and bth column, then B(i, mod(i+s k -1,l)+1)=1. Among them, i=1,2,…,l, and k=1,2,…,t. That is, the mod(i+s k The value of the elements in the column -1,l) is 1. mod(i+sk -1, l) represents i + s k -1 modulo l. Therefore, B(i, mod(i + s1 - 1, l) + 1) = 1, B(i, mod(i + s2 - 1, l) + 1) = 1, …, B(i, mod(i + s t -1, l) + 1) = 1, where s1, s2, …, s t Determined by t translation values Y1, …, Y of the non - 0 elements in the basis matrix corresponding to matrix A t And Zc and l. Exemplarily, Or, Where, Y k Represents the k - th translation value among the t translation values. That is, Or Where, [[ID=​​​​​​​​​​​​​​​​​​In the above scheme, the parity check matrix used to encode the first information includes multiple sub-matrices, each of which is a zero matrix or a non-zero matrix with both row and column weights of 1. Therefore, each sub-matrix is ​​an orthogonal matrix, which can achieve parallel decoding with low decoding complexity, reduce communication latency, and thus improve communication efficiency. Specifically, this scheme introduces orthogonality into multi-edge QC-LDPC codes without changing the degree distribution, allowing for parallel decoding. This solves the problems of limited degree distribution and small design space of single-edge QC-LDPC codes, and also addresses the high decoding complexity and high latency of multi-edge QC-LDPC codes.

[0133] In the embodiment of the present application, if Zc is a multiple of l, the increased size is Zc. If Zc is not a multiple of l, the increased size can be considered to be Zc′=Zc+l-mod(Zc,l) (i.e., the increased size is simulated, not actually increased, and the actual value is still Zc), and the additional expanded matrix part is in H ME The matrix is ​​filled with all zeros. The change in matrix size is only used to indicate the cyclic shift and does not affect the actual matrix expansion. Here, l indicates the number of submatrices in the block matrix. Specifically, the number of submatrices in the block matrix is ​​equal to l*l.

[0134] The following is an exemplary description of some methods in the process of the first device obtaining the check matrix according to the first matrix in the above step 602.

[0135] In one implementation, H is changed during the cyclic shift. ME The position of 1 in H ME The 1 in the row is swapped with a 0 in the same row, or, ME The 1 in the column is swapped with a 0 in the same column. ME If you need to swap the position of element 1 and element 0 in a matrix of size Zc*Zc, you can either swap all the elements in the same row or all the elements in the same column.

[0136] In another implementation method, H ME The element 1 corresponding to a translation value in the image is partially translated, while the other elements 1 remain unchanged. ME Circularly shifting the elements of at least one non-zero matrix in the first matrix refers to shifting some elements 1 corresponding to a shift value in the first matrix.

[0137] In another implementation method, H METhe element 1 in the matrix corresponds to a translation value. If it needs to be translated, the translation method is the same, that is, a fixed translation amount to the left (or right). The translation amount is related to the lifting size Zc and the number of sub-matrices (i.e., l*l) contained in the block matrix corresponding to the element of at least one non-zero matrix. For example, when Zc is an integer multiple of l, the translation amount is or When Zc is not an integer multiple of l, the translation is or Based on this implementation method, the above step 602 may specifically be: the first device calculates the first matrix H ME The elements of the at least one non-zero matrix are cyclically shifted leftward or rightward based on the translation amount corresponding to the elements of the at least one non-zero matrix in , to obtain the check matrix H.

[0138] In another implementation method, H ME The corresponding translation value is or The elements 1 that are non-negative integer multiples of , are not cyclically shifted. It can be understood that the above step 602 describes the operation of H ME The elements of at least one non-zero matrix in are cyclically shifted, and the elements of the at least one non-zero matrix do not include the first type element 1, the first type element 1 corresponds to a translation value, and the translation value is or The block matrix in the check matrix H corresponding to the first type of 1 is composed of l*l sub-matrices.

[0139] In another implementation method, the first matrix H ME The corresponding basis matrix H BG The element with value l in the , if the l translation value pairs corresponding to the element or If the remainders obtained after the modulo operation are the same, the element is not cyclically shifted. It can be understood that the first matrix H described in step 602 is ME The elements of at least one non-zero matrix in the cyclic shift are excluding the second type element 1, the second type 1 corresponds to l translation values, and l translation value pairs or The remainders obtained after the modulo operation are the same. The block matrix in the check matrix H corresponding to the second type element 1 is composed of l*l sub-matrices.

[0140] The relationship between l and the multiplicity t of the multiple edges defined in the embodiments of the present application is described below.

[0141] For the basis matrix H BGThe i-th row and j-th column of the , assuming that the multiplicity of its heavy edge is t i,j , the size of the corresponding block matrix is ​​l i,j .

[0142] In one implementation method, the basis matrix H BG Any multi-edge of has t i,j ≤l i,j The advantage of this implementation is that, at t i,j ≤l i,j In this case, H BG t i,j Promoted to mutually orthogonal sub-units to achieve parallel decoding. Or expressed as, the basis matrix H BG The first element includes a first element in the basis matrix, the first element being an element whose multiplicity of multiple edges is greater than 1, the first element corresponding to the first block matrix in the check matrix, the size of the first block matrix being l1*l1, and the multiplicity of multiple edges of the first element being less than or equal to l1.

[0143] In one implementation method, the basis matrix H BG The block matrices in the check matrix H corresponding to the elements in the same row have the same size. That is, for H BG The i-th row, each of its associated columns j, has l i,j = l(i), that is, all positions in this row share a partition scale l(i), which is only related to the number of rows, not the number of columns. Or it can be expressed as, the basis matrix H BG Each block matrix in the parity check matrix H corresponding to each element in the same row is composed of l2*l2 submatrices. This approach prevents elements in the same row from corresponding to block matrices of different sizes. The advantage of this implementation is that it allows for a regular division of the parallel decoding units for the parity check equation, simplifies the memory storage structure for the entire parity check equation, and reduces hardware complexity.

[0144] In one implementation method, the basis matrix H BG The block matrices in the check matrix H corresponding to each element in the same row contain the same number of sub-matrices, for example, each contains l2*l2 sub-matrices, and l2 is the maximum multiplicity of the multiple edges of each element in the same row. For example, the base matrix H BG The size of the block matrices corresponding to the elements in the i-th row is the same (for example, all are l(i)*l(i)) and is the maximum number of edges in the row, that is, l(i) = max j∈N(i) t i,j , where N(i) is the set of columns associated with row i. It should be noted that the block matrices in the check matrix H corresponding to different rows can have different sizes. That is, l(i) = max j∈N(i) t i,j , l(k)=max j∈N(k) tk,j , where N(i) is the set of columns associated with the i-th row, and N(k) is the set of columns associated with the k-th row. l(i) and l(k) can be equal or different. This implementation method achieves parallel block decoding without memory conflicts at the lowest cost, while maximizing parallelism.

[0145] In one implementation method, the basis matrix H BG The size of the block matrix in the check matrix H corresponding to the element in the i-th row and j1-th column of Basis matrix H BG The size of the block matrix in the check matrix H corresponding to the element in the i-th row and j2-th column of Among them, j1≠j2, or Here, x is an integer greater than 1. The advantage of this implementation method is that, although the parallel decoding unit cannot be divided into the most regular form for the check equation, the memory storage structure of the entire check equation is still simple, the hardware complexity is low, and a larger design space can be achieved, with a better code structure.

[0146] In one implementation method, the basis matrix H BG Including the first sub-matrix region, the multiplicity of the elements in the first sub-matrix region is t, and each block matrix corresponding to the first sub-matrix region in the check matrix H contains l3*l3 sub-matrices, and t=l3. That is, the base matrix H BG In the first sub-matrix region of , all the multi-edge numbers t and l are equal. The first sub-matrix region can be the base matrix H BG The first sub-matrix region may be a sub-matrix region whose code rate is greater than or equal to the code rate threshold (for example, the code rate threshold is equal to 22 / 24, or 44 / 47, or 948 / 1024). Alternatively, the first sub-matrix region may be a base matrix H BG Alternatively, the first sub-matrix region may be a sub-matrix region having a row number greater than or equal to a row number threshold (for example, the row number threshold is equal to 3, or 4, or 5) among the multiple sub-matrix regions of the base matrix H. BG Alternatively, the first sub-matrix region may be a sub-matrix region corresponding to a high-rate information column in the plurality of sub-matrix regions of the base matrix H. BG The submatrix region corresponding to the high-rate core check among the multiple submatrix regions (also referred to as region B) of the .This implementation method has the most unified hardware form, does not need to distinguish specific positions at all, and the cyclic shift method of each position is exactly the same. At the same time, the protocol description is the most concise.

[0147] Refer to Figure 11, which shows the region division method of the base matrix. Among them, region A corresponds to the high-rate information column, region B corresponds to the high-rate core check region, region C is the zero matrix, region D is the incremental redundancy part of the base matrix and corresponds to the low code rate, and region E is the incremental redundancy region and the unit matrix.

[0148] It should be noted that in the various implementations described above, the protocol needs to store l values ​​associated with rows, columns, or matrix regions, so that the embodiment of FIG. 6 can be implemented based on l and t. Furthermore, l1, l2, and l3 used in the above description may be equal to or different from each other, and this is not limited here.

[0149] The encoding process described in the embodiment of FIG. 6 and the corresponding specific implementation method is equivalent to the decoding process. For example, after the first device generates the second information, it sends the second information to the second device, and the second device receives third information. The third information is the superposition of the second information and interference noise. The decoding process is described in the embodiment of FIG. 12 below.

[0150] Figure 12 is a schematic flow chart of a decoding method provided in an embodiment of the present application. The method is executed by a second device or a module (e.g., a chip) of the second device. The following description uses the second device executing the method as an example. The second device may be a terminal device, a network device, or another type of device. The specific type of the second device is not limited in the embodiments of the present application.

[0151] The method comprises the following steps:

[0152] Step 1201: The second device obtains third information.

[0153] Step 1202: The second device determines a first matrix according to the base matrix, the lifting size, and the translation value corresponding to the base matrix.

[0154] Step 1203: The second device obtains a check matrix by performing a cyclic shift on elements of at least one non-zero matrix in the first matrix.

[0155] Step 1204: The second device decodes the third information according to the check matrix to obtain the first information.

[0156] Among them, steps 1202 to 1203 are the same as steps 602 to 603 in the embodiment of FIG. 6 , and reference may be made to the aforementioned description.

[0157] In the above scheme, the parity check matrix used to decode the third information includes multiple sub-matrices, each of which is a zero matrix or a non-zero matrix with both row and column weights of 1. Therefore, each sub-matrix is ​​an orthogonal matrix, enabling parallel decoding with low decoding complexity, reducing communication latency, and thereby improving communication efficiency. Specifically, this scheme introduces orthogonality into multi-edge QC-LDPC codes without changing the degree distribution, enabling parallel decoding. This solves the problems of limited degree distribution and small design space of single-edge QC-LDPC codes, while also addressing the high decoding complexity and high latency of multi-edge QC-LDPC codes.

[0158] The embodiment of FIG. 6 and the embodiment of FIG. 12 may be combined as an embodiment, or may be implemented separately, and this application does not limit this.

[0159] The following simulation results illustrate the performance improvement brought about by the encoding or decoding method in the embodiments of the present application.

[0160] FIG13 is a comparison diagram of the simulation results of the embodiment of the present application and the unilateral QC-LDCP code. The vertical axis is the block error rate (BLER) reaching 10 -2 The corresponding signal-to-noise ratio (SNR) under the condition of , the horizontal axis is the number of iterations. It can be seen that when the code rate is 44 / 47, the performance achieved by 8 iterations of the prior art is close to the performance achieved by 4 iterations of the present invention; when the code rate is 11 / 12, the performance achieved by 7 iterations of the prior art is close to the performance achieved by 4 iterations of the present invention; when the code rate is 7 / 8, the performance achieved by 7 iterations of the prior art is close to the performance achieved by 4 iterations of the present invention; when the code rate is 3 / 4, the performance achieved by 6 iterations of the prior art is close to the performance achieved by 4 iterations of the present invention. Combined with hardware evaluation, compared with the single-sided QC-LDPC code of the prior art, the throughput gain of the solution of the present invention is more than 2 times.

[0161] FIG14 is a comparison diagram of the simulation results of the embodiment of the present application and the multi-edge QC-LDCP code. -2 The corresponding SNR under the condition of [number of iterations] is plotted on the horizontal axis. It can be seen that the decoding method of the present invention (also known as layered decoding) has the fastest convergence speed and the best performance. However, the two decoding methods in the prior art, namely flooding decoding and localized flooding decoding, have slower convergence speeds and suffer performance losses compared to layered decoding at each iteration number.

[0162] It is understandable that in order to implement the functions in the above embodiments, the first device or the second device includes hardware structures and / or software modules corresponding to the execution of each function. It should be readily apparent to those skilled in the art that, in combination with the units and method steps of each example described in the embodiments disclosed in this application, this application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in hardware or in a computer software-driven hardware manner depends on the specific application scenario and design constraints of the technical solution.

[0163] Figures 15 and 16 are schematic diagrams of the structures of possible communication devices provided in embodiments of the present application. These communication devices can be used to implement the functions of the first device or the second device in the above method embodiments, and thus can also achieve the beneficial effects of the above method embodiments. In the embodiments of the present application, the communication device can be the first device or the second device, and can also be a module (such as a chip) applied to the first device or the second device.

[0164] The communication device 1500 shown in Figure 15 includes a processing unit 1510 and a transceiver unit 1520. The communication device 1500 is used to implement the functions of the first device or the second device in the above method embodiment.

[0165] When the communication device 1500 is used to implement the functions of the first device in the above-mentioned method embodiment, the processing unit 1510 is configured to determine a first matrix based on a base matrix, a lifting size, and a translation value corresponding to the base matrix; wherein the base matrix includes a first element, which is an element in the base matrix having a value greater than 1; each zero element in the base matrix corresponds to a zero matrix in the first matrix, and each non-zero element in the base matrix corresponds to a non-zero matrix in the first matrix; a check matrix is ​​obtained by cyclically shifting the elements of at least one non-zero matrix in the first matrix; wherein the at least one non-zero matrix corresponds to at least one first element in the base matrix; the check matrix includes multiple block matrices, at least one block matrix in the multiple block matrices corresponds one-to-one to the at least one non-zero matrix, and the at least one block matrix is ​​composed of multiple sub-matrices, each sub-matrix being a zero matrix or a non-zero matrix with both row weight and column weight being 1; and encoding the first information according to the check matrix to obtain the second information. The transceiver unit 1520 is configured to send the second information.

[0166] When the communication device 1500 is used to implement the function of the second device in the above method embodiment, the transceiver unit 1520 is used to obtain the third information; the processing unit 1510 is used to determine the first matrix according to the base matrix, the lifting size and the translation value corresponding to the base matrix; wherein the base matrix includes a first element, and the first element is an element in the base matrix whose value is greater than 1; wherein each zero element in the base matrix corresponds to a zero matrix in the first matrix, and each non-zero element in the base matrix corresponds to a non-zero matrix in the first matrix; a check matrix is ​​obtained by cyclically shifting the elements of at least one non-zero matrix in the first matrix; wherein the at least one non-zero matrix corresponds to at least one first element in the base matrix, and the check matrix includes multiple block matrices, and at least one block matrix in the multiple block matrices corresponds one-to-one to the at least one non-zero matrix, and the at least one block matrix is ​​composed of multiple sub-matrices, and the sub-matrix is ​​a zero matrix, or a non-zero matrix with both row weight and column weight being 1; the third information is decoded according to the check matrix to obtain the first information.

[0167] Illustratively, the first device or the second device may further provide any one or more of the following implementation methods:

[0168] In a possible implementation method, the multiple block matrices include a first block matrix, the first block matrix is ​​composed of l1*l1 sub-matrices, and the value of the first element corresponding to the first block matrix is ​​less than or equal to l1.

[0169] In a possible implementation method, the block matrices in the check matrix corresponding to each element in the same row of the base matrix are composed of l2*l2 sub-matrices.

[0170] In a possible implementation method, l2 is the maximum value of the values ​​of the elements in the same row.

[0171] In a possible implementation method, the element in the i-th row and j1-th column of the base matrix corresponds to the block matrix in the check matrix. The element in the i-th row and j2-th column of the base matrix corresponds to the size of the block matrix in the check matrix. sub-matrices; where j1≠j2, or Wherein x is an integer greater than 1.

[0172] In one possible implementation method, the base matrix includes a first submatrix region, the values ​​of the elements in the first submatrix region are all t, and each block matrix corresponding to the first submatrix region in the check matrix is ​​composed of l3*l3 submatrices, and t=l3.

[0173] In one possible implementation method, the code rate of the first sub-matrix area is greater than or equal to the code rate threshold; or, the number of rows in the first sub-matrix area is greater than or equal to the row number threshold; or, the first sub-matrix area corresponds to a high code rate information column; or, the first sub-matrix area corresponds to a high code rate core check.

[0174] In one possible implementation method, the elements of the at least one non-zero matrix do not include a first type of 1, the first type of 1 corresponds to a translation value, and the translation value is A non-negative integer multiple of or A non-negative integer multiple of Zc′=Zc+l-mod(Zc,l);

[0175] Here, Zc represents the lifting size, the block matrix corresponding to the first type 1 is composed of l*l sub-matrices, and mod represents a modulo operation.

[0176] In a possible implementation method, the elements of the at least one non-zero matrix do not include a second type of 1, the second type of 1 corresponds to l translation values, and the l translation values ​​are or The remainders obtained after modulo are the same; Zc′=Zc+l-mod(Zc,l);

[0177] Here, Zc represents the lifting size, the block matrix corresponding to the second type 1 is composed of l*l sub-matrices, and mod represents a modulo operation.

[0178] In one possible implementation method, the processing unit 1510 is used to obtain a check matrix by cyclically shifting the elements of at least one non-zero matrix in the first matrix, specifically including: cyclically shifting the elements of the at least one non-zero matrix to the left or right according to the translation amount corresponding to the elements of the at least one non-zero matrix to obtain the check matrix; wherein the translation amount is related to the lifting size and the number of sub-matrices contained in the block matrix corresponding to the elements of the at least one non-zero matrix.

[0179] In one possible implementation method, the translation amount is any one of the following:

[0180] or Zc′=Zc+l-mod(Zc,l);

[0181] Wherein, Zc represents the lifting size, the block matrix corresponding to the elements of the at least one non-zero matrix is ​​composed of l*l sub-matrices, and mod represents a modulo operation.

[0182] In one possible implementation method, the at least one block matrix includes a second block matrix, the second block matrix is ​​composed of l*l sub-matrices, the second block matrix corresponds to the second matrix, the size of the second matrix is ​​l*l, and the elements in the second matrix correspond one-to-one to the sub-matrices in the second block matrix; if the value of the element in the second matrix is ​​0, the corresponding sub-matrix in the second block matrix is ​​a zero matrix; or, if the value of the element in the second matrix is ​​1, the corresponding sub-matrix in the second block matrix is ​​a non-zero matrix.

[0183] In a possible implementation method, the mod(i+s k -1,l) columns have values ​​of 1, i=1,2,…,l, and k=1,2,…,t; among them, s1,s2,…,s t The t translation values ​​are determined by t translation values, the l, and the lifting size, where the t translation values ​​are translation values ​​of the first element in the base matrix corresponding to the second block matrix.

[0184] In one possible implementation method, or, Wherein, Zc is the lifting size, Y k represents the kth translation value among the t translation values, Indicates rounding down. Indicates rounding up.

[0185] In one possible implementation method, the second matrix is ​​composed of N sub-matrices, each of the N sub-matrices is a zero matrix, or a matrix obtained by adding t cyclic shift matrices, where t is the value of the first element in the base matrix corresponding to the second block matrix.

[0186] In a possible implementation method, the non-zero matrix with both row weight and column weight of 1 is a cyclic shift matrix.

[0187] For a more detailed description of the processing unit 1510 and the transceiver unit 1520, reference can be made to the relevant description in the above method embodiment, which will not be repeated here.

[0188] The communication device 1600 shown in Figure 16 includes a processor 1610 and an interface circuit 1620. The processor 1610 and the interface circuit 1620 are coupled to each other. It will be appreciated that the interface circuit 1620 may be a transceiver or an input / output interface. Optionally, the communication device 1600 may further include a memory 1630 for storing instructions executed by the processor 1610, or storing input data required by the processor 1610 to execute instructions, or storing data generated after the processor 1610 executes instructions.

[0189] When the communication device 1600 is used to implement the above method embodiment, the processor 1610 is used to implement the functions of the above processing unit 1510 , and the interface circuit 1620 is used to implement the functions of the above transceiver unit 1520 .

[0190] It is understood that the processor in the embodiments of the present application may be a central processing unit (CPU), or may be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. The general-purpose processor may be a microprocessor or any conventional processor.

[0191] The method steps in the embodiments of the present application can be implemented by hardware or by a processor executing software instructions. The software instructions can be composed of corresponding software modules, and the software modules can be stored in random access memory, flash memory, read-only memory, programmable read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, hard disks, mobile hard disks, compact disc read-only memory (CD-ROM) or any other form of storage medium well known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be an integral part of the processor. The processor and the storage medium can be located in an ASIC. In addition, the ASIC can be located in the first device or the second device. Of course, the processor and the storage medium can also exist as discrete components in the access network device or the terminal.

[0192] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer programs or instructions. A computer program refers to a set of instructions that instruct an electronic computer or other device with message processing capabilities to perform each step of the action, usually written in a certain programming language and running on a certain target architecture. When the computer program or instruction is loaded and executed on a computer, the process or function described in the embodiment of the present application is executed in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network or other programmable device. The computer program or instruction can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer program or instruction can be transmitted from one website, computer, server or data center to another website, computer, server or data center by wired or wireless means. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that integrates one or more available media. The available medium may be a magnetic medium, such as a floppy disk, a hard disk, or a magnetic tape; an optical medium, such as a digital video disk; or a semiconductor medium, such as a solid-state drive. The computer-readable storage medium may be a volatile or non-volatile storage medium, or may include both volatile and non-volatile types of storage media.

[0193] In the various embodiments of the present application, unless otherwise specified or there is a logical conflict, the terms and / or descriptions between different embodiments are consistent and can be referenced by each other. The technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationships.

[0194] In this application, "at least one" means one or more, and "more" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. In the text description of this application, the character " / " generally indicates that the previous and next related objects are in an "or" relationship; in the formulas of this application, the character " / " indicates that the previous and next related objects are in a "division" relationship.

[0195] It is understood that the various numbers used in the embodiments of this application are merely for ease of description and are not intended to limit the scope of the embodiments of this application. The order of the sequence numbers of the above-mentioned processes does not necessarily imply a specific order of execution; the order of execution of the processes should be determined by their functions and inherent logic.

Claims

1. A coding method, characterized in that: The method comprises: Determine a first matrix according to a base matrix, a lifting size, and a translation value corresponding to the base matrix; wherein the base matrix includes a first element, and the first element is an element in the base matrix whose value is greater than 1; each zero element in the base matrix corresponds to a zero matrix in the first matrix, and each non-zero element in the base matrix corresponds to a non-zero matrix in the first matrix; A check matrix is ​​obtained by cyclically shifting elements of at least one non-zero matrix in the first matrix; wherein the at least one non-zero matrix corresponds to at least one first element in the base matrix, the check matrix includes a plurality of block matrices, at least one block matrix among the plurality of block matrices corresponds one-to-one to the at least one non-zero matrix, the at least one block matrix is ​​composed of a plurality of sub-matrices, and the sub-matrix is ​​a zero matrix, or a non-zero matrix with both row weight and column weight being 1; The first information is encoded according to the check matrix to obtain second information.

2. A decoding method, characterized in that: The method comprises: Obtaining third-party information; Determine a first matrix according to a base matrix, a lifting size, and a translation value corresponding to the base matrix; wherein the base matrix includes a first element, and the first element is an element in the base matrix whose value is greater than 1; wherein each zero element in the base matrix corresponds to a zero matrix in the first matrix, and each non-zero element in the base matrix corresponds to a non-zero matrix in the first matrix; A check matrix is ​​obtained by cyclically shifting elements of at least one non-zero matrix in the first matrix; wherein the at least one non-zero matrix corresponds to at least one first element in the base matrix, the check matrix includes a plurality of block matrices, at least one block matrix among the plurality of block matrices corresponds one-to-one to the at least one non-zero matrix, the at least one block matrix is ​​composed of a plurality of sub-matrices, and the sub-matrix is ​​a zero matrix, or a non-zero matrix with both row weight and column weight being 1; The third information is decoded according to the check matrix to obtain the first information.

3. The method according to claim 1 or 2, wherein: The multiple block matrices include a first block matrix, the first block matrix is ​​composed of l1*l1 sub-matrices, and the value of the first element corresponding to the first block matrix is ​​less than or equal to l1.

4. The method according to any one of claims 1 to 3, characterized in that The block matrices in the check matrix corresponding to each element in the same row of the base matrix are all composed of l2*l2 sub-matrices.

5. The method according to claim 4, wherein The l2 is the maximum value of the values ​​of the elements in the same row.

6. The method according to any one of claims 1 to 3, characterized in that The element in the i-th row and j1-th column of the base matrix corresponds to the block matrix in the check matrix. The element in the i-th row and j2-th column of the base matrix corresponds to the size of the block matrix in the check matrix. sub-matrices; where j1≠j2, or Wherein x is an integer greater than 1.

7. The method according to any one of claims 1 to 5, characterized in that The base matrix includes a first submatrix region, the values ​​of the elements in the first submatrix region are all t, and each block matrix corresponding to the first submatrix region in the check matrix is ​​composed of l3*l3 submatrices, and t=l3.

8. The method according to claim 7, wherein The coding rate of the first sub-matrix region is greater than or equal to a coding rate threshold; or, The number of rows in the first sub-matrix region is greater than or equal to a row number threshold; or, The first sub-matrix region corresponds to a high-rate information column; or, The first sub-matrix region corresponds to a high-rate core check.

9. The method according to any one of claims 1 to 8, characterized in that The elements of the at least one non-zero matrix do not include a first type of 1, the first type of 1 corresponds to a translation value, and the translation value is A non-negative integer multiple of or A non-negative integer multiple of Zc′=Zc+l-mod(Zc,l); Here, Zc represents the lifting size, the block matrix corresponding to the first type 1 is composed of l*l sub-matrices, and mod represents a modulo operation.

10. The method according to any one of claims 1 to 8, characterized in that The elements of the at least one non-zero matrix do not include a second type of 1, the second type of 1 corresponds to l translation values, and the l translation values ​​are or The remainders obtained after modulo are the same; Zc′=Zc+l-mod(Zc,l); Here, Zc represents the lifting size, the block matrix corresponding to the second type 1 is composed of l*l sub-matrices, and mod represents a modulo operation.

11. The method according to any one of claims 1 to 8, characterized in that The step of obtaining a check matrix by cyclically shifting elements of at least one non-zero matrix in the first matrix includes: The elements of the at least one non-zero matrix are cyclically shifted leftward or rightward according to the translation amount corresponding to the elements of the at least one non-zero matrix to obtain the check matrix; wherein the translation amount is related to the lifting size and the number of sub-matrices contained in the block matrix corresponding to the elements of the at least one non-zero matrix.

12. The method according to claim 11, wherein The translation amount is any of the following: or Zc′=Zc+l-mod(Zc,l); Wherein, Zc represents the lifting size, the block matrix corresponding to the elements of the at least one non-zero matrix is ​​composed of l*l sub-matrices, and mod represents a modulo operation.

13. The method according to any one of claims 1 to 12, characterized in that The at least one block matrix includes a second block matrix, the second block matrix is ​​composed of l*l sub-matrices, the second block matrix corresponds to the second matrix, the size of the second matrix is ​​l*l, and the elements in the second matrix correspond one-to-one to the sub-matrices in the second block matrix; If the value of an element in the second matrix is ​​0, the corresponding submatrix in the second block matrix is ​​a zero matrix; or, If the value of an element in the second matrix is ​​1, the corresponding sub-matrix in the second block matrix is ​​a non-zero matrix.

14. The method according to claim 13, wherein The mod(i+s k -1, l) columns have values ​​of 1, i = 1, 2, ..., l, and k = 1, 2, ..., t; Among them, s1, s2, …, s t The t translation values ​​are determined by t translation values, the l, and the lifting size, where the t translation values ​​are translation values ​​of the first element in the base matrix corresponding to the second block matrix.

15. The method according to claim 14, wherein or, Wherein, Zc is the lifting size, Y k represents the kth translation value among the t translation values, Indicates rounding down. Indicates rounding up.

16. The method according to claim 13, wherein The second matrix is ​​composed of N sub-matrices, each of the N sub-matrices is a zero matrix, or a matrix obtained by adding t cyclic shift matrices, where t is the value of the first element in the base matrix corresponding to the second block matrix.

17. The method according to any one of claims 1 to 16, characterized in that The non-zero matrix whose row weight and column weight are both 1 is a cyclic shift matrix.

18. A communication device, characterized in that: The method comprises a unit for executing the method according to any one of claims 1, 3 to 17, or executing the method according to any one of claims 2 to 17.

19. A communication device, characterized in that: The device comprises a processor and an interface circuit, wherein the processor is configured to communicate with other devices via the interface circuit and execute the method according to any one of claims 1 and 3 to 17, or execute the method according to any one of claims 2 to 17.

20. The communication device according to claim 19, wherein: It also includes a memory for storing computer instructions, and the processor is used to execute the computer instructions, so that the communication device performs the method as described in any one of claims 1, 3 to 17; or the communication device performs the method as described in any one of claims 2 to 17.

21. A computer program product, characterized in that The computer program product comprises instructions, which, when executed on a processor, cause the processor to execute the method according to any one of claims 1, 3 to 17, or execute the method according to any one of claims 2 to 17.

22. A computer-readable storage medium, characterized in that The storage medium stores a computer program or instruction. When the computer program or instruction is executed by the communication device, the method described in any one of claims 1, 3 to 17, or the method described in any one of claims 2 to 17 is implemented.

23. A chip, characterized in that: The invention comprises a processor coupled to a memory, wherein the memory stores a computer program; the processor is used to call part or all of the computer program in the memory, so that the method described in any one of claims 1 and 3 to 17 is executed, or the method described in any one of claims 2 to 17 is executed.

Images