Semiconductor device

Abstract

This semiconductor device comprises: a substrate 10; a first semiconductor layer 31 provided on the substrate and having a first conductivity type; a second semiconductor layer 32 provided on the substrate and having a second conductivity type different from the first conductivity type; a third semiconductor layer 21 provided in contact with the first semiconductor layer and the second semiconductor layer and between the first semiconductor layer and the second semiconductor layer, and having a third conductivity type that is at least one among the first conductivity type and the second conductivity type; and a fourth semiconductor layer 22 provided in contact with the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer and between the first semiconductor layer and the second semiconductor layer, and having a fourth conductivity type different from the third conductivity type.

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] When forming a diode with a FinFET (Field Effect Transistor) or a nanosheet transistor, it is known to provide a semiconductor layer in a portion of the diode that corresponds to the gate electrode of the transistor. Also, a complementary field effect transistor (CFET) technology is known.

[0003] US Patent Application Publication No. 2023 / 0284427 US Patent No. 10,504,890 US Patent No. 1,532,607 US Patent No. 1,107,5273

[0004] H. Mertens et al., "Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) , 11-16 June 2023, Internet <URL: https: / / ieeexplore.ieee.org / document / 10185218> H. Horiguchi et al., "3D Stacked Devices and MOL Innovations for Post-Nanosheet CMOS Scaling"2023 International Electron Devices Meeting (IEDM), 09-13 December 2023, Internet <URL: https: / / ieeexplore.ieee.org / abstract / document / 10413701?casa_token=UL8DwJOcP LAAAAAA:MnWiX7kpB3_V0LUFvUSt5lfnm3tRcn2XYE829_oRu4HWdXBXEofP6Jbvdx8jTNI9tWQLomu74YhMTL0>

[0005] When forming a diode with a nanosheet transistor or CFET, no detailed consideration has been given to what structure a diode with a large junction area should have.

[0006] An object of the present disclosure is to provide a semiconductor device that can increase the junction area.

[0007] According to an embodiment of the present disclosure, a semiconductor device includes a substrate, a first semiconductor layer provided on the substrate and having a first conductivity type, a second semiconductor layer provided on the substrate and having a second conductivity type different from the first conductivity type, a third semiconductor layer provided between the first semiconductor layer and the second semiconductor layer in contact with the first semiconductor layer and the second semiconductor layer and having a third conductivity type which is either the first conductivity type or the second conductivity type, and a fourth semiconductor layer provided between the first semiconductor layer and the second semiconductor layer in contact with the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer and having a fourth conductivity type different from the third conductivity type.

[0008] According to the disclosed technology, the bonding area can be increased.

[0009] FIGS. 1A to 1C are cross-sectional views of a semiconductor device according to the first embodiment. FIGS. 2A to 2C are cross-sectional views showing a method for manufacturing a semiconductor device according to the first embodiment. FIGS. 3A to 3C are cross-sectional views showing a method for manufacturing a semiconductor device according to the first embodiment. FIGS. 4A and 4B are cross-sectional views showing a method for manufacturing a semiconductor device according to the first embodiment. FIGS. 5A and 5B are cross-sectional views showing a method for manufacturing a semiconductor device according to the first embodiment. FIG. 6 is a cross-sectional view of a semiconductor device according to a first modification of the first embodiment. FIGS. 7A to 7C are cross-sectional views of a semiconductor device according to a second modification of the first embodiment. FIGS. 8A and 8B are cross-sectional views showing a method for manufacturing a semiconductor device according to the first embodiment. FIG. 9 is a circuit diagram of a semiconductor device according to a second embodiment. FIGS. 10A and 10B are plan views of a semiconductor device according to the second embodiment. FIG. 11 is a cross-sectional view taken along line A-A of FIGS. 10A and 10B. 12 is a cross-sectional view taken along line B-B in FIGS. 10(a) and 10(b). FIG. 13 is a cross-sectional view taken along line C-C in FIGS. 10(a) and 10(b). FIG. 14 is a cross-sectional view of a semiconductor device according to a third embodiment. FIG. 15 is a cross-sectional view showing a manufacturing method of the third embodiment. FIG. 16 is a cross-sectional view showing a manufacturing method of the third embodiment. FIG. 17 is a cross-sectional view of a semiconductor device according to a first modified example of the third embodiment. FIG. 18 is a cross-sectional view of a semiconductor device according to a fourth embodiment. FIG. 19 is a cross-sectional view of a semiconductor device according to the fourth embodiment. FIG. 20 is a cross-sectional view of a semiconductor device according to the fourth embodiment. FIG. 21 is a cross-sectional view showing a manufacturing method of a semiconductor device according to the fourth embodiment. FIG. 22 is a cross-sectional view of a semiconductor device according to a fifth embodiment.

[0010] Hereinafter, embodiments for carrying out the present disclosure will be described in detail with reference to the drawings. The following embodiments are examples for embodying the technical ideas of the invention, and the present disclosure is not limited to the described configurations and numerical values. In each drawing, the same components are given the same reference numerals, and duplicate explanations may be omitted as appropriate. The size, positional relationship, etc. of each component shown in each drawing may be exaggerated to facilitate understanding of the invention.

[0011] 1(a) to 1(c) are cross-sectional views of a semiconductor device according to a first embodiment. FIG. 1(a) is a cross-sectional view taken along line A-A in FIGS. 1(b) and 1(c). FIGS. 1(b) and 1(c) are cross-sectional views taken along line B-B and C-C in FIG. 1(a), respectively. The thickness direction of the substrate 10 is defined as the Z direction, the direction in which the semiconductor layers 31 and 32 are arranged as the X direction, and the direction perpendicular to the X and Z directions as the Y direction. Note that the viewpoint of a plane defined by the X and Y directions, i.e., the viewpoint seen from the Z direction, is sometimes referred to as a planar view.

[0012] The semiconductor device 100 includes a substrate 10, a diode D1, a transistor T1, and an interlayer insulating film 50. An insulating film 12 and wirings 14 and 16 are formed on the substrate 10. The wirings 14 and 16 sandwich the diode D1 and the transistor T1 in the Y direction and extend in the X direction. The wirings 14 and 16 are connected to, for example, a first power supply VDD and a second power supply VSS, respectively.

[0013] The substrate 10 is a semiconductor substrate such as a single crystal silicon substrate. The insulating film 12 is an insulating film such as a silicon oxide film or a silicon nitride film. The wirings 14 and 16 are made of a metal material such as copper, ruthenium, molybdenum, cobalt, iridium, or tantalum.

[0014] The diode D1 includes semiconductor layers 31, 32, 21, and 22. The semiconductor layers 31 (first semiconductor layer) and 32 (second semiconductor layer) are provided on a substrate 10. The semiconductor layers 31 and 32 have a thickness in the Z direction.

[0015] The semiconductor layer 21 (third semiconductor layer) is provided between the semiconductor layers 31 and 32 in the X direction and in contact with the semiconductor layers 31 and 32. The semiconductor layer 22 (fourth semiconductor layer) is provided between the semiconductor layers 31 and 32 in the X direction and in contact with the semiconductor layers 31, 32, and 21. A plurality of the semiconductor layers 21 and 22 are provided, and are alternately stacked in the Z direction. In the Y direction, the semiconductor layer 22 covers the end face of the semiconductor layer 21.

[0016] The semiconductor layers 21, 31, and 32 are, for example, silicon layers. The semiconductor layer 22 is, for example, a silicon germanium (SiGe) layer. The semiconductor layers 31, 32, 21, and 22 are single crystal. The semiconductor layer 21 may be a silicon germanium layer, and the semiconductor layer 22 may be a silicon layer. The semiconductor layers 21, 22, 31, and 32 may be semiconductors other than silicon and silicon germanium. The semiconductor layers 31 and 21 are, for example, n-type semiconductor layers. The semiconductor layers 32 and 22 are, for example, p-type semiconductor layers. The semiconductor layers 31 and 21 form the cathode region of the diode D1, and the semiconductor layers 32 and 22 form the anode region of the diode D1. The bold dotted lines in FIGS. 1( a) and 1(c) indicate the junction 28 between the cathode region and the anode region.

[0017] If the conductivity types of the semiconductor layers 31, 32, 21, and 22 are the first conductivity type, the second conductivity type, the third conductivity type, and the fourth conductivity type, respectively, the second conductivity type is different from the first conductivity type. The third conductivity type is either the first conductivity type or the second conductivity type. The fourth conductivity type is different from the third conductivity type. In other words, the fourth conductivity type is the other of the first conductivity type and the second conductivity type. As a result, the semiconductor layers 31, 32, 21, and 22 function as a diode D1.

[0018] The transistor T1 includes semiconductor layers 36, 37, and 21, a gate electrode 41, and a gate insulating film 42. The semiconductor layers 36 (ninth semiconductor layer) and 37 (tenth semiconductor layer) are provided on the substrate 10. The semiconductor layers 36 and 32 have a thickness in the Z direction.

[0019] The semiconductor layer 21 (eleventh semiconductor layer) is provided between the semiconductor layers 36 and 37 in the X direction and in contact with the semiconductor layers 36 and 37. The gate insulating film 42 is provided between the semiconductor layers 36 and 37 in the X direction and in contact with the semiconductor layer 21. The gate electrode 41 is provided between the semiconductor layers 36 and 37 in the X direction so as to cover the periphery of the semiconductor layer 21 and the gate insulating film 42. In the Y direction, the gate electrode 41 covers the end face of the semiconductor layer 21 with the gate insulating film 42 sandwiched therebetween.

[0020] The semiconductor layers 36 and 37 are, for example, silicon layers. The semiconductor layer 21 is, for example, a silicon layer or a silicon germanium (SiGe) layer. The semiconductor layers 21, 36, and 37 may be semiconductors other than silicon and silicon germanium. The semiconductor layer 21 is an n-type semiconductor. The semiconductor layers 36 and 37 are p-type semiconductor layers. The gate insulating film 42 is, for example, an insulating film such as a silicon oxide film or a hafnium oxide film. The gate electrode 41 is a semiconductor layer such as polysilicon or a metal layer.

[0021] If the conductivity types of the semiconductor layers 36, 37, and 21 are the ninth, tenth, and eleventh conductivity types, respectively, the tenth conductivity type is the same as the ninth conductivity type. The eleventh conductivity type is different from the ninth and tenth conductivity types. As a result, the semiconductor layers 36 and 37 function as a source or a drain, and the transistor T1 functions as a MOS (Metal Oxide Semiconductor) FET. When the ninth and tenth conductivity types are p-type and the eleventh conductivity type is n-type, the transistor T1 is a PFET. When the ninth and tenth conductivity types are n-type and the eleventh conductivity type is p-type, the transistor T1 is an NFET.

[0022] The diode D1 and the transistor T1 are surrounded by an interlayer insulating film 50. The interlayer insulating film 50 is a silicon oxide film or an insulating film having a dielectric constant lower than that of silicon oxide.

[0023] (Manufacturing Method of First Embodiment) FIGS. 2(a) to 5(b) are cross-sectional views showing a manufacturing method of a semiconductor device according to the first embodiment. As shown in FIG. 2(a), a laminated film 20 is formed on a substrate 10. The laminated film 20 is formed by alternately stacking a plurality of semiconductor layers 21 and a plurality of semiconductor layers 23. The semiconductor layer 23 is a sacrificial layer, and has a different etching selectivity from the semiconductor layer 21. When the semiconductor layer 21 is a silicon layer, the semiconductor layer 23 is, for example, a silicon germanium layer. The laminated film 20 is formed using, for example, an epitaxial method.

[0024] Next, as shown in FIG. 2( b), a mask layer 60 is formed on the stacked film 20. The mask layer 60 is, for example, an insulating mask. Using the mask layer 60 as a mask, the stacked film 20 is removed. As a result, stacked films 20A and 20B are formed on the substrate 10. At this time, the upper part of the substrate 10 is also etched. The width of the stacked films 20A and 20B in the Y direction may be approximately the same as the width of the semiconductor layers 21 and 22 in FIGS. 1( b) and 1( c).

[0025] Next, as shown in FIG. 2C, the mask layer 60 is removed. An insulating film 12 is formed on the substrate 10. The insulating film 12 is, for example, an STI (Shallow Trench Isolation) film. Before forming the insulating film 12, the wirings 14 and 16 shown in FIGS. 1B and 1C may be formed.

[0026] 3A, a mask layer 62 is formed on the laminated films 20A and 20B. The mask layer 62 is, for example, an insulating mask. The mask layer 62 may be used without removing the mask layer 60. Using the mask layer 62 as a mask, semiconductor layers 31 and 32 are formed on the side surfaces of the laminated film 20A, and semiconductor layers 36 and 37 are formed on the side surfaces of the laminated film 20B.

[0027] 3B, an interlayer insulating film 50 is formed on the substrate 10 to cover the stacked films 20A and 20B, the semiconductor layers 31, 32, 36, and 37, and the mask layer 62. The upper surface of the interlayer insulating film 50 is planarized. The upper surface of the mask layer 62 is exposed. The mask layer 62 is removed using an etching method to form openings 51a and 51b in the interlayer insulating film 50, which expose the upper surfaces of the stacked films 20A and 20B, respectively. The widths of the openings 51a and 51b in the Y direction are set larger than the widths of the stacked films 20A and 20B in the Y direction.

[0028] Next, as shown in FIG. 3C, the semiconductor layer 23 is removed through the openings 51a and 51b. For example, if the semiconductor layers 31, 32, 36, 37, and 21 are silicon layers and the semiconductor layer 23 is a silicon germanium layer, the semiconductor layer 23 is removed using an etchant that selectively etches silicon germanium with respect to silicon. For example, if the semiconductor layers 31, 32, 36, 37, and 21 are silicon germanium layers and the semiconductor layer 23 is a silicon layer, the semiconductor layer 23 is removed using an etchant that selectively etches silicon with respect to silicon germanium. As a result, a gap 52a is formed between the semiconductor layers 21 in the openings 51a. A gap 52b is formed between the semiconductor layers 21 in the openings 51b. The semiconductor layer 21 is exposed to the gaps 52a and 52b.

[0029] Because the width of the openings 51a and 51b in the Y direction is wider than the width in the Y direction, the etchant can remove the semiconductor layer 23 in the −Z direction through the openings 51a and 51b provided on both sides of the stacked films 20A and 20B in the Y direction, thereby exposing the end faces of the semiconductor layer 21 in the Y direction to the voids 52a and 52b.

[0030] 4A, a mask layer 64 is formed to cover the interlayer insulating film 50. The mask layer 64 covers the opening 51a and exposes the opening 51b. Using the mask layer 64 as a mask, the gate insulating film 42 is formed in the opening 51b. As a result, the gate insulating film 42 is formed on the surfaces of the semiconductor layers 36, 37, and 21. Note that an insulating film may be formed between the semiconductor layers 36 and 37 and the gate insulating film 42. A gap 52b remains in the gate insulating film 42.

[0031] Next, as shown in FIG. 4B, the gate electrode 41 is formed in the void 52b. As a result, the void 52b is filled with the gate electrode 41. The gate electrode 41, the gate insulating film 42, the mask layer 64, and the interlayer insulating film 50 are planarized so that the semiconductor layers 31, 32, 36, and 37 are exposed. In FIG. 3C, the voids 52b are provided on both sides of the semiconductor layer 21 in the Y direction, so that the end faces of the semiconductor layer 21 in the Y direction face the gate electrode 41 with the gate insulating film 42 sandwiched therebetween, as in FIG. 1B.

[0032] 5A, the mask layer 64 between the semiconductor layers 31 and 32 is removed, thereby exposing the surfaces of the semiconductor layer 21 in the ±Z directions and the end faces in the Y direction to the gap 52a.

[0033] Next, as shown in FIG. 5B, a mask layer 66 is formed to cover the interlayer insulating film 50. The mask layer 66 covers the gate electrode 41 and exposes the voids 52a. Using the mask layer 66 as a mask, a semiconductor layer 22 is selectively formed in the opening 51a. The semiconductor layer 22 is formed by epitaxial growth. As a result, the voids 52a are filled in the semiconductor layer 22. The ±Z direction surfaces of the semiconductor layer 21 contact the semiconductor layer 22. Furthermore, as shown in FIG. 3C, since the voids 52a are provided on both sides of the semiconductor layer 21 in the Y direction, the end faces of the semiconductor layer 21 in the Y direction contact the semiconductor layer 22 as shown in FIG. 1C.

[0034] Next, the mask layer 66 is removed, thereby completing the manufacturing of the semiconductor device 100 shown in FIGS.

[0035] According to the first embodiment, the semiconductor layer 31 (first semiconductor layer) is of a first conductivity type, and the semiconductor layer 32 (second semiconductor layer) is of a second conductivity type different from the first conductivity type. The semiconductor layer 21 (third semiconductor layer) is of a third conductivity type, which is one of the first conductivity type and the second conductivity type, and the semiconductor layer 22 (fourth semiconductor layer) is of a fourth conductivity type different from the third conductivity type. This makes it possible to increase the area of ​​the junction surface 28 between the cathode region and the anode region, as shown in FIGS. 1A and 1C.

[0036] A plurality of semiconductor layers 21 and a plurality of semiconductor layers 22 are provided, and the plurality of semiconductor layers 21 and the plurality of semiconductor layers 22 are alternately stacked, thereby making it possible to increase the area of ​​the bonding surface 28.

[0037] 1C, the semiconductor layer 22 covers the end face of the semiconductor layer 21 in the Y direction (second direction), which is different from the X direction (first direction) in which the semiconductor layers 31 and 32 are arranged. This allows the area of ​​the junction surface 28 to be larger.

[0038] The semiconductor layer 21 of the transistor T1 and the semiconductor layer 21 of the diode D1 are formed simultaneously as shown in Fig. 2(a), which allows the transistor T1 and the diode D1 to be formed relatively easily on the same substrate 10, as shown in Figs.

[0039] (First Modification of First Embodiment) FIG. 6 is a cross-sectional view of a semiconductor device according to a first modification of the first embodiment. As shown in FIG. 6, in a semiconductor device 102 according to the first modification of the first embodiment, an insulating film 12 is provided between a substrate 10 and a semiconductor layer 22. For example, in FIG. 2A, an insulating film is selectively formed on the substrate 10 before forming the bottom semiconductor layer 23. Alternatively, an SOI (Silicon on Insulator) substrate is used as the substrate 10. This allows the insulating film 12 to be provided between the substrate 10 and the semiconductor layer 22. This allows the substrate 10 to be electrically isolated from the diode D1. The other configurations are the same as those of the first embodiment, and therefore description thereof will be omitted.

[0040] 7(a) to 7(c) are cross-sectional views of a semiconductor device according to a second modification of the first embodiment. Fig. 7(a) is a cross-sectional view taken along line A-A in Fig. 7(b) and Fig. 7(c). Fig. 7(b) and Fig. 7(c) are cross-sectional views taken along line B-B and C-C in Fig. 7(a), respectively.

[0041] In a semiconductor device 104 according to the second modification of the first embodiment, a semiconductor layer 23 is provided in the diode D1 instead of the semiconductor layer 22. In the Y direction, the end faces of the semiconductor layers 21 and 23 contact the interlayer insulating film 50. The other configurations are the same as those of the first embodiment, and therefore description thereof will be omitted.

[0042] (Manufacturing method of second modified example of first embodiment) FIGS. 8(a) and 8(b) are cross-sectional views showing a manufacturing method of a semiconductor device according to the first embodiment. The steps of FIGS. 2(a) to 3(b) of the first embodiment are carried out. At this time, the semiconductor layer 23 has a different conductivity type from the semiconductor layer 21. As shown in FIG. 8(a), an opening 51b is formed in the interlayer insulating film 50, and no opening 51a is formed. The width of the opening 51b in the Y direction is greater than the width of the stacked film 20B in the Y direction. The rest is the same as FIG. 3(c).

[0043] As shown in FIG. 8B, the semiconductor layer 23 is removed through the opening 51b. The semiconductor layer 23 in the -Z direction can also be removed through the openings 51b located on both sides of the stacked film 20B in the Y direction. The rest is the same as FIG. 4A. Thereafter, the processes of FIG. 4B and FIG. 5A are performed. The semiconductor layer 22 in FIG. 5B is not formed. Because the semiconductor layer 22 is not formed, both sides of the semiconductor layer 21 in the Y direction are covered with the interlayer insulating film 50 as shown in FIG. 7C. In this way, the semiconductor device 104 according to the second modification of the first embodiment is manufactured.

[0044] As in the second modification of the first embodiment, the sacrificial layer of the transistor T1 may be used as the semiconductor layer 23 (fourth semiconductor layer) of the diode D1. Therefore, the interlayer insulating film 50 covers the end faces of the semiconductor layers 21 and 23 in the Y direction. The width of the semiconductor layer 21 in the Y direction is the same as the width of the semiconductor layer 23 in the Y direction.

[0045] Second Embodiment The second embodiment is an example in which a diode is provided in a sequential CFET. FIG. 9 is a circuit diagram of a semiconductor device according to the second embodiment. The circuit shown in FIG. 9 is a simple circuit example for facilitating the explanation of the second embodiment, and the second embodiment is not limited to the circuit of FIG.

[0046] 9, the semiconductor device 106 includes an inverter INV and diodes D1 and D2. The inverter INV includes transistors T1 and T2. The transistors T1 and T2 are PMOSFET and NMOSFET, respectively. The source, gate, and drain of the transistor T1 are electrically connected to a first power supply VDD, an input terminal IN, and an output terminal OUT, respectively. The source, gate, and drain of the transistor T2 are electrically connected to a second power supply VSS, an input terminal IN, and an output terminal OUT, respectively. The voltage of the first power supply VDD is higher than the voltage of the second power supply VSS.

[0047] Diode D1 is connected to the first power supply VSS and a node N1 electrically connected to the input terminal IN. Diode D2 is connected to the node N1 and the second power supply VDD. The forward direction of diode D1 is from the second power supply VSS to node N1. The forward direction of diode D2 is from node N1 to the first power supply VDD. Diodes D1 and D2 are, for example, electrostatic protection circuits.

[0048] 10(a) and 10(b) are plan views of the semiconductor device according to the second embodiment. FIG. 10(a) is a plan view of the second layer 72. FIG. 10(b) is a plan view of the first layer 70. FIG. 11 is a cross-sectional view taken along line A-A in FIGS. 10(a) and 10(b). FIG. 12 is a cross-sectional view taken along line B-B in FIGS. 10(a) and 10(b). FIG. 13 is a cross-sectional view taken along line C-C in FIGS. 10(a) and 10(b).

[0049] The semiconductor device 106 according to the second embodiment includes a first layer 70, a second layer 72, and a wiring layer 74. The first layer 70 includes a substrate 10, insulating films 12 and 13, wirings 14 and 16, a diode D1, a transistor T1, and an interlayer insulating film 50. The wiring 14 is supplied with a first power supply VDD, and the wiring 16 is supplied with a second power supply VSS. The wirings 14 and 16 may be provided on the back surface (the surface facing the -Z direction) of the substrate 10. The interlayer insulating film 50 surrounds the diode D1 and the transistor T1. The insulating film 13 is provided on the diode D1 and the transistor T1. The remaining configurations of the substrate 10, the insulating film 12, the wirings 14 and 16, the diode D1, and the transistor T1 are the same as those of the first embodiment and its modified example, and therefore will not be described again.

[0050] The second layer 72 includes an insulating film 12A, a substrate 10A, a diode D2, a transistor T2, and an interlayer insulating film 53. The substrate 10A is provided on the insulating film 13. The insulating film 12A is provided on the substrate 10A. The interlayer insulating film 53 surrounds the diode D2 and the transistor T2. The diode D2 includes semiconductor layers 33, 34, 26, and 27. The semiconductor layers 33 (fifth semiconductor layer) and 34 (sixth semiconductor layer) are provided on the substrate 10A above the semiconductor layers 31 and 32, respectively. The semiconductor layers 33 and 34 have a thickness in the Z direction.

[0051] The semiconductor layer 26 (seventh semiconductor layer) is provided between the semiconductor layers 33 and 34 in the X direction and in contact with the semiconductor layers 33 and 34. The semiconductor layer 27 (eighth semiconductor layer) is provided between the semiconductor layers 33 and 34 in the X direction and in contact with the semiconductor layers 33, 34, and 26. A plurality of semiconductor layers 26 and 27 are provided, and are alternately stacked in the Z direction. In the Y direction, the semiconductor layer 27 covers the end face of the semiconductor layer 26.

[0052] The transistor T2 includes semiconductor layers 38, 39, and 26, a gate electrode 43, and a gate insulating film 44. The semiconductor layers 38 and 39 are provided on the substrate 10A above the semiconductor layers 36 and 37, respectively. The semiconductor layers 38 and 39 have a thickness in the Z direction.

[0053] The semiconductor layer 26 is provided between the semiconductor layers 38 and 39 in the X direction and in contact with the semiconductor layers 38 and 39. The gate insulating film 44 is provided between the semiconductor layers 38 and 39 in the X direction and in contact with the semiconductor layer 26. The gate electrode 43 is provided between the semiconductor layers 38 and 39 in the X direction so as to cover the periphery of the semiconductor layer 26 and the gate insulating film 44. In the Y direction, the gate electrode 43 covers the end face of the semiconductor layer 26 with the gate insulating film 44 sandwiched therebetween.

[0054] The wiring layer 74 is provided on the second layer 72 and includes an interlayer insulating film 54, wirings 56a, 56b, 58a, and vias 55a to 55c, 57a, and 57b. The interlayer insulating film 54 covers the wirings 56a, 56b, 58a, and vias 55a to 55c, 57a, and 57b.

[0055] In the diode D1, the semiconductor layers 31 and 21 are n-type, and the semiconductor layers 32 and 22 are p-type. As a result, the semiconductor layers 31 and 21 are the cathode region, and the semiconductor layers 32 and 22 are the anode region. In the transistor T1, the semiconductor layers 36 and 37 are p-type, and the semiconductor layer 21 is n-type. As a result, the transistor T1 functions as a PMOSFET. The semiconductor layer 36 is the source region, and the semiconductor layer 37 is the drain region.

[0056] In diode D2, semiconductor layers 33 and 26 are p-type, and semiconductor layers 34 and 27 are n-type. As a result, semiconductor layers 33 and 26 are the anode region, and semiconductor layers 34 and 27 are the cathode region. In transistor T2, semiconductor layers 38 and 39 are n-type, and semiconductor layer 26 is p-type. As a result, transistor T2 functions as an NMOSFET. Semiconductor layer 38 is the source region, and semiconductor layer 39 is the drain region.

[0057] 10A, the wirings 46a to 46d are wirings connected to the semiconductor layers 38, 39, 33, and 34, respectively, in the second layer 72. In FIG. 10B, the wirings 45a to 45d are wirings connected to the semiconductor layers 36, 37, 31, and 32, respectively, in the first layer 70.

[0058] 10(a) and 10(b), via 47a electrically connects wiring 45a to wiring 14. Via 47b electrically connects wiring 46a to wiring 16. Via 47c electrically connects wiring 46d to wiring 14. Via 47d electrically connects wiring 45d to wiring 16. Via 48b electrically connects wiring 45b to wiring 46b. Via 48c electrically connects wiring 45c to wiring 46c.

[0059] The via 55a electrically connects the gate electrode 43 to the wiring 56a. The via 55b electrically connects the semiconductor layer 33 to the wiring 56a. The via 55c electrically connects the gate electrode 41 to the wiring 56b. With reference to Fig. 12, the via 57a electrically connects the wirings 56a and 58a. The via 57b electrically connects the wirings 56b and 58a.

[0060] The semiconductor layer 38 (source) of the transistor T2 (NMOSFET) is electrically connected to the wiring 16 (VSS) through the wiring 46a and the via 47b. The semiconductor layer 36 (source) of the transistor T1 (PMOSFET) is electrically connected to the wiring 14 (VDD) through the wiring 45a and the via 47a. The semiconductor layer 39 (drain) of the transistor T2 and the semiconductor layer 37 (drain) of the transistor T1 are electrically connected through the wirings 45b, 46b and the via 48b. The via 48b is electrically connected to the output terminal OUT.

[0061] The gate electrode 43 of the transistor T2 is electrically connected to the wiring 58a through the via 55a, the wiring 56a, and the via 57a. The gate electrode 41 of the transistor T1 is electrically connected to the wiring 58a through the via 55c, the wiring 56b, and the via 57b. The wiring 58b is electrically connected to the input terminal IN.

[0062] The semiconductor layer 32 (anode) of the diode D1 is electrically connected to the wiring 16 (VSS) via the wiring 45d and the via 47d. The semiconductor layer 34 (cathode) of the diode D2 is electrically connected to the wiring 14 (VDD) via the wiring 46d and the via 47c. The semiconductor layer 31 (cathode) of the diode D1 is electrically connected to the semiconductor layer 33 (anode) of the diode D1 via the wiring 45c, the via 48c, and the wiring 46c. The semiconductor layer 33 (anode) of the diode D1 is electrically connected to the wiring 58a (IN) via the via 55b, the wiring 56b, and the via 57a.

[0063] A method for manufacturing the semiconductor device 106 will now be described. As in the first embodiment, a diode D1 and a transistor T1 are formed on a substrate 10. An insulating film 13 is formed on the diode D1 and the transistor T1. As in the first embodiment, a diode D2 and a transistor T2 are formed on a substrate 10A. Then, the substrate 10A is attached onto the insulating film 13. Then, a wiring layer 74 is formed. In this manner, the semiconductor device 106 is manufactured.

[0064] In the semiconductor device 106, a p-type semiconductor layer 33 is provided above an n-type semiconductor layer 31, and an n-type semiconductor layer 34 is provided above a p-type semiconductor layer 32. A semiconductor layer 33 of the same conductivity type as the semiconductor layer 31 may be provided above the semiconductor layer 31, and a semiconductor layer 34 of the same conductivity type as the semiconductor layer 32 may be provided above the semiconductor layer 32.

[0065] That is, the fifth conductivity type of semiconductor layer 36 (fifth semiconductor layer) may be either the first conductivity type of semiconductor layer 31 or the second conductivity type of semiconductor layer 32. The sixth conductivity type of semiconductor layer 37 (sixth semiconductor layer) may be different from the fifth conductivity type. The seventh conductivity type of semiconductor layer 26 (seventh semiconductor layer) may be either the fifth conductivity type or the sixth conductivity type. The eighth conductivity type of semiconductor layer 27 (eighth semiconductor layer) may be different from the seventh conductivity type.

[0066] Although the example in which the transistor T1 is a PMOSFET and the transistor T2 is an NMOSFET has been described, the transistor T1 may be an NMOSFET and the transistor T2 may be a PMOSFET. The transistors T1 and T2 may be either NMOSFETs or PMOSFETs.

[0067] Although an example in which there are two layers (first layer 70 and second layer 72) in which diodes and transistors are formed has been described, there may be three or more layers.

[0068] Third Embodiment The third embodiment is an example in which a diode or a thyristor is provided in a monolithic CFET. FIG. 14 is a cross-sectional view of a semiconductor device according to the third embodiment. As shown in FIG. 14 , in a semiconductor device 108 according to the third embodiment, the uppermost layer of the semiconductor layer 22 in the first layer 70 is in contact with the lowermost layer of the semiconductor layer 27 in the second layer 72. The uppermost layer of the gate electrode 41 in the first layer 70 is in contact with the lowermost layer of the gate electrode 43 in the second layer 72. The interlayer insulating films 50 of the first layer 70 and the second layer 72 are provided continuously as a single unit.

[0069] In diode D1, semiconductor layers 31 and 21 are n-type, and semiconductor layers 32 and 22 are p-type, with p-n junction interface 28a between semiconductor layers 32 and 22 and semiconductor layers 31 and 21. In diode D2, semiconductor layers 33 and 26 are p-type, and semiconductor layers 34 and 27 are n-type, with p-n junction interface 28c between semiconductor layers 33 and 26 and semiconductor layers 34 and 27. Of semiconductor layers 21 and 22, semiconductor layer 22, which is the topmost, and semiconductor layer 27, which is the bottommost, have different conductivity types and are in contact with each other. As a result, p-n junction interface 28b is formed between semiconductor layers 22 and 27. In this way, diodes D1 and D2 function as thyristors having an n-type region, a p-type region, an n-type region, and a p-type region.

[0070] 15 and 16 are cross-sectional views showing a manufacturing method of the third embodiment. As shown in Fig. 15, laminated films 20 and 25 are formed in this order on a substrate 10. The laminated film 20 is formed by alternately stacking a plurality of semiconductor layers 21 and a plurality of semiconductor layers 22. The laminated film 25 is formed by alternately stacking a plurality of semiconductor layers 27 and a plurality of semiconductor layers 26.

[0071] Next, as shown in FIG. 16 , a mask layer 60 is formed on the laminated film 25. The mask layer 60 is, for example, an insulating mask. Using the mask layer 60 as a mask, the laminated films 20 and 25 are removed. As a result, a structure in which laminated films 20A and 25A are stacked and a structure in which laminated films 20B and 25B are stacked are formed on the substrate 10. Thereafter, as in the first embodiment, a first layer 70 having a diode D1 and a transistor T1 is formed. Furthermore, a second layer 72 having a diode D2 and a transistor T2 is formed. In this way, the semiconductor device 108 according to the third embodiment can be manufactured.

[0072] (First Modification of Third Embodiment) FIG. 17 is a cross-sectional view of a semiconductor device according to a first modification of the third embodiment. As shown in FIG. 17 , in a semiconductor device 110 according to the first modification of the third embodiment, the bottommost semiconductor layer 27a of the semiconductor layers 26 and 27 in the diode D2 and the topmost semiconductor layer 22a of the semiconductor layers 21 and 22 in the diode D1 have the same conductivity type and are in contact with each other. The semiconductor layers 22a and 27a may be formed continuously under the same film formation conditions. This prevents a pn junction from being formed between the diodes D1 and D2. The diodes D1 and D2 are connected in series. The other configurations are the same as those of the third embodiment, and therefore a description thereof will be omitted.

[0073] Fourth Embodiment The fourth embodiment is an example in which an insulating film 45 (MDI: Middle Dielectric Isolation) is provided between diodes D1 and D2. Figures 18 to 20 are cross-sectional views of a semiconductor device in the fourth embodiment. Figure 18 is a cross-sectional view taken along line A-A in Figures 19 and 20. Figures 19 and 20 are cross-sectional views taken along line B-B and C-C in Figure 18, respectively.

[0074] 18 and 19 , in the semiconductor device 112 according to the fourth embodiment, an insulating film 45 is provided in the interlayer insulating film 50 between the diodes D1 and D2. The insulating film 45 is provided between the uppermost semiconductor layer 22 of the semiconductor layers 21 and 22 of the diode D1 and the lowermost semiconductor layer 27 of the semiconductor layers 26 and 27 of the diode D2. This allows the insulating film 45 to electrically isolate the diodes D1 and D2.

[0075] 19 and 20 , an insulating film 45 is provided between the gate electrode 41 of transistor T1 and the gate electrode 43 of transistor T2. In the Z direction, the insulating film 45 does not completely separate the gate electrodes 41 and 43. This electrically connects the gate electrode 41 of transistor T1 and the gate electrode 43 of transistor T2. The other configurations are the same as those of the third embodiment, and therefore description thereof will be omitted.

[0076] FIG. 21 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the fourth embodiment. After the process shown in FIG. 16 of the third embodiment, the side surfaces of the semiconductor layers 22 and 27 are selectively etched relative to the semiconductor layers 21 and 26. This results in the formation of convex portions 68 on the side surfaces of the semiconductor layers 21 and 26. A mask layer is then formed on the side surfaces of the stacked films 20A, 20B, 25A, and 25B. When the mask layer is etched, the mask layer remains where the convex portions 68 on the side surfaces are narrow. The mask layer does not remain in regions 69 between the stacked films 20A and 25A and between the stacked films 20B and 25B, where the convex portions 68 are widely spaced. The semiconductor layers 22 and 27 in region 69 are etched using the mask layer and the semiconductor layers 21 and 26 as masks. An insulating film 45 is then formed in region 69. As in the third embodiment, a first layer 70 having a diode D1 and a transistor T1 is then formed. A second layer 72 having a diode D2 and a transistor T2 is then formed. In this way, the semiconductor device 112 according to the fourth embodiment can be manufactured.

[0077] Fifth Embodiment The fifth embodiment is an example in which the diodes D1 and D2 are expanded in the X direction. FIG. 22 is a cross-sectional view of a semiconductor device according to the fifth embodiment. As shown in FIG. 22 , in a semiconductor device 114 according to the fifth embodiment, the diode D1 includes semiconductor layers 32A, 21A, and 22A in addition to the semiconductor layers 31, 32, 21, and 22. The semiconductor layer 32A (another second semiconductor layer) sandwiches the semiconductor layer 31 between the semiconductor layers 31 and 32A. The semiconductor layer 21A (another third semiconductor layer) is provided between the semiconductor layers 31 and 32A in contact with the semiconductor layers 31 and 32A and has the same conductivity type as the semiconductor layer 21. The semiconductor layer 22A (second semiconductor layer) is provided between the semiconductor layers 31 and 32A in contact with the semiconductor layers 31, 32A, and 21A and has the same conductivity type as the semiconductor layer 22. This allows the diode D1 to be expanded in the X direction.

[0078] Diode D2 includes semiconductor layers 34A, 26A, and 27A in addition to semiconductor layers 33, 34, 26, and 27. Semiconductor layer 34A sandwiches semiconductor layer 33 with semiconductor layer 34. Semiconductor layer 26A is provided between semiconductor layers 33 and 34A in contact with semiconductor layers 33 and 34A, and has the same conductivity type as semiconductor layer 26. Semiconductor layer 27A is provided between semiconductor layers 33 and 34A in contact with semiconductor layers 33, 34A, and 26A, and has the same conductivity type as semiconductor layer 27. This allows diode D2 to be expanded in the X direction.

[0079] A plurality of semiconductor layers 31 and a plurality of semiconductor layers 32 are alternately provided in the X direction, and a stacked film of semiconductor layers 21 and 22 is provided between semiconductor layers 31 and 32. This increases the junction area of ​​diode D1. In the first embodiment and its modifications, semiconductor layers 32A, 21A, and 22A may be provided. In the second, third, and fourth embodiments and their modifications, semiconductor layers 32A, 21A, 22A, 34A, 26A, and 27A may be provided.

[0080] Although the present disclosure has been described above based on the embodiments, the present invention is not limited to the requirements set forth in the above embodiments. These requirements can be changed without departing from the spirit of the present disclosure, and can be appropriately determined depending on the application form.

[0081] 10, 10A Substrate 12, 12A, 13, 45 Insulating film 14, 16, 45a, 45b, 45c, 45d, 46a, 46b, 46c, 46d, 56a, 56, 58a, 58b Wiring 20, 20A, 20B, 25, 25A, 25B Stacked film 21, 21A, 22, 22A, 23, 26, 26A, 27, 27A, 31, 32, 32A, 33, 34, 34A, 36, 37, 38, 39 Semiconductor layer 41, 43 Gate electrode 42, 44 Gate insulating film 47a, 47b, 47c, 47d, 48b, 48c, 55a, 55b, 55c, 57a, 57b 50, 53, 54 Interlayer insulating film

Claims

1. A semiconductor device comprising: a substrate; a first semiconductor layer provided on the substrate and having a first conductivity type; a second semiconductor layer provided on the substrate and having a second conductivity type different from the first conductivity type; a third semiconductor layer provided between the first semiconductor layer and the second semiconductor layer and in contact with the first semiconductor layer and the second semiconductor layer, and having a third conductivity type which is either the first conductivity type or the second conductivity type; and a fourth semiconductor layer provided between the first semiconductor layer and the second semiconductor layer and in contact with the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer, and having a fourth conductivity type different from the third conductivity type.

2. The semiconductor device according to claim 1, wherein a plurality of the third semiconductor layers and a plurality of the fourth semiconductor layers are provided, and the plurality of third semiconductor layers and the plurality of fourth semiconductor layers are provided in an alternating stack.

3. The semiconductor device according to claim 1 or 2, wherein the first semiconductor layer and the second semiconductor layer are arranged in a first direction, and the fourth semiconductor layer covers an end face of the third semiconductor layer in a second direction different from the first direction.

4. The semiconductor device according to claim 1 or 2, wherein the first semiconductor layer and the second semiconductor layer are arranged in a first direction, and the semiconductor device comprises an insulating film covering end faces of the third semiconductor layer and the fourth semiconductor layer in a second direction different from the first direction.

5. The semiconductor device according to claim 1 or 2, comprising: a second semiconductor layer provided on the substrate and having a second conductivity type; a third semiconductor layer provided between the first semiconductor layer and the second semiconductor layer and in contact with the first semiconductor layer and the second semiconductor layer and having the third conductivity type; and a fourth semiconductor layer provided between the first semiconductor layer and the second semiconductor layer and in contact with the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer and having the fourth conductivity type.

6. The semiconductor device according to claim 1 or 2, comprising: a fifth semiconductor layer provided above the first semiconductor layer, the fifth semiconductor layer having a fifth conductivity type which is either the first conductivity type or the second conductivity type; a sixth semiconductor layer provided above the second semiconductor layer, the sixth semiconductor layer having a sixth conductivity type different from the fifth conductivity type; a seventh semiconductor layer provided between the fifth semiconductor layer and the sixth semiconductor layer in contact with the fifth semiconductor layer and the sixth semiconductor layer, the seventh semiconductor layer having a seventh conductivity type which is either the fifth conductivity type or the sixth conductivity type; and an eighth semiconductor layer provided between the fifth semiconductor layer and the sixth semiconductor layer in contact with the fifth semiconductor layer, the sixth semiconductor layer, and the seventh semiconductor layer, the eighth semiconductor layer having an eighth conductivity type different from the seventh conductivity type.

7. The semiconductor device according to claim 6, wherein the uppermost semiconductor layer of the third semiconductor layer and the fourth semiconductor layer and the lowermost semiconductor layer of the seventh semiconductor layer and the eighth semiconductor layer have the same conductivity type and are in contact with each other.

8. The semiconductor device according to claim 6, wherein the uppermost semiconductor layer of the third and fourth semiconductor layers and the lowermost semiconductor layer of the seventh and eighth semiconductor layers have different conductivity types and are in contact with each other.

9. The semiconductor device according to claim 8, comprising a thyristor having the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, the fourth semiconductor layer, the fifth semiconductor layer, the sixth semiconductor layer, the seventh semiconductor layer, and the eighth semiconductor layer.

10. The semiconductor device according to claim 6, further comprising an insulating film provided between the uppermost semiconductor layer of the third semiconductor layer and the fourth semiconductor layer and the lowermost semiconductor layer of the seventh semiconductor layer and the eighth semiconductor layer.

11. The semiconductor device according to claim 6, wherein the first semiconductor layer and the second semiconductor layer are arranged in a first direction, the fifth semiconductor layer and the sixth semiconductor layer are arranged in the first direction, and the semiconductor device comprises an insulating film covering end faces of the third semiconductor layer, the fourth semiconductor layer, the seventh semiconductor layer, and the eighth semiconductor layer in a second direction different from the first direction.

12. The semiconductor device according to claim 1 or 2, comprising: a ninth semiconductor layer provided on the substrate and having a ninth conductivity type, which is either the first conductivity type or the second conductivity type; a tenth semiconductor layer provided on the substrate and having a tenth conductivity type that is the same as the ninth conductivity type; an eleventh semiconductor layer provided between the ninth semiconductor layer and the tenth semiconductor layer and in contact with the ninth semiconductor layer and the tenth semiconductor layer, and having an eleventh conductivity type that is different from the ninth conductivity type; a gate insulating film provided between the ninth semiconductor layer and the tenth semiconductor layer and in contact with the eleventh semiconductor layer; and a gate electrode provided between the ninth semiconductor layer and the tenth semiconductor layer so as to cover the periphery of the eleventh semiconductor layer and the gate insulating film.

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