Semiconductor integrated circuit device

Abstract

The present invention provides a layout structure of a capacitive cell that uses a CFET which includes a forksheet FET. The capacitive cell comprises: an FET (P1) that includes a nanosheet (21a) which extends in the X direction; an FET (N1) that is positioned above the FET (P1) in the depth direction and includes a nanosheet (23a) which extends in the X direction and which overlaps the nanosheet (21a) in a plan view; and gate wiring (51a) that surrounds the area around the nanosheets (21a, 23a) in the Y direction and in the depth direction. The nanosheets (21a, 23a) each have a surface that is on one side in the Y direction and that is exposed from the gate wiring (51a). Parts (22a, 22b) that serve respectively as a source and a drain of the FET (P1) are connected to power supply wiring (11) for supplying VDD, and the gate wiring (51a) is supplied with VSS.

Description

semiconductor integrated circuit device

[0001] The present disclosure relates to a semiconductor integrated circuit device having standard cells including CFETs (Complementary Field Effect Transistors).

[0002] The standard cell method is known as a method for forming a semiconductor integrated circuit on a semiconductor substrate. In this method, basic units (e.g., inverters, latches, flip-flops, full adders, etc.) having specific logic functions are prepared in advance as standard cells, and multiple standard cells are arranged on the semiconductor substrate and connected with wiring to design an LSI chip.

[0003] Furthermore, transistors, which are the basic components of LSIs, have achieved increased integration density, reduced operating voltages, and improved operating speeds through the reduction of gate length (scaling). However, in recent years, excessive scaling has led to problems with off-state current and the resulting significant increase in power consumption. To solve this problem, three-dimensional transistors, which change the transistor structure from the conventional planar type to a three-dimensional type, have been actively researched.

[0004] Patent Document 1 discloses a capacitance cell using a CFET.

[0005] Patent Document 2 discloses the structure of a capacitance cell that uses a fork sheet FET, which is a nanosheet FET having a fork-shaped gate electrode, in order to reduce the area of ​​a semiconductor integrated circuit device.

[0006] International Publication No. 2020 / 110733 International Publication No. 2021 / 171969

[0007] An object of the present disclosure is to provide a layout structure of a capacitance cell when a fork-sheet FET is used as a transistor in a standard cell using a CFET in order to further reduce the area.

[0008] A semiconductor integrated circuit device according to a first aspect of the present disclosure includes a first standard cell that is a capacitance cell, and the first standard cell includes a first nanosheet FET (Field Effect Transistor) of a first conductivity type, the first nanosheet FET including a first nanosheet extending in a first direction. a second nanosheet FET of a second conductivity type formed above the first nanosheet FET in the depth direction and including a second nanosheet extending in the first direction and overlapping the first nanosheet in a planar view; a first gate wiring extending in a second direction perpendicular to the first direction, overlapping the first and second nanosheets in a planar view, and surrounding the first and second nanosheets in the second direction and the depth direction; a first power supply wiring extending in the first direction and supplying a first power supply voltage; and a second power supply wiring extending in the first direction and supplying a second power supply voltage, wherein the first and second nanosheets have first side surfaces, which are one side in the second direction, exposed from the first gate wiring, and the source and drain of the first nanosheet FET are connected to the first power supply wiring, and the first gate wiring is supplied with the second power supply voltage.

[0009] According to this aspect, the capacitor cell includes a first nanosheet FET of a first conductivity type, including a first nanosheet extending in a first direction; a second nanosheet FET of a second conductivity type, formed above the first nanosheet FET in the depth direction and including a second nanosheet extending in the first direction and overlapping the first nanosheet in a planar view; and a first gate wiring extending in a second direction perpendicular to the first direction and surrounding the first and second nanosheets in the second direction and the depth direction. The first and second nanosheets have their first side surfaces, which are one side in the second direction, exposed from the first gate wiring. In other words, the first and second nanosheet FETs are fork-sheet FETs. The source and drain of the first nanosheet FET are connected to a first power supply wiring, and a second power supply voltage is supplied to the first gate wiring. This forms a capacitance between the gate and the source and drain of the first nanosheet FET via a gate oxide film. Furthermore, by using a fork-sheet FET, the active area constituting the transistor can be formed larger in the second direction, thereby increasing the capacitance value.

[0010] A semiconductor integrated circuit device according to a second aspect of the present disclosure includes a first standard cell that is a capacitance cell, and the first standard cell includes a first nanosheet field effect transistor (FET) of a first conductivity type that includes a first nanosheet extending in a first direction. a second nanosheet FET of a second conductivity type formed above the first nanosheet FET in the depth direction and including a second nanosheet extending in the first direction and overlapping the first nanosheet in a planar view; a first gate wiring extending in a second direction perpendicular to the first direction, overlapping the first and second nanosheets in a planar view, and surrounding the first and second nanosheets in the second direction and the depth direction; a first power supply wiring extending in the first direction and supplying a first power supply voltage; and a second power supply wiring extending in the first direction and supplying a second power supply voltage, wherein the first and second nanosheets have first side surfaces, which are one side in the second direction, exposed from the first gate wiring, and the source and drain of the second nanosheet FET are connected to the second power supply wiring, and the first gate wiring is supplied with the first power supply voltage.

[0011] According to this aspect, the capacitor cell includes a first nanosheet FET of a first conductivity type including a first nanosheet extending in a first direction; a second nanosheet FET of a second conductivity type formed above the first nanosheet FET in the depth direction and including a second nanosheet extending in the first direction and overlapping the first nanosheet in a planar view; and a first gate wiring extending in a second direction perpendicular to the first direction and surrounding the first and second nanosheets in the second direction and the depth direction. The first and second nanosheets have their first side surfaces, which are one side in the second direction, exposed from the first gate wiring. In other words, the first and second nanosheet FETs are fork-sheet FETs. The source and drain of the second nanosheet FET are connected to a second power supply wiring, and a first power supply voltage is supplied to the first gate wiring. This forms a capacitance between the gate and the source and drain of the second nanosheet FET via a gate oxide film. Furthermore, by using a fork-sheet FET, the active area constituting the transistor can be formed larger in the second direction, thereby increasing the capacitance value.

[0012] According to the present disclosure, it is possible to provide a layout structure of a capacitance cell when a fork-sheet FET is used as a transistor in a standard cell using a CFET.

[0013] (a) and (b) are plan views showing an example of a layout structure of a capacitance cell according to the first embodiment; (a) to (c) are cross-sectional views of the layout structure of FIG. 1; (a) to (d) are plan views showing an example of a layout structure of an inverter cell according to the first embodiment; (a) and (b) are plan views showing an example of a layout structure of a capacitance cell according to a first modification of the first embodiment; (a) and (b) are cross-sectional views of the layout structure of FIG. 6; and (a) and (b) are circuit diagrams of the capacitance cell according to a second modification of the first embodiment. 9 are plan views showing an example of a layout structure of a capacitance cell according to Modification 3 of the first embodiment; FIG. 11 is a plan view showing an example of a layout structure of a capacitance cell according to Modification 4 of the first embodiment; FIG. 13 is a plan view showing an example of a layout structure of a capacitance cell according to a second embodiment; 1A and 1B are plan views showing an example of a layout structure of a capacitor cell according to a modified example 1 of the second embodiment; FIG. 1C is a plan view showing an example of a layout structure of a capacitor cell according to a modified example 2 of the second embodiment; FIG. 1D is a plan view showing an example of a layout structure of a capacitor cell according to a modified example 3 of the second embodiment; FIG. 1E is a plan view showing an example of a layout structure of a capacitor cell according to a modified example 4 of the second embodiment; FIG. 1F is a plan view showing an example of a layout structure of a capacitor cell according to a third embodiment; 1A and 1B are plan views showing an example of a layout structure of a capacitance cell according to a first modification of the third embodiment; FIG. 1C is a plan view showing an example of a layout structure of a capacitance cell according to a fourth embodiment; FIG. 1D is a plan view showing an example of a layout structure of an inverter cell according to the fourth embodiment; FIG. 1E is a plan view showing an example of a layout structure of an inverter cell according to the fourth embodiment; FIG. 1F is a plan view showing an example of a layout structure of a capacitance cell according to a first modification of the fourth embodiment;

[0014] Hereinafter, embodiments will be described with reference to the drawings. In the following embodiments, a semiconductor integrated circuit device includes a plurality of standard cells (hereinafter, simply referred to as cells), and at least some of the plurality of standard cells include CFETs, i.e., three-dimensional devices in which three-dimensional P-type FETs and N-type FETs are stacked vertically relative to a substrate. In this embodiment, the CFETs include nanosheet FETs. In addition, in the semiconductor integrated circuit device, some of the nanosheet FETs are fork sheet FETs with fork-shaped gate electrodes.

[0015] In the plan views and cross-sectional views of the following embodiments, the description of each insulating film, etc. may be omitted. Furthermore, in this specification, expressions such as "same size" that mean that the size, etc., is the same are assumed to include the range of manufacturing variations.

[0016] In the following embodiments, "VDD" and "VSS" are used to indicate a power supply voltage or the power supply itself.

[0017] In the following description, in plan views such as FIG. 1, the horizontal direction of the drawing is the X direction (corresponding to the first direction), the vertical direction of the drawing is the Y direction (corresponding to the second direction), and the direction perpendicular to the substrate surface is the Z direction (corresponding to the depth direction). The dotted lines running vertically and horizontally in plan views such as FIG. 1 and the dotted lines running vertically in cross-sectional views such as FIG. 2 indicate grids used for component placement during design. The grids are arranged at equal intervals in the X direction and at equal intervals in the Y direction. The grid spacing may be the same or different in the X and Y directions. The grid spacing may also differ for each layer. Furthermore, components do not necessarily need to be arranged on a grid. However, from the perspective of suppressing manufacturing variations, it is preferable to arrange components on a grid.

[0018] 1 and 2 are diagrams showing an example of a layout structure of a capacitance cell according to a first embodiment, in which Fig. 1(a) and (b) are plan views, Fig. 2(a) is a cross-sectional view in the horizontal direction as viewed in a plane, and Fig. 2(b) and (c) are cross-sectional views in the vertical direction as viewed in a plane. Fig. 2(a) is a cross-section along line X1-X1', Fig. 2(b) is a cross-section along line Y1-Y1', and Fig. 2(c) is a cross-section along line Y2-Y2'.

[0019] The capacitance cell shown in Figures 1 and 2 includes a CFET. Figure 1(a) shows the lower part, i.e., a P-type nanosheet FET (lower transistor) formed on the side closer to the substrate, and a portion including the BM0 wiring layer, which is the wiring layer on its back side. Figure 1(b) shows the upper part, i.e., an N-type nanosheet FET (upper transistor) formed on the side farther from the substrate, and a portion including the MO wiring layer, which is the wiring layer on its front side. Here, the front side of the nanosheet FET refers to the side on which local wiring, metal wiring, etc. connected to the nanosheet FET are stacked relative to the nanosheet FET. The back side of the nanosheet FET refers to the side opposite to the side on which local wiring, metal wiring, etc. connected to the nanosheet FET are stacked.

[0020] The lower transistor, a P-type nanosheet FET, and the upper transistor, an N-type nanosheet FET, are both fork-sheet FETs.

[0021] 3 is a circuit diagram of the capacitance cell shown in FIGS. 1 and 2. As shown in FIG. 3, the cell shown in FIGS. 1 and 2 has P-type transistors P1, P2, and P3 and N-type transistors N1, N2, and N3. The gates of the P-type transistors P1, P2, and P3 and the N-type transistors N1, N2, and N3 are commonly connected to VSS. The sources and drains of the P-type transistors P1, P2, and P3 are connected to VDD. The sources and drains of the N-type transistors N1, N2, and N3 are floating.

[0022] In the P-type transistors P1, P2, and P3, capacitance is formed via the gate oxide film between the gate connected to VSS and the source and drain connected to VDD. The N-type transistors N1, N2, and N3 are in the off state and serve as dummy transistors.

[0023] As shown in FIG. 1A, a power supply wiring 11 extending in the X direction is formed in the BM0 wiring layer. The power supply wiring 11 supplies VDD. The power supply wiring 11 is located in the center of the capacitance cell in the Y direction in a plan view. Furthermore, in the BM0 wiring layer, a wiring 15a extending in the X direction is formed above the power supply wiring 11 in the drawing, and a wiring 15b extending in the X direction is formed below the power supply wiring 11 in the drawing. The wirings 15a and 15b are dummy wirings in a floating state. It is not necessary to form the wirings 15a and 15b.

[0024] An active region 2P is formed above the power supply wiring 11, constituting the channel, source, and drain of the P-type nanosheet FET that becomes the P-type transistors P1, P2, and P3. The active region 2P overlaps with the power supply wiring 11 in a planar view and also overlaps with the wiring 15b in a planar view. The active region 2P includes nanosheets 21a, 21b, and 21c that become the channel of the P-type nanosheet FET. In addition, portions 22a, 22b, 22c, and 22d of the active region 2P that become the source or drain of the P-type nanosheet FET are connected to the power supply wiring 11 via vias 31 formed on the back surface thereof. The vias 31 overlap with the power supply wiring 11 and the active region 2P in a planar view.

[0025] Local wirings 41a, 41b, 41c, and 41d are formed extending in the Y direction. The local wirings 41a, 41b, 41c, and 41d are in contact with portions 22a, 22b, 22c, and 22d in the active region 2P, respectively.

[0026] As shown in FIG. 1B, a power supply wiring 12 extending in the X direction is formed in the M0 wiring layer. The power supply wiring 12 supplies VSS. The power supply wiring 12 is located in the center of the capacitance cell in the Y direction in a plan view, and overlaps the power supply wiring 11 in a plan view. Note that while FIG. 1 depicts the power supply wirings 11 and 12 as having the same wiring width, the power supply wirings 11 and 12 do not have to have the same wiring width. Also, in the M0 wiring layer, a wiring 16a extending in the X direction is formed above the power supply wiring 12 in the drawing, and a wiring 16b extending in the X direction is formed below the power supply wiring 12 in the drawing. The wirings 16a and 16b are dummy wirings in a floating state. Note that the wirings 16a and 16b do not necessarily have to be formed.

[0027] An active region 2N is formed below the power supply wiring 12, constituting the channel, source, and drain of the N-type nanosheet FET that becomes the N-type transistors N1, N2, and N3. The active region 2N overlaps with the power supply wiring 12 in a planar view, and also overlaps with the wiring 16b in a planar view. The active region 2N also overlaps with the active region 2P in a planar view. The active region 2N includes nanosheets 23a, 23b, and 23c that become the channel of the N-type nanosheet FET. The nanosheets 23a, 23b, and 23c of the N-type nanosheet FET overlap with the nanosheets 21a, 21b, and 21c of the P-type nanosheet FET, respectively, in a planar view.

[0028] Local wirings 42a, 42b, 42c, and 42d are formed extending in the Y direction. The local wirings 42a, 42b, 42c, and 42d are in contact with portions 24a, 24b, 24c, and 24d that become the source or drain of the N-type nanosheet FET in the active region 2N, respectively.

[0029] The gate wirings 51a, 51b, and 51c extend in the Y direction and also extend in the Z direction from top to bottom. The gate wiring 51a surrounds the outer peripheries of the nanosheets 21a and 23a in the Y and Z directions via a gate insulating film (not shown). However, the surfaces of the nanosheets 21a and 23a on the lower side in the Y direction in FIG. 1 are not covered by the gate wiring 51a and are exposed from the gate wiring 51a. The gate wiring 51a serves as the gates of the transistors P1 and N1. The gate wiring 51b surrounds the outer peripheries of the nanosheets 21b and 23b in the Y and Z directions via a gate insulating film (not shown). However, the surfaces of the nanosheets 21b and 23b on the lower side in the Y direction in FIG. 1 are not covered by the gate wiring 51b and are exposed from the gate wiring 51b. The gate wiring 51b serves as the gates of the transistors P2 and N2. The gate wiring 51c surrounds the outer peripheries of the nanosheets 21c and 23c in the Y and Z directions via a gate insulating film (not shown). The gate wiring 51c serves as the gates of the transistors P3 and N3. However, the surfaces of the nanosheets 21c and 23c on the lower side in the Y direction in FIG. 1 are not covered by the gate wiring 51c and are exposed from the gate wiring 51c.

[0030] The gate wirings 51a, 51b, and 51c are connected to the power supply wiring 12 through vias 32 formed on their surfaces. The vias 32 overlap the power supply wiring 12 and the active region 2N in plan view, and are formed at the upper end in the Y direction of the region where the power supply wiring 12 and the gate wirings 51a, 51b, and 51c overlap, i.e., at the position closest to the end opposite the side where the nanosheet is exposed from the gate wiring.

[0031] In FIG. 1, the size of the active areas 2P and 2N in the Y direction is w1, and the distances from the active areas 2P and 2N to the cell frame in the Y direction are s1 and s2 (s1<s2).

[0032] In the capacitance cell according to this embodiment, the sources and drains of the nanosheet FETs P1, P2, and P3 are connected to a power supply wiring 11 that supplies VDD, and the gates of the nanosheet FETs P1, P2, and P3 are supplied with VSS. This creates capacitance between the gate and the source and drain of the nanosheet FETs P1, P2, and P3 via a gate oxide film. Furthermore, by using a fork sheet FET as the transistor that constitutes the CFET, the active area that constitutes the transistor can be made larger in the Y direction, thereby increasing the capacitance value.

[0033] Furthermore, in the capacitance cell according to this embodiment, the portions 22a, 22b, 22c, and 22d that serve as the source and drain of the P-type transistors P1, P2, and P3 are supplied with VDD from the power supply wiring 11 formed in the BM0 wiring layer through vias 31 that overlap the power supply wiring 11 and the active region 2P in a planar view. Therefore, the path length from the power supply wiring 11 to the portions 22a, 22b, 22c, and 22d is short. This reduces the resistance value from the power supply wiring 11 to the nanosheets 21a, 21b, and 21c, thereby improving the high-speed response of the capacitance that is configured.

[0034] Furthermore, in the capacitance cell according to this embodiment, VSS is supplied to gate wirings 51a, 51b, and 51c, which serve as the gates of P-type transistors P1, P2, and P3, from power supply wiring 12 formed in the M0 wiring layer through vias 32. The vias 32 are formed at the end of the region where the power supply wiring 12 and the gate wirings 51a, 51b, and 51c overlap in a plan view, on the side opposite the side where the nanosheet is exposed from the gate wiring in the Y direction. This makes it possible to suppress the resistance value from the power supply wiring 12 to the gates surrounding the nanosheets 21a, 21b, and 21c, thereby improving the high-speed response of the capacitance that is formed.

[0035] 4(a) to 4(d) are plan views showing examples of the layout structure of inverter cells. The inverter cells are an example of standard cells with logic functions included in the semiconductor integrated circuit device according to this embodiment. FIGS. 4(a) and 4(b) respectively show the structures of the lower and upper parts of inverter cell 1, and FIGS. 4(c) and 4(d) respectively show the structures of the lower and upper parts of inverter cell 2. Inverter cell 1 and inverter cell 2 basically have the same layout structure, but differ in the size of their active regions in the Y direction.

[0036] As with the capacitance cell of FIG. 1, the power supply wiring 11 is formed in the BM0 wiring layer at the center of the inverter cell in the Y direction, and the power supply wiring 12 is formed in the M0 wiring layer at the center of the inverter cell in the Y direction.

[0037] 4(a) and (b), an active region 2P1 constituting the channel, source, and drain of a P-type nanosheet FET is formed above a power supply wiring 11 formed in the BM0 wiring layer. The active region 2P1 overlaps the power supply wiring 11 in a planar view. The active region 2P1 includes a nanosheet 25 that serves as the channel of the P-type nanosheet FET. In addition, a portion 26a of the active region 2P1 that serves as the source of the P-type nanosheet FET is connected to the power supply wiring 11 via a via 63 formed on its back surface.

[0038] Local wirings 43a and 43b are formed extending in the Y direction. The local wirings 43a and 43b are in contact with the portions 26a and 26b in the active region 2P1, respectively.

[0039] An active region 2N1 that constitutes the channel, source, and drain of the N-type nanosheet FET is formed below the power supply wiring 12 formed in the M0 wiring layer. The active region 2N1 overlaps the power supply wiring 12 in a planar view. The active region 2N1 includes a nanosheet 27 that becomes the channel of the N-type nanosheet FET.

[0040] Local wirings 44a and 44b are formed extending in the Y direction. The local wirings 44a and 44b are in contact with the portions 28a and 28b in the active region 2N1, respectively. The local wiring 44a is connected to the power supply wiring 12 through a via 64 formed on its surface. The local wiring 44b is connected to the underlying local wiring 43b through a via.

[0041] The gate wiring 52 extends in the Y direction and also extends from top to bottom in the Z direction. The gate wiring 52 surrounds the outer peripheries of the nanosheets 25 and 27 in the Y and Z directions via a gate insulating film (not shown). However, the surfaces of the nanosheets 25 and 27 on the lower side in the Y direction in the drawing are not covered by the gate wiring 52 and are exposed from the gate wiring 52.

[0042] In the M0 wiring layer, wirings 71 and 72 extending in the X direction are formed. The wiring 71 is connected to the gate wiring 52 through a via. The wiring 71 serves as the input A of the inverter. The wiring 72 is connected to the local wiring 44b through a via. The wiring 72 serves as the output Y of the inverter.

[0043] The size of the active regions 2P1 and 2N1 in the Y direction is w1, and the distances from the active regions 2P1 and 2N1 to the cell frame in the Y direction are s1 and s2, respectively, which are the same as those of the capacitance cell shown in FIG.

[0044] The inverter cell 2 shown in Figures 4(c) and (d) has the same layout structure as the inverter cell 1 shown in Figures 4(a) and (b). However, the size w2 in the Y direction of the active regions 2P2 and 2N2 is smaller than the size w1 in the Y direction of the active regions 2P1 and 2N1 shown in Figures 4(a) and (b) (w2<w1). That is, the size in the Y direction of the nanosheet 25A is smaller than that of the nanosheet 25. Also, the size in the Y direction of the nanosheet 27A is smaller than that of the nanosheet 27. Therefore, the drive capability of the inverter cell 2 is smaller than that of the inverter cell 1.

[0045] 5A and 5B are plan views showing an example of the configuration of a cell row in this embodiment, with (a) being the bottom and (b) being the top. In Fig. 5, the cell row includes a cell C1, which is the inverter cell 1 shown in Figs. 4A and 4B, a cell C3, which is the capacity cell shown in Figs. 1A and 1B, and a cell C2, which is the inverter cell 2 shown in Figs. 4C and 4D.

[0046] 5(a), the active region 2P1 of cell C1 and the active region 2P of cell C3 have the same size in the Y direction (w1) and are laid out over the same area in the Y direction. That is, the nanosheet 25 constituting the P-type nanosheet FET of cell C1 has the same size in the Y direction and is laid out over the same area in the Y direction as the nanosheets 21a, 21b, and 21c constituting the P-type nanosheet FET of cell C3.

[0047] 5(b), the active region 2N1 of cell C1 and the active region 2N of cell C3 have the same size in the Y direction (w1) and are laid out over the same area in the Y direction. That is, the nanosheet 27 constituting the N-type nanosheet FET of cell C1 has the same size in the Y direction and is laid out over the same area in the Y direction as the nanosheets 23a, 23b, and 23c constituting the N-type nanosheet FET of cell C3.

[0048] Additionally, the active region 2P1 of cell C1, the active region 2P of cell C3, and the active region 2P2 of cell C2 have the same lower edge position in the Y direction. The active region 2N1 of cell C1, the active region 2N of cell C3, and the active region 2N2 of cell C2 have the same lower edge position in the Y direction. That is, the positions of the surfaces of the nanosheets exposed from the gate wiring of cells C1, C3, and C2 are aligned in the Y direction.

[0049] Here, the fork-sheet FET is formed by providing an insulating structure between the opposing nanosheets exposed from the gate wiring. Therefore, as shown in the configuration of Figure 5, in a cell row in which cells are aligned in the X direction, the position of the nanosheet surface exposed from the gate wiring can be aligned in the Y direction, thereby making the shape of the structure, i.e., the size and layout area in the Y direction, uniform. This facilitates manufacturing.

[0050] The active area of ​​cell C3, which is a capacitance cell, has the same size (w1) in the Y direction as the active area of ​​cell C1, which has the greater drive capability of cells C1 and C2, which are inverter cells 1 and 2. This allows the capacitance value of cell C3 to be increased.

[0051] Furthermore, when a capacitance cell is placed adjacent to inverter cells 1 and 2 having active areas of different sizes, the active area of ​​the adjacent capacitance cell exists relative to the active areas of inverter cells 1 and 2. This determines the distance between the active areas, thereby improving the accuracy of performance estimation.

[0052] 6A and 6B are plan views showing an example of a layout structure of a capacitance cell according to Modification 1 of this embodiment, where (a) shows the lower part and (b) shows the upper part. Fig. 7 is a cross-sectional view showing the cross section taken along line Y1-Y1' in Fig. 6.

[0053] Fig. 8 is a circuit diagram of the capacitance cell shown in Fig. 6 and Fig. 7. The circuit diagram of Fig. 8 is almost the same as Fig. 3, but the sources and drains of N-type transistors N1, N2, and N3 are not in a floating state but are connected to VSS.

[0054] The layout structure according to this modification has basically the same configuration as the layout structure according to the first embodiment, except that vias are added to the layout structure of FIG.

[0055] That is, the local wirings 42a, 42b, 42c, and 42d are connected to the power supply wiring 12 through the vias 33. Furthermore, wiring 16a, which is located above the power supply wiring 12 in the drawing, is connected to the local wirings 42a, 42b, 42c, and 42d through the vias 34, and is also connected to the gate wirings 51a, 51b, and 51c through the vias 35.

[0056] According to this modification, capacitance is also formed between the local wirings 42a, 42b, 42c, and 42d at the upper portion and the portions 24a, 24b, 24c, and 24d in the active region 2N and the local wirings 41a, 41b, 41c, and 41d at the lower portion and the portions 22a, 22b, 22c, and 22d in the active region 2P, thereby increasing the capacitance value of the capacitance cell.

[0057] Furthermore, VSS is also supplied to the gate wirings 51 a, 51 b, and 51 c from wiring 16 a formed on the opposite side to the side where the nanosheet is exposed from the gate wiring, thereby suppressing the resistance value from the power supply wiring 12 to the gates surrounding the nanosheets 21 a, 21 b, and 21 c.

[0058] (Modification 2) FIGS. 9A and 9B are plan views showing an example of a layout structure of a capacitor cell according to Modification 2 of this embodiment, where (a) shows the lower part and (b) shows the upper part.

[0059] 10 is a circuit diagram of the capacitance cell shown in FIG. 9. The circuit diagram in FIG. 10 is almost the same as that in FIG. 8, but the gates of the P-type transistors P1, P2, and P3 and the N-type transistors N1, N2, and N3 are connected to VDD instead of VSS. That is, in this modification, the N-type transistors N1, N2, and N3 form a capacitance. The P-type transistors P1, P2, and P3 are in the off state and serve as dummy transistors.

[0060] 9 , the local wirings 41a, 41b, 41c, and 41d at the bottom are connected to the M0 wiring 16a at the top via the via 36. The M0 wiring 16a is connected to the gate wirings 51a, 51b, and 51c via the via 37. As a result, VDD is supplied to the gate wirings 51a, 51b, and 51c from the power supply wiring 11 of the B-M0 layer via the via 31, the active region 2P, the local wirings 41a, 41b, 41c, and 41d, the via 36, ​​the M0 wiring 16a, and the via 37.

[0061] The local wirings 42a, 42b, 42c, and 42d at the top are connected to the power supply wiring 12 through the vias 38. As a result, VSS is supplied to the portions 24a, 24b, 24c, and 24d that become the sources and drains of the nanosheet FETs N1, N2, and N3.

[0062] According to this modification, the sources and drains of the nanosheet FETs N1, N2, and N3 are connected to a power supply wiring 12 that supplies VSS, and the gates of the nanosheet FETs N1, N2, and N3 are supplied with VDD. This creates capacitance between the gate and the source and drain of the nanosheet FETs N1, N2, and N3 via the gate oxide film. Furthermore, by using a fork sheet FET as the transistor that constitutes the CFET, the active area that constitutes the transistor can be made larger in the Y direction, thereby increasing the capacitance value.

[0063] 11A and 11B are plan views showing an example of a layout structure of a capacitance cell according to Modification 3 of this embodiment, where (a) shows the lower part and (b) shows the upper part. Note that components common to those in FIG. 1 and the like are given the same reference numerals, and detailed description thereof may be omitted here.

[0064] 12 is a circuit diagram of the capacitance cell shown in FIG. 11. As shown in FIG. 12, the cell shown in FIG. 11 has P-type transistors P1, P2, and P3 and N-type transistors N1, N2, and N3. Capacitor section 1 has P-type transistor P3 and N-type transistor N3. Fixed value output section 2 has P-type transistors P1 and P2 and N-type transistors N1 and N2. Fixed value output section 2 outputs a fixed value to the gates of transistors P3 and N3 of capacitor section 1. In FIG. 12, fixed value output section 2 outputs VDD, i.e., a high fixed value.

[0065] The sources of P-type transistors P1 and P2 are both connected to VDD, and their drains are connected to each other. The sources of N-type transistors N1 and N2 are both connected to VSS, and their drains are connected to each other. The gates of P-type transistor P1 and N-type transistor N1 are connected to each other, and the gates of P-type transistor P2 and N-type transistor N2 are connected to each other. The drains of P-type transistors P1 and P2 are connected to the gates of P-type transistor P2 and N-type transistor N2, and the drains of N-type transistors N1 and N2 are connected to the gates of P-type transistor P1 and N-type transistor N1. The source and drain of P-type transistor P3 are connected to VDD, and the source and drain of N-type transistor N3 are connected to VSS. The gates of P-type transistor P3 and N-type transistor N3 are connected to each other. The drains of P-type transistors P1 and P2 are connected to the gates of P-type transistor P3 and N-type transistor N3.

[0066] The drain voltages of P-type transistors P1 and P2 are VDD, i.e., a fixed high value. N-type transistor N3 functions as a capacitor because its source and drain are fixed to VSS and VDD is supplied to its gate. P-type transistor P3 functions as a dummy transistor in the off state because its source and drain are fixed to VDD and VDD is supplied to its gate. P-type transistor P1 and N-type transistor N2 are on, while P-type transistor P2 and N-type transistor N1 are off. P-type transistor P1 functions as a capacitor because its source and drain are fixed to VDD and VSS is supplied to its gate. N-type transistor N2 functions as a capacitor because its source and drain are fixed to VSS and VDD is supplied to its gate.

[0067] 11A, the active region 2P has portions 22a, 22b, 22c, and 22d that serve as the source or drain of the P-type nanosheet FET. The portions 22a, 22c, and 22d are connected to the power supply wiring 11 through vias 31A formed on the back surfaces of the portions 22a, 22b, and 22d. The portion 22b is not connected to the power supply wiring 11.

[0068] As shown in FIG. 11B, in the M0 wiring layer, a wiring 16c extending in the X direction is formed above the power supply wiring 12 in the drawing, and a wiring 16d extending in the X direction is formed below the power supply wiring 12 in the drawing.

[0069] The local wirings 42a, 42b, 42c, and 42d are in contact with the portions 24a, 24b, 24c, and 24d that become the source or drain of the N-type nanosheet FET in the active region 2N, respectively. The local wiring 42b is shorter than that shown in FIG. 1B so as not to overlap with the M0 wiring 16c in plan view. The local wirings 42a, 42c, and 42d are connected to the power supply wiring 12 through the via 38A.

[0070] The wiring 16c is connected to the local wiring 41b at the bottom through a via. The wiring 16c is also connected to the gate wirings 51b and 51c through a via. The wiring 16d is connected to the local wiring 42b through a via. The wiring 16d is also connected to the gate wiring 51a through a via.

[0071] According to this modification, the source and drain of the nanosheet FET N3 are connected to the power supply wiring 12 that supplies VSS, and the gate of the nanosheet FET N3 is supplied with VDD from the fixed value output unit 2. As a result, in the nanosheet FET N3, capacitance is formed between the gate and the source and drain via the gate oxide film. In addition, by using a fork sheet FET as the transistor that constitutes the CFET, the active area that constitutes the transistor can be formed large in the Y direction, thereby increasing the capacitance value.

[0072] In this modification, VDD is supplied to gate wiring 51c, which serves as the gate of transistors P3 and N3, from local wiring 41b, which is in contact with the drains of transistors P1 and P2 that constitute the fixed value output unit 2, via wiring 16c formed in the M0 wiring layer. Wiring 16c is formed on the opposite side of the nanosheet exposed from the gate wiring in the Y direction in plan view. This makes it possible to suppress the resistance value from the fixed value output unit 2 to the gate surrounding the nanosheet of transistor N3, thereby improving the high-speed response of the capacitor that is formed.

[0073] 13A and 13B are plan views showing an example of a layout structure of a capacitance cell according to Modification 4 of this embodiment, where (a) shows the lower part and (b) shows the upper part. Note that components common to those in FIG. 1 and the like are given the same reference numerals, and detailed description thereof may be omitted here.

[0074] Fig. 14 is a circuit diagram of the capacitance cell shown in Fig. 13. As shown in Fig. 14, in the cell shown in Fig. 13, the fixed value output section 2 outputs VSS, i.e., a low fixed value, to the gates of the transistors P3 and N3 of the capacitance section 1. That is, the drains of the N-type transistors N1 and N2 are connected to the gates of the P-type transistor P3 and the N-type transistor N3.

[0075] The drain voltages of N-type transistors N1 and N2 are VSS, i.e., a fixed low value. The source and drain of P-type transistor P3 are fixed to VDD and VSS is supplied to its gate, so it functions as a capacitor. The source and drain of N-type transistor N3 are fixed to VSS and VSS is supplied to its gate, so it functions as a dummy transistor in the off state. The source and drain of P-type transistor P1 are also fixed to VDD and VSS is supplied to its gate, so it functions as a capacitor. The source and drain of N-type transistor N2 are also fixed to VSS and VDD is supplied to its gate, so it also functions as a capacitor. The P-type transistor P2 and N-type transistor N1 are in the off state.

[0076] The layout structure shown in FIG. 13 is almost the same as the layout structure shown in FIG. 11. However, the connection relationship between the wirings 16c and 16d in the M0 wiring layer and other components is different. The wiring 16c is connected to the local wiring 41b through a via, and also to the gate wiring 51b through a via. The wiring 16d is connected to the local wiring 42b through a via, and also to the gate wirings 51a and 51c through vias. In other words, the connection destination of the gate wiring 51c, which serves as the gate of the transistors P3 and N3, has changed from the wiring 16c to the wiring 16d. The other structures are the same as those in FIG. 11.

[0077] According to this modification, the source and drain of the nanosheet FET P3 are connected to the power supply wiring 11 that supplies VDD, and the gate of the nanosheet FET P3 is supplied with VSS from the fixed value output unit 2. As a result, in the nanosheet FET P3, capacitance is formed between the gate and the source and drain via the gate oxide film. In addition, by using a fork sheet FET as the transistor that constitutes the CFET, the active area that constitutes the transistor can be formed large in the Y direction, thereby increasing the capacitance value.

[0078] Second Embodiment Figure 15 is a plan view showing an example of a layout structure of a capacitance cell according to a second embodiment, where (a) shows the lower part and (b) shows the upper part. In this embodiment, components common to the first embodiment are given the same reference numerals, and detailed descriptions of configurations that can be easily inferred from the description of the first embodiment may be omitted. The circuit configuration of the capacitance cell shown in Figure 15 is the same as that shown in the circuit diagram of Figure 3 shown in the first embodiment.

[0079] 15A, a power supply wiring 111 extending in the X direction is formed in the BM0 wiring layer. The power supply wiring 111 supplies VDD. The power supply wiring 111 is arranged at the lower end of the capacitance cell in the Y direction in the drawing so as to straddle the cell frame.

[0080] A portion of the active region 2P on the lower side in the Y direction of the drawing overlaps with the power supply wiring 111 in plan view. In the active region 2P, portions 22a, 22b, 22c, and 22d that become the source or drain of the P-type nanosheet FET are connected to the power supply wiring 111 through vias 131 formed on the back surface thereof. The vias 131 overlap with the power supply wiring 111 and the active region 2P in plan view.

[0081] 15B, a power supply wiring 112 extending in the X direction is formed in the M0 wiring layer. The power supply wiring 112 supplies VSS. In plan view, the power supply wiring 112 is arranged at the lower end of the capacitance cell in the Y direction so as to straddle the cell frame, and overlaps with the power supply wiring 111 in plan view.

[0082] In the active region 2N, a part of the lower side in the Y direction in the drawing overlaps, in plan view, with the power supply wiring 112. The gate wirings 51a, 51b, and 51c are connected to the power supply wiring 112 through vias 132 formed in their surfaces.

[0083] In this embodiment, as in the first embodiment, the surface of the nanosheet on the lower side in the Y direction in the drawing is exposed from the gate wiring, and the power supply wirings 111 and 112 are arranged on the side of the nanosheet exposed from the gate wiring.

[0084] In the capacitance cell according to this embodiment, the sources and drains of the nanosheet FETs P1, P2, and P3 are connected to a power supply wiring 111 that supplies VDD, and the gates of the nanosheet FETs P1, P2, and P3 are supplied with VSS. This creates capacitance between the gate and the source and drain of the nanosheet FETs P1, P2, and P3 via a gate oxide film. Furthermore, by using a fork-sheet FET as the transistor that constitutes the CFET, the active area that constitutes the transistor can be made larger in the Y direction, thereby increasing the capacitance value.

[0085] Furthermore, in the capacitance cell according to this embodiment, VDD is supplied to the portions 22a, 22b, 22c, and 22d that serve as the source and drain of the P-type transistors P1, P2, and P3 from the power supply wiring 111 formed in the BM0 wiring layer via a via 131 that overlaps the power supply wiring 111 and the active region 2P in a planar view. Therefore, the path length from the power supply wiring 111 to the portions 22a, 22b, 22c, and 22d is short. This reduces the resistance value from the power supply wiring 111 to the nanosheets 21a, 21b, and 21c, thereby improving the high-speed response of the capacitance that is configured.

[0086] 16(a) to 16(d) are plan views showing examples of the layout structure of inverter cells. The inverter cells are an example of standard cells with logic functions included in the semiconductor integrated circuit device according to this embodiment. FIGS. 16(a) and 16(b) show the structures of the lower and upper parts, respectively, of inverter cell 1, and FIGS. 16(c) and 16(d) show the structures of the lower and upper parts, respectively, of inverter cell 2. Inverter cell 1 and inverter cell 2 basically have the same layout structure, but differ in the size of their active regions in the Y direction.

[0087] As with the capacitance cell shown in Figure 15, power supply wiring 111 is arranged in the BM0 wiring layer at the lower end of the inverter cell in the Y direction of the drawing, and power supply wiring 112 is arranged in the M0 wiring layer at the lower end of the inverter cell in the Y direction of the drawing.

[0088] 16(a) and 16(b), a part of the lower side of the active region 2P1 in the Y direction overlaps with the power supply wiring 111 in plan view. In the active region 2P1, a portion 26a serving as the source of the P-type nanosheet FET is connected to the power supply wiring 111 through a via 163 formed on its back surface.

[0089] In the active region 2N1, a portion of the lower side in the Y direction of the drawing overlaps in plan view with the power supply wiring 112. In the active region 2N1, a portion 28a serving as the source of the N-type nanosheet FET is connected to the power supply wiring 112 via a local wiring 44a and a via 164 formed on the surface thereof.

[0090] The size of the active regions 2P1 and 2N1 in the Y direction is w1, and the distances from the active regions 2P1 and 2N1 to the cell frame in the Y direction are s1 and s2, which are the same as the capacitance cell shown in FIG.

[0091] The inverter cell 2 shown in Figures 16(c) and (d) has the same layout structure as the inverter cell 1 shown in Figures 16(a) and (b). However, the size w2 in the Y direction of the active regions 2P2 and 2N2 is smaller than the size w1 in the Y direction of the active regions 2P1 and 2N1 shown in Figures 16(a) and (b) (w2<w1). That is, the size in the Y direction of the nanosheet 25A is smaller than that of the nanosheet 25. Also, the size in the Y direction of the nanosheet 27A is smaller than that of the nanosheet 27. Therefore, the drive capability of the inverter cell 2 is smaller than that of the inverter cell 1.

[0092] 17A and 17B are plan views showing an example of the configuration of a cell row in this embodiment, with (a) being the bottom and (b) being the top. In Fig. 17, the cell row includes a cell C1, which is the inverter cell 1 shown in Figs. 16A and 16B, a cell C3, which is the capacity cell shown in Figs. 15A and 15B, and a cell C2, which is the inverter cell 2 shown in Figs. 16C and 16D.

[0093] 17(a), the active region 2P1 of cell C1 and the active region 2P of cell C3 have the same size in the Y direction (w1) and are laid out over the same area in the Y direction. That is, the nanosheet 25 constituting the P-type nanosheet FET of cell C1 has the same size in the Y direction and is laid out over the same area in the Y direction as the nanosheets 21a, 21b, and 21c constituting the P-type nanosheet FET of cell C3.

[0094] 17(b), the active region 2N1 of cell C1 and the active region 2N of cell C3 have the same size in the Y direction (w1) and are laid out over the same area in the Y direction. That is, the nanosheet 27 constituting the N-type nanosheet FET of cell C1 has the same size in the Y direction and is laid out over the same area in the Y direction as the nanosheets 23a, 23b, and 23c constituting the N-type nanosheet FET of cell C3.

[0095] Additionally, the active region 2P1 of cell C1, the active region 2P of cell C3, and the active region 2P2 of cell C2 have the same lower edge position in the Y direction. The active region 2N1 of cell C1, the active region 2N of cell C3, and the active region 2N2 of cell C2 have the same lower edge position in the Y direction. That is, the positions of the surfaces of the nanosheets exposed from the gate wiring of cells C1, C3, and C2 are aligned in the Y direction.

[0096] Here, the fork-sheet FET is formed by providing an insulating structure between the opposing nanosheets exposed from the gate wiring. Therefore, as shown in the configuration of Figure 17, in a cell row in which cells are aligned in the X direction, the position of the nanosheet surface exposed from the gate wiring can be aligned in the Y direction, thereby making the shape of the structure, i.e., the size and layout area in the Y direction, uniform. This facilitates manufacturing.

[0097] The active area of ​​cell C3, which is a capacitance cell, has the same size (w1) in the Y direction as the active area of ​​cell C1, which has the greater drive capability of cells C1 and C2, which are inverter cells 1 and 2. This allows the capacitance value of cell C3 to be increased.

[0098] Furthermore, when a capacitance cell is placed adjacent to inverter cells 1 and 2 having active areas of different sizes, the active area of ​​the adjacent capacitance cell exists relative to the active areas of inverter cells 1 and 2. This determines the distance between the active areas, thereby improving the accuracy of performance estimation.

[0099] 18A and 18B are plan views showing an example of a layout structure of a capacitance cell according to Modification 1 of the present embodiment, where (a) shows the lower part and (b) shows the upper part. The circuit configuration of the capacitance cell shown in Fig. 18 is the same as that shown in the circuit diagram of Fig. 8 shown in Modification 1 of the first embodiment.

[0100] The layout structure according to this modification has basically the same configuration as the layout structure according to the second embodiment. However, vias are added to the layout structure shown in FIG. 18B. That is, the local wirings 42a, 42b, 42c, and 42d are connected to the power supply wiring 112 through vias 133.

[0101] According to this modification, capacitance is also formed between the local wirings 42a, 42b, 42c, and 42d at the upper portion and the portions 27a, 27b, 27c, and 27d in the active region 2N and the local wirings 41a, 41b, 41c, and 41d at the lower portion and the portions 22a, 22b, 22c, and 22d in the active region 2P, thereby increasing the capacitance value of the capacitance cell.

[0102] 19A and 19B are plan views showing an example of a layout structure of a capacitance cell according to Modification 2 of the present embodiment, where (a) shows the lower part and (b) shows the upper part. The circuit configuration of the capacitance cell shown in Fig. 19 is the same as that shown in the circuit diagram of Fig. 10 shown in Modification 2 of the first embodiment.

[0103] 19 , the local wirings 41a, 41b, 41c, and 41d at the bottom are connected to the M0 wiring 116a at the top via a via 136. The M0 wiring 116a is connected to the gate wirings 51a, 51b, and 51c via a via 137. As a result, VDD is supplied to the gate wirings 51a, 51b, and 51c from the power supply wiring 111 of the B-M0 layer via the via 131, the active region 2P, the local wirings 41a, 41b, 41c, and 41d, the via 136, the M0 wiring 116a, and the via 137.

[0104] According to this modification, the sources and drains of the nanosheet FETs N1, N2, and N3 are connected to a power supply wiring 112 that supplies VSS, and the gates of the nanosheet FETs N1, N2, and N3 are supplied with VDD. As a result, in the nanosheet FETs N1, N2, and N3, capacitance is formed between the gate and the source and drain via the gate oxide film. Furthermore, by using a fork sheet FET as the transistor that constitutes the CFET, the active area that constitutes the transistor can be formed large in the Y direction, thereby increasing the capacitance value.

[0105] 20 is a plan view showing an example of a layout structure of a capacitance cell according to Modification 3 of this embodiment, where (a) shows the lower part and (b) shows the upper part. The circuit configuration of the capacitance cell shown in FIG. 20 is the same as that shown in the circuit diagram of FIG. 12 shown in Modification 3 of the first embodiment. Note that components common to those in FIG. 15 and the like are given the same reference numerals, and detailed description thereof may be omitted here.

[0106] 20(a), in the active region 2P, of the portions 22a, 22b, 22c, and 22d that become the source or drain of the P-type nanosheet FET, the portions 22a, 22c, and 22d are connected to the power supply wiring 111 through a via 131A formed on the back surface thereof. The portion 22b is not connected to the power supply wiring 111.

[0107] As shown in FIG. 20B, in the M0 wiring layer, wirings 116c and 116d extending in the X direction are formed above the power supply wiring 112 in the drawing.

[0108] The local wirings 42a, 42b, 42c, and 42d are in contact with the portions 24a, 24b, 24c, and 24d that become the source or drain of the N-type nanosheet FET in the active region 2N, respectively. The local wiring 42b is shorter than that shown in FIG. 15B so as not to overlap with the M0 wiring 116c in plan view. The local wirings 42a, 42c, and 42d are connected to the power supply wiring 112 via a via 133A.

[0109] The wiring 116c is connected to the local wiring 41b at the bottom through a via. The wiring 116c is also connected to the gate wirings 51b and 51c through a via. The wiring 116d is connected to the local wiring 42b through a via. The wiring 116d is also connected to the gate wiring 51a through a via.

[0110] According to this modification, the source and drain of the nanosheet FET N3 are connected to the power supply wiring 112 that supplies VSS, and the gate of the nanosheet FET N3 is supplied with VDD from the fixed value output unit 2. As a result, in the nanosheet FET N3, capacitance is formed between the gate and the source and drain via the gate oxide film. In addition, by using a fork sheet FET as the transistor that constitutes the CFET, the active area that constitutes the transistor can be formed large in the Y direction, thereby increasing the capacitance value.

[0111] In this modification, VDD is supplied to gate wiring 51c, which serves as the gate of transistors P3 and N3, from local wiring 41b, which is in contact with the drains of transistors P1 and P2 that constitute the fixed value output unit 2, via wiring 116c formed in the M0 wiring layer. Wiring 116c is formed on the opposite side in the Y direction from the side where the nanosheet is exposed from the gate wiring, in a plan view. This makes it possible to suppress the resistance value from the fixed value output unit 2 to the gate surrounding the nanosheet of transistor N3, thereby improving the high-speed response of the capacitor that is formed.

[0112] 21 is a plan view showing an example of a layout structure of a capacitance cell according to a fourth modification of this embodiment, where (a) shows the lower part and (b) shows the upper part. The circuit configuration of the capacitance cell shown in FIG. 21 is the same as that shown in the circuit diagram of FIG. 14 shown in the fourth modification of the first embodiment. Note that components common to those in FIG. 15 and the like are given the same reference numerals, and detailed description thereof may be omitted here.

[0113] The layout structure shown in FIG. 21 is almost the same as the layout structure shown in FIG. 20 . However, the connection relationship between the wirings 116c and 116d in the M0 wiring layer and other components is different. The wiring 116c is connected to the local wiring 41b through a via, and also to the gate wiring 51b through a via. The wiring 116d is connected to the local wiring 42b through a via, and also to the gate wirings 51a and 51c through vias. In other words, the connection destination of the gate wiring 51c, which serves as the gates of the P-type transistor P3 and the N-type transistor N3, has changed from the wiring 116c to the wiring 116d. The other structures are the same as those in FIG. 20 .

[0114] According to this modification, the source and drain of the nanosheet FET P3 are connected to the power supply wiring 111 that supplies VDD, and the gate of the nanosheet FET P3 is supplied with VSS from the fixed value output unit 2. As a result, in the nanosheet FET P3, capacitance is formed between the gate and the source and drain via the gate oxide film. In addition, by using a fork sheet FET as the transistor that constitutes the CFET, the active area that constitutes the transistor can be formed large in the Y direction, thereby increasing the capacitance value.

[0115] 22 is a plan view showing an example of a layout structure of a capacitance cell according to a third embodiment, where (a) shows the lower part and (b) shows the upper part. In this embodiment, components common to the first embodiment are given the same reference numerals, and detailed descriptions of configurations that can be easily inferred from the description of the first embodiment may be omitted. The circuit configuration of the capacitance cell shown in FIG. 22 is as shown in the circuit diagram of FIG.

[0116] 22A, a power supply wiring 211 extending in the X direction is formed in the BM0 wiring layer. The power supply wiring 211 supplies VDD. In plan view, the power supply wiring 211 is arranged at the upper end of the capacitance cell in the Y direction so as to straddle the cell frame.

[0117] The active region 2P does not overlap with the power supply wiring 211 in a plan view. The local wirings 41a, 41b, 41c, and 41d, which are in contact with the portions 22a, 22b, 22c, and 22d that become the source or drain of the P-type nanosheet FET, have their ends on the upper side of the drawing in the Y direction overlap with the power supply wiring 211. The local wirings 41a, 41b, 41c, and 41d are connected to the power supply wiring 211 through vias 231 formed on their back surfaces.

[0118] 22B, a power supply wiring 212 extending in the X direction is formed in the M0 wiring layer. The power supply wiring 212 supplies VSS. In plan view, the power supply wiring 212 is arranged at the upper end of the capacitance cell in the Y direction so as to straddle the cell frame.

[0119] The active region 2N does not overlap, in plan view, with the power supply wiring 212. The gate wirings 51a, 51b, and 51c are connected to the power supply wiring 212 through vias 232 formed on the surfaces thereof.

[0120] As in the first embodiment, the surface of the nanosheet on the lower side in the Y direction in the drawing is exposed from the gate wiring, and the power supply wirings 211 and 212 are arranged on the side opposite to the side of the nanosheet exposed from the gate wiring.

[0121] In the capacitance cell according to this embodiment, the sources and drains of the nanosheet FETs P1, P2, and P3 are connected to a power supply wiring 211 that supplies VDD, and the gates of the nanosheet FETs P1, P2, and P3 are supplied with VSS. This creates capacitance between the gate and the source and drain of the nanosheet FETs P1, P2, and P3 via a gate oxide film. Furthermore, by using a fork sheet FET as the transistor that constitutes the CFET, the active area that constitutes the transistor can be made larger in the Y direction, thereby increasing the capacitance value.

[0122] Furthermore, in the capacitance cell according to this embodiment, gate wirings 51a, 51b, and 51c, which serve as the gates of P-type transistors P1, P2, and P3, are supplied with VSS from a power supply wiring 212 formed in the M0 wiring layer through vias 232. The power supply wiring 212 is formed at the end of the capacitance cell on the side opposite to the side where the nanosheet is exposed from the gate wiring in the Y direction. This reduces the resistance value from the power supply wiring 212 to the gates surrounding the nanosheets 21a, 21b, and 21c, thereby improving the high-speed response of the capacitance that is formed.

[0123] 23(a) to 23(d) are plan views showing examples of the layout structure of inverter cells. The inverter cells are an example of standard cells with logic functions included in the semiconductor integrated circuit device according to this embodiment. 23(a) and 23(b) respectively show the structures of the lower and upper parts of inverter cell 1, and 23(c) and 23(d) respectively show the structures of the lower and upper parts of inverter cell 2. Inverter cell 1 and inverter cell 2 basically have the same layout structure, but differ in the size of their active regions in the Y direction.

[0124] As with the capacitance cell of Figure 22, the power supply wiring 211 is arranged in the BM0 wiring layer at the upper end of the inverter cell in the Y direction in a planar view, and the power supply wiring 212 is arranged in the M0 wiring layer at the upper end of the inverter cell in the Y direction in a planar view.

[0125] 23(a) and 23(b), the active region 2P1 does not overlap in plan view with the power supply wiring 211 formed in the BM0 wiring layer. The local wiring 43a in contact with the portion 26a that serves as the source of the P-type nanosheet FET in the active region 2P1 is connected to the power supply wiring 211 through a via 263 formed on its back surface.

[0126] The active region 2N1 does not overlap in plan view with the power supply wiring 212 formed in the M0 wiring layer. The local wiring 44a in contact with the portion 28a that becomes the source of the N-type nanosheet FET in the active region 2N1 is connected to the power supply wiring 212 through a via 264 formed on its surface.

[0127] The size of the active regions 2P1 and 2N1 in the Y direction is w1, and the distances from the active regions 2P1 and 2N1 to the cell frame in the Y direction are s1 and s2, respectively, which are the same as the capacitance cell shown in FIG.

[0128] The inverter cell 2 shown in Figures 23(c) and (d) has the same layout structure as the inverter cell 1 shown in Figures 23(a) and (b). However, the size w2 in the Y direction of the active regions 2P2 and 2N2 is smaller than the size w1 in the Y direction of the active regions 2P1 and 2N1 shown in Figures 23(a) and (b) (w2<w1). That is, the size in the Y direction of the nanosheet 25A is smaller than that of the nanosheet 25. Also, the size in the Y direction of the nanosheet 27A is smaller than that of the nanosheet 27. Therefore, the drive capability of the inverter cell 2 is smaller than that of the inverter cell 1.

[0129] 24A and 24B are plan views showing an example of the configuration of a cell row in this embodiment, with (a) being the bottom and (b) being the top. In Fig. 24, in the cell row, cell C1, which is the inverter cell 1 shown in Figs. 23A and 23B, cell C3, which is the capacity cell shown in Figs. 22A and 22B, and cell C2, which is the inverter cell 2 shown in Figs. 23C and 23D, are arranged side by side.

[0130] 24(a), the active region 2P1 of cell C1 and the active region 2P of cell C3 have the same size in the Y direction (w1) and are laid out over the same area in the Y direction. That is, the nanosheet 25 constituting the P-type nanosheet FET of cell C1 has the same size in the Y direction and is laid out over the same area in the Y direction as the nanosheets 21a, 21b, and 21c constituting the P-type nanosheet FET of cell C3.

[0131] 24(b), the active region 2N1 of cell C1 and the active region 2N of cell C3 have the same size in the Y direction (w1) and are laid out over the same area in the Y direction. That is, the nanosheet 27 constituting the N-type nanosheet FET of cell C1 has the same size in the Y direction and is laid out over the same area in the Y direction as the nanosheets 23a, 23b, and 23c constituting the N-type nanosheet FET of cell C3.

[0132] Additionally, the active region 2P1 of cell C1, the active region 2P of cell C3, and the active region 2P2 of cell C2 have the same lower edge position in the Y direction. The active region 2N1 of cell C1, the active region 2N of cell C3, and the active region 2N2 of cell C2 have the same lower edge position in the Y direction. That is, the positions of the surfaces of the nanosheets exposed from the gate wiring of cells C1, C3, and C2 are aligned in the Y direction.

[0133] Here, the fork-sheet FET is formed by providing an insulating structure between the opposing nanosheets exposed from the gate wiring. Therefore, as shown in the configuration of Figure 24, in a cell row in which cells are aligned in the X direction, the position of the surface of the nanosheet exposed from the gate wiring can be aligned in the Y direction, thereby making the shape of the structure, i.e., the size and layout area in the Y direction, uniform. This facilitates manufacturing.

[0134] The active area of ​​cell C3, which is a capacitance cell, has the same size (w1) in the Y direction as the active area of ​​cell C1, which has the greater drive capability of cells C1 and C2, which are inverter cells 1 and 2. This allows the capacitance value of cell C3 to be increased.

[0135] Furthermore, when a capacitance cell is placed adjacent to inverter cells 1 and 2 having active areas of different sizes, the active area of ​​the adjacent capacitance cell exists relative to the active areas of inverter cells 1 and 2. This determines the distance between the active areas, thereby improving the accuracy of performance estimation.

[0136] 25A and 25B are plan views showing an example of a layout structure of a capacitance cell according to Modification 1 of the present embodiment, where (a) shows the lower part and (b) shows the upper part. The circuit configuration of the capacitance cell shown in Fig. 25 is the same as that shown in the circuit diagram of Fig. 8 shown in Modification 1 of the first embodiment.

[0137] The layout structure according to this modification has basically the same configuration as the layout structure according to the third embodiment. However, vias are added to the layout structure of FIG. 25B. That is, the local wirings 42a, 42b, 42c, and 42d are connected to the power supply wiring 212 through vias 233.

[0138] According to this modification, capacitance is also formed between the local wirings 42a, 42b, 42c, and 42d at the upper portion and the portions 27a, 27b, 27c, and 27d in the active region 2N and the local wirings 41a, 41b, 41c, and 41d at the lower portion and the portions 22a, 22b, 22c, and 22d in the active region 2P, thereby increasing the capacitance value of the capacitance cell.

[0139] 26 is a plan view showing an example of a layout structure of a capacitance cell according to a fourth embodiment, where (a) shows the lower part and (b) shows the upper part. In this embodiment, components common to the first embodiment are assigned the same reference numerals, and detailed descriptions of configurations that can be easily inferred from the description of the first embodiment may be omitted. The circuit configuration of the capacitance cell shown in FIG. 26 is the same as that shown in the circuit diagram of FIG. 8 shown in Modification 1 of the first embodiment.

[0140] As shown in FIG. 26A, power supply wiring 311 and 312 extending in the X direction are formed in the BM0 wiring layer. The power supply wiring 311 supplies VDD. The power supply wiring 311 is arranged at the lower end of the capacitance cell in the Y direction in the drawing, straddling the cell frame. The power supply wiring 312 supplies VSS. The power supply wiring 312 is arranged at the upper end of the capacitance cell in the Y direction in the drawing, straddling the cell frame.

[0141] A part of the active region 2P on the lower side in the Y direction of the drawing overlaps with the power supply wiring 311 in plan view. In the active region 2P, portions 22a, 22b, 22c, and 22d that become the source or drain of the P-type nanosheet FET are connected to the power supply wiring 311 through vias 331 formed on the back surfaces thereof. The vias 331 overlap with the power supply wiring 311 and the active region 2P in plan view.

[0142] 26(b), the local wirings 42a, 42b, 42c, and 42d are in contact with the portions 24a, 24b, 24c, and 24d that become the source or drain of the N-type nanosheet FET in the active region 2N. The ends of the local wirings 42a, 42b, 42c, and 42d on the upper side in the Y direction of the drawing overlap with the power supply wiring 312 in a plan view. The local wirings 42a, 42b, 42c, and 42d are connected to the power supply wiring 312 through vias 332 formed on their back surfaces.

[0143] In the M0 wiring layer, wiring 313 extending in the X direction is formed. The wiring 313 is disposed on the opposite side in the Y direction from the side where the nanosheet is exposed from the gate wiring. The wiring 313 is connected to the local wirings 42a, 42b, 42c, and 42d through vias 334. The wiring 313 is also connected to the gate wirings 51a, 51b, and 51c through vias 335.

[0144] As in the first embodiment, the surface of the nanosheet on the lower side in the Y direction in the drawing is exposed from the gate wiring. The power supply wiring 311 is arranged on the side where the nanosheet is exposed from the gate wiring, and the power supply wiring 312 is arranged on the opposite side to the side where the nanosheet is exposed from the gate wiring.

[0145] In the capacitance cell according to this embodiment, the sources and drains of the nanosheet FETs P1, P2, and P3 are connected to a power supply wiring 311 that supplies VDD, and the gates of the nanosheet FETs P1, P2, and P3 are supplied with VSS. This creates capacitance between the gate and the source and drain of the nanosheet FETs P1, P2, and P3 via a gate oxide film. Furthermore, by using a fork sheet FET as the transistor that constitutes the CFET, the active area that constitutes the transistor can be made larger in the Y direction, thereby increasing the capacitance value.

[0146] Furthermore, in the capacitance cell according to this embodiment, VDD is supplied to the portions 22a, 22b, 22c, and 22d that serve as the source and drain of the P-type transistors P1, P2, and P3 from a power supply wiring 311 formed in the BM0 wiring layer via a via 331 that overlaps the power supply wiring 311 and the active region 2P in a planar view. Therefore, the path length from the power supply wiring 311 to the portions 22a, 22b, 22c, and 22d is short. This reduces the resistance value from the power supply wiring 311 to the nanosheets 21a, 21b, and 21c, thereby improving the high-speed response of the capacitance that is configured.

[0147] Capacitance is also formed between the local wirings 42a, 42b, 42c, and 42d at the upper portion and the portions 24a, 24b, 24c, and 24d in the active region 2N and the local wirings 41a, 41b, 41c, and 41d at the lower portion and the portions 22a, 22b, 22c, and 22d in the active region 2P, thereby increasing the capacitance value of the capacitance cell.

[0148] Furthermore, VSS is supplied to the gate wirings 51 a, 51 b, and 51 c from the M0 wiring 313 arranged on the opposite side to the side where the nanosheet is exposed from the gate wiring, thereby suppressing the resistance value from the power supply wiring 312 to the gates surrounding the nanosheets 21 a, 21 b, and 21 c.

[0149] 27(a) to 27(d) are plan views showing examples of the layout structure of inverter cells. The inverter cells are an example of standard cells with logic functions included in the semiconductor integrated circuit device according to this embodiment. FIGS. 27(a) and 27(b) show the structures of the lower and upper parts, respectively, of inverter cell 1, and FIGS. 27(c) and 27(d) show the structures of the lower and upper parts, respectively, of inverter cell 2. Inverter cell 1 and inverter cell 2 basically have the same layout structure, but differ in the size in the Y direction of the active regions that form the channel, source, and drain of the transistor.

[0150] As with the capacitance cell of Figure 26, in the BM0 wiring layer, power supply wiring 311 is arranged at the lower end of the inverter cell in the Y direction in the drawing, and power supply wiring 312 is arranged at the upper end of the inverter cell in the Y direction in the drawing.

[0151] 27(a) and 27(b), a part of the lower side of the active region 2P1 in the Y direction overlaps with the power supply wiring 311 in plan view. In the active region 2P1, the portion 26a serving as the source of the P-type nanosheet FET is connected to the power supply wiring 311 through a via 363 formed on its back surface.

[0152] A local wiring 44a contacts a portion 28a that serves as the source of the N-type nanosheet FET in the active region 2N1. The upper end of the local wiring 44a in the Y direction overlaps with the power supply wiring 312 in plan view. The local wiring 44a is connected to the power supply wiring 312 through a via 364 formed on its back surface.

[0153] The size of the active regions 2P1 and 2N1 in the Y direction is w1, and the distances from the active regions 2P1 and 2N1 to the cell frame in the Y direction are s1 and s2, which are the same as the capacitance cell shown in FIG.

[0154] The inverter cell 2 shown in Figures 27(c) and (d) has a layout structure similar to that of the inverter cell 1 shown in Figures 27(a) and (b). However, the size w2 in the Y direction of the active regions 2P2 and 2N2 is smaller than the size w1 in the Y direction of the active regions 2P1 and 2N1 shown in Figures 27(a) and (b) (w2<w1). That is, the size in the Y direction of the nanosheet 25A is smaller than that of the nanosheet 25. Furthermore, the size in the Y direction of the nanosheet 27A is smaller than that of the nanosheet 27. Therefore, the drive capability of the inverter cell 2 is smaller than that of the inverter cell 1.

[0155] 28A and 28B are plan views showing an example of the configuration of a cell row in this embodiment, with (a) being the bottom and (b) being the top. In Fig. 28, in the cell row, cell C1, which is the inverter cell 1 shown in Figs. 27A and 27B, cell C3, which is the capacity cell shown in Figs. 26A and 26B, and cell C2, which is the inverter cell 2 shown in Figs. 27C and 27D, are arranged side by side.

[0156] 28(a), the active region 2P1 of cell C1 and the active region 2P of cell C3 have the same size in the Y direction (w1) and are laid out over the same area in the Y direction. That is, the nanosheet 25 constituting the P-type nanosheet FET of cell C1 has the same size in the Y direction and is laid out over the same area in the Y direction as the nanosheets 21a, 21b, and 21c constituting the P-type nanosheet FET of cell C3.

[0157] 28(b), the active region 2N1 of cell C1 and the active region 2N of cell C3 have the same size in the Y direction (w1) and are laid out over the same area in the Y direction. That is, the nanosheet 27 constituting the N-type nanosheet FET of cell C1 has the same size in the Y direction and is laid out over the same area in the Y direction as the nanosheets 23a, 23b, and 23c constituting the N-type nanosheet FET of cell C3.

[0158] Additionally, the active region 2P1 of cell C1, the active region 2P of cell C3, and the active region 2P2 of cell C2 have the same lower edge position in the Y direction. The active region 2N1 of cell C1, the active region 2N of cell C3, and the active region 2N2 of cell C2 have the same lower edge position in the Y direction. That is, the positions of the surfaces of the nanosheets exposed from the gate wiring of cells C1, C3, and C2 are aligned in the Y direction.

[0159] Here, the fork-sheet FET is formed by providing an insulating structure between the opposing nanosheets exposed from the gate wiring. Therefore, as shown in the configuration of Figure 28, in a cell row in which cells are aligned in the X direction, the position of the nanosheet surface exposed from the gate wiring can be aligned in the Y direction, thereby making the shape of the structure, i.e., the size and layout area in the Y direction, uniform. This facilitates manufacturing.

[0160] Additionally, the active regions 2P and 2N of cell C3, which is a capacitance cell, have the same size (w1) in the Y direction as the active regions 2P1 and 2N1 of cell C1, which has the greater drive capability of cells C1 and C2, which are inverter cells 1 and 2. This allows the capacitance value of cell C3 to be increased.

[0161] Furthermore, when a capacitance cell is placed adjacent to inverter cells 1 and 2 having active areas of different sizes, the active area of ​​the adjacent capacitance cell exists relative to the active areas of inverter cells 1 and 2. This determines the distance between the active areas, thereby improving the accuracy of performance estimation.

[0162] (Modification 1) Figure 29 is a plan view showing an example of a layout structure of a capacitance cell according to Modification 1 of this embodiment, where (a) shows the lower part and (b) shows the upper part. Note that components common to Figure 26 and the like are given the same reference numerals, and detailed description may be omitted here. The circuit configuration of the capacitance cell shown in Figure 29 is the same as that shown in Figure 12 shown in Modification 3 of the first embodiment.

[0163] 29(a), in the active region 2P, of the portions 22a, 22b, 22c, and 22d that become the source or drain of the P-type nanosheet FET, the portions 22a, 22c, and 22d are connected to the power supply wiring 311 through vias 331A formed on the back surfaces thereof. The portion 22b is not connected to the power supply wiring 311.

[0164] The local wirings 41a, 41b, 41c, and 41d are in contact with the portions 22a, 22b, 22c, and 22d that become the source or drain of the P-type nanosheet FET in the active region 2P, respectively. The local wiring 41b extends longer toward the top of the drawing compared to FIG. 26(a).

[0165] As shown in FIG. 29B, in the M0 wiring layer, wirings 314 and 315 extending in the X direction are formed.

[0166] The local wirings 42a, 42b, 42c, and 42d are in contact with the portions 24a, 24b, 24c, and 24d that become the source or drain of the N-type nanosheet FET in the active region 2N, respectively. The local wiring 42b is shorter than that shown in FIG. 26(b) so as not to overlap with the M0 wiring 314 in plan view. The local wirings 42a, 42c, and 42d are connected to the power supply wiring 312 through vias 332A formed on their back surfaces.

[0167] The wiring 314 is connected to the local wiring 41b at the bottom through a via hole. The wiring 314 is also connected to the gate wirings 51b and 51c through a via hole. The wiring 315 is connected to the local wiring 42b through a via hole. The wiring 315 is also connected to the gate wiring 51a through a via hole.

[0168] According to this modification, the source and drain of the nanosheet FET N3 are connected to the power supply wiring 312 that supplies VSS, and the gate of the nanosheet FET N3 is supplied with VDD from the fixed value output unit 2. As a result, in the nanosheet FET N3, capacitance is formed between the gate and the source and drain via the gate oxide film. In addition, by using a fork sheet FET as the transistor that constitutes the CFET, the active area that constitutes the transistor can be formed large in the Y direction, thereby increasing the capacitance value.

[0169] In this modification, VDD is supplied to gate wiring 51c, which serves as the gate of transistors P3 and N3, from local wiring 41b, which is in contact with the drains of transistors P1 and P2 that constitute the fixed value output unit 2, via wiring 314 formed in the M0 wiring layer. Wiring 314 is formed on the opposite side in the Y direction from the side where the nanosheet is exposed from the gate wiring in a plan view. This makes it possible to suppress the resistance value from the fixed value output unit 2 to the gate surrounding the nanosheet of transistor N3, thereby improving the high-speed response of the capacitor that is formed.

[0170] (Modification 2) Figure 30 is a plan view showing an example of a layout structure of a capacitance cell according to Modification 2 of this embodiment, where (a) shows the lower part and (b) shows the upper part. Note that components common to Figure 26 etc. are given the same reference numerals, and detailed description may be omitted here. The circuit configuration of the capacitance cell shown in Figure 30 is the same as that shown in Figure 14 shown in Modification 4 of the first embodiment.

[0171] The layout structure shown in FIG. 30 is almost the same as the layout structure shown in FIG. 29. However, the connection relationship between the wirings 314 and 315 in the M0 wiring layer and other components is different. The wiring 314 is connected to the local wiring 41b through a via, and also to the gate wiring 51b through a via. The wiring 315 is connected to the local wiring 42b through a via, and also to the gate wirings 51a and 51c through vias. In other words, the connection destination of the gate wiring 51c, which serves as the gate of the transistors P3 and N3, has changed from the wiring 314 to the wiring 315. The other structures are the same as those in FIG. 29.

[0172] According to this modification, the source and drain of the nanosheet FET P3 are connected to the power supply wiring 311 that supplies VDD, and the gate of the nanosheet FET P3 is supplied with VSS from the fixed value output unit 2. As a result, in the nanosheet FET P3, capacitance is formed between the gate and the source and drain via the gate oxide film. In addition, by using a fork sheet FET as the transistor that constitutes the CFET, the active area that constitutes the transistor can be formed large in the Y direction, thereby increasing the capacitance value.

[0173] In the above-described embodiments, a P-type conductivity transistor is formed in the lower portion of the CFET, and an N-type conductivity transistor is formed in the upper portion. However, the conductivity types of the formed transistors may be reversed. That is, an N-type conductivity transistor may be formed in the lower portion, and a P-type conductivity transistor may be formed in the upper portion. In this case, the VDD and VSS supplied by the power supply wiring may be swapped in the above-described embodiments.

[0174] In the above-described embodiment, the nanosheet FET has three overlapping sheets in a plan view, and the cross-sectional shape of the sheets is rectangular, but the number and cross-sectional shape of the nanosheets of the nanosheet FET are not limited to this. In addition, the number and cross-sectional shape of the nanosheets may be different between the lower and upper parts of the CFET.

[0175] The present disclosure can provide a layout structure for a capacitance cell using a CFET and a fork-sheet FET, which is useful for improving the performance of a semiconductor chip, for example.

[0176] 2 Fixed value output section 2P, 2N Active area 2P1, 2N1, 2P2, 2N2 Active area 11, 12 Power supply wiring 21a, 21b, 21c Nanosheet 22a, 22b, 22c, 22d Portion to become source or drain 23a, 23b, 23c Nanosheet 24a, 24b, 24c, 24d Portion to become source or drain 25, 25A, 27, 27A Nanosheet 26a, 26b Portion to become source or drain 28a, 28b Portion to become source or drain 51a, 51b, 51c Gate wiring 52 Gate wiring 111, 112 Power supply wiring 211, 212 Power supply wiring 311, 312 Power supply wiring C1, C2, C3 Standard cell P1, P2, P3 P-type nanosheet FET N1, N2, N3 N-type nanosheet FET

Claims

1. A semiconductor integrated circuit device including a first standard cell that is a capacitance cell, the first standard cell comprising: a first nanosheet FET (Field Effect Transistor) of a first conductivity type that includes a first nanosheet extending in a first direction; a second nanosheet FET of a second conductivity type that is formed above the first nanosheet FET in the depth direction and includes a second nanosheet that extends in the first direction and overlaps the first nanosheet in a planar view; a first gate wiring that extends in a second direction perpendicular to the first direction, overlaps the first and second nanosheets in a planar view, and surrounds the first and second nanosheets in the second direction and the depth direction; a first power supply wiring that extends in the first direction and supplies a first power supply voltage; and a second power supply wiring that extends in the first direction and supplies a second power supply voltage, wherein the first and second nanosheets have first side surfaces that are one side in the second direction that are exposed from the first gate wiring; and the source and drain of the first nanosheet FET are connected to the first power supply wiring. the first gate wiring is supplied with the second power supply voltage.

2. A semiconductor integrated circuit device according to claim 1, wherein the first power supply wiring is formed in a first wiring layer on the back side of the first nanosheet FET, and the second power supply wiring is formed in a second wiring layer on the front side of the second nanosheet FET and is connected to the first gate wiring.

3. A semiconductor integrated circuit device according to claim 2, wherein the first and second power supply wirings are arranged in the center of the first standard cell in the second direction in a plan view.

4. A semiconductor integrated circuit device according to claim 2, wherein the first and second power supply wirings are arranged at the first end of the first standard cell in the second direction in a plan view.

5. A semiconductor integrated circuit device according to claim 2, wherein the first and second power supply wirings are arranged at an end of the first standard cell opposite the first side in the second direction in a plan view.

6. A semiconductor integrated circuit device according to claim 1, wherein the first power supply wiring is formed in a first wiring layer on the back side of the first nanosheet FET and is arranged at the end of the first side in the second direction of the first standard cell in a planar view; and the second power supply wiring is formed in the first wiring layer and is arranged at the end of the first standard cell opposite to the first side in the second direction in a planar view, and is connected to the first gate wiring.

7. A semiconductor integrated circuit device according to claim 1, wherein the first standard cell is connected to the first and second power supply wirings and includes a fixed value output section that supplies the second power supply voltage to the first gate wiring.

8. A semiconductor integrated circuit device according to claim 1, wherein the second power supply voltage is supplied to the source and drain of the second nanosheet FET.

9. A semiconductor integrated circuit device according to claim 1, comprising: a second standard cell having a logic function and arranged in the same cell row as the first standard cell; the second standard cell comprising: a third nanosheet FET of the first conductivity type, formed at the same height as the first nanosheet FET in the depth direction and including a third nanosheet extending in the first direction; a fourth nanosheet FET of the second conductivity type, formed at the same height as the second nanosheet FET in the depth direction and including a fourth nanosheet extending in the first direction and overlapping the third nanosheet in a planar view; and a second gate wiring extending in the second direction, overlapping the third and fourth nanosheets in a planar view, and surrounding the third and fourth nanosheets in the second direction and the depth direction, wherein the first side surfaces in the second direction of the third and fourth nanosheets are exposed from the second gate wiring, and the first side ends of the first nanosheet and the third nanosheet are positioned at the same position in the second direction.

10. A semiconductor integrated circuit device according to claim 9, further comprising: a third standard cell having a logic function and arranged in the same cell row as the first and second standard cells, wherein the third standard cell comprises: a fifth nanosheet FET of the first conductivity type formed at the same height as the first nanosheet FET in the depth direction and including a fifth nanosheet extending in the first direction; a sixth nanosheet FET of the second conductivity type formed at the same height as the second nanosheet FET in the depth direction and including a sixth nanosheet extending in the first direction and overlapping the fifth nanosheet in a planar view; and a third gate wiring extending in the second direction, overlapping the fifth and sixth nanosheets in a planar view, and surrounding the fifth and sixth nanosheets in the second direction and the depth direction, wherein the first side surfaces in the second direction of the fifth and sixth nanosheets are exposed from the third gate wiring, and the first side ends in the second direction of the first nanosheet, the third nanosheet, and the fifth nanosheet are positioned at the same position.

11. A semiconductor integrated circuit device according to claim 10, wherein the first nanosheet and the third nanosheet have the same size in the second direction and the same laying range in the second direction, and the fifth nanosheet has a size in the second direction that is smaller than that of the first nanosheet.

12. A semiconductor integrated circuit device including a first standard cell that is a capacitance cell, the first standard cell comprising: a first nanosheet FET (Field Effect Transistor) of a first conductivity type that includes a first nanosheet extending in a first direction; a second nanosheet FET of a second conductivity type that is formed above the first nanosheet FET in the depth direction and includes a second nanosheet that extends in the first direction and overlaps the first nanosheet in a planar view; a first gate wiring that extends in a second direction perpendicular to the first direction, overlaps the first and second nanosheets in a planar view, and surrounds the first and second nanosheets in the second direction and the depth direction; a first power supply wiring that extends in the first direction and supplies a first power supply voltage; and a second power supply wiring that extends in the first direction and supplies a second power supply voltage, wherein the first and second nanosheets have first side surfaces that are one side in the second direction that are exposed from the first gate wiring; and the second power supply wiring is connected to the source and drain of the second nanosheet FET. the first gate wiring is supplied with the first power supply voltage.

13. A semiconductor integrated circuit device according to claim 12, wherein the first power supply wiring is formed in a first wiring layer on the back side of the first nanosheet FET and is connected to the first gate wiring, and the second power supply wiring is formed in a second wiring layer on the front side of the second nanosheet FET.

14. A semiconductor integrated circuit device according to claim 13, wherein the first and second power supply wirings are arranged in the center of the first standard cell in the second direction in a plan view.

15. A semiconductor integrated circuit device according to claim 13, wherein the first and second power supply wirings are arranged at the first end of the first standard cell in the second direction in a plan view.

16. A semiconductor integrated circuit device according to claim 12, wherein the first standard cell is connected to the first and second power supply wirings and includes a fixed value output section that supplies the first power supply voltage to the first gate wiring.

17. A semiconductor integrated circuit device according to claim 12, wherein the second power supply voltage is supplied to the source and drain of the first nanosheet FET.

18. A semiconductor integrated circuit device according to claim 12, comprising a second standard cell arranged in the same cell row as the first standard cell and having a logic function, wherein the second standard cell comprises: a third nanosheet FET of the first conductivity type formed at the same height as the first nanosheet FET in the depth direction and including a third nanosheet extending in the first direction; a fourth nanosheet FET of the second conductivity type formed at the same height as the second nanosheet FET in the depth direction and including a fourth nanosheet extending in the first direction and overlapping the third nanosheet in a planar view; and a second gate wiring extending in the second direction, overlapping the third and fourth nanosheets in a planar view, and surrounding the third and fourth nanosheets in the second direction and the depth direction, wherein the first side surfaces in the second direction of the third and fourth nanosheets are exposed from the second gate wiring, and the first side ends of the second nanosheet and the fourth nanosheet are positioned at the same position in the second direction.

19. A semiconductor integrated circuit device according to claim 18, further comprising: a third standard cell having a logic function and arranged in the same cell row as the first and second standard cells, wherein the third standard cell comprises: a fifth nanosheet FET of the first conductivity type, formed at the same height as the first nanosheet FET in the depth direction and including a fifth nanosheet extending in the first direction; a sixth nanosheet FET of the second conductivity type, formed at the same height as the second nanosheet FET in the depth direction and including a sixth nanosheet extending in the first direction and overlapping the fifth nanosheet in a planar view; and a third gate wiring extending in the second direction, overlapping the fifth and sixth nanosheets in a planar view, and surrounding the fifth and sixth nanosheets in the second direction and the depth direction, wherein the first side surfaces in the second direction of the fifth and sixth nanosheets are exposed from the third gate wiring, and the first side ends of the second nanosheet, the fourth nanosheet, and the sixth nanosheet are positioned at the same position in the second direction.

20. A semiconductor integrated circuit device according to claim 19, wherein the second nanosheet and the fourth nanosheet have the same size in the second direction and the same laying range in the second direction, and the sixth nanosheet has a size in the second direction that is smaller than that of the first nanosheet.

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