Preparation method for semiconductor device, semiconductor device and electronic apparatus

Abstract

Provided in the present disclosure are a preparation method for a semiconductor device, the semiconductor device and an electronic apparatus. The preparation method for a semiconductor device comprises: forming an active structure on a substrate; forming a first semiconductor structure; bonding the first semiconductor structure and a first carrier wafer and flipping same over; removing the substrate to expose a second active structure; forming a second semiconductor structure; bonding the second semiconductor structure and a second carrier wafer and flipping same over; removing the first carrier wafer to expose the first semiconductor structure; forming a first gate structure in the first semiconductor structure; forming first source-drain metal on a first source-drain structure; forming a first metal interconnect structure on a first transistor; bonding the first metal interconnect structure and a third carrier wafer and flipping same over; removing the second carrier wafer to expose the second semiconductor structure; and forming a second metal interconnect structure.

Description

Method for manufacturing semiconductor structure, semiconductor structure and semiconductor device

[0001] Cross-reference to related applications

[0002] This application is based on and claims priority to Chinese Patent Application No. 202410434413.4, filed on April 11, 2024, the entire contents of which is incorporated herein by reference. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of semiconductor technology, and particularly relates to a preparation method of semiconductor device, semiconductor device and electronic equipment. BACKGROUND

[0004] At present, it is a hot issue in the industry to continue to promote the miniaturization of transistors as Moore's law continues to deepen. Stacked transistors integrate two or more layers of transistors in the vertical space to further improve the transistor integration density, and become one of the important technologies to continue the miniaturization of integrated circuits.

[0005] In the preparation process of the transistor, the preparation process temperature of the source epitaxial structure and the drain epitaxial structure is relatively high, while the process temperature that the metal gate and the metal interconnection line can withstand is relatively low. For stacked transistors, two layers of transistors and their interconnection lines need to be prepared, and the thermal process of processing the upper device may affect the lower device and the interconnection line.

[0006] SUMMARY

[0007] The present disclosure provides a preparation method of semiconductor device, semiconductor device and electronic equipment.

[0008] The first aspect of the present disclosure provides a method for manufacturing a semiconductor device, comprising: forming an active structure on a substrate; wherein the active structure comprises a first active structure and a second active structure stacked in a first direction, the first direction being perpendicular to the substrate; forming a first semiconductor structure based on the first active structure, the first semiconductor structure comprising a first dummy gate structure and a first source-drain structure; bonding the first semiconductor structure with a first carrier wafer and flipping; removing the substrate and exposing the second active structure; forming a second semiconductor structure based on the second active structure, the second semiconductor structure comprising a second gate structure and a second source-drain structure; bonding the second semiconductor structure with a second carrier wafer and flipping; removing the first carrier wafer to expose the first semiconductor structure; removing a first dummy gate structure filling metal in the first semiconductor structure to form a first gate structure; forming a first source-drain metal on the first source-drain structure to form a first transistor; forming a first metal interconnection structure on the first transistor through a back-end-of-line process; bonding the first metal interconnection structure with a third carrier wafer and flipping; removing the second carrier wafer to expose the second semiconductor structure; forming a second metal interconnection structure based on the second semiconductor structure.

[0009] The second aspect of the present disclosure provides a semiconductor device, which is manufactured by the method of the first aspect or any possible implementation of the first aspect; the semiconductor device comprises: a first transistor; and a second transistor, the second transistor being disposed opposite to the first transistor; wherein the first active structure of the first transistor and the second active structure of the second transistor are formed by the same process, and the first transistor and the second transistor are self-aligned in a vertical direction.

[0010] The third aspect of the present disclosure provides an electronic device. The electronic device comprises: a circuit board; and the semiconductor device of the second aspect, the semiconductor device being disposed on the circuit board.

[0011] Compared with the prior art, the present disclosure has the following beneficial effects:

[0012] The method for manufacturing a semiconductor device provided by the embodiments of the present disclosure forms the first gate structure and the first metal interconnection structure of the first transistor after the second source-drain structure of the second transistor through multiple wafer bonding and flipping, thereby avoiding the influence of the high process temperature of the second transistor when forming the second source-drain structure on the first gate structure and the first metal interconnection structure of the first transistor, and improving the thermal budget of the semiconductor device.

[0013] It should be understood that the general description above and the detailed description below are only exemplary and explanatory, but not limiting the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0014] The accompanying drawings, which are incorporated herein and constitute part of this specification, illustrate exemplary embodiments consistent with the present disclosure and, together with the description, further serve to explain the principles of embodiments of the present disclosure.

[0015] FIG. 1 is a flow diagram of a method for fabricating a semiconductor device according to embodiments of the present disclosure.

[0016] FIG. 2 is a top view of a semiconductor device according to embodiments of the present disclosure.

[0017] FIGS. 3-17 are schematic diagrams of a fabrication process of a semiconductor device according to embodiments of the present disclosure.

[0018] FIGS. 18-24 are schematic diagrams of a fabrication process of a semiconductor device according to embodiments of the present disclosure.

[0019] Legend of Signs

[0020] semiconductor device 10; first transistor 11; second transistor 12; first dummy gate sidewall 111; first source / drain structure 112; first interlayer dielectric structure 113; first gate structure 114; first source / drain metal 115; first metal interconnect structure 116; second dummy gate sidewall 121; second source / drain structure 122; second interlayer dielectric structure 123; second gate structure 124; second source / drain metal 125; second metal interconnect structure 126; substrate 20; first active structure 21; second active structure 22; stack structure 23; first dummy gate structure 24; shallow trench isolation structure 25; first insulating layer 26; first handle wafer 27; second insulating layer 28; second handle wafer 29; third insulating layer 30; third handle wafer 31; first metal contact hole 32; second metal contact hole 33; first metal interconnect layer 34; second metal interconnect layer 35; first contact metal layer 36; second contact metal layer 37. DETAILED DESCRIPTION

[0021] The exemplary embodiments will be described in detail herein with reference to the attached drawings figures. The following description is made with reference to the accompanying drawings, in which like reference numerals refer to like elements throughout the several figures. The following description is made with reference to the accompanying drawings, in which like reference numerals refer to like elements throughout the several figures. The embodiments described in the following examples do not represent all of the embodiments consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with aspects of the present disclosure.

[0022] The terms used in the embodiments of the present disclosure are for the purpose of describing specific embodiments only and are not intended to limit the embodiments of the present disclosure. The singular forms "a," "the," and "the" used in the present disclosure are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0023] As Moore's Law continues to advance, continuing to scale transistors is a hot topic in the industry. Stacked transistors, through three-dimensional stacking, can integrate two or more layers of transistors in a vertical space, helping to further increase transistor integration density and improve circuit performance. It is considered one of the key technologies for continuing the scaling of integrated circuits. There are at least two manufacturing processes for stacked transistors: a monolithic approach and a sequential approach.

[0024] The characteristics of the monolithic solution include: (1) Instead of using wafer bonding technology, N-type Metal-Oxide-Semiconductor (NMOS) transistors and P-type Metal-Oxide-Semiconductor (PMOS) transistors are made on the same substrate and the two types of transistors are stacked vertically. This means that transistors on the same layer must be of the same type, i.e., NMOS or PMOS; (2) Transistors on the same layer must be strictly in the same plane space, with no alignment deviation. The advantage of the monolithic solution is that it has a better integration density, while the disadvantages of the monolithic solution include the following: (1) The process is complex and requires a lot of process technology development and optimization; (2) The polarity of each layer of transistors is fixed, and two layers of transistors must be relied upon to form a basic complementary metal oxide semiconductor circuit, resulting in poor design flexibility.

[0025] The characteristics of the sequential approach include: based on wafer bonding and layer-by-layer processing, vertical stacking of upper and lower transistors is achieved. Thanks to wafer bonding, the device structure, channel crystal orientation, and even channel materials used by the upper and lower transistors can be optimized accordingly to obtain better and more matched device performance. However, the thermal process during the processing of the upper transistors may affect the lower transistors and interconnects, and the thermal budget of the entire processing process must be strictly controlled. At the same time, the temperature that the back-end interconnects can withstand is also limited, which will also limit the thermal budget. Therefore, the sequential approach currently has the following technical challenges: (1) Preparation of a high-quality upper transistor active layer; (2) Thinning and defect control of the upper transistor bonding wafer; (3) Alignment errors between the upper and lower transistors, which requires extremely high lithography accuracy.

[0026] The common technical difficulties faced by the above two solutions include: (1) the thermal stability of the lower layer device when manufacturing the upper layer device; (2) the performance of the upper layer device under a low thermal budget; and (3) the metal interconnection between the transistors in the upper and lower layers.

[0027] During transistor fabrication, the source and drain epitaxial structures require higher process temperatures, while the metal gates and metal interconnects can withstand lower temperatures. Stacked transistors, on the other hand, require two layers of transistors and their interconnects. The thermal process during fabrication of the upper layer can affect the lower layer devices and interconnects.

[0028] In order to solve the above technical problems, an embodiment of the present disclosure provides a method for manufacturing a semiconductor device to achieve self-alignment of gate structures between upper and lower transistors.

[0029] In some embodiments, the present disclosure provides a method for fabricating a semiconductor device. This method can be used to fabricate a stacked transistor. FIG1 is a schematic flow diagram of a method for fabricating a semiconductor device according to an embodiment of the present disclosure. Referring to FIG1 , the method can include steps S101 to S113.

[0030] Step S101: forming an active structure on a substrate; wherein the active structure includes a first active structure and a second active structure stacked in a first direction, and the first direction is perpendicular to the substrate;

[0031] Step S102: forming a first semiconductor structure based on the first active structure, where the first semiconductor structure includes a first dummy gate structure and a first source-drain structure;

[0032] Step S103: bonding the first semiconductor structure to the first carrier wafer and flipping the wafer over;

[0033] Step S104: removing the substrate and exposing the second active structure;

[0034] Step S105: forming a second semiconductor structure based on the second active structure, where the second semiconductor structure includes a second gate structure and a second source-drain structure;

[0035] Step S106: bonding the second semiconductor structure to the second carrier wafer and flipping the wafer over;

[0036] Step S107: removing the first carrier wafer to expose the first semiconductor structure;

[0037] Step S108: removing the first dummy gate structure filling metal in the first semiconductor structure to form a first gate structure;

[0038] Step S109: forming a first source-drain metal on the first source-drain structure to form a first transistor;

[0039] Step S110: forming a first metal interconnection structure on the first transistor through a post-process;

[0040] Step S111: bonding the first metal interconnection structure with a third carrier wafer and flipping over;

[0041] Step S112: removing the second carrier wafer to expose a second semiconductor structure;

[0042] Step S113: forming a second metal interconnection structure based on the second semiconductor structure.

[0043] It should be noted that the steps shown in FIG. 1 are not exclusive, and other steps can be performed before, after or between any of the steps shown; the steps shown in FIG. 1 can be adjusted in order according to actual needs.

[0044] FIG. 2 is a top view of a semiconductor device according to an embodiment of the present disclosure, and has A-A' cross section, B-B' cross section and C-C' cross section in FIG. 2. Among them, the A-A' cross section is a cross section cut along the gate structure of the semiconductor device; the B-B' cross section is a cross section cut along the source-drain structure of the semiconductor device; the C-C' cross section is a cross section cut along the gate structure of the semiconductor device. FIGS. 3-17 are schematic diagrams of a preparation process of a semiconductor device according to an embodiment of the present disclosure, wherein (a) in FIGS. 3-17 is a cross-sectional view along the direction of the dashed line A-A' in FIG. 2; (b) in FIGS. 3-17 is a cross-sectional view along the direction of the dashed line B-B' in FIG. 2; (c) in FIGS. 3-17 is a cross-sectional view along the direction of the dashed line C-C' in FIG. 2.

[0045] The preparation method of the semiconductor device 10 and the semiconductor device 10 prepared according to an embodiment of the present disclosure will be described below in conjunction with FIGS. 1-17.

[0046] In step S101, an active structure is formed on a substrate 20.

[0047] In an embodiment, the active structure includes a first active structure 21 and a second active structure 22 stacked in a first direction. Here, the first direction is a direction perpendicular to the substrate 20.

[0048] In some embodiments, the first active structure 21 and the second active structure 22 are two parts of an active structure, wherein the second active structure 22 is closer to the substrate 20 than the first active structure 21. Since the first active structure 21 and the second active structure 22 are formed by etching the substrate 20 once, the transistor formed based on the first active structure 21 and the second active structure 22 can achieve self-alignment of the active structure in the first direction, thereby achieving self-alignment of the first transistor 11 and the second transistor 12.

[0049] In some embodiments, in step S101, a semiconductor material layer may be grown on a substrate 20. By etching the semiconductor material layer, one or more active structures are formed on the substrate 20. The active structure may be divided into two parts, the upper part (i.e., the first active structure 21) serving as the active structure of the first transistor 11, and the lower part (i.e., the second active structure 22) serving as the active structure of the second transistor 12.

[0050] In some embodiments, in step S101, a sacrificial layer and a silicon layer may be sequentially grown on substrate 20. By etching the sacrificial layer and the silicon layer, an active structure is formed on substrate 20. For example, a sacrificial layer (e.g., a silicon germanium (SiGe) layer) is epitaxially grown on the bottom silicon layer (i.e., substrate 20), and a top silicon layer is epitaxially grown on top of the sacrificial layer. The sacrificial layer is used to protect the main structure of the top silicon layer, reduce external impact and vibration, improve the durability and reliability of the top silicon layer, and extend its service life.

[0051] In one embodiment, the thickness of the sacrificial layer is approximately 10nm-20nm, and the thickness of the top silicon layer is greater than 100nm. It should be noted that the thickness of the sacrificial layer and the top silicon layer can be selected based on actual use requirements. For example, in a fin field-effect transistor, the top silicon layer has a relatively large thickness to facilitate etching of the fin structure; while in a gate-all-around transistor, the sacrificial layer and the silicon layer are stacked, and the sacrificial layer is a semiconductor material layer disposed in the stack. In this case, the thickness of the sacrificial layer and the silicon layer are both selected based on actual use requirements; this is not limited in the present embodiment.

[0052] In one embodiment, anisotropic etching can be used to form an active structure extending in the same direction in the active area (see the fin-shaped structure in Figure 4). Of course, in other types of transistors, the fin-shaped structure can also be replaced by parallel nanosheets, block planar structures, etc. In the case where the active structure is a fin structure, the first transistor 11 and the second transistor 12 can be fin field effect transistors (FinFET); in the case where the active structure is a plurality of parallel nanosheets, the first transistor 11 and the second transistor 12 can be gate-all-around field effect transistors (GAAFET); in the case where the active structure is a block planar structure, the first transistor 11 and the second transistor 12 are planar transistors.

[0053] In some embodiments, the first transistor 11 and the second transistor 12 may be different types of transistors. For example, one transistor is a FinFET and the other is a gate-all-around transistor; or one transistor is a FinFET and the other is a planar transistor; or one transistor is a gate-all-around transistor and the other is a planar transistor.

[0054] In one embodiment, first, a stacked structure 23 is epitaxially grown on a substrate 20 , as shown in FIG3 ; then, the stacked structure 23 is etched to form an active structure, as shown in FIG4 . The active structure includes a first active structure 21 and a second active structure 22 .

[0055] In one embodiment, the substrate 20 may be a silicon (Si) substrate or a silicon-on-insulator (SOI) substrate. Of course, the substrate 20 may also be made of other semiconductor materials, which is not limited in the present embodiment. It should be noted that the etching process mentioned in the present embodiment may include any of the following: dry etching, wet etching, reactive ion etching, and chemical oxide removal process, which is not limited in the present embodiment.

[0056] In some embodiments, after the active structure is formed in S101 , ion implantation may be performed at the connection between the first active structure 21 and the second active structure 22 to form an electrical isolation layer for electrically isolating the first active structure 21 and the second active structure 22 .

[0057] Exemplarily, the ions for ion implantation can include P-type ions, N-type ions, oxygen ions, etc. The P-type ions can be one of boron (B), gallium (Ga), and aluminum (Al). The N-type ions can be one of phosphorus (P), arsenic (As), and antimony (Sb).

[0058] In step S102, a first semiconductor structure is formed based on the first active structure 21.

[0059] In an embodiment, the first semiconductor structure can include a first dummy gate structure 24 and a first source-drain structure 112.

[0060] In some embodiments, in step S102, a dummy gate material can be deposited on the first active structure 21 to form the first dummy gate structure 24, as shown in FIG. 7; then, a sidewall is deposited on the periphery of the first dummy gate structure 24, and the first source-drain structure 112 is epitaxially grown on the first active structure 21 and filled with an interlayer dielectric material to form a first interlayer dielectric structure 113, as shown in FIG. 8.

[0061] It should be noted that the dummy gate material can define the shape, structure, and size of the subsequent gate structure. Meanwhile, compared with a metal gate, the dummy gate structure formed by the dummy gate material is resistant to high temperature and is conducive to the formation of the source-drain structure.

[0062] It should be noted that the dummy gate structure needs to be replaced by a metal gate in subsequent processes to meet the electrical performance requirements of the device (i.e., metal replacement gate process).

[0063] In an example, the dummy gate material can be polysilicon or amorphous silicon.

[0064] In an example, the interlayer dielectric material can be silicon oxide, silicon nitride, etc.

[0065] In some embodiments, after the formation of the active structure, a region between adjacent active structures is formed with a trench. The trench is filled with an oxide to form a shallow trench isolation (STI) structure 25, as shown in FIG. 5. Next, after the formation of the shallow trench isolation structure 25, the shallow trench isolation structure 25 is etched until the first active structure 21 is exposed and flush with the connection between the first active structure 21 and the second active structure 22, i.e., the upper half of the shallow trench isolation structure 25 is removed, as shown in FIG. 6. Then, semiconductor material (such as polysilicon) is deposited in the gate region above the etched shallow trench isolation structure 25, and thus the first dummy gate structure 24 is formed, as shown in FIG. 7. In an example, the first dummy gate structure 24 covers the first active structure 21.

[0066] In some embodiments, after the first dummy gate structure 24 is formed, first dummy gate sidewalls 111 can be formed on both sides of the first dummy gate structure 24, and the first dummy gate sidewalls 111 can be used as a mask to form source and drain structures (i.e., first source and drain structures 112).

[0067] In some embodiments, the oxide used to form the shallow trench isolation structure 25 can be silicon dioxide (SiO2), silicon carbon oxide (SiCO), or the like. In some embodiments, the solvent used to etch the shallow trench isolation structure 25 can be a DHF (including hydrogen fluoride (HF), hydrogen peroxide (H2O2), and water (H2O)) solution or a buffered oxide etch (BOE) solution. The solvent used in the etching process in the embodiments of the present disclosure can be selected according to actual conditions, and is not limited to the above-mentioned DHF solution or BOE solution.

[0068] In some embodiments, to facilitate subsequent processing, after the first dummy gate structure 24 is formed, the shallow trench isolation structure 25 can be subjected to a polishing process or a chemical-mechanical planarization (CMP) process, so that when the shallow trench isolation structure 25 is etched later, the etching depths of the shallow trench isolation structures 25 in different regions are the same, thereby making the top heights of the exposed active structures the same.

[0069] In some embodiments, after the first dummy gate structure 24 is completed, the first source and drain structures 112 can be formed on both sides of the first dummy gate structure 24 based on the first active structure 21. Here, the first source and drain structures 112 can be understood as the source and / or drain structures of the first transistor 11. Next, an interlayer dielectric material (such as silicon dioxide) can be deposited on the first source and drain structures 112 to form a first interlayer dielectric structure 113, as shown in FIG. 8. At this point, the preparation of the first semiconductor structure is completed.

[0070] In the embodiments of the present disclosure, since only the first dummy gate structure 24 and the first source and drain structures 112 are prepared in the step S102 of preparing the first semiconductor structure, and the gate dielectric, the metal gate, the metal interconnection structure, and the like are not prepared, when the second source and drain structures 122 of the second transistor 12 are prepared, the gate dielectric, the metal gate, the metal interconnection structure, and the like in the first transistor 11 are not affected, thereby effectively improving the thermal budget of the semiconductor device.

[0071] In step S103, the first semiconductor structure is bonded to the first carrier wafer 27 and flipped.

[0072] In some embodiments, after the first semiconductor structure is formed, an insulating material (e.g., silicon oxide) is deposited on top of the first semiconductor structure to form a first insulating layer 26 in step S103. The formed first insulating layer 26 can be planarized by a CMP process. Then, the first insulating layer 26 after planarization can be bonded to a first carrier wafer 27. The substrate 20 can then be flipped so that the first semiconductor structure is placed downward and the substrate 20 is placed upward.

[0073] In step S104, the substrate 20 is removed and the second active structure 22 is exposed.

[0074] In some embodiments, after the substrate 20 is flipped, wafer thinning can be performed to remove the substrate 20 and expose the surface of the second active structure 22, as shown in FIG. 9. Next, the lower half of the shallow trench isolation structure 25 is removed by etching to expose the second active structure 22 covered by the shallow trench isolation structure 25, as shown in FIG. 10.

[0075] In some embodiments, when the lower half of the shallow trench isolation structure 25 is removed, a portion of the shallow trench isolation structure 25 can be retained as an isolation layer to isolate the first transistor 11 and the second transistor 12.

[0076] In step S105, a second semiconductor structure is formed based on the second active structure 22.

[0077] In an embodiment, the second semiconductor structure includes a second gate structure 124 and a second source-drain structure 122.

[0078] In some embodiments, after the second active structure 22 is exposed, a front-end process can be performed first. First, a semiconductor material (e.g., polysilicon) is deposited in the gate region above the etched shallow trench isolation structure 25 to form a second dummy gate structure. Here, the second dummy gate structure covers the second active structure 22. Next, a source structure and a drain structure (i.e., the second source-drain structure 122) are formed based on the second active structure 22 on both sides of the second dummy gate structure. Here, the second source-drain structure 122 can be understood as the source structure and / or the drain structure of the second transistor 12. Next, an interlayer dielectric material (e.g., silicon dioxide) is deposited on the second source-drain structure 122 and the retained shallow trench isolation structure 25 to form a second interlayer dielectric structure 123. Thus, the preparation of the second semiconductor structure is completed.

[0079] In an embodiment, after the second semiconductor structure is formed, the second dummy gate structure can be removed by an etching process, and a metal material is deposited at the etched second dummy gate structure to form a second gate structure 124, i.e., the gate structure of the second transistor 12, as shown in FIG. 11.

[0080] It should be noted that when the gate structure of the second transistor 12 is prepared, the gate dielectric, the metal gate, and the metal interconnection structure of the first transistor 11 have not been formed, and therefore the heat budget is basically not limited.

[0081] In some embodiments, the second gate structure 124 can be formed by a metal replacement gate process, and the second gate structure 124 can be a high-k metal gate (HKMG) at this time. Here, k refers to the dielectric constant. Then, after the second dummy gate structure is removed, a gate dielectric layer can be deposited on the surface of the second active structure 22 to isolate the second active structure 22 from the second gate structure 124. In an example, the gate dielectric layer is formed of a high-k material.

[0082] In step S106, the second semiconductor structure is bonded to the second carrier wafer 29 and flipped.

[0083] In some embodiments, in step S106, after the second semiconductor structure is formed, an insulating material (such as silicon oxide) is deposited on the top of the second semiconductor structure to form a second insulating layer 28, and the second insulating layer 28 is bonded to the second carrier wafer 29. Then, the second carrier wafer 29 can be flipped so that the second semiconductor structure is placed downward and the first carrier wafer 27 is placed upward, as shown in FIG. 12.

[0084] It can be understood that when the second semiconductor structure includes the second gate structure 124 and the second source-drain structure 122, depositing an insulating material on the top of the second semiconductor structure can include: depositing an insulating material on the second gate structure 124 and the second interlayer dielectric structure 123 to form the second insulating layer 28.

[0085] In step S107, the first carrier wafer 27 is removed to expose the first semiconductor structure.

[0086] In some embodiments, after the first carrier wafer 27 is flipped, wafer thinning can be performed by a CMP process until the first dummy gate structure 24 is exposed, i.e., the first insulating layer 26 and the first carrier wafer 27 are removed, as shown in FIG. 13.

[0087] In step S108, in the first semiconductor structure, the first dummy gate structure 24 filling metal is removed to form a first gate structure 114.

[0088] In some embodiments, in step S108, the first dummy gate structure 24 can be removed by a counting process. Then, a metal material is filled at the removed first dummy gate structure 24 to form the first gate structure 114, as shown in FIG. 14.

[0089] In some embodiments, the first gate structure 114 can be formed by a metal replacement gate process, and the first gate structure 114 can be an HKMG. Then, after the first dummy gate structure 24 is removed, a gate dielectric layer can be deposited on the surface of the first active structure 21 to isolate the first active structure 21 from the first gate structure 114. In an example, the gate dielectric layer is formed of a high-K material.

[0090] In some embodiments, a shallow trench isolation structure 25 can not be provided between the first gate structure 114 and the second gate structure 124, as needed. In an example, before the first gate structure 114 is formed, the shallow trench isolation structure 25 is etched until the second gate structure 124 is exposed, forming a gate direct connection groove. A metal is deposited on the second gate structure to form the first gate structure 114. In this way, the first transistor 11 and the second transistor 12 can be interconnected by the contact of the gate structures of the two transistors, without the need to introduce an interconnection line.

[0091] In the embodiments of the present disclosure, the metal material used to form the first gate structure 114 and the metal material used to form the second gate structure 124 can be the same or different, as needed, and the embodiments of the present disclosure are not limited in this regard.

[0092] In the embodiments of the present disclosure, the metal material can be one of the following: tantalum nitride (TaN), titanium nitride (TiN), aluminum nitride (AlN), titanium aluminum carbide (TiAlC), titanium aluminum nitride (TiAlN), and can be selected as needed and is not limited to the metal materials listed above.

[0093] In step S109, a first source / drain metal 115 is formed on the first source / drain structure 112 to form the first transistor 11.

[0094] In some embodiments, the first interlayer dielectric structure 113 located above the first source / drain structure 112 is etched until the first source / drain structure 112 is exposed. Then, a metal material is deposited at the etched location to form the first source / drain metal 115. At this point, the front-end process of the first transistor 11 is completed, and the first transistor 11 is obtained, as shown in FIG. 14.

[0095] In step S110, a first metal interconnection structure 116 is formed on the first transistor 11.

[0096] In some embodiments, still referring to FIG. 14, an interlayer dielectric material (such as silicon dioxide) is deposited on the first source / drain metal 115 by a middle-end process to form an interlayer dielectric layer, and a first metal contact hole 32 of the first source / drain structure 112 is formed on the interlayer dielectric layer. Then, a first metal interconnection layer 34 is formed on the interlayer dielectric layer by a back-end process. At this point, the first metal interconnection structure 116 is formed.

[0097] In an embodiment, the interlayer dielectric layer in which the first metal contact hole 32 is formed constitutes the first contact metal layer 36.

[0098] In step S111, the first metal interconnection structure 116 is bonded with the third carrier wafer 31 and flipped over.

[0099] In some embodiments, after the first metal interconnection structure 116 is formed, an insulating material (such as silicon oxide) is deposited on the top of the first metal interconnection structure 116 to form the third insulating layer 30 in step S111; the formed third insulating layer 30 can be planarized by a CMP process; then, the planarized third insulating layer 30 can be bonded with the third carrier wafer 31. Then, the third carrier wafer 31 can be flipped over so that the first transistor 11 is placed downward again and the second carrier wafer 29 is placed upward, as shown in FIG. 15.

[0100] In step S112, the second carrier wafer 29 is removed to expose the second semiconductor structure.

[0101] In some embodiments, after the second carrier wafer 29 is flipped over, wafer thinning can be performed by a CMP process until the second gate structure 124 is exposed, i.e., the second insulating layer 28 and the second carrier wafer 29 are removed, as shown in FIG. 16.

[0102] It can be understood that when the second semiconductor structure includes the second gate structure 124 and the second source-drain structure 122, the second carrier wafer 29 can be removed to expose the second gate structure 124 and the second interlayer dielectric structure 123.

[0103] In step S113, based on the second semiconductor structure, the second metal interconnection structure 126 is formed.

[0104] In some embodiments, referring to FIG. 17, the second interlayer dielectric structure 123 above the second source-drain structure 122 is etched until the second source-drain structure 122 is exposed. Then, a metal material is deposited at the etched position to form the second source-drain metal 125. At this point, the front-end process of the second transistor 12 is completed. Then, by using a middle-end process, an interlayer dielectric material (such as silicon dioxide) is deposited on the second source-drain metal 125 to form an interlayer dielectric layer, and a second metal contact hole 33 of the second source-drain structure 122 is made on the interlayer dielectric layer. Then, by using a back-end process, a second metal interconnection layer 35 is formed on the interlayer dielectric layer. At this point, the second metal interconnection structure 126 is formed.

[0105] It should be noted that the interlayer dielectric layer in which the second metal contact hole 33 is formed constitutes a second contact metal layer 37, and the second contact metal layer 37 is formed on the second gate structure 124 and the second source-drain metal 125. A second metal interconnection layer 35 can be formed on the second contact metal layer 37, so as to obtain a second metal interconnection structure 126.

[0106] It can be understood that the metal material forming the second metal contact hole 33 can be a high-temperature-resistant material. In an example, the metal material forming the second metal contact hole 33 can be tungsten (W), cobalt (Co), etc.

[0107] So far, the preparation of the semiconductor device in the embodiment of the present disclosure is completed.

[0108] In the embodiment of the present disclosure, by multiple times of wafer bonding and flipping, the first gate structure and the first metal interconnection structure of the first transistor are formed after the second source-drain structure of the second transistor, which avoids the influence of the high process temperature of the second transistor on the first gate structure and the first metal interconnection structure of the first transistor when the second source-drain structure is formed, and improves the thermal budget of the semiconductor device.

[0109] FIGS. 18-24 are schematic diagrams of a preparation process of a semiconductor device according to an embodiment of the present disclosure. In FIGS. 18-24, (a) is a cross-sectional view along the direction of the dashed line A-A' in FIG. 2; (b) is a cross-sectional view along the direction of the dashed line B-B' in FIG. 2; and (c) is a cross-sectional view along the direction of the dashed line C-C' in FIG. 2.

[0110] The preparation method of the semiconductor device 10 and the semiconductor device 10 prepared by the method provided in the embodiment of the present disclosure will be described below in conjunction with FIGS. 1-2 and 18-24.

[0111] In some embodiments, in the above preparation process, in order to simplify the process flow, under the premise of improving the thermal budget of the stacked transistor preparation process, step S201 can also be performed in the process of preparing the second semiconductor structure by step S105. In this case, the second semiconductor structure further includes the second source-drain metal 125 and the second contact metal layer 37. The second source-drain metal 125 is formed by depositing metal on the second source-drain structure 122, and the second contact metal layer 37 is formed on the second gate structure 124 and the second source-drain metal 125.

[0112] In step S201, based on the second active structure 22, the second source-drain metal 125 and the second contact metal layer 37 are formed.

[0113] In some embodiments, referring to FIG. 10, after steps S101-S104, the second active structure 22 is exposed. Then, referring to FIG. 11, a second source-drain structure 122, a second interlayer dielectric structure 123 and a second gate structure 124 are formed by step S105. Then, a second source-drain metal 125 and a second contact metal layer 37 are formed by step S201.

[0114] In an embodiment, the second interlayer dielectric structure 123 above the second source-drain structure 122 is etched until the second source-drain structure 122 is exposed. Then, a metal material is deposited at the etched position to form the second source-drain metal 125. An interlayer dielectric layer is formed on the second interlayer dielectric structure 123 and the second source-drain metal 125, and a second metal contact hole 33 of the second source-drain structure 122 is formed on the interlayer dielectric layer, as shown in FIG. 18.

[0115] It should be noted that the interlayer dielectric layer with the second metal contact hole 33 forms the second contact metal layer 37, which is formed on the second gate structure 124 and the second source-drain metal 125. Here, the metal material forming the second metal contact hole 33 can be a high-temperature-resistant metal material such as tungsten, cobalt, etc.

[0116] It should be noted that the process temperature during steps S108 and S109 is higher than the process temperature for forming the second contact metal layer 37, so the second contact metal layer 37 uses a high-temperature-resistant metal material, which can avoid affecting the second contact metal layer 37 when steps S108 and S109 are performed.

[0117] It should be noted that the preparation of the second contact metal layer 37 helps the photolithography alignment of the front and back transistors.

[0118] In some embodiments, after step S201 is performed, the front-end and middle-end processes of the second transistor 12 are completed. Next, step S106 is performed, referring to FIG. 19, the second semiconductor structure is bonded to the second carrier wafer 29, including bonding the second contact metal layer 37 to the second carrier wafer 29.

[0119] It can be understood that after the second contact metal layer 37 is formed, an insulating material (such as silicon oxide) can be deposited on top of the second contact metal layer 37 to form a second insulating layer 28, and the second insulating layer 28 is bonded to the second carrier wafer 29 to obtain the structure shown in FIG. 19.

[0120] In some embodiments, after step S106 is performed, steps S107-S111 can be performed.

[0121] Referring to FIGS. 20-22, after the second semiconductor structure (including the second source / drain metal 125 and the second contact metal layer 37) is formed, the steps in one or more embodiments described above can be used to complete the second stripping and re-fabricate the first transistor 11.

[0122] In one embodiment, the second wafer carrier 29 can be flipped first so that the second semiconductor structure is placed downward and the first semiconductor structure and the first wafer carrier 27 are placed upward. Then, wafer thinning can be performed using a CMP process until the first dummy gate structure 24 is exposed, as shown in FIG. 20. Then, a first gate structure 114 can be formed using a replacement metal gate (RMG) process, a first source / drain metal 115 can be formed above the first source / drain structure 112 using a process of the first interlayer dielectric structure 113, and a first metal interconnection structure 116 can be formed using a back-end-of-line process, as shown in FIG. 21. Then, the first metal interconnection structure 116 can be bonded with the third wafer carrier 31 and flipped so that the third wafer carrier 31 is placed downward and the second wafer carrier 29 is placed upward, as shown in FIG. 22.

[0123] In some embodiments, after step S111 is performed, step S112 can be performed to remove the second wafer carrier 29 to expose the second semiconductor structure (including the second source / drain metal 125 and the second contact metal layer 37). In one example, wafer thinning can be performed using a CMP process to expose the second contact metal layer 37, as shown in FIG. 23. Then, step S113 can be performed to form a second metal interconnection layer 35 on the second contact metal layer 37 by a back-end-of-line process to form a second metal interconnection structure 126, as shown in FIG. 24.

[0124] At this point, the fabrication of the semiconductor device 10 in the embodiments of the present disclosure is completed.

[0125] In the embodiments of the present disclosure, the first gate structure and the first metal interconnection structure of the first transistor are formed after the second source / drain structure of the second transistor by multiple wafer bonding and flipping, which avoids the influence of the high process temperature of the second transistor when forming the second source / drain structure on the first gate structure and the first metal interconnection structure of the first transistor, and improves the thermal budget of the semiconductor device.

[0126] In some embodiments, the present disclosure provides a semiconductor device. As shown in FIG. 18 and FIG. 24, the semiconductor device 10 is prepared by the method in one or more embodiments described above. The semiconductor device 10 includes a first transistor 11 and a second transistor 12. The second transistor 12 is disposed opposite to the first transistor 11. The first active structure 21 of the first transistor 11 and the second active structure 22 of the second transistor 12 are formed by the same process, and the first transistor 11 and the second transistor 12 are self-aligned in the vertical direction.

[0127] In an embodiment, the vertical direction refers to a direction perpendicular to a substrate on which the semiconductor device 10 is formed. The self-alignment of the first transistor 11 and the second transistor 12 refers to that the gate region of the first transistor 11 is aligned with the gate region of the second transistor 12, and the source-drain region of the first transistor 11 is aligned with the source-drain region of the second transistor 12.

[0128] In an example, the gate region refers to a region in which a gate structure is formed, and the source-drain region refers to a region in which a source-drain structure is formed.

[0129] It can be understood that, in the preparation process of the semiconductor device in the present disclosure, a deep STI and a higher active region are first formed by etching, then the source-drain structure of the first transistor is prepared above the active region, then the film is peeled off, the lower part of the active region is exposed by self-aligned etching, and part of the structure of the second transistor is formed. After the preparation of part of the structure of the second transistor is completed, the film is peeled off again to complete the subsequent preparation of the first transistor. Then, the film is peeled off for the third time to complete the subsequent preparation of the second transistor.

[0130] In an embodiment, the pseudo-gate of the upper and lower transistors is formed by multiple times of film peeling, and the source-drain is prepared to replace the metal gate process. The order of processes such as middle-of-line (MOL) and back-end-of-line (BEOL) is optimized and adjusted, so that the source-drain structure with high temperature resistance has a priority in the preparation order, thereby effectively improving the thermal budget in the subsequent preparation process, and solving the technical problem that the source-drain preparation process temperature of the transistor is relatively high, while the process temperature that the metal gate and the metal interconnection line can withstand is relatively low, resulting in limited thermal budget of the stacked transistors.

[0131] It should be noted that the first preparation process and the second preparation process of the semiconductor device described above are only two exemplary embodiments for embodying the technical concept of the present disclosure. It should be understood that the technical solution of forming the first gate structure and the first metal interconnection structure of the first transistor after forming the second source-drain structure of the second transistor, so as to avoid the influence of the process temperature when forming the second source-drain structure on the first gate structure and the first metal interconnection structure of the first transistor, is within the protection scope of the present disclosure.

[0132] In an example, there is a secondary flip-chip solution. The secondary flip-chip solution can be implemented by a standard process flow to etch deep STI and higher active regions on a raw silicon substrate, and deposit dummy gates to form source-drain structures of a first transistor. Then, the first transistor is bonded to a first carrier wafer for a first flip-chip to expose the substrate to the front side. Then, a standard STI etching and active region exposure process is used to expose active regions of a second transistor in a self-aligned manner. Then, after completing the front-end process, the middle-end process, and the back-end process of the second transistor (i.e., metal interconnection layers are prepared to the second transistor, and each metal interconnection line is made of a high-temperature-resistant material to improve the thermal budget of subsequent processes), the second transistor is bonded to a second carrier wafer for a second flip-chip. After the flip-chip, the first carrier wafer is removed to expose the first transistor, and the gate forming process, the middle-end process, and the back-end process are completed in the first transistor.

[0133] The embodiments of the present disclosure optimize the process flow of the stacked transistors, and also take into account the consistency, defect density, alignment, and thermal budget of the active regions and gates of the upper and lower transistors. The embodiments of the present disclosure use a secondary flip-chip solution, consider the preparation sequence of the stacked transistor device structure and the back-end interconnection lines, and improve the thermal budget of the overall device preparation process. The embodiments of the present disclosure solve the long-term problems of the existing single-chip solution of the stacked transistors, such as process complexity and fixed polarity. The embodiments of the present disclosure solve the long-term problems of the existing sequential solution of the stacked transistors, such as alignment difficulty and high defect density of the upper semiconductor material. The embodiments of the present disclosure promote the industrialization of the stacked transistor technology.

[0134] The solution in the embodiments of the present disclosure is also an organic integration of the current sequential and single-chip stacked transistor solutions, has high mature technology reuse degree, can avoid a large amount of costly process development to save costs, and has high feasibility. Meanwhile, in the embodiments of the present disclosure, the flip-chip transistor uses a self-aligned "back-to-back" active region and metal gate design, the front and back transistors have independent signal and power supply networks, and are connected through local interconnection. Without changing the 4T track unit design of the extreme miniaturization, the metal wiring resources are greatly released (more than 60% compared with the current solution), and there is a huge space for process design and collaborative optimization. Finally, the flip-chip transistor solution is compatible with the existing mainstream device architecture, can realize front and back stacking of planar transistors, fin transistors, full-surround-gate transistors, and even vertical transistors, does not need special process development for specific device architectures, and has strong flexibility. From the perspective of semiconductor process node iteration, the flip-chip transistor has strong extensibility. The flip-chip transistor is very advanced in concept, has important industrial value, and has strong practicality and wide development prospects.

[0135] In some embodiments, the present disclosure provides an electronic device. The electronic device includes a circuit board and a semiconductor device as in one or more of the above embodiments, the semiconductor device is disposed on the circuit board.

[0136] In the above embodiments, the description of each embodiment has its emphasis, and the parts not described in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0137] The above describes only the exemplary specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A method for preparing a semiconductor device, wherein: include: An active structure is formed on a substrate; wherein the active structure includes a first active structure and a second active structure stacked in a first direction, the first direction being perpendicular to the substrate; Based on the first active structure, forming a first semiconductor structure, wherein the first semiconductor structure includes a first dummy gate structure and a first source-drain structure; Bonding the first semiconductor structure to the first carrier wafer and flipping the wafer over; removing the substrate and exposing the second active structure; Based on the second active structure, forming a second semiconductor structure, wherein the second semiconductor structure includes a second gate structure and a second source-drain structure; bonding the second semiconductor structure to the second carrier wafer and flipping the wafer over; removing the first carrier wafer to expose the first semiconductor structure; In the first semiconductor structure, removing the first dummy gate structure filling metal to form a first gate structure; forming a first source-drain metal on the first source-drain structure to form a first transistor; forming a first metal interconnection structure on the first transistor through a back-end process; bonding the first metal interconnect structure to a third carrier wafer and flipping the wafer over; removing the second carrier wafer to expose the second semiconductor structure; A second metal interconnection structure is formed based on the second semiconductor structure.

2. The method according to claim 1, wherein The step of forming a second metal interconnect structure based on the second semiconductor structure includes: forming a second source-drain metal on the second source-drain structure to form a second transistor; The second metal interconnect structure is formed on the second transistor.

3. The method according to claim 1, wherein The second semiconductor structure further includes: a second source-drain metal and a second contact metal layer, wherein the second source-drain metal is formed by depositing metal on the second source-drain structure, and the second contact metal layer is formed on the second gate structure and the second source-drain metal; The step of forming a second metal interconnect structure based on the second semiconductor structure includes: A second metal interconnection layer is formed on the second contact metal layer through a back-end process to form a second metal interconnection structure.

4. The method according to claim 3, wherein: The second contact metal layer is formed of a high-temperature resistant metal material.

5. The method according to claim 1, wherein After forming an active structure on the substrate and before forming a first semiconductor structure based on the first active structure, the method further includes: A semiconductor material is deposited on the substrate to form a shallow trench isolation layer, wherein the shallow trench isolation layer wraps the second active structure, and the first active structure is exposed outside the shallow trench isolation layer.

6. The method according to claim 5, wherein: The removing of the substrate and exposing the second active structure comprises: The substrate and a portion of the shallow trench isolation layer are removed by a chemical mechanical polishing process to expose the second active structure.

7. The method according to claim 1, wherein An electrical isolation layer is formed at the connection between the first active structure and the second active structure by ion implantation, and the electrical isolation layer is used to electrically isolate the first active structure from the second active structure.

8. The method according to claim 1, wherein The first transistor is one of a fin field effect transistor, a gate-all-around transistor, and a planar transistor.

9. A semiconductor device, wherein the semiconductor device is prepared by the method according to any one of claims 1 to 8; The semiconductor device comprises: a first transistor; a second transistor, the second transistor being arranged opposite to the first transistor; The first active structure of the first transistor and the second active structure of the second transistor are formed by the same process, and the first transistor and the second transistor are self-aligned in a vertical direction.

10. An electronic device, wherein: include: A circuit board and the semiconductor device according to claim 9, wherein the semiconductor device is provided on the circuit board.

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