Data processor, data processing method, electronic device and storage medium

Abstract

Provided in the embodiments of the present disclosure are a data processor, a data processing method, an electronic device and a non-transitory computer-readable storage medium. The data processor comprises N levels of caches, a memory, and N levels of data proxy modules, wherein each level of data proxy module among the N levels of data proxy modules correspond to each level of cache among the N level of caches on a one-to-one basis, and the N levels of data proxy modules are configured to acquire a data access instruction sequence in a task currently executed by the data processor, adjust an instruction sending order of the data access instruction sequence on the basis of the storage location of target data for data access instructions in the data access instruction sequence, sequentially send the data access instructions according to the instruction sending order, and cache in a corresponding first-level data proxy module target data returned by each data access instruction. The data processor reduces the occupancy time of a register, and prevents a data access instruction at a remote storage location from preempting a bandwidth of a data access instruction at a near storage location, thereby greatly improving data access efficiency.

Description

Data processor, data processing method, electronic device and storage medium

[0001] This application claims priority to Chinese Patent Application No. 202410420140.8, filed on April 9, 2024, the disclosure of which is incorporated herein in its entirety as part of the present application. TECHNICAL FIELD

[0002] Embodiments of the present disclosure relate to a data processor, a data processing method, an electronic device and a non-transitory computer-readable storage medium. BACKGROUND

[0003] A data access instruction (e.g., a Load instruction) is a basic instruction in computer organization and principles, which is used to load data from a storage component such as a memory into a register, and the role is to read data in the storage component such as a memory into a specified register for subsequent operation and processing.

[0004] SUMMARY

[0005] At least one embodiment of the present disclosure provides a data processor, comprising an N-level cache and a memory, an i-level cache in the N-level cache comprising at least one i-level cache node, at least part of the at least one i-level cache node sharing one i+1-level cache node, N being a positive integer greater than 1, i being any positive integer between 1 and N-1, the N-level cache being electrically connected with the memory, each 1-level cache node being electrically connected with a corresponding computing core, the data processor further comprising an N-level data agent module, wherein each level data agent module in the N-level data agent module corresponds to each level cache in the N-level cache, the N-level data agent module being configured to obtain a data access instruction sequence in a task currently executed by the data processor, adjust an instruction sending order of the data access instruction sequence according to a storage location of destination data of each data access instruction in the data access instruction sequence, send the each data access instruction in turn according to the instruction sending order, and cache the destination data returned by the each data access instruction to a corresponding first-level data agent module, wherein the corresponding first-level data agent module corresponds to a first-level cache.

[0006] For example, in the data processor provided by at least one of the embodiments of the present disclosure, when the N-level data agent module adjusts the instruction sending sequence of the data access instruction sequence according to the storage positions of the target data of each data access instruction in the memory, the N-level data agent module comprises: obtaining the physical distance corresponding to each data access instruction, wherein the physical distance corresponding to each data access instruction is the distance between the storage position of the target data of each data access instruction in the memory and the computing core in the data processor; and adjusting the instruction sending sequence of the data access instruction sequence according to the physical distance corresponding to each data access instruction, wherein the data access instruction with a smaller corresponding physical distance is sent earlier.

[0007] For example, in the data processor provided by at least one of the embodiments of the present disclosure, when the N-level data agent module adjusts the instruction sending sequence of the data access instruction sequence according to the physical distance corresponding to each data access instruction, the N-level data agent module comprises: classifying the data access instructions into different channels according to the physical distance corresponding to each data access instruction, wherein the data access instructions in different channels correspond to different physical distances; and arranging the data access instructions in each channel in the order of the physical distance corresponding to the data access instructions in different channels from small to large in units of channels to obtain the instruction sending sequence, wherein in the instruction sending sequence, the data access instructions in a first channel are sent first, the data access instructions in a second channel are sent last, the data access instructions in the same channel are sent in series according to the relative sequence relationship in the data access instruction sequence, the data access instructions in the first channel correspond to the smallest physical distance, and the data access instructions in the second channel correspond to the largest physical distance.

[0008] For example, in the data processor provided by at least one of the embodiments of the present disclosure, when the N-level data agent module adjusts the instruction sending sequence of the data access instruction sequence according to the storage positions of the target data of each data access instruction in the memory, the N-level data agent module comprises: obtaining the priority of each data access instruction; obtaining the physical distance corresponding to each data access instruction, wherein the physical distance corresponding to each data access instruction is the distance between the storage position of the target data of each data access instruction in the memory and the computing core in the data processor; and adjusting the instruction sending sequence of the data access instruction sequence according to the priority of each data access instruction and the physical distance corresponding to each data access instruction, wherein the data access instruction with a higher priority is sent earlier, and in the case of the same priority, the data access instruction with a smaller corresponding physical distance is sent earlier.

[0009] For example, in the data processor provided by at least one embodiment of the present disclosure, the N-level data agent module performs the operation of obtaining the priority of each data access instruction, including the following operation: determining the priority of each data access instruction according to the time of returning the destination data of the respective data access instruction when pre-running the task, wherein the respective data access instruction is sent in sequence according to the order in the data access instruction sequence, and the time of returning the destination data of the respective data access instruction is collected.

[0010] For example, in the data processor provided by at least one embodiment of the present disclosure, when the N-level data agent module performs the operation of caching the destination data returned by the respective data access instruction into the corresponding first-level data agent module, it includes the following operation: for each data access instruction, caching the destination data returned by the data access instruction into a first-level cache node or shared memory electrically connected with the computing core using the destination data, wherein the corresponding first-level data agent module includes a plurality of cache blocks, the plurality of cache blocks are mapped to the first-level cache node or the shared memory, and the plurality of cache blocks are used to cache the received destination data.

[0011] For example, in the data processor provided by at least one embodiment of the present disclosure, the at least one i-level cache node corresponds to at least one i-level data agent module, the i-level data agent module corresponding to the at least part of i-level cache nodes is electrically connected with the i+1-level data agent module corresponding to the one i+1-level cache node, and the first-level data agent module corresponding to each first-level cache node is electrically connected with at least one computing core, wherein the at least one computing core is electrically connected with the first-level cache node; the N-level cache corresponding to the N-level data agent module is electrically connected with the memory.

[0012] For example, in the data processor provided by at least one embodiment of the present disclosure, each data agent module includes a scheduler, a request state list, a data request list, and a plurality of cache blocks, the data agent module includes any i-level data agent module or the N-level data agent module, the data request list is used to cache the data access instruction to be sent, the scheduler is used to send the data access instruction cached in the data request list in sequence according to the instruction sending order, and send the received destination data to the cache block in the corresponding computing core or the upper-level data agent module electrically connected, the request state list includes a plurality of state items, wherein each state item in the plurality of state items is used to indicate the cache block associated with the data access instruction corresponding to the state item, and the position of the data access instruction in the instruction sending order, and the plurality of cache blocks are used to cache the received destination data.

[0013] For example, in the data processor provided in at least one embodiment of the present disclosure, the data request list of the data agent module is provided with multiple channels for caching the to-be-sent data access instructions, the data access instructions in different channels correspond to different physical distances, the scheduler is configured to arrange the data access instructions in each channel in order of the physical distances corresponding to the data access instructions in different channels from small to large, to obtain the instruction sending order of the data access instructions cached in the data request list, and sequentially send the to-be-sent data access instructions according to the instruction sending order, wherein the physical distance corresponding to each data access instruction is the distance between the storage location of the destination data of each data access instruction in the memory and the computing core in the data processor, and the physical distance corresponding to each data access instruction is determined by the read address of the destination data as an input parameter in each data access instruction.

[0014] For example, in the data processor provided in at least one embodiment of the present disclosure, the data agent module is configured to: in response to the existence of an unassociated cache block in the data agent module, associate the unassociated cache block with one data access instruction selected from the data request list of the data agent module according to the instruction sending order.

[0015] For example, in the data processor provided in at least one embodiment of the present disclosure, each cache block has a unique corresponding cache block number, each data access instruction in the data request list has a unique corresponding request number, and the data agent module performs the operation of associating the unassociated cache block with one data access instruction selected from the data request list of the data agent module according to the instruction sending order, including: setting the request number of the one data access instruction and the cache block number of the unassociated cache block in the state item corresponding to the one data access instruction, to associate the unassociated cache block and the one data access instruction.

[0016] For example, in the data processor provided in at least one embodiment of the present disclosure, the i+1-level data agent module is further configured to: in response to the destination data cached in any cache block in the i+1-level data agent module having been sent to the i-level data agent module, clear the data access instruction associated with the any cache block from the data request list of the i+1-level data agent module, and empty the state item corresponding to the cleared data access instruction in the request state list of the i+1-level data agent module.

[0017] For example, in the data processor provided by at least one embodiment of the present disclosure, the scheduler of the Nth data agent module is configured to: send the cached data access instructions in the data request list of the Nth data agent module to the memory in the order of instruction sending of the cached data access instructions; and receive the target data returned from the memory in sequence and store each returned target data in the cache block associated with the corresponding data access instruction.

[0018] For example, in the data processor provided by at least one embodiment of the present disclosure, the scheduler of the i-th data agent module is configured to: send a data request signal to the i+1-th data agent module electrically connected thereto, and cache the received returned data in the cache block associated with the data access instruction corresponding to the sent data request signal; and the scheduler of the i+1-th data agent module is configured to: in response to receiving the data request signal, send the target data of the data access instruction corresponding to the data request signal to the i-th data agent module.

[0019] For example, in the data processor provided by at least one embodiment of the present disclosure, the first data agent module is further configured to: before executing the task, select at least one data access instruction from the data access instruction sequence in the order of the data access instruction sequence and perform an initialization operation on the at least one data access instruction, wherein the at least one data access instruction is executed by a computing core electrically connected to the first data agent module.

[0020] For example, in the data processor provided by at least one embodiment of the present disclosure, when the first data agent module performs the initialization operation on the at least one data access instruction, the first data agent module includes the following operations: caching the at least one data access instruction in the data request list of the first data agent module; initializing the state item corresponding to the at least one data access instruction and storing it in the request state list of the first data agent module; and synchronizing the at least one data access instruction and the corresponding state item to other data agent modules having a direct or indirect electrical connection relationship with the first data agent module.

[0021] For example, in the data processor provided in at least one of the embodiments of the present disclosure, the first-level data agent module is further configured to: in response to receiving a data access instruction sent by a computing core electrically connected to the first-level data agent module, determine a cache block associated with the sent data access instruction, send data in the associated cache block to a destination register indicated by the data access instruction; clear the data access instruction associated with the associated cache block from a data request list of the first-level data agent module, and clear a state item corresponding to the cleared data access instruction in a request state list of the first-level data agent module; select at least one data access instruction from the data access instruction sequence in the order of the data access instruction sequence, and perform an initialization operation on the at least one data access instruction.

[0022] For example, in the data processor provided in at least one of the embodiments of the present disclosure, the state item includes a cache block number and a request number, used to indicate the data access instruction corresponding to the state item and the cache block associated with the data access instruction, the state item further includes a channel number of a channel to which the data access instruction belongs and a priority of the data access instruction, the channel number and the priority being used to indicate a position of the data access instruction in the instruction sending order, the state item further includes request receiving state information and request sending state information, used to indicate a current state of the data access instruction, and the state item further includes data state information, used to indicate a current state of destination data returned by the data access instruction.

[0023] For example, in the data processor provided in at least one of the embodiments of the present disclosure, before performing the task, the data processor is further configured to: select a plurality of cache lines from a cache node corresponding to each data agent module to be mapped to the plurality of cache blocks in the data agent module.

[0024] For example, in the data processor provided in at least one of the embodiments of the present disclosure, the data access instruction sequence is obtained by arranging all data access instructions in the task according to a position relationship in a program corresponding to the task.

[0025] For example, in the data processor provided in at least one of the embodiments of the present disclosure, the data processor is a general-purpose graphics processor or a graphics processor, the data processor includes a plurality of computing units, N=2, the first-level cache in the N-level cache includes a plurality of first-level cache nodes, the second-level cache in the N-level cache includes one second-level cache node, each first-level cache node is used for data sharing within one computing unit, the second-level cache node is used for data sharing between the plurality of computing units, each first-level cache node corresponds to one first-level data agent module, and the second-level cache node corresponds to one second-level data agent module.

[0026] The data processing method provided in at least one embodiment of the present disclosure comprises: obtaining a data access instruction sequence in a task currently executed by the data processor; adjusting an instruction sending order of the data access instruction sequence according to a storage location of destination data of each data access instruction in the memory; sequentially sending the data access instructions according to the instruction sending order; and caching destination data returned by each data access instruction to a first cache node or a shared memory that is electrically connected to a calculation core using the destination data.

[0027] For example, in the data processing method provided in at least one embodiment of the present disclosure, adjusting the instruction sending order of the data access instruction sequence according to the storage location of the destination data of each data access instruction in the memory comprises: obtaining a physical distance corresponding to each data access instruction, wherein the physical distance corresponding to each data access instruction is a physical distance between the storage location of the destination data of each data access instruction in the memory and a calculation core in the data processor; and adjusting the instruction sending order of the data access instruction sequence according to the physical distance corresponding to each data access instruction, wherein the data access instruction with a smaller corresponding physical distance is sent earlier.

[0028] For example, in the data processing method provided in at least one embodiment of the present disclosure, adjusting the instruction sending order of the data access instruction sequence according to the storage location of the destination data of each data access instruction in the memory comprises: obtaining a priority of each data access instruction; obtaining a physical distance corresponding to each data access instruction, wherein the physical distance corresponding to each data access instruction is a physical distance between the storage location of the destination data of each data access instruction in the memory and a calculation core in the data processor; and adjusting the instruction sending order of the data access instruction sequence according to the priority and the physical distance corresponding to each data access instruction, wherein the data access instruction with a higher priority is sent earlier, and the data access instruction with a smaller corresponding physical distance is sent earlier in the case of the same priority.

[0029] The electronic device provided by at least one embodiment of the present disclosure comprises a memory, and a processor, wherein the memory is configured to store computer-executable instructions, and the processor is configured to execute the computer-executable instructions.

[0030] The non-transitory computer-readable storage medium provided by at least one embodiment of the present disclosure stores computer-executable instructions, and the computer-executable instructions are executed by a processor to implement the data processing method according to any one of the embodiments of the present disclosure.

[0031] The electronic device provided by at least one embodiment of the present disclosure comprises the data processor according to any one of the embodiments of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present disclosure, the drawings required to be used in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative effort on the basis of the provided drawings.

[0033] FIG. 1 is a schematic structural diagram of a multi-core chip system;

[0034] FIG. 2 is a schematic structural diagram of a general-purpose graphics processor;

[0035] FIG. 3 is a schematic diagram of a data access instruction flowing between a cache and a memory;

[0036] FIG. 4A-FIG. 4D are timing diagrams of a data access instruction;

[0037] FIG. 5 is a schematic structural diagram of a data processor provided by at least one embodiment of the present disclosure;

[0038] FIG. 6 is a schematic block diagram of a data proxy module provided by at least one embodiment of the present disclosure;

[0039] FIG. 7 is a schematic block diagram of a data processor provided by at least one embodiment of the present disclosure;

[0040] FIG. 8A-FIG. 8G are schematic diagrams of a processing process of a multi-stage data proxy module provided by at least one embodiment of the present disclosure;

[0041] FIG. 9A-FIG. 9B are timing diagrams of a data processor provided by at least one embodiment of the present disclosure;

[0042] FIG. 10 is a schematic flowchart of a data processing method provided by at least one embodiment of the present disclosure;

[0043] FIG. 11 is a schematic block diagram of an electronic device according to an embodiment of the present disclosure;

[0044] FIG. 12 is a schematic diagram of a non-transitory computer-readable storage medium according to at least one embodiment of the present disclosure;

[0045] FIG. 13 is a schematic block diagram of another electronic device according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0046] In order to make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some but not all of the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of the present disclosure.

[0047] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meaning of the terms to a person of ordinary skill in the art to which the present disclosure belongs. The terms "first", "second" and similar terms used in the present disclosure do not denote any order, quantity or importance, but are used to distinguish different components. The terms "include" or "contain" and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right" and the like are used only to represent relative positional relationships, and when the absolute positions of the described objects are changed, the relative positional relationships can also be changed accordingly.

[0048] In order to keep the following description of the embodiments of the present disclosure clear and brief, the present disclosure omits the detailed description of some known functions and known components.

[0049] The working speed of a processor is much higher than that of a memory. If the processor directly accesses the memory to read and write data, it needs to wait for a certain period of time. Therefore, a cache is usually used in the process of accessing the memory to improve the system efficiency and the speed of the processor accessing the memory. Generally, the processor first searches for data in the cache. For example, if the data requested by an application program or software exists in the cache, it is called a cache hit, otherwise it is called a cache miss.

[0050] Figure 1 is a schematic diagram of a multi-core chip system. As shown in Figure 1, the system is a typical 4-core on-chip system, including 4 cores, 4 cores respectively corresponding to three-level cache (L1 cache, L2 cache and L3 cache), on-chip interconnection network, memory and other intellectual property cores. I-L1$ is the private instruction L1 cache of each core, D-L1$ is the private data L1 cache of each core, each two cores share an L2 cache, and four cores share an L3 cache. The L3 cache and other intellectual property cores (such as direct memory access / video / display, etc.) access the memory through the on-chip interconnection network.

[0051] The L1 cache is closest to the core, has the smallest capacity and the fastest speed.

[0052] The L2 cache has a larger capacity, for example, 256K, and is slower than the L1 cache. The L2 cache can be understood as a buffer of the L1 cache. The L1 cache has a high manufacturing cost and therefore has a limited capacity. The role of the L2 cache is to store data that the processor needs to process and that the L1 cache cannot store.

[0053] The L3 cache is the largest capacity level in the three-level cache, for example, 12MB, and is also the slowest level. The L3 cache and the memory can be regarded as a buffer of the L2 cache. The capacity of the L1 cache to the L3 cache increases, but the unit manufacturing cost decreases.

[0054] When the processor is operating, it first looks for the data it needs in the L1 cache. If it is not found, it looks for the data in the L2 cache. If it is still not found, it looks for the data in the L3 cache. If the data needed by the processor is not found in the three-level cache, it is obtained from the memory. The longer the path of searching, the longer the time consumed.

[0055] Similarly, in the cache of a GPGPU (General-Purpose Graphics Processing Unit) or GPU (Graphic Processing Unit), there is also a similar cache structure as the multi-core on-chip system shown in Figure 1, for example, also including a hierarchical multi-level cache structure.

[0056] Figure 2 is a schematic diagram of a general-purpose graphics processor.

[0057] As shown in FIG. 2, the general-purpose graphics processor is actually an array of Streaming Processor Clusters (SPCs), such as SPC 1,..., SPC M shown in FIG. 2, where M is a positive integer greater than 1. In the general-purpose graphics processor, one SPC processes one computing task, or multiple SPCs process one computing task. The multiple SPCs share data through a global cache (L2 cache) or a global memory.

[0058] As shown in FIG. 2, taking SPC 1 as an example, one SPC includes multiple compute units, such as compute unit 1, compute unit 2,..., compute unit N shown in FIG. 1, where N is a positive integer. Each compute unit (CU) is configured to perform, for example, accumulation, reduction, regular addition, subtraction, multiplication, division, and the like. One compute unit includes multiple cores (also referred to as compute cores or computing cores), each of which includes an arithmetic logic unit (ALU), a floating-point computing unit, and the like, and is configured to perform a specific computing task. In addition, the compute unit also includes a register file, a shared memory, and an L1 cache, which are configured to store source data and destination data related to the computing task in a hierarchical manner. The shared memory in one compute unit is configured to share data among the cores in the compute unit, and the L1 cache is configured to cache data from the memory or the L2 cache that has been used by the compute unit. Of course, in some general-purpose graphics processors, the compute unit can only use the L1 cache and the register file to store data.

[0059] As shown in FIG. 2, the general-purpose graphics processor can also include an L2 cache (also referred to as a global cache) and a memory, such as a High Bandwidth Memory (HBM).

[0060] In parallel computing, a computing task is generally executed by multiple threads. Before being executed in the general-purpose graphics processor (also referred to as a parallel computing processor), the threads are divided into multiple thread blocks, and then the multiple thread blocks are distributed to the compute units via a thread block distribution module (not shown in FIG. 2). All threads in one thread block must be assigned to the same compute unit for execution. Meanwhile, the thread blocks are split into the smallest execution thread bundles (or simply referred to as thread bundles, warps), each of which includes a fixed number (or less than the fixed number) of threads, for example, 32 threads. Multiple thread blocks can be executed in the same compute unit, or in different compute units.

[0061] In each compute unit, a thread bundle scheduling / distribution module (not shown in FIG. 1) schedules and distributes the thread bundle so that the multiple compute cores of the compute unit execute the thread bundle. According to the number of compute cores in the compute unit, the multiple thread bundles in one thread block can be executed simultaneously or in time-sharing manner. The multiple threads in each thread bundle execute the same instruction. Data access instructions are transmitted to the L1 cache (or shared memory) in the compute unit or further transmitted to the L2 cache or global memory for read / write operation, etc.

[0062] When the data access instruction is executed, the address to be read needs to be specified, and the read data is stored in the target register. Taking the read data in the memory as an example, the data access instruction usually includes the following steps:

[0063] 1. Load the memory address into the address register (MAR);

[0064] 2. Load the data of the memory into the data register (MDR);

[0065] 3. Transmit the data from the MDR to the target register. FIG. 3 is a schematic diagram of the flow of a data access instruction between the cache and the memory. In FIG. 3, a two-level cache structure is shown, and of course, similar flow logic also exists for more levels of cache structure, which will not be described here.

[0066] For the multi-level cache structure as described above, when the data access instruction is executed, as shown by the black solid line in FIG. 3, the core first queries whether the data address is cached hit from the L1 cache, and if hit, the data is returned to the corresponding core. If the data is not hit in the L1 cache, as shown by the black dashed line in FIG. 3, the data is further queried from the L2 cache, and if the data is hit in the L2 cache, the data is returned to the L1 cache and the core. If the data is not hit in the L2 cache, as shown by the black dotted line in FIG. 3, the data needs to be loaded from the memory and returned to the L2 cache, the L1 cache and the corresponding core.

[0067] The data access instruction includes the read address of the target data as an input parameter and the address of the target register as an output parameter. The read address is, for example, a memory address, and the data access instruction is used to read the target data from the read address in the memory and load it into the target register.

[0068] Current data access instructions are not efficient enough, and require high sending data access instructions. This is because the time of returning data by data access instructions is uncertain, such as different distances between the storage location of the destination data and the computing core, and the time of returning data is different. For example, the memory is usually composed of multiple memory blocks, and the distances between different memory blocks and the computing core are also different, so that the data can be stored in the remote memory (the memory block far away from the computing core) or the near-end memory (the memory block close to the computing core). In addition, since it takes time to return data from the memory, the returned data cannot be immediately received, so the data returned by the data access instruction needs to be waited for when using the data, and the data may not arrive exactly when it is used.

[0069] Figure 4A is a timing diagram of a data access instruction.

[0070] As shown in Figure 4A, the data access instruction is sent when the data needs to be used (as shown by the dashed line in Figure 4A), the destination data is located in the memory, the instruction needs to be transmitted from the computing core to the L1 cache, the L2 cache to the memory, and the data read from the memory is returned to the computing core via the L2 cache, the L1 cache, even if other instructions (such as instruction 2) are executed after the data access instruction is sent, a long time of data waiting will still be generated.

[0071] In order to avoid the above problems, the data access instruction is usually sent early, so that the data is returned before use, thereby avoiding data waiting as much as possible. However, this method will occupy the destination register after sending the data access instruction, and will be occupied until the data is returned, so that the register resource will be occupied for a long time, so that the register resource cannot be used for other instructions, resulting in waste of register resources.

[0072] Figures 4B and 4C are timing diagrams of another data access instruction.

[0073] As shown in Figure 4B, the data arrives just before use (as shown by the dashed line in Figure 4B), but the destination register needs to be occupied from the time of sending the data access instruction, so even if the data waiting time is short, the register resource is still wasted.

[0074] As shown in Figure 4C, due to the uncertainty of the time of returning data, the data is more likely to arrive early, and the data has arrived when it is used (as shown by the dashed line in Figure 4C), and the register is occupied for a long time without waiting for the data, resulting in waste of register resources.

[0075] The user can set the time of issuing different data access instructions by experience, but it is still impossible to guarantee that the data is returned in the expected order because the user is difficult to determine the actual storage location of the data in the processor. Moreover, the time of returning data of multiple data access instructions can be out of order, and if multiple threads simultaneously issue many data access instructions, the time required for returning data is different, so the data can not be returned in the order of the sending of the data access instructions when returned, for example, the data that is not needed in the short term can occupy the bandwidth, and the current desired data is blocked and arrives later.

[0076] FIG. 4D is a timing diagram of another data access instruction.

[0077] As shown in FIG. 4D, the user believes that the returned data of the data access instruction 2 will arrive at the expected time (black thick dashed line in FIG. 4D) by experience, but the returned data can be occupied by other data that is not needed in the short term, for example, the returned data 1 of the data access instruction 1 is occupying the bandwidth so that the returned data of the data access instruction 2 cannot be returned in the expected time, the actual return time of the returned data of the data access instruction 2 is later than the expected time, and multiple data waiting with different lengths is caused, for example, after waiting for a period of time, other instructions (for example, instruction 1 or instruction 2 in FIG. 4D) are executed first and then the waiting is continued, which can make the total waiting time longer.

[0078] At least one embodiment of the present disclosure provides a data processor, a data processing method, an electronic device and a non-transitory computer-readable storage medium. The data processor comprises an N-level cache and a memory, an i-level cache in the N-level cache comprises at least one i-level cache node, at least part of the at least one i-level cache node shares an i+1-level cache node, N is a positive integer greater than 1, i is any positive integer between 1 and N-1, an N-level cache in the N-level cache is electrically connected with the memory, each 1-level cache node is electrically connected with a corresponding computing core, and the data processor further comprises an N-level data agent module. Each level of the N-level data agent module corresponds to each level of the N-level cache, the N-level data agent module is configured to obtain a data access instruction sequence in a task currently executed by the data processor, adjust the instruction sending order of the data access instruction sequence according to the storage location of the destination data of each data access instruction in the memory, send each data access instruction in turn according to the instruction sending order, and cache the destination data returned by each data access instruction in a corresponding first-level data agent module, wherein the corresponding first-level data agent module corresponds to the first-level cache.

[0079] In the data processor provided in at least one embodiment of the present disclosure, an N-level data agent module is used to uniformly send data access instructions, and the data access operation is decoupled between the computing core and the memory, so that the computing core does not need to care about the sending, receiving and scheduling of the data access instructions, and only needs to extract the data from the corresponding first-level data agent module when the data is needed.

[0080] Since the data is extracted to the first-level data agent module in advance instead of being directly loaded to the destination register, the data access instruction can be sent early, the data is cached in the first-level data agent module in advance, and the destination register does not need to be occupied all the time before the data is used. Only when the destination data is used, the register is occupied to load the destination data to the destination register, which greatly reduces the occupation time of the register and reduces the consumption of the register resource.

[0081] In addition, the sending order of the instructions is adjusted according to the storage positions of the destination data of different instructions, so as to avoid that the data access instructions with far storage positions squeeze the bandwidth of the data access instructions with near storage positions, so that the return time of the data meets the user's expectation, and the data access efficiency is improved.

[0082] The embodiments of the present disclosure will be described in detail below with reference to the drawings, but the present disclosure is not limited to these specific embodiments.

[0083] FIG. 5 is a schematic structural diagram of a data processor provided in at least one embodiment of the present disclosure.

[0084] As shown in FIG. 5, the data processor 100 includes a memory, an N-level cache and an N-level data agent module.

[0085] The specific structures of the first-level cache, the second-level cache and the N-level cache are shown in FIG. 5, and the structures of the other level caches are similar and will not be repeatedly shown. Of course, in some embodiments, it can also be a two-level cache structure, that is, N = 2, for example, refer to the content shown in FIG. 7, which will not be described here.

[0086] For example, the i-level cache in the N-level cache includes at least one i-level cache node, and at least part of the i-level cache nodes share one i+1-level cache node. Here, N is a positive integer greater than 1, and i is any positive integer between 1 and N-1.

[0087] For example, as shown in FIG. 5, when i = 1, for the first-level cache, it includes a plurality of first-level cache nodes. When i = 2, for the second-level cache, it includes a plurality of second-level cache nodes.

[0088] For example, as shown in FIG. 5, the N-level cache includes one N-level cache node.

[0089] For example, multiple i-level cache nodes can share one i+1-level cache node, and all N-1-level cache nodes share one N-level cache node. Here, sharing means that the multiple (e.g., M, M is a positive integer) i-level cache nodes are electrically connected to the i+1-level cache node, and the M i-level cache nodes can exchange data with the i+1-level cache node, such as obtaining the required data from the i+1-level cache node.

[0090] For example, referring to FIG. 5, multiple 1-level cache nodes share one 2-level cache node, such as some 1-level cache nodes sharing one 2-level cache node, and other 1-level cache nodes sharing another 2-level cache node. For example, all N-1-level cache nodes share one N-level cache node.

[0091] For example, in each level, how many cache nodes share one higher-level cache node can be set as needed, and each level can be different, and the present disclosure does not make specific limitations on this. For example, in response to N = 4, it can be set that every 4 1-level cache nodes share one 2-level cache node, every 8 2-level cache nodes share one 3-level cache node, and all 3-level cache nodes share one 4-level cache node.

[0092] For example, as shown in FIG. 5, the N-level cache is electrically connected to the memory. For example, the memory can be a high-bandwidth memory.

[0093] For example, as shown in FIG. 5, each 1-level cache node is electrically connected to a corresponding computing core. For example, referring to the processor architecture shown in FIG. 1, one 1-level cache node can be electrically connected to one computing core, and the 1-level cache node can be an L1 cache, and the 1-level cache node is electrically connected to one computing core. For example, referring to the processor architecture shown in FIG. 2, one 1-level cache node can be electrically connected to multiple computing cores, and the 1-level cache node can be an L1 cache, and in one computing unit, the 1-level cache node can be electrically connected to four computing cores.

[0094] As shown in FIG. 5, the data processor includes one-to-one correspondence between each of the N-level data agent modules and each of the N-level caches.

[0095] For example, the N-level data agent modules include a first-level data agent module corresponding to the first-level cache, a second-level data agent module corresponding to the second-level cache, and an N-level data agent module corresponding to the N-level cache.

[0096] For example, for the first-level to the N-1-level data agent modules, in some embodiments, each level of cache corresponds to one data agent module, for example, all 1-level cache nodes in the first-level cache correspond to one first-level data agent module.

[0097] For example, in some other embodiments, as shown in FIG. 5, a single cache node in each level of cache corresponds to one data agent module, for example, the data processor includes a plurality of first-level data agent modules, which one-to-one correspond to a plurality of first-level cache nodes included in the first-level cache.

[0098] For example, the Nth-level cache includes one Nth-level cache node, which corresponds to one Nth-level data agent module.

[0099] For example, the same electrical connection relationship exists between the data agent modules and the corresponding cache nodes. For example, M i-level cache nodes share one i+1-level cache node, and the M i-level cache nodes correspond to M i-level data agent modules, respectively, which have an electrical connection relationship with the i+1-level data agent module corresponding to the i+1-level cache node. The i-level data agent modules corresponding to other i-level cache nodes can not have an electrical connection relationship with the i+1-level data agent module.

[0100] In addition, for the first-level data agent module, each first-level data agent module can be electrically connected to some computing cores for data interaction, and these computing cores are in an electrical connection relationship with the first-level cache node corresponding to the first-level data agent module, that is, these computing cores share the first-level cache node.

[0101] For the Nth-level data agent module, it is similar to the Nth-level cache node and has an electrical connection relationship with the memory, and the Nth-level data agent module can interact with the memory.

[0102] For example, the Nth-level data agent module is configured to obtain a data access instruction sequence in a task currently executed by the data processor, adjust the instruction sending order of the data access instruction sequence according to the storage location of the target data of each data access instruction in the data access instruction sequence, send each data access instruction in turn according to the instruction sending order, and cache the target data returned by each data access instruction to the corresponding first-level data agent module.

[0103] Here, the first-level data agent module corresponds to the first-level cache. For example, if only one first-level data agent module is provided in the data processor, the returned target data is cached in the first-level data agent module. For example, if a plurality of first-level data agent modules are provided in the data processor, the plurality of first-level data agent modules one-to-one correspond to a plurality of first-level cache nodes, the returned target data is cached in the first-level data agent module corresponding to the target first-level cache node, and the computing core electrically connected to the target first-level cache node uses the returned target data. For different data access instructions, the returned target data can be cached in different first-level data agent modules.

[0104] For example, the data access instruction sequence is a raw instruction sequence, which is obtained by arranging all data access instructions in the task according to the position relationship in the corresponding program of the task. That is, the data access instruction sequence reflects the original sending order in the task program, which is arranged according to the order expected by the user.

[0105] For example, the data access instruction sequence can be obtained by scanning the program code corresponding to the task, or by pre-running the task.

[0106] For example, in some embodiments, the N-level data agent module adjusts the instruction sending order of the data access instruction sequence according to the storage location of the destination data of each data access instruction in the data access instruction sequence, including the following operations: obtaining the physical distance corresponding to each data access instruction, wherein the physical distance corresponding to each data access instruction is the distance between the storage location of the destination data of each data access instruction in the memory and the computing core in the data processor; adjusting the instruction sending order of the data access instruction sequence according to the physical distance corresponding to each data access instruction, wherein the sending time of the data access instruction with smaller corresponding physical distance is earlier.

[0107] For example, the destination data to be loaded by the data access instruction is placed in the memory, and the memory has multiple memory blocks. As described above, different memory blocks have different distances from the computing core, and the destination data on the same memory block can be considered to have the same distance, and the destination data on different memory blocks can be considered to have different distances. Alternatively, several adjacent memory blocks can be considered to have the same distance from the computing core, which can be set by those skilled in the art as needed.

[0108] According to the different physical distances corresponding to each data access instruction, the instruction sending order of the data access instruction sequence can be adjusted, for example, on the basis of the original data access instruction sequence, the sending order is adjusted according to the physical distance corresponding to each data access instruction.

[0109] For example, the sending time of the data access instruction with smaller corresponding physical distance is earlier, that is, it is placed in the front position in the instruction sending order, and the sending time of the data access instruction with larger corresponding physical distance is later, that is, it is placed in the rear position in the instruction sending order. For example, the data access instructions with the same corresponding physical distance are sent in turn according to the relative order relationship in the data access instruction sequence.

[0110] In at least one embodiment of the present disclosure, the physical distance corresponding to the data access instruction is not necessarily a real, spatial distance value, and can be represented in any manner capable of distinguishing and calculating the distance of the core. For example, when the read address of the data access instruction is located in the far-end memory, the physical distance corresponding to the data access instruction can be marked as a first value, and when the read address is located in the near-end memory, the physical distance corresponding to the data access instruction can be marked as a second value, and the like, to distinguish the physical distance corresponding to different data access instructions.

[0111] For example, when the N-level data proxy module performs adjustment of the instruction sending order of the data access instruction sequence according to the physical distance corresponding to each data access instruction, the following operations are included: classifying each data access instruction into different channels according to the physical distance corresponding to each data access instruction, wherein the data access instructions in different channels correspond to different physical distances; arranging the data access instructions in each channel in order of the physical distance corresponding to the data access instructions in different channels from small to large, to obtain the instruction sending order, wherein in the instruction sending order, the data access instructions belonging to the first channel are sent first, the data access instructions belonging to the second channel are sent last, the data access instructions belonging to the same channel are sent in series according to the relative order relationship in the data access instruction sequence, the data access instructions in the first channel correspond to the smallest physical distance, and the data access instructions in the second channel correspond to the largest physical distance.

[0112] For example, a plurality of channels can be provided in the data proxy module, and the data access instructions can be classified into different channels according to the corresponding physical distance. For example, data access instructions whose destination data are in the same memory block can be classified into one channel, or data access instructions whose destination data are in several memory blocks that are relatively close can be classified into one channel.

[0113] For example, a first channel, a second channel, a third channel, and the like can be provided. For example, the first channel is a fast channel, and the data access instructions in the first channel correspond to a small physical distance, for example, the destination data of the data access instructions in the first channel is located in the near-end memory. For example, the second channel is a slow channel, and the data access instructions in the second channel correspond to a large physical distance, for example, the destination data of the data access instructions in the second channel is located in the far-end memory. For example, a third channel and the like can also be provided, and the data access addresses in these channels correspond to a physical distance that is smaller than the physical distance corresponding to the data access addresses in the second channel, but larger than the physical distance corresponding to the data access addresses in the first channel.

[0114] For example, when arranging the sending order of instructions, data access instructions are arranged in units of channels. For example, assume that three channels are set in the data agent module, the first channel is a fast channel, the second channel is a slow channel, and the third channel is an intermediate channel. The data access instructions classified into the first channel correspond to the smallest physical distance, the data access instructions classified into the third channel correspond to a physical distance greater than that of the data access instructions classified into the first channel, and the data access instructions classified into the second channel correspond to the largest physical distance, i.e., greater than that of the data access instructions classified into the third channel. It should be noted that more channels or only two channels can be set to classify different data access instructions according to actual conditions, and the present disclosure does not make a specific limitation in this regard.

[0115] All data access instructions in the first channel are placed at the front of the sending order of instructions to be sent earliest, all data access instructions in the third channel are placed after the data access instructions in the first channel to be sent, and all data access instructions in the second channel are placed after the data access instructions in the third channel to be sent.

[0116] If multiple data access instructions are included in a channel, these data access instructions can be sent in any order in series; or, they are sent in order according to the relative order relationship of the data access instructions in the data access instruction sequence, i.e., for these data access instructions, the data access instructions earlier in the data access instruction sequence are sent first, and the data access instructions later are sent later. At this time, the sending order of instructions more meets the expected sending order of instructions of the program itself, and the purpose data expected to be loaded earlier can be returned earlier.

[0117] In the above embodiment, the channel is introduced to classify and manage data access instructions, and according to the distance between the storage location of the purpose data to be loaded and the computing core, the data access instructions are classified into different channels, the data access instructions corresponding to the close physical distance are sent first, and the data access instructions corresponding to the far physical distance are sent later. The data access instructions corresponding to different physical distances are sent separately, so as to avoid that the far distance request squeezes the bandwidth of the near distance request as much as possible, and the return time of the purpose data meets the user's expectation as much as possible.

[0118] For example, in some embodiments, the sending order of instructions can also consider the priority of data access instructions. For example, the physical distance corresponding to some data access instructions is relatively large, but these data access instructions can be important to the user, for example, the user expects to use the data returned by these data access instructions early, and therefore these data access instructions can be set to a high priority to be sent early.

[0119] For example, the N-stage data agent module performs adjustment on the sending order of the data access instruction sequence according to the storage locations of the target data of each data access instruction in the data access instruction sequence, including the following operations: obtaining the priority of each data access instruction; obtaining the corresponding physical distance of each data access instruction, wherein the corresponding physical distance of each data access instruction is the distance between the storage location of the target data of each data access instruction in the memory and the computing core in the data processor; and adjusting the sending order of the data access instruction sequence according to the priority and the corresponding physical distance of each data access instruction, wherein the data access instruction with higher priority is sent earlier, and in the case of the same priority, the data access instruction with smaller corresponding physical distance is sent earlier.

[0120] For example, the N-stage data agent module performs obtaining the priority of each data access instruction, including the following operations: determining the priority of each data access instruction according to the time of returning the target data of each data access instruction when pre-running the task, wherein when pre-running the task, each data access instruction in the data access instruction sequence is sent in sequence, and the time of returning the target data of each data access instruction is collected.

[0121] For example, through the time of returning the target data of each data access instruction collected in the process of pre-running the task, it can be determined which data access instructions need to be sent in advance, for example, some data access instructions return the target data later but need to use the target data earlier, and these data access instructions can be set to have high priority.

[0122] In the adjusted sending order, the priority of the data access instruction is given priority, and then the channel to which the data access instruction belongs is considered. For example, the data access instruction with higher priority is sent earlier, even if the data access instruction belongs to a slow channel, it is still sent in priority, and other data access instructions (for example, low priority but in a fast channel) are sent after delaying the corresponding clock period. If the priority is the same, the data access instructions are sent in order of the corresponding physical distance from small to large. Specifically, the data access instructions in different channels can be arranged in order of the corresponding physical distance from small to large in the channel, and the sending order of the data access instructions can be obtained by referring to the classification of the data access instructions into different channels as described above.

[0123] In this embodiment, the priority of each data access instruction is set so that the data access instruction with high priority can be sent as soon as possible, and the return time meets the user's expectation; in addition, the data access instructions are sent in multiple channels, and the data access instructions in the fast and slow channels are sent separately to avoid the bandwidth of the fast request from the fast channel being squeezed by the slow request from the slow channel.

[0124] For example, when the N-level data agent module performs caching the destination data returned by each data access instruction into the corresponding first-level data agent module, the following operations are performed: for each data access instruction, caching the destination data returned by the data access instruction into a first-level cache node or shared memory electrically connected with the computing core using the destination data. For example, the corresponding first-level data agent module includes a plurality of cache blocks, the plurality of cache blocks are mapped to the first-level cache node or the shared memory, and the plurality of cache blocks are used to cache the received destination data.

[0125] For example, assuming that the data access instruction 1 is sent by a computing core in FIG. 5, the computing core needs to use the destination data 1 returned by the data access instruction 1, the destination data 1 is read from the memory by the N-level data agent module and cached into a first-level cache node or shared memory electrically connected with the computing core. Specifically, the first-level data agent module can include a plurality of cache blocks, the plurality of cache blocks are mapped to the first-level cache node or the shared memory, that is, the cache blocks actually use the first-level cache node or the shared memory to cache the received destination data. For example, as shown in FIG. 1 and FIG. 2, the first-level cache node can be an L1 cache, and as shown in FIG. 2, the shared memory can be a shared memory electrically connected with the computing core.

[0126] Therefore, the destination data returned by each data access instruction is cached into a first-level cache node or shared memory very close to the computing core, and when the computing core needs the destination data, the computing core can send a data access instruction to the corresponding first-level data agent module, and the first-level data agent module directly returns the destination data cached in the first-level cache node or the shared memory to the destination register. Since the first-level cache node or the shared memory is closest to the computing core, has high bandwidth and fast data transmission speed, and does not need to take data from the memory, the data waiting time is greatly reduced, and the register is occupied only when the destination data is used, the data waiting time is short, so the register occupation time is also greatly reduced, the register resources are saved, the resource consumption is reduced, and the data access efficiency is improved.

[0127] For example, as described above, each data agent module has an electrical connection relationship similar to the corresponding cache node, that is, the cache nodes are electrically connected in the same relationship. Taking the i-level data agent module in the N-level data agent module as an example, at least one i-level cache node corresponds to at least one i-level data agent module one by one, and the i-level data agent module corresponding to at least part of the i-level cache nodes is electrically connected with the i+1-level data agent module corresponding to an i+1-level cache node.

[0128] For example, the first-level data agent module has the same electrical connection relationship with the compute core as the first-level cache node, that is, the first-level cache node and which compute cores are electrically connected, and the corresponding first-level data agent module is also electrically connected with these compute cores.

[0129] For example, the Nth-level data agent module is also electrically connected with the memory.

[0130] FIG. 6 is a schematic block diagram of a data agent module provided by at least one embodiment of the present disclosure.

[0131] For example, the data agent module can be any ith-level data agent module or Nth-level data agent module, that is, each data agent module has the same structure as shown in FIG. 6.

[0132] As shown in FIG. 6, the data agent module 200 includes a scheduler 201, a request state list 202, and a data request list 203.

[0133] The data request list 203 is used to cache data access instructions to be sent, including instruction information of the data access instructions, for example, the instruction information includes input parameters and output parameters of the data access instructions, the input parameters include the read address of the destination data, and the output parameters include the address of the destination register. In addition, a unique request number can be set for each data access instruction, and the instruction information can also include the request number.

[0134] For example, P data access instructions can be cached in the data request list 203, when P is less than the total number of data access instructions in the data access instruction sequence, the first P data access instructions in the data access instruction sequence can be cached in the data request list 203 in order, and after the data access instructions are processed, the P+1th data access instruction in the data access instruction sequence can be cached in the data request list 203, and so on. Here, P is a positive integer.

[0135] For example, as shown in FIG. 6, the data request list 203 is provided with multiple channels (multiple rectangular boxes in the data request list 203), for example, including a first channel, a second channel, etc., each channel is used to cache at least one data access instruction, and the data access instructions in different channels correspond to different physical distances.

[0136] For example, the physical distance corresponding to a data access instruction can be determined by the read address in the data access instruction. For example, when the data access instruction is cached into the data request list 203, the physical distance corresponding to the data access instruction is determined according to the read address of the data access instruction, and the data access instruction is cached into different channels according to the corresponding physical distance. For example, the data access instruction with the read address in the near-end memory is placed in the first channel, the data access instruction with the read address in the far-end memory is placed in the second channel, and so on. The description of the channel can refer to the foregoing related part, and will not be described here.

[0137] The scheduler 201 is configured to send the data access instructions cached in the data request list 203 in the order of the instruction sending sequence, and send the received destination data to the corresponding cache block in the computing core or the upper-level data agent module electrically connected.

[0138] For example, for the first-level data agent module, in response to receiving the data access instruction sent by the computing core electrically connected to the first-level data agent module, the cache block associated with the sent data access instruction is determined, and the data in the associated cache block is sent to the destination register indicated by the data access instruction.

[0139] For other levels of data agent modules except the first-level data agent module, for example, for the (i+1)th-level data agent module, when the data request signal sent by the upper-level data agent module (for example, the ith-level data agent module) is received, the scheduler 201 of the (i+1)th-level data agent module sends the destination data of the data access instruction corresponding to the data request signal to the ith-level data agent module.

[0140] The request state list 202 includes a plurality of state items, wherein each state item in the plurality of state items is used to indicate the cache block associated with the data access instruction corresponding to the state item, the position of the data access instruction corresponding to the state item in the instruction sending sequence, and the like.

[0141] As shown in FIG. 6, the data agent module further includes a plurality of cache blocks, for example, cache block 0 to cache block N, used to cache the destination data received by the data agent module.

[0142] For example, for the Nth-level data agent module, the received destination data can come from the memory, and for the ith-level data agent module, the received destination data can come from the lower-level data agent module, that is, the (i+1)th-level data agent module.

[0143] For example, before executing the task, the data processor is further configured to select at least one cache line from the cache node corresponding to each data agent module to be mapped as a cache block in the data agent module.

[0144] For example, as shown in FIG. 6, the cache node includes a plurality of cache lines, which are the basic units of the cache. Each cache line is mapped with a cache tag in one of the direct connection, group connection or full connection, that is, each cache tag has a one-to-one fixed mapping relationship or static mapping relationship with a cache line. For example, each cache tag includes a virtual address (VA), access information (age count) and reference information (reference count / ref_cnt) and the like.

[0145] As shown in FIG. 6, the data agent module 200 selects some cache lines in the corresponding cache node of the data agent module 200 to generate a mapping relationship with the cache block, that is, actually stores the target data cached in the cache block in the mapped cache line.

[0146] Of course, as described above, the cache block in the data agent module can also be mapped to the shared memory in the computing unit. For example, the on-chip memory and the like can also be used to map the cache block.

[0147] When the 1st-level cache node and the shared memory are used to map the cache block, since the distance between them and the computing core is the closest, the data transmission bandwidth is high and fast, thus the data waiting delay can be reduced, the register occupation time can be reduced, the resource consumption can be reduced, and the data access efficiency can be improved.

[0148] For example, the received target data needs to be stored in the corresponding cache block, and the data access instruction associated with the corresponding cache block is used to load the target data.

[0149] For example, each cache block has a unique cache block number, as shown in FIG. 6, the state item includes the cache block number and the request number, which are used to indicate the data access instruction corresponding to the state item and the cache block associated with the data access instruction. For example, by setting the cache block number and the request number in the state item, a data access instruction and a cache block can be associated, and the target data returned by the data access instruction is stored in the associated cache block.

[0150] For example, in some embodiments, as shown in FIG. 6, the state item further includes a channel number, which represents the channel to which the data access instruction (identified by the request number) corresponding to the state item belongs. For example, the first channel marks the channel number as 0, the second channel marks the channel number as 1, and the like. For example, the channel number is used to indicate the position of the data access instruction in the instruction sending sequence, for example, the channel to which the data access instruction belongs can be determined through the channel number, and the sending of the instruction is performed according to the foregoing process.

[0151] For example, the scheduler 201 arranges the data access instructions in the data request list 203 in the order of the physical distance from small to large in different channels when sending the data access instructions, and obtains the instruction sending order of the data access instructions in the data request list 203. The data access instructions are sent in the order.

[0152] For example, in some embodiments, as shown in FIG. 6, the state item can further include a priority. The channel number and the priority together indicate the position of the data access instruction in the instruction sending order.

[0153] For example, when the state item includes the priority, as described above, the scheduler 201 first considers the priority when sending the data access instructions in the data request list 203, and sends the data access instructions with high priority first. Then, for other data access instructions with low priority, the data access instructions are sent in the order of the physical distance from small to large in different channels.

[0154] For example, the state item can only include the channel number without the priority, and the position of the data access instruction in the instruction sending order is determined by the channel number. For example, the state item can include both the channel number and the priority, and the position of the data access instruction in the instruction sending order is determined by the channel number and the priority.

[0155] For example, as shown in FIG. 6, the state item further includes request receiving state information and request sending state information, which are used to indicate the current state of the data access instruction. The user can monitor the state of the data access instruction according to the request receiving state information and the request sending state information.

[0156] For example, the request receiving state information includes three states: the first state is that the request has not been received, for example, the state item is not bound to any data access instruction after initialization; the second state is that the request is being received, for example, the previous data agent module is synchronizing the data access instruction; and the third state is that the request already exists, for example, the state item has the corresponding data access instruction, for example, the request number of the data access instruction has been filled in the corresponding position of the state item.

[0157] For example, the request sending state information includes three states: a first state is that no request is received, for example, the state item is not bound to any data access instruction after initialization; a second state is that a request is being sent, for example, a data access instruction is being synchronized or sent to a memory or a next level data agent module; and a third state is that a request has been sent, for example, the request has been sent completely.

[0158] For example, as shown in FIG. 6, the state item further includes data state information, which is used to indicate a current state of the destination data returned by the data access instruction.

[0159] For example, the data state information includes four states: a first state is empty, for example, the state item is not bound to any data access instruction after initialization; a second state is waiting for data, for example, the data access instruction or the data request signal has been sent and is waiting for data return; a third state is receiving data, indicating that the data has been returned from the memory or the next level data agent module; and a fourth state is that data already exists, for example, the data has been cached to the corresponding cache block.

[0160] The specific settings of the request receiving state information, the request sending state information and the data state information can be adjusted as needed, and the present disclosure does not make specific limitations thereon.

[0161] For example, before executing a task, each data agent module is initialized.

[0162] For example, the first level data agent module is configured to, before executing a task, select at least one data access instruction from the data access instruction sequence in the order of the data access instruction sequence, and perform an initialization operation on the at least one data access instruction. Here, the at least one data access instruction is executed by a computing core electrically connected to the first level data agent module.

[0163] For example, the first level data agent module selects at least one data access instruction from the data access instructions executed by the computing core electrically connected to the first level cache node corresponding to the first level data agent module, in the order of the data access instructions in the data access instruction sequence, which is the original order of the data access instruction sequence, that is, the order of the data access instructions appearing in the program code corresponding to the task. In the initialization stage before the task is executed, P data access instructions are selected and cached into the data request list to perform the initialization operation, and after the task starts to be executed, when the destination data of a data access instruction is sent to the destination register, one or more data access instructions that have not been sent are selected from the data access instruction sequence in order and cached into the data request list to perform the initialization operation.

[0164] For example, the first-level data agent module performs an initialization operation on the at least one data access instruction, including the following operations: caching the at least one data access instruction into a data request list of the first-level data agent module; initializing a state item corresponding to the at least one data access instruction and storing the state item into a request state list of the first-level data agent module; and synchronizing the at least one data access instruction and the corresponding state item to other-level data agent modules which have a direct or indirect electrical connection relationship with the first-level data agent module.

[0165] For example, when the first-level data agent module caches the at least one data access instruction into a data request list of the first-level data agent module, the at least one data access instruction is cached into a corresponding channel according to a physical distance corresponding to the at least one data access instruction.

[0166] For example, when the first-level data agent module initializes the state item corresponding to the at least one data access instruction, a cache block number and a request number in the state item are set to determine the data access instruction corresponding to the state item and the associated cache block. The specific process is described below and will not be repeated here.

[0167] According to the read address in the data access instruction, the physical distance corresponding to the data access instruction can be determined to set the channel number in the state item; when the state item includes a priority, the priority of the data access instruction obtained can also be used to set the priority in the state item.

[0168] In addition, the request receiving state information, the request sending state information and the data state information are set to initial values, which will not be repeated here.

[0169] Then, the first-level data agent module synchronizes the data access instructions and the corresponding state items to other-level data agent modules which have a direct or indirect electrical connection relationship with the first-level data agent module.

[0170] For example, the other-level data agent modules include a second-level data agent module to an Nth-level data agent module, and the electrical connection relationship is determined according to the electrical connection relationship between the corresponding cache nodes. For example, the synchronized information includes instruction information of the data access instruction, the state item, etc. For example, after synchronization, the data request list of the other-level data agent module also stores the data access instructions to be sent, and the request state list stores the corresponding state items. For example, for the Nth-level data agent module, all data access instructions selected by the first-level data agent module and the state items are stored.

[0171] For example, in response to an unassociated cache block existing in the data agent module, the unassociated cache block is associated with a data access instruction selected from the data request list of the data agent module in the instruction sending order. For example, the unassociated cache block refers to the cache block that has not been associated with any data access instruction, and the unassociated cache block can be determined by the request number and the cache block number in the state item.

[0172] For example, when the data agent module performs the operation of associating the unassociated cache block with the data access instruction selected from the data request list of the data agent module in the instruction sending order, the operation includes the following operations: setting the request number of the data access instruction and the cache block number of the unassociated cache block in the state item corresponding to the data access instruction, so as to associate the unassociated cache block with the data access instruction.

[0173] For example, the Nth data agent module is configured to: send the data access instructions cached in the data request list of the Nth data agent module to the memory in the instruction sending order; and receive the target data returned from the memory in sequence and store each returned target data in the cache block associated with the data access instruction.

[0174] That is, when the first block of data is started to be moved, the Nth data agent module sends the data access instruction determined to be sent earliest according to the instruction sending order to the memory, and stores the received target data in the cache block associated with the data access instruction. If there is a free cache block, the data access instruction determined to be sent second according to the instruction sending order is sent to the memory, and the received target data is stored in the cache block associated with the data access instruction. The above operations are repeated.

[0175] For the first data agent module to the (N-1)th data agent module, that is, the ith data agent module, the configuration is that, in response to the existence of the cache block in the idle state in the ith data agent module, a data request signal is sent to the (i+1)th data agent module connected by electricity, and the received return data is cached in the cache block associated with the data access instruction corresponding to the data request signal. For example, the (i+1)th data agent module is configured to, in response to receiving the data request signal, send the target data of the data access instruction corresponding to the data request signal to the ith data agent module sending the data request signal.

[0176] For example, the cache block in the idle state refers to the cache block that has an associated data access instruction, but has no stored data and has not sent the data access instruction associated with the cache block. The cache block in the idle state can be determined by the data state information and the request sending state information.

[0177] For example, the i-th data agent module discovers that there is a cache block in an idle state, and sends a data request signal NEED_DATA to the (i+1)-th data agent module. Upon receiving the data request signal NEED_DATA, the (i+1)-th data agent module determines the destination data of the data access instruction corresponding to the data request signal NEED_DATA from the cache block, and sends the destination data to the i-th data agent module. The i-th data agent module caches the received return data in the cache block associated with the data access instruction corresponding to the sent data request signal.

[0178] Through the above process, the N-th data agent module caches the destination data read from the memory in the cache block of the N-th data agent module, the (N-1)-th data agent module obtains the destination data from the N-th data agent module and caches it in the cache block of the (N-1)-th data agent module, and so on, until the destination data is cached in the cache block of the first data agent module. Moreover, each data agent module obtains the destination data in the same instruction sending order.

[0179] In this way, the data access instruction can be sent early, and the data of the memory can be cached in the first data agent module in advance. When the destination data is used, the data can be directly read from the first data agent module, without the need to read the data from the memory, thereby reducing the data waiting time. Moreover, the data is cached in the cache block of the first data agent module, so even if the data access instruction is sent early, the destination register does not need to be occupied in advance, the occupation time of the destination register is reduced, resource consumption is reduced, and data access efficiency is improved.

[0180] For example, the first data agent module is further configured to: in response to receiving a data access instruction sent by a computing core electrically connected to the first cache node corresponding to the first data agent module, determine a cache block associated with the sent data access instruction, and send the data in the associated cache block to a destination register indicated by the data access instruction; clear the data access instruction associated with the associated cache block from the data request list of the first data agent module, and empty the state item corresponding to the cleared data access instruction in the request state list of the first data agent module; select at least one data access instruction in sequence from the data access instruction sequence, and perform an initialization operation on the at least one data access instruction.

[0181] For example, after sending the data to the compute core, the first level data agent module clears the data access instruction from the data request list and clears the state item corresponding to the cleared data access instruction in the request state list, which can be used for other data access instructions. Then, one data access instruction is selected from the data access instruction sequence and cached in the data request list, and the initialization operation is performed according to the foregoing process, for example, including setting the state item, caching the corresponding channel in the data request list according to the physical distance corresponding to the data access instruction, synchronizing to other level data agent modules, and the like, which will not be described herein again.

[0182] For other level data agent modules, taking the i+1 level data agent module as an example, the i+1 level data agent module is further configured to, in response to the data in any cache block in the i+1 level data agent module being sent to the i level data agent module, clear the data access instruction associated with the cache block from the data request list of the i+1 level data agent module, and clear the state item corresponding to the cleared data access instruction in the request state list of the i+1 level data agent module.

[0183] For example, after clearing and clearing the information related to the data access instruction, the i+1 level data agent module can associate the cache block with other unassociated data access instructions in the data request list.

[0184] FIG. 7 is a schematic block diagram of a data processor provided by at least one embodiment of the present disclosure.

[0185] For example, the data processor shown in FIG. 7 can be a general-purpose graphics processor or a graphics processor. The data processor includes a plurality of compute units. The structure in FIG. 7 can refer to the related description of FIG. 2, which will not be described herein again.

[0186] For example, N=2, the first level cache in the N level cache includes a plurality of first level cache nodes, each of which is used for data sharing within one compute unit, and each of which can be an L1 cache or a shared memory in FIG. 7. The second level cache in the N level cache includes one second level cache node, which is used for data sharing between all compute units, and the second level cache node can be an L2 cache, i.e., a global cache in FIG. 7.

[0187] For example, each first level cache node corresponds to one first level data agent module, and the second level cache node corresponds to one second level data agent module. For example, taking FIG. 7 as an example, one first level data agent module is provided in each compute unit in FIG. 7, and the first level data agent module is electrically connected with all compute cores in the compute unit; one second level data agent module corresponding to the L2 cache is provided, and the second level data agent module is electrically connected with the memory and all first level data agent modules.

[0188] For example, the data processor shown in FIG. 7 is taken as an example to specifically describe the scheduling of the multi-level data agent module and the specific process of data caching.

[0189] FIGS. 8A to 8G are schematic diagrams of the processing process of the multi-level data agent module according to at least one embodiment of the present disclosure.

[0190] First, as shown in FIG. 8A, the computing core initializes the data agent modules of each level before starting to execute the task.

[0191] For example, the initialization of the data agent modules of each level includes allocating cache blocks for each data agent module, for example, selecting some cache lines or memory lines from the 1st cache node or shared memory to map as cache blocks in the 1st data agent module, and selecting some cache lines from the 2nd cache node to map as cache blocks in the 2nd data agent module. In addition, the 1st data agent module also selects some data access instructions in sequence from the data access instruction sequence and performs initialization operations on these data access instructions. For example, the initialization operations include caching these data access instructions into the corresponding channels in the data request list of the 1st data agent module, initializing the state items corresponding to these data access instructions and storing them in the request state list of the 1st data agent module, and synchronizing these data access instructions and the corresponding state items to other data agent modules (i.e., the 2nd data agent module) that have a direct or indirect electrical connection relationship with the 1st data agent module. The specific process is as described above, and will not be described here again.

[0192] After initializing the data agent modules of each level, the data request list of each data agent module caches the data access instructions to be sent, and the cached data access instructions are classified according to the channels, in addition, the state items corresponding to the data access instructions are also initialized and set and stored in the request state list of each data agent module.

[0193] For example, as shown in FIG. 8A, five data access instructions are cached in the first channel, which are data access instruction Req#0, data access instruction Req#1, data access instruction Req#2, data access instruction Req#3, and data access instruction Req#4 in FIG. 8A. For example, the 1st data agent module includes multiple channels, each of which can cache up to five data access instructions, and the data access instructions are selected in the order from front to back in the data access instruction sequence. Assuming that the first data access instruction Req#0 in the data access instruction sequence corresponds to a small physical distance, for example, the read address of the data access instruction Req#0 is in the near-end memory, then it is cached in the first channel, and so on. For example, the first channel is a fast channel, and the order of the data access instruction Req#0 to the data access instruction Req#4 is the same as the relative order in the data access instruction sequence.

[0194] For example, as shown in FIG. 8A, each data agent module provides 2 cache blocks, namely cache block 0 and cache block 1, in each data agent module, for example, in the initialization stage, data access instruction Req#0 is associated with cache block 0, and data access instruction Req#1 is associated with cache block 1.

[0195] Then, as shown in FIG. 8B, when the first block of data starts to be moved, the second-level data agent module selects a data access instruction from the data request list according to the instruction sending order and sends it to the memory, for example, the first data access instruction Req#0 in the first channel (fast channel) is selected and sent to the memory, and the destination data Data#0 of the data access instruction Req#0 returned by the memory is stored in the cache block 0 of the second-level data agent module associated with the data access instruction Req#0.

[0196] Then, as shown in FIG. 8C, the second block of data starts to be moved and the destination data Data#0 is returned to the first-level data agent module.

[0197] For example, since the cache block 1 in the second-level data agent module is in an idle state, the scheduler of the second-level data agent module sends data access instruction Req#1 to the memory, and the destination data Data#1 of the data access instruction Req#1 returned by the memory is stored in the cache block 1 of the second-level data agent module associated with the data access instruction Req#1.

[0198] For example, since the cache block 0 in the first-level data agent module is in an idle state, the scheduler of the first-level data agent module sends a data request signal to the second-level data agent module, which indicates that the destination data of the data access instruction Req#0 is needed. After receiving the data request signal, the second-level data agent module sends the destination data Data#0 to the first-level data agent module, and clears the data access instruction Req#0 from the data request list of the second-level data agent module, and clears the state item corresponding to the data access instruction Req#0 in the request state list, that is, at this time, the cache block 0 of the second-level data agent module can be associated with other data access instructions, for example, associated with data access instruction Req#2. After receiving the destination data Data#0, the first-level data agent module stores it in the cache block 0 associated with the data access instruction Req#0.

[0199] For example, as shown in FIG. 8D, when the core sends the data access instruction Req#0 to the first level data agent module, the first level data agent module returns the data Data#0 in the cache block 0 associated with the data access instruction Req#0 to the destination register. Then, the data access instruction Req#0 is removed from the data request list of the first level data agent module, and the state item corresponding to the data access instruction Req#0 in the request state list of the first level data agent module is emptied, i.e., at this time, the cache block 0 can be associated with other data access instructions, for example, the data access instruction Req#2.

[0200] Then, as shown in FIG. 8E, the first level data agent module selects the data access instruction Req#5 from the data access instruction sequence in sequence and caches the data access instruction Req#5 into the data request list of the first level data agent module, for example, the data access instruction Req#5 has a smaller physical distance and is classified into the first channel. At the same time, the state item corresponding to the data access instruction Req#5 is initialized and stored in the request state list of the first level data agent module, and the data access instruction Req#5 and the corresponding state item are synchronized to the second level data agent module.

[0201] For example, as shown in FIG. 8E, since the cache block 1 in the first level data agent module is in an idle state, the scheduler of the first level data agent module sends a data request signal to the second level data agent module, which indicates that the destination data of the data access instruction Req#1 is needed. After receiving the data request signal, the second level data agent module sends the destination data Data#1 to the first level data agent module, and removes the data access instruction Req#1 from the data request list of the second level data agent module, and empties the state item corresponding to the data access instruction Req#1 in the request state list, i.e., at this time, the cache block 1 of the second level data agent module can be associated with other data access instructions, for example, the data access instruction Req#3. After receiving the destination data Data#1, the first level data agent module stores the destination data Data#1 in the cache block 1 associated with the data access instruction Req#1.

[0202] As shown in FIG. 8E, since the cache block 0 in the second level data agent module is in an idle state again, the scheduler of the second level data agent module sends the data access instruction Req#2 to the memory, and stores the destination data Data#2 of the data access instruction Req#2 returned by the memory into the cache block 0 of the second level data agent module associated with the data access instruction Req#2.

[0203] For example, as shown in FIG. 8F, when the core sends the data access instruction Req#1 to the first level data agent module, the first level data agent module returns the data Data#1 in the cache block 1 associated with the data access instruction Req#1 to the destination register. Then, the data access instruction Req#1 is removed from the data request list of the first level data agent module, and the state item corresponding to the data access instruction Req#1 in the request state list of the first level data agent module is emptied, i.e., at this time, the cache block 1 can be associated with other data access instructions, for example, the data access instruction Req#3.

[0204] Then, as shown in FIG. 8G, the first level data agent module selects the data access instruction Req#6 from the data access instruction sequence in sequence and caches the data access instruction Req#6 into the data request list of the first level data agent module, for example, the data access instruction Req#6 corresponds to a smaller physical distance and is classified into the first channel. At the same time, the state item corresponding to the data access instruction Req#6 is initialized and stored in the request state list of the first level data agent module, and in addition, the data access instruction Req#6 and the corresponding state item are synchronized to the second level data agent module.

[0205] For example, as shown in FIG. 8G, since the cache block 0 in the first level data agent module is in an idle state, the scheduler of the first level data agent module sends a data request signal to the second level data agent module, which indicates that the destination data of the data access instruction Req#2 is needed. After receiving the data request signal, the second level data agent module sends the destination data Data#2 to the first level data agent module, and removes the data access instruction Req#2 from the data request list of the second level data agent module, and empties the state item corresponding to the data access instruction Req#2 in the request state list, i.e., at this time, the cache block 0 of the second level data agent module can be associated with other data access instructions, for example, the data access instruction Req#4. After receiving the destination data Data#2, the first level data agent module stores it in the cache block 0 associated with the data access instruction Req#2.

[0206] For example, as shown in FIG. 8G, since the cache block 1 in the second level data agent module is in an idle state again, the scheduler of the second level data agent module sends the data access instruction Req#3 to the memory, and stores the destination data Data#3 of the data access instruction Req#3 returned by the memory into the cache block 1 of the second level data agent module associated with the data access instruction Req#3.

[0207] The above process is repeatedly performed, so that the data access instructions are sequentially sent according to the instruction sending order, and the destination data returned by each data access instruction is cached in the corresponding first-level data agent module, for example, in the first-level cache node corresponding to the first-level data agent module. Thus, even if the data access instruction is sent early, the register does not need to be occupied early, the occupation time of the register is reduced, and even if the data access instruction is sent late, for example, when the destination data is needed, since only the data needs to be read in the first-level data agent module, the overall waiting time is short, and the data access efficiency is improved.

[0208] In addition, the instruction sending order is determined according to the original order of the data access instruction sequence and the distance between the storage position of the destination data of each data access instruction and the computing core, the data access instruction with a short distance is sent first, and the data access instruction with a long distance is sent later, so as to avoid that a slow request squeezes the bandwidth of a fast request; in some embodiments, the instruction sending order is determined according to the original order of the data access instruction sequence, the distance between the storage position of the destination data of each data access instruction and the computing core, and the priority of each data access instruction, the data access instruction with a high priority can be sent as early as possible, so that the return time meets the user's expectation.

[0209] FIG. 9A is a timing diagram of a data processor according to at least one embodiment of the present disclosure.

[0210] As shown in FIG. 9A, the computing core caches the destination data from the memory into the L1 cache at an early time according to the above process, and compared with the timing diagram shown in FIG. 4A, since only the destination data needs to be read in the first-level data agent module, the overall waiting time is short.

[0211] In addition, since only the destination data needs to be read in the first-level data agent module, as shown in FIG. 9A, compared with the timing diagrams shown in FIG. 4B and FIG. 4C, the register occupation time is greatly reduced, the resource consumption is reduced, and the data access efficiency is improved.

[0212] FIG. 9B is a timing diagram of a data processor according to at least one embodiment of the present disclosure.

[0213] As shown in FIG. 9B, the computing core caches the destination data from the memory into the L1 cache at an early time according to the above process, and compared with the timing diagram shown in FIG. 4D, the register occupation time is short; and the present disclosure sends the data access instructions in the unit of channel, the data access instruction with a short distance from the computing core is sent first, and the data access instruction with a long distance from the computing core is sent later, so as to avoid that a slow request squeezes the bandwidth of a fast request; in addition, the data access request can also be set with a priority, so that the data access instruction with a high priority can be sent as early as possible, and the data return time meets the user's expectation.

[0214] It should be noted that the components and structures of the data processor 100 shown in FIG. 5 and the like are only exemplary and are not restrictive, and the data processor 100 can also have other components and structures as needed.

[0215] For example, the modules can be implemented by hardware (for example, circuit) modules, software modules, or any combination of the two, and the following embodiments are the same, which will not be repeated here.

[0216] For example, the data processor can be a central processing unit (CPU), a graphics processor, a general-purpose graphics processor, a digital signal processor, or the like, or a tensor processing unit (TPU), a neural network processor (NPU), or the like, or other forms of processing units with data processing capabilities and / or instruction execution capabilities and corresponding computer instructions to implement these units.

[0217] It should be noted that in the embodiments of the present disclosure, the data processor 100 can include more or fewer circuits or units, and the connection relationship between the circuits or units is not limited and can be determined according to actual needs. The specific constituting manner of each circuit or unit is not limited and can be constituted by an analog device according to the circuit principle, or can be constituted by a digital chip, or constituted in other applicable manners.

[0218] The present disclosure at least one embodiment also provides a data processing method. FIG. 10 is a schematic flowchart of a data processing method provided by at least one embodiment of the present disclosure.

[0219] For example, the data processing method is used for a data processor including N-level caches and a memory.

[0220] For example, the data processor can be a central processing unit (CPU), a graphics processor, a general-purpose graphics processor, a tensor processing unit (TPU), a neural network processor (NPU), and the like, and the present disclosure does not make specific limitations.

[0221] For example, the data processor can adopt a similar architecture as shown in FIG. 1 or FIG. 2 as described above.

[0222] The i-th cache in the N-level cache includes at least one i-level cache node, at least part of the at least one i-level cache node shares one i+1-level cache node, N is a positive integer greater than 1, and i is any positive integer between 1 and N-1.

[0223] The N-th cache in the N-level cache is electrically connected with the memory, and each 1-level cache node is electrically connected with a corresponding calculation core.

[0224] For the related content of the N-level cache, the memory, and the calculation core, reference can be made to the related description of the aforementioned data processor, and the repeated parts will not be repeated here.

[0225] As shown in FIG. 10, the data processing method provided by at least one embodiment of the present disclosure at least includes steps S10-S40.

[0226] In step S10, a data access instruction sequence in a task currently executed by the data processor is acquired.

[0227] For example, the data access instruction sequence is obtained by arranging all data access instructions in the task according to the position relationship in the corresponding program.

[0228] The specific content of acquiring the data access instruction sequence can refer to the description of the related part of the foregoing data processor, and the repeated part will not be described herein.

[0229] In step S20, the sending order of the data access instruction sequence is adjusted according to the storage position of the target data of each data access instruction in the data access instruction sequence.

[0230] For example, in some embodiments, step S20 can include: acquiring a physical distance corresponding to each data access instruction, wherein the physical distance corresponding to each data access instruction is the physical distance between the storage position of the target data of each data access instruction in the memory and the computing core in the data processor; and adjusting the sending order of the data access instruction sequence according to the physical distance corresponding to each data access instruction, wherein the data access instruction with smaller corresponding physical distance is sent earlier.

[0231] For example, the physical distance corresponding to each data access instruction can be acquired through the read address in each data access instruction.

[0232] According to the different physical distances corresponding to each data access instruction, the sending order of the data access instruction sequence is adjusted, for example, the sending order is adjusted according to the physical distance corresponding to each data access instruction on the basis of the original data access instruction sequence. For example, the data access instruction with smaller corresponding physical distance is sent earlier, i.e., placed in the front position in the sending order; the data access instruction with larger corresponding physical distance is sent later, i.e., placed in the rear position in the sending order. For example, the data access instructions with the same corresponding physical distance are sent in turn according to the relative order relationship in the data access instruction sequence.

[0233] For example, the adjusting the instruction sending sequence of the data access instruction sequence according to the physical distance corresponding to each data access instruction can include: classifying each data access instruction into different channels according to the physical distance corresponding to each data access instruction, wherein the data access instructions in different channels correspond to different physical distances; and arranging the data access instructions in each channel in order of the physical distance corresponding to the data access instructions in different channels from small to large, to obtain the instruction sending sequence, wherein in the instruction sending sequence, the data access instructions belonging to a first channel are sent first, the data access instructions belonging to a second channel are sent last, the data access instructions belonging to the same channel are sent in series according to the relative order relationship in the data access instruction sequence, the data access instructions in the first channel correspond to the smallest physical distance, and the data access instructions in the second channel correspond to the largest physical distance.

[0234] For example, a plurality of channels can be provided in the data proxy module, and the data access instructions can be classified into different channels according to the corresponding physical distance. For example, the data access instructions whose destination data are in the same memory block can be classified into one channel, or the data access instructions whose destination data are in several memory blocks that are relatively close can be placed in one channel.

[0235] More details about the adjusting the instruction sending sequence of the data access instruction sequence according to the physical distance corresponding to each data access instruction can be referred to the related description in the foregoing data processor, and the repeated parts will not be described herein.

[0236] In the foregoing embodiments, the channels are introduced for the classification and management of the data access instructions, the data access instructions are classified into different channels according to the distance between the storage location of the destination data to be loaded and the computing core, the data access instructions with a short physical distance are sent preferentially, the data access instructions with a long physical distance are sent later, the data access instructions corresponding to different physical distances are sent separately, the bandwidth of the data access instructions with a short distance is prevented from being squeezed by the data access instructions with a long distance, and the return time of the destination data is made to meet the user's expectation as much as possible.

[0237] For example, in some other embodiments, the step S20 can include: obtaining the priority of each data access instruction; obtaining the physical distance corresponding to each data access instruction, wherein the physical distance corresponding to each data access instruction is the physical distance between the storage location of the destination data of each data access instruction in the memory and the computing core in the data processor; and adjusting the instruction sending sequence of the data access instruction sequence according to the priority and the corresponding physical distance of each data access instruction, wherein the data access instruction with a higher priority is sent earlier, and the data access instruction corresponding to a smaller physical distance is sent earlier in the case of the same priority.

[0238] For example, the priority of each data access instruction can be obtained according to the time at which each data access instruction returns the destination data when the task is pre-run, wherein each data access instruction is sent in sequence according to the order in the data access instruction sequence, and the time at which each data access instruction returns the destination data is collected.

[0239] For more details about obtaining the priority of each data access instruction, refer to the foregoing description of the data processor.

[0240] In the adjusted instruction sending order, the priority of the data access instruction is considered first, and then the channel to which the data access instruction belongs is considered. For example, the data access instruction with a higher priority is sent earlier, even if the data access instruction belongs to a slow channel. Other data access instructions (for example, with a lower priority but located in a fast channel) are sent after a corresponding clock cycle. If the priorities are the same, the data access instructions are sent according to the order of the physical distances corresponding to the data access instructions from small to large. Specifically, refer to the foregoing description of classifying the data access instructions into different channels, arranging the data access instructions in each channel in the order of the physical distances corresponding to the data access instructions from small to large, and obtaining the instruction sending order in the unit of the channel.

[0241] In this embodiment, the priority of each data access instruction is set so that a high priority can be sent as soon as possible, and the return time meets the user's expectation. In addition, the data access instructions are sent in multiple channels, and the data access instructions in the fast and slow channels are sent separately to avoid that a slow request with a longer time consumption from the slow channel squeezes the bandwidth of a fast request with a shorter time consumption from the fast channel.

[0242] For more details about adjusting the instruction sending order of the data access instruction sequence according to the priority and the physical distance, refer to the foregoing description of the data processor.

[0243] In step S30, each data access instruction is sent in sequence according to the instruction sending order.

[0244] For example, each data access instruction is sent to the memory in sequence according to the instruction sending order.

[0245] In step S40, the destination data returned by each data access instruction is cached in a first-level cache node or a shared memory that is electrically connected to the computing core that uses the destination data.

[0246] For example, the first-level cache node can be an L1 cache, and the shared memory can be the shared memory in the computing unit shown in FIG. 2.

[0247] The data processing method provided by at least one embodiment of the present disclosure can cache target data in advance into a storage component closest to the calculation core, such as an L1 cache or a shared memory, so that even if the time of sending a data access instruction is relatively late, the overall waiting time is relatively short because the target data only needs to be read from the L1 cache or the shared memory, and the register occupation time is greatly reduced, the resource consumption is reduced, and the data access efficiency is improved. Moreover, in the data processing method, the data access instructions are sent in channels, the data access instructions close to the calculation core are sent first, and the data access instructions far from the calculation core are sent later, so as to avoid that slow requests squeeze the bandwidth of fast requests as much as possible. In addition, the data access requests can also be set with priorities, so that the data access instructions with high priorities can be sent as soon as possible, and the data return time meets the user's expectation.

[0248] For example, the data processor further comprises N-level data agent modules, wherein each data agent module in the N-level data agent modules corresponds to each cache in the N-level cache. For example, the N-level data agent modules can be used to implement steps S10-S40 as described above. For specific processes of implementing steps S10-S40 as described above by using the N-level data agent modules, reference can be made to the related description of the foregoing data processor, and repeated descriptions are not repeated.

[0249] Of course, the present disclosure is not limited thereto, and other ways can also be used to implement steps S10-S40 as described above, such as using other module structures or program codes to implement the data processing method described in at least one embodiment of the present disclosure, and the present disclosure does not make specific limitations thereto.

[0250] FIG. 11 is a schematic block diagram of an electronic device according to an embodiment of the present disclosure. As shown in FIG. 11, the electronic device 300 is suitable for implementing the data processing method provided by the embodiments of the present disclosure. It should be noted that the components of the electronic device 300 shown in FIG. 11 are only exemplary and are not limiting, and the electronic device 300 can also have other components according to actual application needs.

[0251] As shown in FIG. 11, the electronic device 300 can include a processing device (such as a central processing unit, a graphics processing unit, etc.) 301, which can perform various appropriate actions and processes according to non-transitory computer-readable instructions stored in a memory to implement various functions.

[0252] For example, when the computer-readable instructions are run by the processing device 301, one or more steps in the data processing method according to any of the above embodiments can be performed. It should be noted that the detailed description of the processing process of the data processing method can refer to the related description in the above embodiments of the data processing method, and repeated descriptions are not repeated.

[0253] For example, the memory can include any combination of one or more computer program products, which can include various forms of computer-readable storage media, for example, volatile memory and / or non-volatile memory. Volatile memory, for example, can include random access memory (RAM) 303 and / or cache, etc., for example, computer-readable instructions can be loaded from the storage 308 into the random access memory (RAM) 303 to run the computer-readable instructions. Non-volatile memory, for example, can include read-only memory (ROM) 302, a hard disk, an erasable programmable read-only memory (EPROM), a portable compact disc read-only memory (CD-ROM), a USB memory, a flash memory, etc. Various application programs and various data, for example, style images, and various data used and / or generated by the application programs, etc., can also be stored in the computer-readable storage medium.

[0254] For example, the processing device 301, the read-only memory 302, and the random access memory 303 are connected to each other through the bus 304. The input / output (I / O) interface 305 is also connected to the bus 304.

[0255] Generally, the following devices can be connected to the input / output interface 305: input devices 306 including, for example, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; output devices 307 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; storage devices 308 including, for example, a magnetic tape, a hard disk, a flash memory, etc.; and communication devices 309. The communication devices 309 can allow the electronic device 300 to communicate wirelessly or wired with other electronic devices to exchange data. Although FIG. 11 shows the electronic device 300 with various devices, it should be understood that it is not required to implement or have all the shown devices, and the electronic device 300 can instead implement or have more or less devices. For example, the processor 301 can control other components in the electronic device 300 to perform desired functions. The processor 301 can be a central processing unit, a tensor processing unit, or a graphics processing unit, etc., which has data processing capability and / or program execution capability. The central processing unit can be X86 or ARM architecture, etc. The graphics processing unit can be integrated on the motherboard directly, or built-in in the north bridge chip of the motherboard. The graphics processing unit can also be built-in on the central processing unit.

[0256] The technical effects of the electronic device 300 shown in FIG. 11 are the same as the technical effects of the data processing method provided by the present disclosure, which will not be repeated here.

[0257] FIG. 12 is a schematic diagram of a non-transitory computer-readable storage medium according to at least one embodiment of the present disclosure. For example, as shown in FIG. 12, the storage medium 400 can be a non-transitory computer-readable storage medium, and one or more computer-readable instructions 401 can be stored on the storage medium 400 in a non-transitory manner. For example, when the computer-readable instructions 401 are executed by a processor, the data processing method according to the above description can be performed.

[0258] For example, the storage medium 400 can be applied to the electronic device described above. For example, the storage medium 400 can include the memory in the electronic device 300.

[0259] For example, the storage medium can include a memory card of a smart phone, a memory component of a tablet computer, a hard disk of a personal computer, a random access memory, a read-only memory, an erasable programmable read-only memory, a portable compact disc read-only memory, a flash memory, or any combination of the above storage media, or other applicable storage media.

[0260] For example, the description of the storage medium 400 can refer to the description of the memory in the embodiments of the electronic device, and the repeated description will not be repeated.

[0261] Some embodiments of the present disclosure further provide another electronic device. FIG. 13 is a schematic block diagram of another electronic device according to at least one embodiment of the present disclosure.

[0262] For example, as shown in FIG. 13, the electronic device 500 can include a data processor 501 according to any embodiment of the present disclosure. For example, the data processor 501 can be the data processor 100 described above, and the repeated description will not be repeated.

[0263] It should be noted that the components of the electronic device 500 shown in FIG. 13 are exemplary and non-limiting, and the electronic device 500 can further have other components according to actual application needs, for example, including more or fewer circuits or units, for example, further including other circuits or units supporting the operation of the data processor 501, and the present disclosure does not make specific limitations thereto.

[0264] The connection relationship between each circuit or unit is not limited and can be determined according to actual needs. The specific constituting manner of each circuit or unit is not limited and can be constituted by an analog device according to the circuit principle, or can be constituted by a digital chip, or constituted in other applicable manners.

[0265] Those skilled in the art can understand that the disclosed content of the present disclosure can have various modifications and improvements. For example, the various devices or components described above can be implemented by hardware, or implemented by software, firmware, or a combination of some or all of the three.

[0266] Furthermore, while the present disclosure has been described with respect to certain embodiments only, many modifications can be made by those skilled in the art, having the benefit of the teachings of the present disclosure, without departing from the scope of the present disclosure. Therefore, the scope of the present disclosure is not intended to be limited to the described embodiments but is to be accorded the full scope consistent with the claims, the full scope of which depends on the following claims and equivalents thereof.

[0267] Flow diagrams have been used herein to illustrate the steps of methods in accordance with embodiments of the present disclosure. It should be understood that the steps need not necessarily be performed in the order shown. Rather, various steps can be performed in different order or simultaneously. Other operations can also be added to the processes.

[0268] It is understood by those skilled in the art that all or part of the steps of the above method can be instructed by a computer program to relevant hardware, and the program can be stored in a computer readable storage medium, such as a read-only memory, a magnetic disk or an optical disk. Alternatively, all or part of the steps of the above embodiments can also be implemented using one or more integrated circuits. Accordingly, each module / unit in the above embodiments can be implemented in the form of hardware or in the form of a software functional module. The present disclosure is not limited to any specific form of combination of hardware and software.

[0269] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0270] The above is a description of the present disclosure and should not be considered as a limitation. Although several exemplary embodiments of the present disclosure are described, those skilled in the art will readily understand that many modifications can be made to the exemplary embodiments without departing from the novel teachings and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure defined by the claims. It should be understood that the above is a description of the present disclosure and should not be considered as a limitation. The disclosed embodiments are not intended to be limited to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The present disclosure is defined by the claims and their equivalents.

Claims

1. A data processor comprising an N-level cache and a memory, wherein an i-th level cache in the N-level cache comprises at least one i-level cache node, at least some of the at least one i-level cache node share an i+1-level cache node, where N is a positive integer greater than 1, and i is any positive integer between 1 and N-1. The Nth level cache in the N-level cache is electrically connected to the memory, and each level 1 cache node is electrically connected to the corresponding computing core. The data processor also includes an N-level data proxy module, wherein: Each level of data proxy module in the N-level data proxy module corresponds to each level of cache in the N-level cache in a one-to-one manner. The N-level data proxy module is configured to obtain a data access instruction sequence in a task currently executed by the data processor, adjust an instruction sending order of the data access instruction sequence according to a storage position in the memory of the destination data of each data access instruction in the data access instruction sequence, send each data access instruction in sequence according to the instruction sending order, and cache the destination data returned by each data access instruction in a corresponding first-level data proxy module, wherein the corresponding first-level data proxy module corresponds to a first-level cache.

2. The data processor according to claim 1, wherein: When the N-level data proxy module adjusts the instruction sending order of the data access instruction sequence according to the storage position of the destination data of each data access instruction in the data access instruction sequence in the memory, the N-level data proxy module includes the following operations: Obtaining a physical distance corresponding to each data access instruction, wherein the physical distance corresponding to each data access instruction is a distance between a storage location of target data of each data access instruction in the memory and a computing core in the data processor; The instruction sending order is adjusted according to the physical distances corresponding to the data access instructions, wherein the data access instruction with a smaller corresponding physical distance is sent earlier.

3. The data processor according to claim 2, wherein: When the N-level data proxy module adjusts the instruction sending order of the data access instruction sequence according to the physical distance corresponding to each data access instruction, the N-level data proxy module includes performing the following operations: Classifying the data access instructions into different channels according to the physical distances corresponding to the data access instructions, wherein the physical distances corresponding to the data access instructions in different channels are different; Arrange the data access instructions in each channel in ascending order of the physical distances corresponding to the data access instructions in each channel, using the channel as a unit, to obtain the instruction sending order. Among them, in the instruction sending order, the data access memory instruction belonging to the first channel is sent first, and the data access memory instruction belonging to the second channel is sent last. The data access memory instructions belonging to the same channel are sent serially according to the relative order relationship in the data access memory instruction sequence. The physical distance corresponding to the data access memory instruction in the first channel is the smallest, and the physical distance corresponding to the data access memory instruction in the second channel is the largest.

4. The data processor according to claim 2, wherein: The N-level data proxy module adjusts the instruction sending order of the data access instruction sequence according to the storage location of the destination data of each data access instruction in the data access instruction sequence in the memory, including performing the following operations: Get the priority of each data access instruction; Obtaining a physical distance corresponding to each data access instruction, wherein the physical distance corresponding to each data access instruction is a distance between a storage location of target data of each data access instruction in the memory and a computing core in the data processor; The instruction sending order is adjusted according to the priority of each data access instruction and the corresponding physical distance, wherein, in the instruction sending order, the data access instruction with a higher priority is sent earlier, and under the same priority, the data access instruction with a smaller corresponding physical distance is sent earlier.

5. The data processor according to claim 4, wherein: The N-level data agent module executes to obtain the priority of each data access instruction, including performing the following operations: The priority of each data access instruction is determined based on the time when each data access instruction returns the destination data when pre-running the task, wherein, when pre-running the task, each data access instruction is sent in sequence according to the order in the data access instruction sequence, and the time when each data access instruction returns the destination data is collected.

6. The data processor according to any one of claims 1 to 5, wherein: When the N-level data proxy module executes to cache the target data returned by each data access instruction into the corresponding first-level data proxy module, the following operations are performed: For each data access instruction, the target data returned by the data access instruction is cached in a level 1 cache node or shared memory electrically connected to the computing core using the target data, wherein the The corresponding first-level data proxy module includes a plurality of cache blocks, which are mapped to the first-level cache node or the shared memory, and the plurality of cache blocks are used to cache the received destination data.

7. The data processor according to any one of claims 1 to 6, wherein: The at least one i-level cache node corresponds to at least one i-th level data proxy module in a one-to-one manner, and the i-th level data proxy modules corresponding to at least some of the i-level cache nodes are electrically connected to the i+1-th level data proxy module corresponding to the one i+1-level cache node. The level 1 data proxy module corresponding to each level 1 cache node is electrically connected to at least one computing core, wherein the at least one computing core is electrically connected to the level 1 cache node; The N-level data proxy module corresponding to the N-level cache is electrically connected to the memory.

8. The data processor according to claim 7, wherein: Each data proxy module includes a scheduler, a request status list, a data request list, and a plurality of cache blocks. The data proxy module includes any i-th level data proxy module or the N-th level data proxy module. The data request list is used to cache data access instructions to be sent, The scheduler is used to send the data access instructions to be sent cached in the data request list in sequence according to the instruction sending order, and send the destination data received by the data proxy module to the corresponding computing core or the cache block in the electrically connected upper-level data proxy module, The request status list includes a plurality of status items, wherein each of the plurality of status items is used to indicate a cache block associated with a data access instruction corresponding to the status item and a position of the data access instruction corresponding to the status item in the instruction sending sequence. The multiple cache blocks are used to cache the destination data received by the data proxy module.

9. The data processor according to claim 8, wherein: The data request list is provided with multiple channels for caching the data access instructions to be sent, and the data access instructions in different channels correspond to different physical distances. The scheduler is configured to arrange the data access instructions in each channel in ascending order of the physical distances corresponding to the data access instructions in each channel, obtain the instruction sending order, and send the data access instructions to be sent in sequence according to the instruction sending order. The physical distance corresponding to each data access instruction is the distance between the storage location of the target data of each data access instruction in the memory and the computing core in the data processor. The physical distance corresponding to each data access instruction is determined by the read address of the destination data used as an input parameter in each data access instruction.

10. The data processor according to claim 8, wherein: The data proxy module is configured as follows: In response to the existence of an unassociated cache block in the data agent module, the unassociated cache block is associated with a data access instruction selected from the data request list according to the instruction sending order.

11. The data processor according to claim 10, wherein: Each cache block has a unique corresponding cache block number, and each data access instruction in the data request list has a unique corresponding request number. When the data proxy module associates the unassociated cache block with a data access instruction selected from the data request list according to the instruction sending order, the following operations are performed: The request number of the data access instruction and the cache block number of the unassociated cache block are set in a status item corresponding to the data access instruction to associate the unassociated cache block with the data access instruction.

12. The data processor according to claim 8, wherein: The i+1th level data proxy module is further configured as follows: In response to the destination data cached in any cache block in the i+1-level data proxy module having been sent to the i-level data proxy module, the data access instruction associated with any cache block is cleared from the data request list of the i+1-level data proxy module, and the status item corresponding to the cleared data access instruction in the request status list of the i+1-level data proxy module is cleared.

13. The data processor according to claim 8, wherein: The scheduler configuration of the Nth level data proxy module is: sending, in sequence to the memory, data access instructions cached in the data request list of the N-level data proxy module according to the instruction sending order; Receive the target data returned from the memory in sequence, and store each returned target data into a cache block associated with a corresponding data access instruction.

14. The data processor according to claim 8, wherein: The scheduler configuration of the i-th level data proxy module corresponding to any i-level cache node among the at least some of the i-level cache nodes is: Send a data request signal to the electrically connected i+1th level data proxy module, and receive the received Cache the returned data in a cache block associated with the data access instruction corresponding to the data request signal; The scheduler configuration of the i+1th level data proxy module is: In response to receiving the data request signal, the destination data of the data access instruction corresponding to the data request signal is sent to the i-th level data agent module.

15. The data processor according to claim 8, wherein: The first-level data proxy module is further configured to: Before executing the task, at least one data access instruction is selected from the data access instruction sequence in the order of the data access instruction sequence, and an initialization operation is performed on the at least one data access instruction, wherein the at least one data access instruction is executed by a computing core electrically connected to the first-level data agent module.

16. The data processor according to claim 15, wherein: When the first-level data agent module performs the initialization operation on the at least one data access instruction, the following operations are performed: caching the at least one data access instruction into a data request list of the first-level data proxy module; Initializing a status item corresponding to the at least one data access instruction and storing the status item in a request status list of the first-level data proxy module; as well as The at least one data access instruction and the corresponding status item are synchronized to other-level data proxy modules that are directly or indirectly electrically connected to the first-level data proxy module.

17. The data processor according to claim 8, wherein: The first-level data proxy module is further configured to: In response to receiving a data memory access instruction sent by a computing core electrically connected to the first-level data proxy module, determining a cache block associated with the sent data memory access instruction, and sending data in the associated cache block to a destination register indicated by the sent data memory access instruction; Clearing the sent data access instruction from the data request list of the first-level data proxy module, and clearing the status item corresponding to the sent data access instruction in the request status list of the first-level data proxy module; At least one data access instruction is selected from the data access instruction sequence in the order of the data access instruction sequence, and an initialization operation is performed on the at least one data access instruction.

18. The data processor according to claim 8, wherein: The status item includes a cache block number and a request number, which are used to indicate the data access instruction corresponding to the status item and the cache block associated with the data access instruction corresponding to the status item. The status item further includes a channel number of a channel to which the data access instruction corresponding to the status item belongs and a priority of the data access instruction corresponding to the status item, wherein the channel number and the priority are used to indicate the position of the data access instruction corresponding to the status item in the instruction sending sequence. The status item also includes request receiving status information and request sending status information, which are used to indicate the current status of the data access instruction corresponding to the status item. The status item further includes data status information for indicating the current status of the destination data returned by the data access instruction corresponding to the status item.

19. The data processor according to claim 8, wherein: Before executing the task, the data processor is further configured to: A plurality of cache lines are selected from the cache nodes corresponding to each data proxy module and mapped to the plurality of cache blocks in the data proxy module.

20. The data processor according to any one of claims 1 to 6, wherein: The data access instruction sequence is obtained by arranging all the data access instructions in the task according to the order in which they appear in the program corresponding to the task.

21. The data processor according to claim 7, wherein: The data processor is a general-purpose graphics processor or a graphics processor, and the data processor includes a plurality of computing units. In response to N=2, the first level cache in the N-level cache includes a plurality of first level cache nodes, and the second level cache in the N-level cache includes one second level cache node. Each level 1 cache node is used for data sharing within one computing unit, and the level 2 cache node is used for data sharing between the multiple computing units. Each level 1 cache node corresponds to a level 1 data proxy module, and the level 2 cache node corresponds to a level 2 data proxy module.

22. A data processing method for a data processor comprising an N-level cache and a memory, The i-th level cache in the N-level cache includes at least one i-level cache node, at least some of the at least one i-level cache node share an i+1-level cache node, N is a positive integer greater than 1, and i is any positive integer between 1 and N-1. The Nth level cache in the N-level cache is electrically connected to the memory, and each level 1 cache node is electrically connected to the corresponding computing core. The data processing method includes: Obtaining a data access instruction sequence in a task currently executed by the data processor; adjusting the instruction sending order of the data access instruction sequence according to the storage position of the destination data of each data access instruction in the data access instruction sequence in the memory; Sending the data access instructions in sequence according to the instruction sending order; The destination data returned by each data access instruction is cached in a level 1 cache node or shared memory electrically connected to the computing core that uses the destination data.

23. The data processing method according to claim 22, wherein: The adjusting the instruction sending order of the data access instruction sequence according to the storage position of the destination data of each data access instruction in the data access instruction sequence in the memory includes: Obtaining a physical distance corresponding to each data access instruction, wherein the physical distance corresponding to each data access instruction is a distance between a storage location of target data of each data access instruction in the memory and a computing core in the data processor; The instruction sending sequence is adjusted according to the physical distances corresponding to the respective data access instructions, wherein, in the instruction sending sequence, the data access instruction corresponding to the smaller physical distance is sent earlier.

24. The data processing method according to claim 22, wherein: Adjusting the instruction sending order of the data access instruction sequence according to the storage position of the destination data of each data access instruction in the data access instruction sequence in the memory, including: Get the priority of each data access instruction; Obtaining a physical distance corresponding to each data access instruction, wherein the physical distance corresponding to each data access instruction is a distance between a storage location of target data of each data access instruction in the memory and a computing core in the data processor; The instruction sending order is adjusted according to the priority of each data access instruction and the corresponding physical distance, wherein, in the instruction sending order, the data access instruction with a higher priority is sent earlier, and under the same priority, the data access instruction with a smaller corresponding physical distance is sent earlier.

25. An electronic device comprising: a memory that non-transitorily stores computer-executable instructions; a processor configured to execute the computer-executable instructions, Wherein, when the computer executable instructions are executed by the processor, the data processing method according to any one of claims 22-24 is implemented.

26. A non-transitory computer-readable storage medium, wherein: The non-transitory computer-readable storage medium stores computer-executable instructions, When the computer-executable instructions are executed by a processor, the data processing method according to any one of claims 22 to 24 is implemented.

27. An electronic device comprising the data processor according to any one of claims 1 to 21.

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