Solar cell

Abstract

A solar cell, comprising: a silicon substrate, a first tunnel oxide layer, a first doped polysilicon layer, a first gate line, a transparent conductive dielectric layer and a first passivation layer, wherein the first doped polysilicon layer comprises a first gate line region and a first non-gate line region, the first gate line is located in the first gate line region, the transparent conductive dielectric layer is located in the first non-gate line region, and the band-gap width of the transparent conductive dielectric layer is different from the band-gap width of the first doped polysilicon layer.

Description

Solar cell

[0001] Cross-reference to related applications

[0002] The present application is based on the Chinese patent application No. 202410415038.9, filed on April 8, 2024, and claims the priority of the Chinese patent application, the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of solar cells, in particular, to a solar cell and a preparation method of the solar cell. BACKGROUND

[0004] TOPCon (Tunnel Oxide Passivated Contact) cell is a kind of solar cell, which forms a passivation contact structure through a tunneling oxide layer and a doped polysilicon layer, reduces electron-hole recombination, and improves the open-circuit voltage and short-circuit current of the cell, and has characteristics such as high conversion efficiency, low attenuation performance, and high production cost performance.

[0005] The theoretical limit efficiency of the TOPCon cell is 28.7%, close to the efficiency limit of 29.43% of the crystalline silicon photovoltaic cell, and the parasitic absorption of sunlight and the passivation performance of the cell are important factors affecting the final conversion efficiency of the TOPCon cell. At present, the parasitic absorption of light is mainly reduced by doping concentration, but this kind of technology has limited improvement on the passivation performance of the cell, and the final conversion efficiency of the cell is low. SUMMARY

[0006] The present disclosure aims to at least solve one of the technical problems existing in the prior art. To this end, the present disclosure provides a solar cell and a preparation method of the solar cell, which can enhance the passivation performance of the cell and help to improve the conversion efficiency of the cell.

[0007] In a first aspect, the present disclosure provides a solar cell, comprising:

[0008] a silicon substrate;

[0009] a first tunneling oxide layer disposed on a light-receiving surface of the silicon substrate;

[0010] a first doped polysilicon layer disposed on a side of the first tunneling oxide layer away from the silicon substrate, the first doped polysilicon layer being divided into a first grid line region and a first non-grid line region, and the first doped polysilicon layer comprising a first doping element;

[0011] a first grid line disposed on a side of the first doped polysilicon layer away from the first tunneling oxide layer and located in the first grid line region;

[0012] a transparent conductive medium layer disposed on a side of the first doped polysilicon layer away from the first tunneling oxide layer and located in the first non-gate line region, a band gap width of the transparent conductive medium layer being different from a band gap width of the first doped polysilicon layer;

[0013] a first passivation layer disposed on a side of the transparent conductive medium layer away from the first doped polysilicon layer.

[0014] According to the solar cell of the present disclosure, by disposing a structure in which the first doped polysilicon layer and the transparent conductive medium layer are in contact in the non-gate line region on the front side of the cell, the band gap width of the first doped polysilicon layer and the transparent conductive medium layer is different, a larger energy band offset is formed, the reverse saturation current is reduced, the passivation performance of the cell is effectively improved, the transparent conductive medium layer can also reduce the shading area on the front side and reduce the contact resistance, and the conversion efficiency of the cell is effectively improved.

[0015] According to some embodiments of the present disclosure, further comprising:

[0016] a second tunneling oxide layer disposed on a back side of the silicon substrate;

[0017] a second doped polysilicon layer disposed on a side of the second tunneling oxide layer away from the silicon substrate, the second doped polysilicon layer comprising a second doping element opposite to the doping type of the first doping element, the second doped polysilicon layer being divided into a second gate line region and a second non-gate line region;

[0018] a second gate line disposed on a side of the second doped polysilicon layer away from the second tunneling oxide layer and located in the second gate line region;

[0019] a second passivation layer disposed on a side of the second doped polysilicon layer away from the second tunneling oxide layer and located in the second non-gate line region.

[0020] According to some embodiments of the present disclosure, the second gate line region further comprises a third doping element.

[0021] According to some embodiments of the present disclosure, the third doping element is an oxygen element.

[0022] According to some embodiments of the present disclosure, a doping concentration of the second doping element in the second gate line region is greater than a doping concentration of the second doping element in the second non-gate line region.

[0023] According to some embodiments of the present disclosure, a doping concentration of the first doping element in the first gate line region is greater than a doping concentration of the first doping element in the first non-gate line region.

[0024] According to some embodiments of the present disclosure, the transparent conductive medium layer is a transparent conductive oxide film.

[0025] In a second aspect, the present disclosure provides a method for manufacturing a solar cell, the method comprising:

[0026] a first tunneling oxide layer is prepared on a light-receiving surface of a silicon substrate, and a first precursor layer is prepared on a side of the first tunneling oxide layer away from the silicon substrate;

[0027] a first doped polysilicon layer is obtained by doping the first precursor layer with a first doping element, the first doped polysilicon layer being divided into a first gate line region and a first non-gate line region;

[0028] a transparent conductive medium layer is prepared on the first non-gate line region of the first doped polysilicon layer away from the first tunneling oxide layer, the transparent conductive medium layer having a different band gap width from that of the first doped polysilicon layer;

[0029] a first passivation layer is prepared on a side of the transparent conductive medium layer away from the first doped polysilicon layer, and a first gate line is prepared on the first gate line region of the first doped polysilicon layer away from the first tunneling oxide layer.

[0030] According to the method for manufacturing a solar cell of the present disclosure, by arranging a structure in which the first doped polysilicon layer and the transparent conductive medium layer are in contact on the non-gate line region of the front surface of the cell, and by making the band gap widths of the first doped polysilicon layer and the transparent conductive medium layer different, a larger energy band offset is formed, the reverse saturation current is reduced, the passivation performance of the cell is effectively improved, and the transparent conductive medium layer can also reduce the light-blocking area on the front surface, reduce the contact resistance, and effectively improve the conversion efficiency of the cell.

[0031] According to some embodiments of the present disclosure, the method further comprises:

[0032] a second tunneling oxide layer is prepared on a back surface of the silicon substrate, and a second precursor layer is prepared on a side of the second tunneling oxide layer away from the silicon substrate;

[0033] a second doped polysilicon layer is obtained by doping the second precursor layer with a second doping element having a doping type opposite to that of the first doping element, the second doped polysilicon layer being divided into a second gate line region and a second non-gate line region;

[0034] a second gate is prepared on the second gate line region of the second doped polysilicon layer away from the second tunneling oxide layer, and a second passivation layer is prepared on the second non-gate line region of the second doped polysilicon layer away from the second tunneling oxide layer.

[0035] According to some embodiments of the present disclosure, the doping treatment of the second precursor layer with a second doping element opposite to the doping type of the first doping element comprises:

[0036] diffusing the second doping element into the second precursor layer;

[0037] laser opening the second gate line region;

[0038] doping the second gate line region with the second doping element and a third doping element.

[0039] According to some embodiments of the present disclosure, the doping of the second gate line region with the second doping element and a third doping element comprises:

[0040] generating the second doped polysilicon layer by plasma enhanced chemical vapor deposition with the second doping element and the third doping element as doping sources.

[0041] According to some embodiments of the present disclosure, the doping concentration of the second doping element in the second gate line region is greater than the doping concentration of the second doping element in the second non-gate line region.

[0042] According to some embodiments of the present disclosure, the doping concentration of the first doping element in the first gate line region is greater than the doping concentration of the first doping element in the first non-gate line region.

[0043] Additional aspects and advantages of the present disclosure will be made apparent from the following description of embodiments of the present disclosure, which is given for purposes of illustration and not limitation. BRIEF DESCRIPTION OF DRAWINGS

[0044] The above and / or additional aspects and advantages of the present disclosure will become apparent and more readily appreciated from the following description of embodiments, taken in conjunction with the accompanying drawings, in which:

[0045] FIG. 1 is one of the structural schematic diagrams of a solar cell according to an embodiment of the present disclosure;

[0046] FIG. 2 is another of the structural schematic diagrams of a solar cell according to an embodiment of the present disclosure;

[0047] FIG. 3 is a third of the structural schematic diagrams of a solar cell according to an embodiment of the present disclosure;

[0048] FIG. 4 is one of the structural schematic diagrams of a method for manufacturing a solar cell according to an embodiment of the present disclosure;

[0049] FIG. 5 is another of the structural schematic diagrams of a method for manufacturing a solar cell according to an embodiment of the present disclosure.

[0050] Figure 1: Silicon substrate 100, first tunneling oxide layer 210, first gate line region 221, first non-gate line region 222, first gate line 230, transparent conductive dielectric layer 240, first passivation layer 260, second tunneling oxide layer 310, first silicon oxide film layer 311, second silicon oxide film layer 312, second doped polysilicon layer 320, second gate line region 321, second non-gate line region 322, second gate line 330, second passivation layer 340. DETAILED DESCRIPTION

[0051] The following describes in detail embodiments of the present disclosure, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended only to explain the present disclosure and are not to be construed as limiting the present disclosure.

[0052] A solar cell and a method for manufacturing the solar cell according to an embodiment of the present disclosure will be described below with reference to FIG. 1 to FIG. 5 .

[0053] As shown in FIG. 1 , the solar cell according to the embodiment of the present disclosure may include a silicon substrate 100 , a first tunneling oxide layer 210 , a first doped polysilicon layer, a first gate line 230 , a transparent conductive dielectric layer 240 and a first passivation layer 260 .

[0054] In this embodiment, the first tunneling oxide layer 210 is disposed on the light-receiving surface of the silicon substrate 100 , and the first doped polysilicon layer is disposed on a surface of the first tunneling oxide layer 210 away from the silicon substrate 100 .

[0055] The first tunneling oxide layer 210 and the first doped polysilicon layer form a passivation contact structure.

[0056] In actual implementation, the silicon substrate 100 can be an N-type silicon wafer or a P-type silicon wafer; the first tunneling oxide layer 210 can be silicon oxide; and the first doped polysilicon layer can be an N-type doped polysilicon layer or a P-type doped polysilicon layer.

[0057] The first doped polysilicon layer includes a first doping element. When the first doped polysilicon layer is an N-type doped polysilicon layer, the first doping element may be phosphorus. When the first doped polysilicon layer is a P-type doped polysilicon layer, the first doping element may be boron.

[0058] In this embodiment, the first doped polysilicon layer is divided into a first gate line region 221 and a first non-gate line region 222, wherein the first gate line region 221 is an area on the first doped polysilicon layer that contacts the first gate line 230, and the first non-gate line region 222 is an area on the first doped polysilicon layer without the first gate line 230.

[0059] The first gate line 230 is arranged on the side of the first doped polysilicon layer away from the first tunneling oxide layer 210 and located in the first gate line area 221.

[0060] In actual implementation, the first gate line 230 can be printed by using a metal material such as silver paste or copper paste.

[0061] In this embodiment, the solar cell further comprises a transparent conductive medium layer 240, which is arranged on the side of the first doped polysilicon layer away from the first tunneling oxide layer 210 and located in the first non-gate line area 222.

[0062] The transparent conductive medium layer 240 is a transparent and conductive medium layer in the first non-gate line area 222, which covers the first non-gate line area 222 and does not block the sunlight entering the first doped polysilicon layer.

[0063] In this embodiment, the first passivation layer 260 is arranged on the side of the transparent conductive medium layer 240 away from the first doped polysilicon layer, and the transparent conductive medium layer 240 is arranged between the first doped polysilicon layer and the first passivation layer 260.

[0064] The first passivation layer 260 can be made of a material such as silicon nitride, silicon oxide or aluminum oxide.

[0065] It should be noted that the band gap width of the transparent conductive medium layer 240 is different from that of the first doped polysilicon layer, a large energy band offset is formed between the first doped polysilicon layer and the transparent conductive medium layer 240, which can effectively reduce the recombination of electrons and holes and enhance the passivation performance of the solar cell.

[0066] The stacking of the first doped polysilicon layer and the transparent conductive medium layer 240 can also form a heterojunction structure to reduce the reverse saturation current. The conductive performance of the transparent conductive medium layer 240 can enhance the lateral transport capacity of the carriers, which is helpful to reduce the gate line density of the first gate line 230 on the front side of the solar cell, reduce the reverse saturation current and the shading area, and also maintain a small contact resistance.

[0067] According to the solar cell provided by the embodiment of the present disclosure, the structure of the first doped polysilicon layer and the transparent conductive medium layer 240 in contact with each other is arranged in the non-gate line area on the front side of the cell. The band gap width of the first doped polysilicon layer is different from that of the transparent conductive medium layer 240, a large energy band offset is formed, the reverse saturation current is reduced, the passivation performance of the cell is effectively improved, the transparent conductive medium layer 240 can also reduce the shading area on the front side and reduce the contact resistance, and the conversion efficiency of the cell is effectively improved.

[0068] In some embodiments, the doping concentration of the first doping element in the first gate line region 221 is greater than the doping concentration of the first doping element in the first non-gate line region 222.

[0069] In this embodiment, the first gate line region 221 is set to a heavy doping concentration, which can effectively improve the contact performance of the first doping polysilicon layer and the first gate line 230 at the first gate line region 221. The first non-gate line region 222 is set to a low doping concentration, which can effectively reduce the parasitic absorption at the first non-gate line region 222 and improve the battery conversion efficiency.

[0070] It should be noted that the reverse saturation current is related to the doping concentration. By setting the first non-gate line region 222 to a low doping concentration and setting the transparent conductive dielectric layer 240 with different band gap widths on the first non-gate line region 222, a larger energy band offset is formed, which can effectively reduce the reverse saturation current and improve the passivation performance of the battery.

[0071] The large-area first non-gate line region 222 on the front side of the solar cell is composed of a first doping polysilicon layer with a low doping concentration and a transparent conductive dielectric layer 240. The low doping concentration reduces parasitic absorption, and the first doping polysilicon layer and the transparent conductive dielectric layer 240 enhance the passivation performance. The first gate line region 221 is a first doping polysilicon layer with a heavy doping concentration, which can easily form excellent contact with the first gate line 230 and reduce the contact resistance of the battery.

[0072] In some embodiments, the transparent conductive dielectric layer 240 is a transparent conductive oxide (TCO) thin film.

[0073] The transparent conductive oxide (TCO) thin film mainly includes oxides of indium (In), tin (Sn), antimony (Sb), zinc (Zn), and cadmium (Cd), as well as composite multi-element oxide thin film materials.

[0074] For example, the transparent conductive dielectric layer 240 can be indium tin oxide (ITO), which is composed of indium oxide (In2O3) and tin oxide (SnO2).

[0075] It can be understood that the solar cell includes a passivation contact structure formed by the first tunneling oxide layer 210 and the first doping polysilicon layer, and the solar cell belongs to a TOPCon battery. The solar cell can be a bifacial poly TOPCon battery.

[0076] In some embodiments, as shown in FIG. 2, the solar cell can further include a second tunneling oxide layer 310, a second doping polysilicon layer 320, a second gate line 330, and a second passivation layer 340.

[0077] In this embodiment, the second tunneling oxide layer 310 is arranged on the back surface of the silicon substrate 100, and the second doped polysilicon layer 320 is arranged on the side of the second tunneling oxide layer 310 away from the silicon substrate 100.

[0078] The second tunneling oxide layer 310 and the second doped polysilicon layer 320 form a passivated contact structure.

[0079] In actual implementation, the second tunneling oxide layer 310 can be silicon oxide, and the second doped polysilicon layer 320 can be an N-type doped polysilicon layer or a P-type doped polysilicon layer.

[0080] The second doped polysilicon layer 320 includes a second doping element opposite to the first doping element. When the first doped polysilicon layer is an N-type doped polysilicon layer, the first doping element can be phosphorus, the second doped polysilicon layer 320 is a P-type doped polysilicon layer, and the second doping element can be boron. When the first doped polysilicon layer is a P-type doped polysilicon layer, the first doping element can be boron, the second doped polysilicon layer 320 is an N-type doped polysilicon layer, and the second doping element can be phosphorus.

[0081] As shown in FIG. 3, the second doped polysilicon layer 320 is divided into a second gate line area 321 and a second non-gate line area 322. The second gate line area 321 is an area of the second doped polysilicon layer 320 in contact with the second gate line 330, and the second non-gate line area 322 is an area of the second doped polysilicon layer 320 without the second gate line 330.

[0082] The second gate line 330 is arranged on the side of the second doped polysilicon layer 320 away from the second tunneling oxide layer 310 and located in the second gate line area 321.

[0083] In actual implementation, the second gate line 330 can be printed with metal materials such as silver paste and copper paste.

[0084] In this embodiment, the second passivation layer 340 is arranged on the side of the second doped polysilicon layer 320 away from the second tunneling oxide layer 310 and located in the second non-gate line area 322. The second passivation layer 340 can be made of materials such as silicon nitride, silicon oxide, and aluminum oxide.

[0085] The double-sided poly TOPCon cell has a theoretical conversion efficiency of 28.5%. The polysilicon on the front surface has a large parasitic absorption of light, and the passivation contact performance is poor, which affects the conversion efficiency of the cell.

[0086] In the embodiment of the present disclosure, the first non-grid line area 222 of the front surface of the solar cell receiving light is composed of a first doped polysilicon layer with a low doping concentration and a transparent conductive medium layer 240, and the low doping concentration reduces parasitic absorption. The band gap difference between the first doped polysilicon layer and the transparent conductive medium layer 240 can effectively enhance the passivation performance. The first grid line area 221 is a first doped polysilicon layer with a heavy doping concentration, which forms excellent contact with the first grid line 230, reduces the contact resistance of the cell, and effectively improves the conversion efficiency of the double-sided poly TOPCon cell.

[0087] In some embodiments, the second grid line area 321 further comprises a third doped element.

[0088] It should be noted that the second doped element and the third doped element are different elements and can have a difference. By doping the third doped element into the second grid line area 321, the doping concentration of the N-type or P-type second doped element can be appropriately reduced, and a band offset can be formed to effectively improve the contact performance.

[0089] In some embodiments, the third doped element is an oxygen element.

[0090] In this embodiment, in the second grid line area 321 in contact with the grid line, the second doped polysilicon layer 320 has a third doped element, i.e., an oxygen element, in addition to the N-type or P-type second doped element. The doped oxygen element can effectively reduce the contact resistance between the second doped polysilicon layer 320 and the second grid line 330, thereby improving the conversion efficiency of the cell.

[0091] In actual implementation, when doping the second grid line area 321, carbon dioxide (CO2) or other oxygen-containing doping sources can be added to the N-type or P-type doping source to achieve oxygen element doping.

[0092] In some embodiments, the doping concentration of the second doped element in the second grid line area 321 is greater than the doping concentration of the second doped element in the second non-grid line area 322.

[0093] In this embodiment, the second grid line area 321 is set to a heavy doping concentration, which can effectively improve the contact performance of the second doped polysilicon layer 320 and the second grid line 330 in the second grid line area 321. The second non-grid line area 322 is set to a low doping concentration, which can effectively reduce the parasitic absorption in the second non-grid line area 322 and improve the conversion efficiency of the cell.

[0094] In actual implementation, while the second non-grid line area 322 adopts a low doping concentration to ensure low parasitic absorption, the second grid line area 321 can increase oxygen element doping to improve the contact performance and improve the conversion efficiency of the cell.

[0095] The first non-grid line area 222 of the light-receiving surface of the solar cell of the embodiment of the present disclosure is provided with a first doped polysilicon layer with a low doping concentration and a transparent conductive medium layer 240, the low doping concentration effectively reduces parasitic absorption, and the first doped polysilicon layer and the transparent conductive medium layer 240 with different band gaps can effectively enhance the passivation performance, and the first grid line area 221 is provided with a first doped polysilicon layer with a heavy doping concentration, thereby forming good contact with the first grid line 230 and reducing the contact resistance of the cell.

[0096] The second non-grid line area 322 of the back surface is provided with a low doping concentration, and the second grid line area 321 is provided with a heavy doping concentration, thereby ensuring the passivation performance of the back surface of the cell, and the second grid line area 321 further increases the doping of oxygen elements, thereby further reducing the contact resistance with the second grid line 330, and the front surface and the back surface of the cell have excellent contact ability and electrical performance, thereby effectively improving the conversion efficiency of the cell.

[0097] The embodiment of the present disclosure further provides a preparation method of a solar cell, which can be used to prepare the solar cell.

[0098] As shown in FIG. 4, the preparation method of the solar cell includes steps 410 to 440.

[0099] In step 410, a first tunneling oxide layer 210 is prepared on the light-receiving surface of a silicon substrate 100, and a first precursor layer is prepared on the side of the first tunneling oxide layer 210 away from the silicon substrate 100.

[0100] The silicon substrate 100 can be an N-type silicon wafer or a P-type silicon wafer.

[0101] In this step, the first tunneling oxide layer 210 is prepared on the light-receiving surface of the silicon substrate 100, and the first tunneling oxide layer 210 can be silicon oxide. After the first tunneling oxide layer 210 is prepared, the first precursor layer is prepared on the side of the first tunneling oxide layer 210 away from the silicon substrate 100.

[0102] The first precursor layer is a hierarchical structure for doping to prepare a first doped polysilicon layer.

[0103] In actual execution, the first precursor layer can be microcrystalline silicon and amorphous silicon, and the polysilicon is formed after a high-temperature diffusion doping process.

[0104] In step 420, a first doped polysilicon layer is obtained by doping the first precursor layer with a first doping element.

[0105] The first doping element can be an N-type doping element or a P-type doping element.

[0106] In this embodiment, the first doping element can be phosphorus, and doping treatment of the first precursor layer using the first doping element can obtain an N-type doped first doped polysilicon layer; the first doping element can be boron, and doping treatment of the first precursor layer using the first doping element can obtain a P-type doped first doped polysilicon layer.

[0107] In this step, the first precursor layer can be subjected to regional doping treatment through a mask or the like, and the first doped polysilicon layer is divided into a first gate line area 221 and a first non-gate line area 222.

[0108] The first gate line area 221 is an area of the first doped polysilicon layer in contact with the first gate line 230, and the first non-gate line area 222 is an area of the first doped polysilicon layer without the first gate line 230. The first precursor layer can be subjected to regional doping treatment according to a printed pattern corresponding to the first gate line 230 as a mask.

[0109] Step 430, a transparent conductive medium layer 240 is prepared in the first non-gate line area 222 of the first doped polysilicon layer away from the first tunnel oxide layer 210.

[0110] The transparent conductive medium layer 240 has a different band gap width from that of the first doped polysilicon layer.

[0111] It should be noted that the transparent conductive medium layer 240 has a different band gap width from that of the first doped polysilicon layer, and a large energy band offset is formed between the first doped polysilicon layer and the transparent conductive medium layer 240, which can effectively reduce the recombination of electrons and holes and enhance the passivation performance of the solar cell.

[0112] The first doped polysilicon layer and the transparent conductive medium layer 240 can also form a heterojunction structure, which can reduce the reverse saturation current. The transparent conductive medium layer 240 can enhance the carrier lateral transport capability, which can help to reduce the gate line density of the first gate line 230 on the front surface of the solar cell, reduce the reverse saturation current and shading area, and also maintain a small contact resistance.

[0113] In some embodiments, the transparent conductive medium layer 240 can be a transparent conductive oxide film.

[0114] Step 440, a first passivation layer 260 is prepared on the side of the transparent conductive medium layer 240 away from the first doped polysilicon layer, and a first gate line 230 is prepared in the first gate line area 221 of the first doped polysilicon layer away from the first tunnel oxide layer 210.

[0115] In actual implementation, the first grid line 230 can be printed by using a metal material such as silver paste or copper paste, and the first passivation layer 260 can be prepared by using a material such as silicon nitride, silicon oxide or aluminum oxide.

[0116] According to the method for manufacturing the solar cell provided in the embodiments of the present disclosure, the structure that the first doped polysilicon layer and the transparent conductive medium layer 240 are in contact is arranged in the non-grid line area on the front side of the cell, the first doped polysilicon layer and the transparent conductive medium layer 240 have different band gap widths, a larger energy band offset is formed, the reverse saturation current is reduced, the passivation performance of the cell is effectively improved, the transparent conductive medium layer 240 can also reduce the light-shielding area on the front side and reduce the contact resistance, and the conversion efficiency of the cell is effectively improved.

[0117] In some embodiments, the doping concentration of the first doped element in the first grid line area 221 is greater than the doping concentration of the first doped element in the first non-grid line area 222.

[0118] In this embodiment, the first grid line area 221 is set to a heavy doping concentration, which can effectively improve the contact performance of the first doped polysilicon layer and the first grid line 230 at the first grid line area 221, and the first non-grid line area 222 is set to a low doping concentration, which can effectively reduce the parasitic absorption at the first non-grid line area 222 and improve the conversion efficiency of the cell.

[0119] In some embodiments, the step 420 of doping the first precursor layer by using the first doped element can include:

[0120] diffusing the first doped element to the first precursor layer;

[0121] using a laser to push the first doped element at the position corresponding to the first grid line area 221, so that the doping concentration of the first doped element in the first grid line area 221 is greater than the doping concentration of the first doped element in the first non-grid line area 222.

[0122] In this embodiment, the first diffusion of the first doped element can be performed by using a high-temperature deposition method to diffuse the first doped element to the first precursor layer, so as to form the first doped polysilicon layer with an overall low doping concentration; and then a laser is used for secondary doping to push the first doped element at the position corresponding to the first grid line area 221, so as to form the first doped polysilicon layer with a heavy doping concentration.

[0123] In actual implementation, when the secondary doping is performed, a paste containing a doped source can also be used to print the first grid line area 221 to push the first doped element, so as to form the first non-grid line area 222 with a low doping concentration and the grid line area with a heavy doping concentration.

[0124] In this embodiment, the first gate line region 221 is set to a heavy doping concentration, which can effectively improve the contact performance of the first doped polysilicon layer and the first gate line 230 at the first gate line region 221. The first non-gate line region 222 is set to a low doping concentration, which can effectively reduce the parasitic absorption at the first non-gate line region 222 and improve the battery conversion efficiency.

[0125] It should be noted that the reverse saturation current is related to the doping concentration. The first non-gate line region 222 is set to a low doping concentration, and the transparent conductive medium layer 240 with different band gap widths is arranged on the first non-gate line region 222, so that a larger energy band offset is formed, which can effectively reduce the reverse saturation current and improve the passivation performance of the battery.

[0126] The preparation method of the solar cell in the embodiments of the present disclosure can also be used to prepare a double-sided poly TOPCon cell.

[0127] In some embodiments, as shown in FIG. 5, the preparation method of the solar cell includes steps 510 to 530.

[0128] Step 510: A second tunneling oxide layer 310 is prepared on the back surface of the silicon substrate 100, and a second precursor layer is prepared on the side of the second tunneling oxide layer 310 away from the silicon substrate 100.

[0129] The second tunneling oxide layer 310 can be silicon oxide. After the first tunneling oxide layer 210 is prepared, the second precursor layer is a hierarchical structure for doping to prepare a second doped polysilicon layer 320.

[0130] In actual implementation, the second precursor layer can be microcrystalline silicon and amorphous silicon, which forms polysilicon after a high-temperature diffusion doping process.

[0131] Step 520: A second doped polysilicon layer 320 is obtained by using a second doping element with a doping type opposite to that of the first doping element to dope the second precursor layer.

[0132] In this embodiment, when the first doped polysilicon layer is an N-type doped polysilicon layer, the first doping element can be phosphorus, the second doped polysilicon layer 320 is a P-type doped polysilicon layer, and the second doping element can be boron; when the first doped polysilicon layer is a P-type doped polysilicon layer, the first doping element can be boron, the second doped polysilicon layer 320 is an N-type doped polysilicon layer, and the second doping element can be phosphorus.

[0133] The second doped polysilicon layer 320 is divided into a second gate line region 321 and a second non-gate line region 322.

[0134] The second gate line region 321 is a region of the second doped polysilicon layer 320 in contact with the second gate line 330, and the second non-gate line region 322 is a region of the second doped polysilicon layer 320 without the second gate line 330.

[0135] In step 530, a second gate is prepared in the second gate line region 321 of the second doped polysilicon layer 320 away from the second tunneling oxide layer 310, and a second passivation layer 340 is prepared in the second non-gate line region 322 of the second doped polysilicon layer 320 away from the second tunneling oxide layer 310.

[0136] In actual implementation, the second gate line 330 can be prepared by printing using a metal material such as silver paste or copper paste, and the second passivation layer 340 can be prepared using a material such as silicon nitride, silicon oxide, or aluminum oxide.

[0137] In some embodiments, step 520 includes:

[0138] diffusing the second doped element into the second precursor layer;

[0139] performing laser opening on the second gate line region 321;

[0140] performing doping of the second doped element and a third doped element in the second gate line region 321.

[0141] In this embodiment, in the second gate line region 321 in contact with the gate line, the second doped polysilicon layer 320 is doped with a third doped element in addition to the second doped element of N type or P type, which can effectively reduce the contact resistance between the second doped polysilicon layer 320 and the second gate line 330 and improve the battery conversion efficiency.

[0142] It can be understood that doping of the third doped element in the second gate line region 321 can appropriately reduce the doping concentration of the second doped element of N type or P type, while forming a band offset to effectively improve the contact performance.

[0143] In actual implementation, the third doped element can be oxygen element, and when doping the second gate line region 321, a carbon dioxide (CO2) or other oxygen-containing doping source can be added to the doping source of N type or P type to realize doping of the oxygen element.

[0144] In this embodiment, the second precursor layer is diffused using a second doping element to form a low-doped second doped polysilicon layer 320, and the second gate line area 321 is laser opened on the second doped polysilicon layer 320 to remove borosilicate glass or phosphosilicate glass formed by the second doping element during diffusion, and the borosilicate glass or phosphosilicate glass of the second non-gate line area 322 is retained as a mask to dope the second gate line area 321 with the second doping element and a third doping element.

[0145] In actual implementation, the laser opening may remove part of the silicon oxide film layer on the second tunnel oxide layer 310, and when the second doped polysilicon layer 320 is prepared by doping the second doping element and the third doping element in the subsequent process, the silicon oxide film layer of the second tunnel oxide layer 310 can be deposited to make up for the loss.

[0146] For example, as shown in FIG. 3, the borosilicate glass or phosphosilicate glass formed by the second doping element during diffusion in the second gate line area 321 is removed by laser opening, and part of the first silicon oxide film layer 311 is removed, and in the subsequent doping process, the second silicon oxide film layer 312 is formed in the second gate line area 321.

[0147] In some embodiments, doping the second gate line area 321 with the second doping element and the third doping element can include:

[0148] The second doped polysilicon layer 320 is generated by plasma enhanced chemical vapor deposition (PECVD) using the second doping element and the third doping element as a doping source.

[0149] The plasma enhanced chemical vapor deposition (PECVD) is a semiconductor thin film material preparation and other material thin film preparation method that utilizes glow discharge to ionize in a deposition chamber and then performs chemical reaction deposition on a substrate.

[0150] In this embodiment, the polysilicon layer doped with oxygen elements is prepared by PECVD, and the surface concentration is high during PECVD preparation, which can ensure the contact effect of the second gate line area 321.

[0151] In actual implementation, the second doping element can be boron or phosphorus, the third doping element can be oxygen, and the doping source containing the third doping element can be carbon dioxide (CO2) or other oxygen-containing doping sources.

[0152] In some embodiments, the doping concentration of the second doping element in the second gate line area 321 is greater than the doping concentration of the second doping element in the second non-gate line area 322.

[0153] In this embodiment, the second gate line region 321 is set to a heavy doping concentration, which can effectively improve the contact performance of the second doped polysilicon layer 320 and the second gate line 330 at the second gate line region 321, and the second non-gate line region 322 is set to a low doping concentration, which can effectively reduce the parasitic absorption at the second non-gate line region 322 and improve the battery conversion efficiency.

[0154] In actual implementation, the second non-gate line region 322 adopts a low doping concentration to ensure low parasitic absorption, while the second gate line region 321 can increase oxygen element doping to improve the contact performance and improve the battery conversion efficiency.

[0155] A specific embodiment will be described below.

[0156] An N-type silicon wafer is used as a silicon substrate 100, the N-type silicon wafer is textured and cleaned to remove contaminants on the surface of the N-type silicon wafer.

[0157] A silicon oxide layer (corresponding to the first tunnel oxide layer 210) and a first precursor layer are formed on the N-type silicon wafer by low pressure chemical vapor deposition (LPCVD).

[0158] The N-type silicon wafer subjected to LPCVD is placed in a phosphorus diffusion tube, high-temperature deposition and advancement are performed to form a front low-doped N-type first doped polysilicon layer, and laser is used for secondary doping to form a heavily doped first doped polysilicon layer at the first gate line region 221.

[0159] It can be understood that the back of the N-type silicon wafer also forms a phosphosilicate glass (PSG) in the phosphorus diffusion tube, the back PSG is removed using a chain machine, and polishing treatment and cleaning are performed.

[0160] The N-type silicon wafer is placed in LPCVD to form a back first silicon oxide film layer 311 and a second precursor layer, and the silicon wafer is placed in a boron diffusion tube, high-temperature deposition and advancement are performed to form a back low-doped P-type second doped polysilicon layer 320.

[0161] Laser film opening is used to remove borosilicate glass (BSG) at the back second gate line region 321, and a polishing / texturing scheme is used to remove laser damage, and after the treatment, the first silicon oxide film layer 311 remains, part of the silicon oxide film layer is thinned to prevent the silicon oxide from being too thick and causing poor contact.

[0162] The silicon wafer is placed in PECVD to form a second silicon oxide film layer 312 and a heavily doped P-type second doped polysilicon layer 320, B2H6 and other boron sources are adjusted by PECVD to realize heavy doping, and oxygen doping at the second gate line region 321 can be realized by CO2.

[0163] The P-type second doped polysilicon layer 320 in the second grid line area 321 is protected by INK mask, the rest is removed by chain machine, and borosilicate glass is polished.

[0164] After cleaning, the transparent conductive medium layer 240 is deposited on the front surface of the first non-grid line area 222 by magnetron sputtering (PVD) and reactive plasma deposition (RPD) in cooperation with the mask plate.

[0165] The battery is placed in PECVD to deposit the first passivation layer 260 and the second passivation layer 340 on both sides, and the first grid line 230 on the front surface and the second grid line 330 on the back surface are prepared by printing with slurry after the passivation layer is prepared.

[0166] In this embodiment, the first non-grid line area 222 on the light-receiving surface of the prepared solar cell is provided with a first doped polysilicon layer with low doping concentration and a transparent conductive medium layer 240, which can effectively reduce parasitic absorption, and the first doped polysilicon layer and the transparent conductive medium layer 240 with different band gaps can effectively enhance the passivation performance, and the first grid line area 221 is provided with a first doped polysilicon layer with high doping concentration, which forms good contact with the first grid line 230 and reduces the contact resistance of the battery.

[0167] The second non-grid line area 322 on the back surface is provided with a low doping concentration, and the second grid line area 321 is provided with a high doping concentration, which ensures the passivation performance of the back surface of the battery, and the second grid line area 321 also increases the doping of oxygen elements, which further reduces the contact resistance of the second grid line 330, and the front and back surfaces of the battery have excellent contact ability and electrical performance, which effectively improves the conversion efficiency of the battery.

[0168] The terms "first", "second", and the like in the specification and claims of the present disclosure are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present disclosure can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of a kind and do not limit the number of objects, for example, the first object can be one or more. In addition, "and / or" in the specification and claims indicates at least one of the connected objects, and the character " / ", generally indicates that the objects before and after are in a "or" relationship.

[0169] In the description of the present disclosure, it should be understood that the terms "up", "down", "front", "back", "top", "bottom", "inner", "outer", etc. indicate the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the present disclosure and simplify the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0170] In the description of the disclosure, "first feature", "second feature" can include one or more of the features.

[0171] In the description of the disclosure, the meaning of "a plurality of" is two or more.

[0172] In the description of the disclosure, "on" or "under" the first feature of the second feature can include that the first and second features are in direct contact, or can include that the first and second features are not in direct contact but are in contact through another feature between them.

[0173] In the description of the disclosure, "on", "above" and "over" the first feature of the second feature includes that the first feature is directly above and obliquely above the second feature, or only means that the first feature is higher than the second feature in horizontal height.

[0174] In the description of the disclosure, the description of the reference terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example", or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the disclosure. In the description of the disclosure, the exemplary description of the above terms does not necessarily mean the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0175] Although the embodiments of the disclosure have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and variations can be made to the embodiments without departing from the principles and spirit of the disclosure, and the scope of the disclosure is defined by the claims and their equivalents.

Claims

1. A solar cell, wherein: include: Silicon substrate; a first tunneling oxide layer, wherein the first tunneling oxide layer is disposed on the light-receiving surface of the silicon substrate; a first doped polysilicon layer, the first doped polysilicon layer being disposed on a side of the first tunneling oxide layer away from the silicon substrate, the first doped polysilicon layer being divided into a first gate line region and a first non-gate line region, and the first doped polysilicon layer comprising a first doping element; a first gate line, the first gate line being disposed on a side of the first doped polysilicon layer away from the first tunnel oxide layer and located in the first gate line region; a transparent conductive dielectric layer, the transparent conductive dielectric layer being disposed on a side of the first doped polysilicon layer away from the first tunneling oxide layer and located in the first non-gate line region, the bandgap width of the transparent conductive dielectric layer being different from the bandgap width of the first doped polysilicon layer; A first passivation layer is provided on a side of the transparent conductive medium layer away from the first doped polysilicon layer.

2. The solar cell according to claim 1, wherein Also includes: a second tunneling oxide layer, wherein the second tunneling oxide layer is disposed on a backlight surface of the silicon substrate; a second doped polysilicon layer, the second doped polysilicon layer being disposed on a side of the second tunneling oxide layer away from the silicon substrate, the second doped polysilicon layer comprising a second doping element of opposite doping type to the first doping element, the second doped polysilicon layer being divided into a second gate line region and a second non-gate line region; a second gate line, the second gate line being disposed on a side of the second doped polysilicon layer away from the second tunneling oxide layer and located in the second gate line region; A second passivation layer is provided on a side of the second doped polysilicon layer away from the second tunneling oxide layer and is located in the second non-gate line region.

3. The solar cell according to claim 2, wherein The second gate line region further includes a third doping element.

4. The solar cell according to claim 3, wherein The third doping element is oxygen.

5. The solar cell according to any one of claims 2 to 4, wherein: The doping concentration of the second doping element in the second gate line region is greater than the doping concentration of the second doping element in the second non-gate line region.

6. The solar cell according to any one of claims 1 to 5, wherein: The doping concentration of the first doping element in the first gate line region is greater than the doping concentration of the first doping element in the first non-gate line region.

7. The solar cell according to any one of claims 1 to 6, wherein: The transparent conductive medium layer is a transparent conductive oxide film.

8. A method for preparing a solar cell, wherein: include: forming a first tunneling oxide layer on the light-receiving surface of the silicon substrate, and forming a first precursor layer on a side of the first tunneling oxide layer away from the silicon substrate; Doping the first precursor layer with a first doping element to obtain a first doped polysilicon layer, wherein the first doped polysilicon layer is divided into a first gate line region and a first non-gate line region; forming a transparent conductive dielectric layer in the first non-gate line region on a side of the first doped polysilicon layer away from the first tunnel oxide layer, wherein the band gap width of the transparent conductive dielectric layer is different from the band gap width of the first doped polysilicon layer; A first passivation layer is formed on a side of the transparent conductive medium layer away from the first doped polysilicon layer, and a first gate line is formed in the first gate line region on a side of the first doped polysilicon layer away from the first tunnel oxide layer.

9. The method for preparing a solar cell according to claim 8, wherein: The method further comprises: forming a second tunneling oxide layer on the backlight surface of the silicon substrate, and forming a second precursor layer on a side of the second tunneling oxide layer away from the silicon substrate; doping the second precursor layer with a second doping element having a doping type opposite to that of the first doping element to obtain a second doped polysilicon layer, wherein the second doped polysilicon layer is divided into a second gate line region and a second non-gate line region; A second gate is formed in the second gate line region on a side of the second doped polysilicon layer away from the second tunnel oxide layer, and a second passivation layer is formed in the second non-gate line region on a side of the second doped polysilicon layer away from the second tunnel oxide layer.

10. The method for preparing a solar cell according to claim 9, wherein: The step of doping the second precursor layer with a second doping element having a doping type opposite to that of the first doping element comprises: diffusing the second doping element into the second precursor layer; Performing laser molding on the second gate line region; The second gate line region is doped with the second doping element and the third doping element.

11. The method for preparing a solar cell according to claim 10, wherein: The step of doping the second doping element and the third doping element in the second gate line region includes: The second doping element and the third doping element are used as doping sources to form the second doped polysilicon layer through plasma enhanced chemical vapor deposition.

12. The method for preparing a solar cell according to claim 10 or 11, wherein: The doping concentration of the second doping element in the second gate line region is greater than the doping concentration of the second doping element in the second non-gate line region.

13. The method for preparing a solar cell according to any one of claims 8 to 12, wherein: The doping concentration of the first doping element in the first gate line region is greater than the doping concentration of the first doping element in the first non-gate line region.

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