Pixel driving circuit, display device, and display driving method

Abstract

A pixel driving circuit, a display device, and a display driving method. The pixel driving circuit comprises a driving transistor (DTFT) and a voltage measurement and acquisition circuit, the voltage measurement and acquisition circuit comprising a signal holding capacitor (Chdg), and the voltage measurement and acquisition circuit being used for measuring and acquiring a threshold voltage (Vth) of the driving transistor (DTFT) when a charging power supply charges the signal holding capacitor (Chdg) by means of the driving transistor (DTFT), or when a discharging power supply discharges the signal holding capacitor (Chdg) by means of the driving transistor (DTFT); and the pixel driving circuit further comprises a compensation sub-circuit, the compensation sub-circuit being connected to the driving transistor (DTFT), and the compensation sub-circuit being used for compensating for the charge rate or discharge rate difference of the driving transistor (DTFT) when the voltage measurement and acquisition circuit measures and acquires the threshold voltage (Vth) of the driving transistor (DTFT).

Description

Pixel driving circuit, display device and display driving method

[0001] Cross-reference to related applications

[0002] The present disclosure claims priority to Chinese Patent Application No. 202410417872.1, filed in China on April 8, 2024, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] The present application relates to the technical field of display, in particular to a pixel driving circuit, a display device and a display driving method. BACKGROUND

[0004] In flat panel display technology, the threshold voltage (Threshold Voltage, V th ) of the driving thin film transistor (Driving Thin Film Transistor, DTFT) usually has certain spatial and temporal variability. Such variability will affect the consistency of the pixel OLED driving current output by the DTFT of the AMOLED (Active Matrix Organic Light Emitting Diode, Active Matrix Organic Light Emitting Diode) pixel circuit according to the data voltage (Data Voltage, V dt ). Therefore, the AMOLED pixel circuit needs to have a DTFT V th variability compensation function. The voltage signal driving (Voltage driving scheme) pixel circuit carries out V th compensation. The basis is to detect (detect, obtain) the DTFT V th signal, and then use the detected V th signal and the refresh V dt signal to couple to form a voltage signal loaded between the DTFT gate-source. The V th component in the DTFT gate-source voltage (Gate-source Voltage, V gs ) compensates for the variability of V th , and the V dt component controls the DTFT output driving current. SUMMARY

[0005] The present application provides a pixel driving circuit, a display device and a display driving method.

[0006] In a first aspect, embodiments of the present application provide a pixel driving circuit, comprising a driving transistor and a voltage detection circuit, the voltage detection circuit comprising a signal holding capacitor, the voltage detection circuit being configured to detect a threshold voltage of the driving transistor when a charging power source charges the signal holding capacitor through the driving transistor or when a discharging power source discharges the signal holding capacitor through the driving transistor.

[0007] The pixel driving circuit further comprises a compensation sub-circuit, the compensation sub-circuit being connected to the driving transistor, the compensation sub-circuit being configured to compensate for a charging rate or discharging rate difference of the driving transistor when the voltage detection circuit detects the threshold voltage of the driving transistor.

[0008] In some embodiments, the driving transistor is a P-type transistor, a voltage variation end of the signal holding capacitor is connected to a gate of the driving transistor, and the compensation sub-circuit comprises a compensation element, the compensation element being connected between the voltage variation end of the signal holding capacitor and a charging path switch.

[0009] In some embodiments, the driving transistor is a P-type transistor, a voltage variation end of the signal holding capacitor is connected to a source of the driving transistor, and the compensation sub-circuit comprises a compensation element, the compensation element being connected between the voltage variation end of the signal holding capacitor and a discharging path switch.

[0010] In some embodiments, the driving transistor is an N-type transistor, a voltage variation end of the signal holding capacitor is connected to a gate of the driving transistor, and the compensation sub-circuit comprises a compensation element, the compensation element being connected between the voltage variation end of the signal holding capacitor and a discharging path switch.

[0011] In some embodiments, the driving transistor is an N-type transistor, a voltage variation end of the signal holding capacitor is connected to a source of the driving transistor, and the compensation sub-circuit comprises a compensation element, the compensation element being connected between the voltage variation end of the signal holding capacitor and a charging path switch.

[0012] In some embodiments, the compensation sub-circuit comprises a compensation capacitor, a field effect transistor having a voltage-controlled variable capacitance characteristic, or a thin film transistor having a voltage-controlled variable capacitance characteristic.

[0013] In some embodiments, the pixel driving circuit comprises a switching transistor, the switching transistor being a double-gate transistor, the switching transistor comprising a first switching transistor relatively far away from the signal holding capacitor, and a second switching transistor relatively close to the signal holding capacitor, the second switching transistor being multiplexed as the compensation sub-circuit.

[0014] In some embodiments, a width of a channel region of the first switch transistor is less than a width of a channel region of the second switch transistor.

[0015] In a second aspect, the embodiments of the present application provide a display device, comprising the pixel driving circuit of any one of the first aspect.

[0016] In a third aspect, the embodiments of the present application provide a display driving method, applied to the display device of the second aspect, and the method comprises the following steps:

[0017] controlling the driving transistor to be turned on to charge or discharge the signal holding capacitor;

[0018] compensating the electric quantity of the signal holding capacitor by the compensation sub-circuit.

[0019] In some embodiments, the compensating the electric quantity of the signal holding capacitor by the compensation sub-circuit comprises:

[0020] compensating the electric quantity of the signal holding capacitor when or after the charging path switch or the discharging path switch is turned off, and before the driving transistor forms an effective drive to the light emitting unit.

[0021] In some embodiments, when displaying the Nth frame of image, the compensating the electric quantity of the signal holding capacitor further comprises:

[0022] resetting the signal holding capacitor before a driving period of the (N-1)th frame of image ends and before the voltage detection circuit detects the threshold voltage of the driving transistor corresponding to the Nth frame of image.

[0023] In some embodiments, the method further comprises:

[0024] resetting the signal holding capacitor before a circuit reset period corresponding to the Nth frame of image.

[0025] In some embodiments, the method further comprises:

[0026] multiplexing a path switch timing control signal of the voltage detection circuit as a timing control signal for resetting and operating the compensation sub-circuit. BRIEF DESCRIPTION OF DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the description of the embodiments of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor under the premise of the drawings.

[0028] FIG. 1A is a circuit diagram of a pixel driving circuit in an embodiment of the present application;

[0029] FIG. 1B is another circuit diagram of a pixel driving circuit in an embodiment of the present application;

[0030] FIG. 1C is another circuit diagram of a pixel driving circuit in an embodiment of the present application;

[0031] FIG. 2A is another circuit diagram of a pixel driving circuit in an embodiment of the present application;

[0032] FIG. 2B is another circuit diagram of a pixel driving circuit in an embodiment of the present application;

[0033] FIG. 2C is another circuit diagram of a pixel driving circuit in an embodiment of the present application;

[0034] FIG. 2D is another circuit diagram of a pixel driving circuit in an embodiment of the present application;

[0035] FIG. 3A is another circuit diagram of a pixel driving circuit in an embodiment of the present application;

[0036] FIG. 3B is a driving timing diagram of the pixel driving circuit shown in FIG. 3A;

[0037] FIG. 4A is another circuit diagram of a pixel driving circuit in an embodiment of the present application;

[0038] FIG. 4B is a driving timing diagram of the pixel driving circuit shown in FIG. 4A;

[0039] FIG. 5A is another circuit diagram of a pixel driving circuit in an embodiment of the present application;

[0040] FIG. 5B is a driving timing diagram of the pixel driving circuit shown in FIG. 5A;

[0041] FIG. 6A is another circuit diagram of a pixel driving circuit in an embodiment of the present application;

[0042] FIG. 6B is a driving timing diagram of the pixel driving circuit shown in FIG. 6A;

[0043] FIG. 7A is another circuit diagram of a pixel driving circuit in an embodiment of the present application;

[0044] FIG. 7B is a driving timing diagram of the pixel driving circuit shown in FIG. 7A;

[0045] FIG. 8A is another circuit diagram of a pixel driving circuit in an embodiment of the present application;

[0046] FIG. 8B is a driving timing diagram of the pixel driving circuit shown in FIG. 8A;

[0047] FIG. 9 is another circuit diagram of a pixel driving circuit in an embodiment of the present application;

[0048] FIG. 10 is another circuit diagram of a pixel driving circuit according to an embodiment of the present application. DETAILED DESCRIPTION

[0049] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort belong to the scope of the present application.

[0050] The terms "first", "second", and the like in the embodiments of the present application are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product, or device including a series of steps or units does not necessarily limit to those clearly listed steps or units, but can include other steps or units not clearly listed or inherent to the process, method, product, or device. In addition, "and / or" is used in the present application to represent at least one of the connected objects, for example, A and / or B and / or C represents seven cases including A alone, B alone, C alone, A and B both exist, B and C both exist, A and C both exist, and A, B and C all exist.

[0051] The present application provides a pixel driving circuit and a display device using the same.

[0052] In one embodiment, the pixel driving circuit includes a driving transistor DTFT and a voltage sensing circuit, the voltage sensing circuit includes a holding capacitance C hdg , and the voltage sensing circuit is configured to sense a threshold voltage V hdg of the driving transistor DTFT when a charging source charges the holding capacitance C hdg or a discharging source discharges the holding capacitance C th .

[0053] As shown in FIGS. 1A to 1C, taking a P-type TFT as an example, specifically, a charging source or a discharging source is connected to the DTFT to charge or discharge a voltage variation end (N var ) of the holding capacitance C var , and the other end of the holding capacitance C hdg is connected to a voltage fixing end (N fxd ) with a fixed voltage (V fxd ).

[0054] At the start time t0 of the charging or discharging process, the voltage at the changing terminal V var =V t0 , DTFT is in the on state. Then, as the charging or discharging process V var The change of the gate-source voltage (V gs ), the current through the DTFT continues to decrease. When V var Change to DTFT V gs Approximately equal to V th When the charge or discharge process tends to stop.

[0055] At this moment, the signal holding capacitor C hdg Changing end N var V th The voltage signal V var Based on the fixed end N fxd Voltage V fxd Keep.

[0056] As shown in FIG. 1A and FIG. 1B , in some embodiments, C hdg The variable terminal voltage feedback structure is N var Directly connected to the gate or source of the DTFT, where g represents the gate, s represents the source, and d represents the drain.

[0057] As shown in FIG. 1C , in some other embodiments, C hdg Connected between the gate and source of DTFT, but the variable terminal N var It is connected to the source, so it can be considered as a special form of the connection shown in Figure 1B.

[0058] It is understandable that the embodiments shown in FIG. 1A to FIG. 1C are exemplified by taking the DTFT as a P-type TFT. Obviously, the DTFT may also be an N-type TFT, the only difference being that the charging and discharging polarities are different.

[0059] It should be understood that the switch SW in the circuit is used to end V th Detection process. According to the equivalent principle, SW can be set at C hdg Other locations between the charging or discharging power source, for C hdg There is no special process end control switch circuit in the path between the charging or discharging power supply, so it can be considered that the V th In the later stage of the detection process, the DTFT is close to being cut off, that is, the DTFT is equivalent to a switch that ends the charging or discharging process.

[0060] According to the characteristics of TFT devices, the current through the DTFT will increase as the gate-source voltage approaches V thIt decreases sharply, so compared with other working processes of AMOLED pixel circuit, it is more convenient to obtain accurate V th A longer charging or discharging process is required.

[0061] Set V th The collection process takes enough time, V gs Close enough to V th Time (t off ), the process charge or discharge rate is 1; at the beginning of the process (t0), the charge or discharge rate is 0. Due to the systematic limitations of the pixel circuit, usually V th The capture process occurs sometime before the charge or discharge rate approaches 1 sufficiently (t stp ) is controlled and ends, at this moment the process charge or discharge rate R chr for:

[0062] In the above formula, the difference V var (t off )-V var (t stp ) is equal to the time sufficient (t off ) Picked up the ideal V th With time limit (t stp ) Seized V th stp The difference between th Error ER caused by insufficient charging or discharging rate during the pickup process chr ; Difference V var (t off )-V var (t0) is the capacitance change terminal N during the charging or discharging process var Voltage swing, denoted as V amp .

[0063] Set V t0 ,V fxd ,V ref and V var Related voltages and V th The same DTFT source potential is used as the reference zero voltage, then V amp It can also be expressed as V th With V t0 The difference between the process error ER chr and the charge swing V amp The charge or discharge rate is

[0064] The closer the charge or discharge rate is to 1, the more V th stp The closer to the ideal V th The smaller the error in the value, charging or discharging process.

[0065] However, due to the increase of display resolution (PPI) and frame frequency, the limitation of DTFT itself, and other reasons, the AMOLED pixel circuit V th The capture process often has insufficient charging or discharging rate, which affects the V th The capture accuracy and variability compensation quality. By setting a compensation capacitor, the charging or discharging rate of the V th The capture process can be improved by setting a compensation capacitor, which can improve the charging or discharging rate of the V th The variability compensation quality.

[0066] In this embodiment, the pixel driving circuit further includes a compensation sub-circuit connected to the driving transistor DTFT, and the compensation sub-circuit is used to compensate for the charging or discharging rate difference of the driving transistor DTFT when the voltage capture circuit captures the threshold voltage of the driving transistor DTFT.

[0067] The application also provides a display driving method applied to a display device including any of the pixel driving circuits in the application.

[0068] In one embodiment, the display driving method includes the following steps:

[0069] The driving transistor is turned on to charge or discharge the signal holding capacitor;

[0070] The amount of electricity of the signal holding capacitor is compensated by the compensation sub-circuit.

[0071] In this embodiment, according to the specific V th The compensation capacitor is set according to the charging or discharging circuit structure of the detection acquisition process, and the compensation capacitor capacity increment or decrement is used to compensate for the V th The error caused by insufficient charging or discharging rate in the detection process is used to obtain more accurate V th value.

[0072] Further, the influence of the switching error of the switching transistor STFT in the charging or discharging path on the acquisition of V th In some embodiments, the switching error is also used to compensate for the charging rate error.

[0073] In one embodiment, the driving transistor is a P-type transistor, the voltage variable end of the signal holding capacitor is connected to the gate of the driving transistor, and the compensation sub-circuit includes a compensation element connected between the voltage variable end of the signal holding capacitor and the charging path switch.

[0074] As shown in FIG. 2A, in this embodiment, the V th The capture circuit capacitor C hdg The variable end is connected to the DTFT gate, and the charging power source charges Chdg Charging, in this embodiment, the compensating element is a compensating capacitor C comp For example, more specifically, the compensating capacitor C comp Is a voltage-controlled decremental compensating capacitor.

[0075] In practice, in C hdg The varying terminal or C hdg The compensating capacitor C is connected to the other node between the charging path switch and the varying terminal of the signal holding capacitor. comp After the charging process is completed, the compensating capacitor C comp is controlled to reduce its capacity to absorb the charge to compensate for V th The pickup process C hdg The lack of charging rate improves the accuracy of obtaining V th .

[0076] In one of the embodiments, the driving transistor is a P-type transistor, the voltage varying terminal of the signal holding capacitor is connected to the source of the driving transistor, and the compensating sub-circuit includes a voltage-controlled incremental compensating element, which is connected between the voltage varying terminal of the signal holding capacitor and the discharging path switch.

[0077] As shown in FIG. 2B, in this embodiment, V th The pickup circuit capacitor C hdg The varying terminal is connected to the source of the DTFT, and the discharge source is connected to C hdg Discharging, in this embodiment, the compensating element is a compensating capacitor C comp For example, more specifically, the compensating capacitor C comp Is a voltage-controlled decremental compensating capacitor.

[0078] In practice, in C hdg The varying terminal or C hdg The compensating capacitor C is connected to the other node between the charging path switch and the varying terminal of the signal holding capacitor. comp After the discharging process is completed, the compensating capacitor C comp is controlled to increase its capacity to absorb the charge to compensate for V th The pickup process C hdg The lack of discharging rate improves the accuracy of obtaining V th .

[0079] In some of the embodiments, the driving transistor DTFT is an N-type transistor, the voltage varying terminal of the signal holding capacitor is connected to the gate of the driving transistor DTFT, and the compensating sub-circuit includes a voltage-controlled incremental compensating element, which is connected between the voltage varying terminal of the signal holding capacitor and the discharging path switch.

[0080] In some embodiments, the driving transistor DTFT is an N-type transistor, the voltage variation end of the signal holding capacitor is connected to the source of the driving transistor DTFT, and the compensation sub-circuit comprises a voltage-controlled decrement compensation element connected between the voltage variation end of the signal holding capacitor and the charging path switch.

[0081] As shown in FIG. 2C and FIG. 2D, when an N-type TFT is used as the DTFT, only when V th C hdg The charging and discharging polarities and the setting of the compensation capacitor capacity variation polarity are opposite to those in the case of the P-type DTFT.

[0082] In this embodiment, V th During the detection process, C hdg If the variation end is charged, the insufficient charging rate compensation capacitor is a capacitor decrement compensation; and if the variation end is discharged, the insufficient discharging rate compensation capacitor is a capacitor increment compensation. th During the detection process, C hdg If the variation end is charged, the insufficient charging rate compensation capacitor is a capacitor decrement compensation; and if the variation end is discharged, the insufficient discharging rate compensation capacitor is a capacitor increment compensation.

[0083] In some embodiments, the voltage-controlled variable-capacitance compensation capacitor is a MOS (Metal Oxide Semiconductor) capacitor, an equivalent MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having similar voltage-controlled variable-capacitance characteristics, or an equivalent TFT device having similar voltage-controlled variable-capacitance characteristics. When the voltage across the compensation capacitor rises or falls across the threshold of the device, the capacitance capacity of the P-type MOS capacitor or the equivalent MOSFET / TFT device monotonically decreases or increases, and the capacitance capacity of the N-type MOS capacitor or the equivalent MOSFET / TFT device monotonically increases or decreases. In an AMOLED pixel circuit, if the compensation capacitor is an equivalent TFT, the compensation timing control signal can also be V gH → V gL or V gL → V gH The compensation capacitor is controlled by a step voltage.

[0084] In some embodiments, the compensation of the electric quantity of the signal holding capacitor by the compensation sub-circuit comprises:

[0085] The electric quantity of the signal holding capacitor is compensated when or after the charging path switch or the discharging path switch is turned off, and before the driving transistor forms an effective drive to the light-emitting unit.

[0086] As shown in FIG. 3A and FIG. 3B, in this embodiment, the compensation capacitor timing control signal CT acts (V gH → V gL or V gL → VgH ) control the compensation capacitor capacity C comp The corresponding change compensates for the insufficient charging or discharging rate at the time when the charging or discharging path switch SW is turned off or after the switch is turned off, before the DTFT effectively drives the pixel OLED.

[0087] In some embodiments, when displaying the Nth frame of image, the method further comprises, before compensating the electric quantity of the signal holding capacitor:

[0088] At the end of the driving period of the (N-1)th frame of image, and before the voltage detection circuit detects the threshold voltage of the driving transistor corresponding to the Nth frame of image, the signal holding capacitor is controlled to be reset.

[0089] Further, in some embodiments, the method further comprises, before the circuit reset period corresponding to the Nth frame of image, controlling the signal holding capacitor to be reset.

[0090] In the technical solution of the embodiment, V th The condition for the precision compensation effect is that the fixed end potential of the signal holding capacitor still maintains a fixed potential.

[0091] It is found through tests that, during the circuit V th of the current frame period, the charge absorbed or discharged during the reset process of the equivalent compensation capacitor T comp has a smaller influence, so that the signal holding capacitor can be controlled to be reset before the voltage detection circuit detects the threshold voltage of the driving transistor corresponding to the Nth frame of image, or even before the circuit V th of the current frame period detects the threshold voltage.

[0092] In order to further reduce the interference on the display process of the previous frame period or the circuit V dt refresh and V th acquisition compensation process of the current frame period, the time when the timing control signal controls the reset of the compensation capacitor is set to be before the driving process of the previous frame period is basically completed and before the reset process of the circuit of the current frame period in the embodiment. During this period, the charge absorbed or discharged during the reset process of the equivalent compensation capacitor T comp has no influence on the display process of the previous frame period or the circuit V dt refresh and V th acquisition compensation process of the current frame period.

[0093] The following is further described in combination with an exemplary pixel driving circuit.

[0094] As shown in FIG. 3A, FIG. 3A is a pixel driving circuit including a P-type DTFT (T3). The circuit itself is a related art, which is not further limited and described herein.

[0095] Similar to the pixel driving circuit shown in Fig. 1A, in this embodiment, a TFT is used as the equivalent compensation capacitor T comp . th The capture process is the signal holding capacitor C st . The variable terminal N1 is connected to the gate of the DTFT, and through C st The charging process obtains V th The voltage at the gate of the DTFT.

[0096] As shown in Fig. 3B, the timing AZj falling edge controls the STFT T2 to turn on V th The capture process starts, and the voltage at node N1 is V init +V dt -V ref , and the voltage at the fixed terminal of the capacitor C st The voltage at node N2 is V dt . The AZj rising edge controls the STFT T2 to turn off V th The capture process stops. The corresponding relationship between the relevant marks in Fig. 3A and the above description and the relevant marks in Fig. 1 and equations (1), (2), and (3) is as follows:

[0097] The node N1 corresponds to the node N var in Fig. 1A, and the node N2 corresponds to the node N fxd in Fig. 1A. The falling edge of the AZj timing corresponds to the start time t0 of the charging and discharging, and the rising edge corresponds to the end time t stp of the charging and discharging. st As the signal holding capacitor C hdg , the voltage at node N1 at the falling edge of the AZj timing is V t0 , and the voltage at node N2 is V fxd . In this way, the V th stp captured by node N1 at the process stop is:

[0098] In the circuit in Fig. 3A, a P-type TFT T comp is used as the equivalent device for the compensation capacitor (the capacity is still represented as C comp ), and a special compensation capacitor action and reset control timing CTj is set.

[0099] After the charging process ends and the charging path STFT T2 (corresponding to SW in Fig. 1A) is controlled to turn off by the timing AZj, the timing CTj step voltage V gL →V gH controls the action of the equivalent device T comp , and the C comp bf →C comp aft capacity changes (decreases).

[0100] Because C comp The charge discharged due to the decrease in capacity enters the holding capacitor C st (C hdg ), so that node N1(N var )The voltage on the th stp →V th comp , the charge and voltage in the capacitor system are balanced again. T comp Before and after the equivalent device compensation action, the capacitor T comp (C comp ) and C st The amount of charge and the change in the voltage of the related nodes satisfy the charge conservation relationship:

[0101] Arranging the above formula, we get:

[0102] The capacitance change of the compensation capacitor before and after the controlled change is δC comp =C comp aft -C comp bf After the compensation action, the total capacitance C connected to node N1 sum =C st +C comp aft .

[0103] V th stp Substituting expression (3) into the equation, we get:

[0104] Typically, V th The charging rate during the collection process is relatively close to 1, and the change in the compensation capacitor capacity is also relatively small relative to the total capacity. Therefore, the third term in (5) is a high-order small quantity. Ignore the high-order small quantity and substitute V amp After sorting out the expression, formula (5) can be approximated as:

[0105] Among them, the second and third items are related to V th Variability is not directly related to the effective signal V dt -V ref Other than that, the rest can be largely controlled by V dt γ correction method improves the translation error. th (and its variability) directly related to the first item:

[0106] From formula (6+), we can see that by using appropriate compensation capacitor C compThe setting (change amount polarity and size) can compensate for V th The detection process error caused by insufficient charging rate.

[0107] In one embodiment, the display driving method further comprises:

[0108] The pass switch timing control signal of the voltage detection circuit is multiplexed as the timing control signal for resetting and operating the compensation sub-circuit.

[0109] As shown in FIGS. 4A and 4B, the main difference from the embodiment shown in FIGS. 3A and 3B is that, in the present embodiment, the shared V th The detection charging pass switch timing control signal AZj is multiplexed as the timing control signal CTj for resetting and operating the compensation capacitor.

[0110] In the embodiment shown in FIG. 3B, the control T comp The rising edge V gL →V gH of the timing control signal CTj for compensation operation and the timing control signal AZj for controlling the charging pass STFT T2 to be off are adjacent in time and both satisfy the condition for controlling the timing of compensation capacitor operation, so the timing control signal AZj can be shared as the T com timing control signal for compensation operation.

[0111] As shown in FIG. 4, the CTj controls the equivalent compensation capacitor T comp to be reset at the falling edge V gH →V gL of the timing control signal AZj. The ideal time for this to occur is before the n frame circuit is reset after the basic display driving of the n-1 frame is basically completed. The falling of the AZj timing initiates the V th detection process, and the T comp with the storage capacitor C st (C hdg ) exchanges charges, which has a certain impact on the charging / discharging rate of the V th detection process. Since the DTFT current is relatively large at the start time of the compensation process, the impact of the compensation capacitor reset on the charging current proportion is very small, and the impact on the final charging rate is relatively small.

[0112] As shown in FIGS. 5A and 5B, in the present embodiment, the basic circuit of the pixel circuit uses an N-type DTFT (T3). The pixel circuit V th The equivalent circuit of the detection process is the same as the basic structure shown in FIG. 1C, and the compensation capacitor is the equivalent TFT T comp . The access point of the compensation capacitor T comp may be the node N2 (i.e., the C hdg variable terminal) shown in FIG. 5A, or the node N0.

[0113] In some of these embodiments, considering V th In the later stage of the acquisition process, the channel resistance of the DTFT is usually relatively large, so setting the compensation capacitor access point at node N2 is more conducive to the equivalent compensation capacitor T comp with C st Rapidly exchange charge to compensate node N1 to obtain V th Charging error.

[0114] In this embodiment, since the fixed terminal N of the signal holding capacitor fxd In V th During the working process after the seizure process, it will become a DC floating node. The action step voltage of the compensation capacitor timing control signal CTj should be set before the potential of the capacitor fixed end floats, and sufficient time should be left for the compensation capacitor C comp and the signal holding capacitor C hdg The charge exchange reaches equilibrium.

[0115] In another embodiment, the compensation capacitor timing control signal may also be shared with the charging path switch timing control signal.

[0116] As shown in FIG6A and FIG6B, in this embodiment, V is shared based on the embodiment shown in FIG5A and FIG5B. th The charging path switch timing control signal EMj is captured as the timing control signal CTj for resetting and operating the compensation capacitor.

[0117] In another embodiment, as shown in FIG7A and FIG7B , the driving transistor DTFT (T1) is an N-type TFT. th The equivalent circuit of the seizure process corresponds to that shown in Figure 1A, but due to the different polarity of the DTFT, V th The capture process is the signal holding capacitor C hdg During the discharge process, the equivalent compensation capacitor T comp for incremental capacitance compensation.

[0118] In another embodiment, as shown in FIG8A and FIG8B , the difference from the embodiment shown in FIG4A and FIG6A is that in the discharge process-related circuit of this embodiment, the compensation capacitor operation timing control signal cannot directly share the discharge path STFT timing control signal with equivalent TFT devices of the same type. However, this embodiment can share the path STFT timing control signal by using equivalent TFT devices of the opposite type.

[0119] In one embodiment, the pixel driving circuit includes a switching transistor STFT, which is a dual-gate transistor. The switching transistor STFT includes a first switching transistor T2-1 that is relatively far away from the signal holding capacitor, and a second switching transistor T2-2 that is relatively close to the signal holding capacitor; wherein the second switching transistor T2-2 is multiplexed as a compensation sub-circuit.

[0120] As shown in FIG9 , in this embodiment, the switch transistor STFT T3 of the discharge path is an N-type TFT, and an inverse type (P-type) compensation capacitor equivalent device T is used. comp , and it is also possible to share the timing control signal Sj with the discharge path STFT T3.

[0121] Since the pixel circuit V th The switching error of the STFT in the charging path is affected by the V th The error caused by insufficient charging rate has a certain compensation effect. Usually, the switching transistor STFT of the charging path is a double-gate TFT, in which the one near C st (C hdg ) can be specially designed for the channel capacitance to obtain the capacitance change required as a compensation capacitor.

[0122] It should be understood that since the equivalent capacitance decreases when the STFT is turned off, it is only suitable for charging to obtain V as a compensation capacitor. th Related structural circuits.

[0123] In this embodiment, using V th The solution of seizing the equivalent capacitance of the charging path STFT T2 (dual-gate STFT, which can be divided into two sections, T2-1 and T2-2) as the compensation capacitance was found.

[0124] In the embodiment shown in FIG9 , V th The timing control signal AZj of the charging path switch and the timing control signal CTj of the compensation capacitor reset and action use different signals. The timing CTj action controls the time when T2-2 is turned off slightly later than T2-1, so that the charge discharged by the T2-2 reduction capacitor will all flow to C st Therefore, the T2-2 channel of the dual-gate STFT needs to be adjusted according to the compensation charge requirement. Generally speaking, a larger T2-2C gs +C gd .

[0125] In implementation, the double-gate STFT (T2-1, T2-2) can adjust the width of the channel region of the first switch tube T2-1 and the second switch tube T2-2 according to the requirement of suppressing the leakage current. Further, in some embodiments, the width of the channel region of the first switch tube T2-1 is smaller than the width of the channel region of the second switch tube T2-2, which can further improve the compensation effect on the signal holding capacitor.

[0126] The above is the preferred embodiment of the present disclosure, it should be pointed out that, for those skilled in the art, without departing from the principles of the present disclosure, can make a number of improvements and refinements, these improvements and refinements should also be considered as the protection scope of the present disclosure.

Claims

1. A pixel driving circuit, comprising a driving transistor and a voltage detection circuit, wherein the voltage detection circuit includes a signal holding capacitor, and the voltage detection circuit is configured to detect a threshold voltage of the driving transistor when a charging power source charges the signal holding capacitor through the driving transistor, or when a discharging power source discharges the signal holding capacitor through the driving transistor; The pixel driving circuit further includes a compensation subcircuit connected to the driving transistor, and configured to compensate for a difference in a charging rate or a discharging rate of the driving transistor when the voltage detecting circuit detects a threshold voltage of the driving transistor.

2. The pixel driving circuit according to claim 1, wherein: The driving transistor is a P-type transistor, the voltage change end of the signal holding capacitor is connected to the gate of the driving transistor, and the compensation subcircuit includes a compensation element connected between the voltage change end of the signal holding capacitor and the charging path switch.

3. The pixel driving circuit according to claim 1, wherein: The driving transistor is a P-type transistor, the voltage change end of the signal holding capacitor is connected to the source of the driving transistor, and the compensation subcircuit includes a compensation element connected between the voltage change end of the signal holding capacitor and the discharge path switch.

4. The pixel driving circuit according to claim 1, wherein: The driving transistor is an N-type transistor, the voltage change end of the signal holding capacitor is connected to the gate of the driving transistor, and the compensation subcircuit includes a compensation element connected between the voltage change end of the signal holding capacitor and the discharge path switch.

5. The pixel driving circuit according to claim 1, wherein: The driving transistor is an N-type transistor, the voltage change end of the signal holding capacitor is connected to the source of the driving transistor, and the compensation subcircuit includes a compensation element connected between the voltage change end of the signal holding capacitor and the charging path switch.

6. The pixel driving circuit according to any one of claims 1 to 5, wherein: The compensation subcircuit includes a compensation capacitor, a field effect transistor with voltage-controlled variable capacitance characteristics, or a thin film transistor with voltage-controlled variable capacitance characteristics.

7. The pixel driving circuit according to claim 1, wherein: The pixel driving circuit includes a switching transistor, which is a dual-gate transistor. The switching transistor includes a first switching transistor relatively far away from the signal holding capacitor and a second switching transistor relatively close to the signal holding capacitor. The second switching transistor is multiplexed as the compensation sub-circuit.

8. The pixel driving circuit according to claim 7, wherein: The width of the channel region of the first switching transistor is smaller than the width of the channel region of the second switching transistor. 9 . A display device comprising the pixel driving circuit according to claim 1 .

10. A display driving method, applied to the display device according to claim 9, the method comprising the following steps: Controlling the driving transistor to conduct to charge or discharge the signal holding capacitor; The electric quantity of the signal holding capacitor is compensated by the compensation sub-circuit.

11. The method according to claim 10, wherein: The compensating the electric quantity of the signal holding capacitor by the compensation sub-circuit includes: When the charging path switch or the discharging path switch is turned off or after being turned off, and before the driving transistor effectively drives the light emitting unit, the electric quantity of the signal storage capacitor is compensated.

12. The method of claim 11, wherein: When displaying the Nth frame of image, before compensating the electric quantity of the signal storage capacitor, the method further includes: After the driving period of the N-1th frame image ends and before the voltage detection circuit detects the threshold voltage of the driving transistor corresponding to the Nth frame image, the signal holding capacitor is controlled to be reset.

13. The method of claim 12, wherein: The method further comprises: Before the circuit reset period corresponding to the Nth frame image, the signal holding capacitor is controlled to be reset.

14. The method according to any one of claims 10 to 13, wherein The method further comprises: The path switch timing control signal of the voltage detection circuit is reused as the timing control signal for resetting and operating the compensation sub-circuit.

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