Mask transmission method and apparatus, and electronic device, storage medium and program product

Abstract

The present disclosure relates to the field of image rendering. Provided are a mask transmission method and apparatus, and an electronic device, a storage medium and a program product. The method is applied to a rendering pipeline of a graphics processing unit, and comprises: respectively performing rasterization processing on M primitives to determine M first masks, and respectively performing a depth test and / or a stencil test on the M first masks to determine M second masks; on the basis of the M second masks, performing a hidden surface removal test on the M first masks to determine a third mask; splitting the third mask to obtain M fourth masks, wherein the first mask and the fourth mask corresponding to the same primitive are identical; and inputting the M fourth masks into a pixel shader. The method not only ensures that a pixel shader can correctly receive rasterized masks, but also avoids the defect where a depth / stencil test and a hidden surface removal test remain disabled before the masks enter the pixel shader in a rendering pipeline, such that a graphics processing unit has lower design complexity and higher performance.

Description

Mask transmission method and device, electronic equipment, storage medium and program product

[0001] The present application claims priority to the Chinese patent application No. 202410437585.7, filed on April 11, 2024, and entitled "Mask transmission method and device, electronic equipment, storage medium and program product", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present disclosure relates to the field of image rendering, and in particular, to a mask transmission method and device, electronic equipment, storage medium and program product. BACKGROUND

[0003] In a Graphics Processing Unit (GPU) rendering pipeline, after a primitive is processed by vertex processing, clipping, viewport transformation and other operations, the primitive enters a rasterization stage. The rasterization calculates the pixel (or sampling point) positions covered by the primitive, and then outputs a mask indicating the pixel (or sampling point) information covered by the primitive and the starting coordinates of the pixel to a pixel shader.

[0004] In some application scenarios, in order to improve the image rendering quality, the mask after rasterization will be subjected to a Depth / Stencil Test and a Hidden Surface Removal (HSR) test. The opening of the Depth / Stencil Test and the HSR test can change the mask after rasterization, and output a new mask. At this time, the mask output by the HSR test will enter the pixel shader.

[0005] With the upgrade of the operating system, an Application Programming Interface (API) supporting the use of the mask after rasterization by the pixel shader for data processing has appeared. Since the opening of the Depth / Stencil Test and the HSR test can change the mask after rasterization, in order to adapt to the function of the API, two rendering pipelines are needed to transmit the mask after rasterization and the mask after the HSR test, respectively, which greatly increases the design complexity of the GPU.

[0006] The prior art proposes to close the Depth / Stencil Test and the HSR test before the mask enters the pixel shader, so as to realize the transmission of the mask after rasterization to the pixel shader by one rendering pipeline, and reduce the design complexity of the GPU. However, the cost is the performance degradation of the GPU. Therefore, how to correctly transmit the mask after rasterization to the pixel shader while the GPU has low design complexity and high performance has become a technical problem to be solved. SUMMARY

[0007] Therefore, the disclosure provides a mask transmission method and device, electronic equipment, storage medium and program product. The mask transmission method according to the disclosure improves the mechanism of hidden surface removal test, ensures that the pixel shader can correctly receive the rasterized mask, avoids the defect that the depth / stencil test and the hidden surface removal test cannot be opened before the mask enters the pixel shader in a rendering pipeline, and makes the graphics processor have lower design complexity and higher performance.

[0008] According to an aspect of the disclosure, a mask transmission method is provided. The method is applied to a rendering pipeline of a graphics processor, and the rendering pipeline includes a pixel shader. The method includes: performing rasterization processing on M primitives respectively, determining M first masks corresponding to the M primitives respectively, M being an integer greater than 1; performing depth test and / or stencil test on the M first masks respectively, determining M second masks corresponding to the M primitives respectively; performing hidden surface removal test on the M first masks according to the M second masks, determining a third mask corresponding to all of the M primitives; splitting the third mask to obtain M fourth masks corresponding to the M primitives respectively, the first mask and the fourth mask corresponding to the same primitive being the same; and in response to a first indication, inputting the M fourth masks into the pixel shader.

[0009] In a possible implementation, the rendering pipeline is used to render the M primitives to generate an image including N pixels, each pixel including K sampling points, N and K being integers greater than 1, each first mask including N masks corresponding to the N pixels respectively, each mask including K bits; each second mask including N masks corresponding to the N pixels respectively, each mask including K bits; the third mask including N groups of masks corresponding to the N pixels respectively, each group of masks including K masks, each mask including K bits; and each fourth mask including N masks corresponding to the N pixels respectively, each mask including K bits.

[0010] In a possible implementation, the rendering pipeline is used to render the M primitives to generate an image including N pixels, each pixel including K sampling points, N and K being integers greater than 1, and the performing hidden surface removal test on the M first masks according to the M second masks to determine the third mask corresponding to all of the M primitives includes: performing processing on the M first masks according to the M second masks to obtain M fifth masks, each fifth mask including N groups of masks corresponding to the N pixels respectively, each group of masks including K masks, each mask including K bits; and performing hidden surface removal test on the M fifth masks to determine the third mask.

[0011] In a possible implementation, the processing of the M first masks according to the M second masks to obtain M fifth masks comprises: when the tth bit of the jth mask of the ith second mask is equal to a first value, taking the jth mask of the ith first mask as the tth mask of the jth group of masks of the ith fifth mask, 0 < i ≤ M and being an integer, 0 < j ≤ N and being an integer, and 0 < t ≤ K and being an integer; when the tth bit of the jth mask of the ith second mask is equal to a second value, taking a mask of K second values as the tth mask of the jth group of masks of the ith fifth mask.

[0012] In a possible implementation, the hidden surface removal test on the M fifth masks to determine the third mask comprises: covering the fifth mask corresponding to a first overlaid primitive by the fifth mask corresponding to a second overlaid primitive according to the order of the overlaying of the M primitives to obtain the third mask.

[0013] In a possible implementation, the rendering pipeline is configured to render the M primitives to generate an image comprising N pixels, each pixel comprising K sampling points, N and K being integers greater than 1, the third mask comprising N groups of masks corresponding to the N pixels respectively, each group of masks comprising K masks, and each mask comprising K bits; and the splitting of the third mask to obtain M fourth masks corresponding to the M primitives respectively comprises: when the tth mask of the jth group of masks of the third mask corresponds to the ith primitive, taking the tth mask of the jth group of masks of the third mask as the jth mask of the ith fourth mask, 0 < i ≤ M and being an integer, 0 < j ≤ N and being an integer, and 0 < t ≤ K and being an integer; and when the ith primitive does not correspond to any mask of the jth group of masks of the third mask, taking a mask of K second values as the jth mask of the ith fourth mask.

[0014] In a possible implementation, the rendering pipeline is configured to render the M primitives to generate an image comprising N pixels, each pixel comprising K samples, N and K being integers greater than 1, the third mask comprises N groups of masks corresponding to the N pixels respectively, each group of masks comprises K masks, and each mask comprises K bits; the splitting the third mask to obtain M fourth masks corresponding to the M primitives respectively comprises: when the i th primitive corresponds to the t th mask of the j th group of masks of the third mask, taking the t th mask of the j th group of masks of the third mask as the t th mask of the j th group of masks of the i th seventh mask, 0 < i ≤ M and i is an integer, 0 < j ≤ N and j is an integer, and 0 < t ≤ K and t is an integer; when the i th primitive does not correspond to the t th mask of the j th group of masks of the third mask, taking a mask of K second values as the t th mask of the j th group of masks of the i th seventh mask; taking an or operation result of the j th group of masks of the i th seventh mask as the j th mask of the i th fourth mask.

[0015] In a possible implementation, the method further comprises: performing a hidden surface removal test on the M second masks to determine a sixth mask corresponding to all of the M primitives; splitting the sixth mask to obtain M eighth masks corresponding to the M primitives respectively; and in response to the second indication, inputting the M eighth masks to the pixel shader.

[0016] In a possible implementation, the rendering pipeline supports tile-based deferred rendering.

[0017] In a possible implementation, the rendering pipeline corresponds to a buffer, the buffer is used when performing the hidden surface removal test on the M first masks, the third mask comprises N groups of masks corresponding to N pixels respectively, each group of masks comprises K masks, and each mask comprises K bits, N and K being integers greater than 1; and the buffer comprises N storage locations, the j th storage location storing the j th group of masks of the third mask, 0 < j ≤ N and j is an integer.

[0018] According to another aspect of the present disclosure, a mask transmission apparatus is provided, which is applied to a rendering pipeline of a graphics processor, the rendering pipeline comprising a pixel shader, the apparatus comprising: a rasterization module configured to perform rasterization on M primitives respectively, determine M first masks corresponding to the M primitives respectively, M being an integer greater than 1; a first test module configured to perform depth test and / or stencil test on the M first masks respectively, determine M second masks corresponding to the M primitives respectively; a second test module configured to perform hidden surface removal test on the M first masks according to the M second masks, determine a third mask corresponding to all of the M primitives; split the third mask to obtain M fourth masks corresponding to the M primitives respectively; and in response to a first indication, input the M fourth masks to the pixel shader.

[0019] In a possible implementation, the rendering pipeline is configured to render the M primitives to generate an image comprising N pixels, each pixel comprising K sample points, N and K being integers greater than 1, each first mask comprising N masks corresponding to the N pixels respectively, each mask comprising K bits; each second mask comprising N masks corresponding to the N pixels respectively, each mask comprising K bits; the third mask comprising N groups of masks corresponding to the N pixels respectively, each group of masks comprising K masks, each mask comprising K bits; and each fourth mask comprising N masks corresponding to the N pixels respectively, each mask comprising K bits.

[0020] In a possible implementation, the rendering pipeline is configured to render the M primitives to generate an image comprising N pixels, each pixel comprising K sample points, N and K being integers greater than 1, and the performing hidden surface removal test on the M first masks according to the M second masks to determine the third mask corresponding to all of the M primitives comprises: performing processing on the M first masks according to the M second masks to obtain M fifth masks, each fifth mask comprising N groups of masks corresponding to the N pixels respectively, each group of masks comprising K masks, each mask comprising K bits; and performing hidden surface removal test on the M fifth masks to determine the third mask.

[0021] In a possible implementation, the performing processing on the M first masks according to the M second masks to obtain M fifth masks comprises: when a t-th bit of a j-th mask of an i-th second mask is equal to a first value, taking a t-th mask of a j-th group of masks of an i-th fifth mask as a t-th mask of a j-th mask of an i-th first mask, 0 < i ≤ M and i being an integer, 0 < j ≤ N and j being an integer, and 0 < t ≤ K and t being an integer; and when the t-th bit of the j-th mask of the i-th second mask is equal to a second value, taking K second value masks as the t-th mask of the j-th group of masks of the i-th fifth mask.

[0022] In a possible implementation, the hidden surface removal test on the M fifth masks, and determining the third mask, comprises: covering the fifth mask corresponding to a former overlaid primitive with the fifth mask corresponding to a latter overlaid primitive according to the order of the overlaying of the M primitives, to obtain the third mask.

[0023] In a possible implementation, the rendering pipeline is configured to render the M primitives to generate an image comprising N pixels, each pixel comprising K sampling points, N and K being integers greater than 1, the third mask comprises N groups of masks corresponding to the N pixels respectively, each group of masks comprising K masks, and each mask comprising K bits; and the splitting the third mask to obtain the M fourth masks corresponding to the M primitives respectively comprises: when the i th primitive corresponds to the t th mask of the j th group of masks of the third mask, taking the t th mask of the j th group of masks of the third mask as the j th mask of the i th fourth mask, 0 < i ≤ M and i being an integer, 0 < j ≤ N and j being an integer, and 0 < t ≤ K and t being an integer; and when the i th primitive does not correspond to each mask of the j th group of masks of the third mask, taking a mask of K second values as the j th mask of the i th fourth mask.

[0024] In a possible implementation, the rendering pipeline is configured to render the M primitives to generate an image comprising N pixels, each pixel comprising K sampling points, N and K being integers greater than 1, the third mask comprises N groups of masks corresponding to the N pixels respectively, each group of masks comprising K masks, and each mask comprising K bits; and the splitting the third mask to obtain the M fourth masks corresponding to the M primitives respectively comprises: when the i th primitive corresponds to the t th mask of the j th group of masks of the third mask, taking the t th mask of the j th group of masks of the third mask as the t th mask of the j th group of masks of the i th seventh mask, 0 < i ≤ M and i being an integer, 0 < j ≤ N and j being an integer, and 0 < t ≤ K and t being an integer; when the i th primitive does not correspond to the t th mask of the j th group of masks of the third mask, taking a mask of K second values as the t th mask of the j th group of masks of the i th seventh mask; and taking the or operation result of the j th group of masks of the i th seventh mask as the j th mask of the i th fourth mask.

[0025] In a possible implementation, the second test module is further configured to: perform a hidden surface removal test on the M second masks to determine a sixth mask corresponding to the M primitives; split the sixth mask to obtain M eighth masks corresponding to the M primitives respectively; and in response to the second indication, input the M eighth masks to the pixel shader.

[0026] In a possible implementation, the rendering pipeline supports tile-based deferred rendering.

[0027] In a possible implementation, the rendering pipeline corresponds to a cache, which is used when performing the hidden surface removal test on the M first masks,

[0028] The third mask includes N groups of masks corresponding to N pixels respectively, each group of masks includes K masks, and each mask includes K bits, N and K are integers greater than 1.

[0029] The cache includes N storage locations, and the jth storage location stores the jth group of masks of the third mask, 0 < j ≤ N and j is an integer.

[0030] According to another aspect of the present disclosure, an electronic device is provided, comprising: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to implement the above method when executing the instructions stored in the memory.

[0031] According to another aspect of the present disclosure, a non-volatile computer readable storage medium having computer program instructions stored thereon is provided, wherein the computer program instructions are executed by a processor to implement the above method.

[0032] According to another aspect of the present disclosure, a computer program product is provided, comprising computer readable code, or a non-volatile computer readable storage medium carrying computer readable code, when the computer readable code is run in a processor of an electronic device, the processor in the electronic device executes the above method.

[0033] According to the mask transmission method of the embodiment of the present disclosure, by rasterizing the M primitives respectively, M first masks corresponding to the M primitives are determined, M is an integer greater than 1, the rasterization of the primitives can be completed, and the first masks after rasterization are obtained; by performing depth test and / or stencil test on the M first masks respectively, M second masks corresponding to the M primitives are determined, so that the graphics processor has the function of implementing the depth test and / or the stencil test; according to the M second masks, the M first masks are subjected to hidden surface removal test, a third mask corresponding to the M primitives is determined, and the third mask is split to obtain M fourth masks corresponding to the M primitives, so that the graphics processor has the function of implementing the hidden surface removal test; the first mask and the fourth mask corresponding to the same primitive are the same, and in response to the first indication, the M fourth masks are input into the pixel shader, so that the pixel shader can correctly receive the masks after rasterization. The mask transmission method of the embodiment of the present disclosure is executed by a rendering pipeline, without the need to close the early depth / stencil test, reduce the amount of data entering the pixel shader, and reduce the data processing pressure of the graphics processor; without the need to open the late depth / stencil test, the time length of the rendering cycle is reduced; without the need to close the hidden surface removal test function, the performance of the graphics processor is improved. In summary, the mask transmission method of the embodiment of the present disclosure improves the mechanism of the hidden surface removal test, which not only ensures that the pixel shader can correctly receive the masks after rasterization, but also avoids the defect that the depth / stencil test and the hidden surface removal test cannot be opened before the masks enter the pixel shader in the one-way rendering pipeline, so that the graphics processor has lower design complexity and higher performance.

[0034] Other features and aspects of the present disclosure will become apparent from the following detailed description of example embodiments, taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0035] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate example embodiments, features, and aspects of the present disclosure and serve to explain the principles of the present disclosure.

[0036] FIG. 1 shows one example of a mask after rasterization.

[0037] FIG. 2 shows another example of a mask after rasterization.

[0038] FIG. 3 shows one example of a mask after early depth / stencil test.

[0039] FIG. 4 shows one example of a mask after hidden surface removal test.

[0040] FIG. 5a shows an example application scenario of the mask transmission method according to the embodiment of the present disclosure.

[0041] FIG. 5b shows an exemplary application scenario of the mask transmission method according to an embodiment of the present disclosure.

[0042] FIG. 6 shows a schematic diagram of a flow of the mask transmission method according to an embodiment of the present disclosure.

[0043] FIG. 7 shows an example of a mask determined by each step of the mask transmission method and an indicated sample point coverage according to an embodiment of the present disclosure.

[0044] FIG. 8 shows a schematic diagram of a cache according to an embodiment of the present disclosure.

[0045] FIG. 9 shows a schematic diagram of a seventh mask according to an embodiment of the present disclosure.

[0046] FIG. 10 shows a schematic diagram of an exemplary flow of the mask transmission method according to an embodiment of the present disclosure.

[0047] FIG. 11 shows a schematic diagram of a structure of a mask transmission apparatus according to an embodiment of the present disclosure.

[0048] FIG. 12 shows a block diagram of an apparatus 1900 according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0049] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numbers in different drawings denote the same or similar elements. Although various aspects of the embodiments are illustrated in the drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

[0050] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other implementations.

[0051] In addition, for the purpose of better illustrating the present disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will appreciate that the present disclosure can be practiced without some or all of the specific details. In some instances, well-known methods, apparatuses, elements and circuits have not been described in detail in order to avoid obscuring the present disclosure.

[0052] The principle of mask generation and transmission is described below.

[0053] In a Graphics Processing Unit (GPU) rendering pipeline, after a primitive is processed by vertex processing, clipping, viewport transformation and other operations, the primitive enters a rasterization stage. The rasterization stage calculates the positions of the pixels (or sample points) covered by the primitive, and outputs a mask indicating the coverage of the pixels (or sample points) by the primitive and the starting coordinates of the pixels to a pixel shader for shading. The mask can indicate the coverage of the pixels (or sample points) by the primitive.

[0054] FIG. 1 shows an example of a mask after rasterization.

[0055] As shown in FIG. 1, a pixel block includes four pixels P3-P0. Assuming that each pixel corresponds to one sample point and is the center of the pixel during rasterization, the triangle primitive covers the sample points of pixels P2-P0 and does not cover the sample point of pixel P3. One sample point corresponds to one bit of a binary mask. The mask of a covered sample point can be 1, and the mask of an uncovered sample point can be 0. Therefore, the mask corresponding to the pixel block can be 0111 (in the order of pixels P3-P0).

[0056] The mask output by the rasterization stage can be referred to as a raw mask. The starting coordinates of the pixels are known, so it can be easily determined whether each pixel is covered by combining the mask and the starting coordinates. Of course, in a graphics processor, a pixel block can include more than four pixels, such as a pixel block with a size of 32x32 or 8x8. For pixel blocks including a large number of pixels, it is more convenient to pass information about whether a pixel (or sample point) is covered in the form of a mask and starting coordinates in the rendering pipeline.

[0057] If a Multisample Antialiasing (MSAA) method is used during rasterization, more sample points are rasterized for each pixel, and the number of bits of the mask also increases. FIG. 2 shows another example of a mask after rasterization. For ease of understanding, the following describes an example in which each pixel has four sample points (i.e., MSAA 4x). It should be understood that the present disclosure is not limited thereto, and is also applicable to cases in which each pixel has two to sixteen sample points (e.g., MSAA 2x, MSAA 8x, MSAA 16x).

[0058] As shown in FIG. 2, the pixel block includes 4 pixels P3-P0, each pixel includes 4 sampling points, and the pixel block includes 16 sampling points in total. One sampling point corresponds to one bit of the binary mask, so each pixel has 4 bits of the mask, and the mask of the pixel block has 16 bits. The sampling points of the pixel P3 are not covered, so the mask of the pixel P3 is 0000. The sampling points of the pixel P2 are covered, so the mask of the pixel P2 is 1111. The 1st and 3rd sampling points of the pixel P1 are not covered, and the 2nd and 4th sampling points are covered, so the mask of the pixel P1 is 0101. The sampling points of the pixel P0 are covered, so the mask of the pixel P0 is 1111. Therefore, the mask of the pixel block is 0000 1111 0101 1111 (in the order of the pixels P3-P0).

[0059] In some application scenarios, in order to improve the image rendering quality, the mask after rasterization will be subjected to a depth / stencil test. The test determines whether the coverage of the primitive to the pixel (or sampling point) determined by rasterization is valid. Some originally valid coverage can be determined as invalid. The mask output by the depth / stencil test indicates the sampling point information covered by the primitive after the depth / stencil test. At this time, the mask output by the depth / stencil test will enter the pixel shader. This depth / stencil test performed before the mask enters the pixel shader is also called early depth / stencil test. FIG. 3 shows an example of the mask after early depth / stencil test.

[0060] As shown in FIG. 3, the mask of the pixel block after rasterization is 0000 1111 0101 1111. The depth / stencil test can determine that the primitive does not cover the 4th sampling point of the pixel P0 and the 1st and 3rd sampling points of the pixel P2. According to the determination result, the mask 0000 0101 0101 1110 can be output. The mask output by the depth / stencil test can be called active mask. If the 4-bit mask corresponding to a pixel is all 0, the pixel shader does not need to determine the color of the pixel when the pixel is covered by the triangle primitive. Therefore, the depth / stencil test can greatly reduce the data processing cost of the pixel shader.

[0061] For a rendering pipeline using a Tile_base Deferred Rendering (TBDR) architecture, the mask after the depth / stencil test also needs to undergo a Hidden Surface Removal (HSR) test, which determines whether the coverage of a primitive on a pixel (or sample) is valid after the depth / stencil test. Some coverage that is originally valid may be determined as invalid because it is covered by the pixel or sample of another primitive. The mask output by the HSR test indicates the sample information covered by the primitive after the HSR test. At this time, the mask output by the HSR test enters the pixel shader.

[0062] FIG. 4 shows an example of a mask after the HSR test. For clarity of description, only one pixel is shown in FIG. 4.

[0063] As shown in FIG. 4, it is assumed that there are 4 samples during pixel rasterization. The mask after rasterization of the primitive A can be 1111, and the mask output by the depth / stencil test can be 1110, at which time the primitive A covers the 1st-3rd samples (in the order from bottom to top). The mask after rasterization of the primitive B can be 1101, and the mask output by the depth / stencil test can be 1101, at which time the primitive B covers the 1st, 2nd, and 4th samples (in the order from bottom to top). It is assumed that the primitive B covers the primitive A, so the 1st, 2nd, and 4th samples (in the order from bottom to top) of the pixel will present the color of the primitive B, and the 3rd sample presents the color of the primitive A. Whether the 1st, 2nd, and 4th bits of the mask corresponding to the primitive A have values does not affect the shading. In order to save the shading cost, the 1st, 2nd, and 4th bits of the mask can be 0, that is, the mask output by the HSR test of the primitive A is 0010. The primitive B is not covered by other primitives, so the mask output by the HSR test of the primitive B is still 1101. In this case, the mask of the primitive A input to the pixel shader and the mask after rasterization of the primitive A are different.

[0064] With the upgrade of the operating system, an Application Programming Interface (API) supporting the use of the mask after rasterization by the pixel shader for data processing has appeared, such as DirectX 11. The API supports the mask after rasterization as an input attribute to perform data calculation or centroid attribute interpolation. Because the depth / stencil test and the HSR test can change the mask after rasterization, in order to adapt to the function of the API, two rendering pipelines are needed to transmit the mask after rasterization and the mask after the HSR test, respectively. Due to the limitation of the size of the mask buffer, this operation will greatly increase the design complexity of the graphics processor.

[0065] The existing technical solution adopts a simplified process, that is, the mask is still transmitted to the pixel shader by one rendering pipeline from the rasterization stage. If it is known in advance that the pixel shader uses the mask after rasterization, early depth / stencil test is directly turned off, and the function of hidden surface removal test is also turned off, so as to ensure that the mask obtained by the pixel shader is consistent with the mask after rasterization. After the pixel processor completes the shading, the depth / stencil test is started again. This depth / stencil test performed after the mask enters the pixel shader is also called later depth / stencil test.

[0066] Although the existing technical solution realizes transmission of the mask after rasterization to the pixel shader by one rendering pipeline, and reduces the design complexity of the graphics processor, the performance of the graphics processor is reduced. The inventors find that the reduction of performance is specifically manifested in the following aspects:

[0067] 1. The early depth / stencil test is forcibly turned off, which may cause a sharp increase in the number of pixels entering the pixel shader. For example, in a scene containing overdraw, other pixels are drawn again at a position where a pixel already exists. The early depth / stencil test can remove most of the pixels in advance, but now the masks of these pixels all enter the pixel shader, which increases the data processing pressure of the graphics processor.

[0068] 2. The later depth / stencil test is forcibly turned on, which causes the entire rendering cycle to be correspondingly lengthened.

[0069] 3. The hidden surface removal test is a key technology for improving the performance of the tile-based deferred rendering architecture. Forcibly turning off this function undoubtedly causes further reduction of the performance of the graphics processor.

[0070] Therefore, how to correctly transmit the mask after rasterization to the pixel shader while the graphics processor has low design complexity and high performance has become a technical problem to be solved.

[0071] In view of this, the present disclosure provides a mask transmission method and device, electronic equipment, storage medium and program product. According to the mask transmission method of the present disclosure, the mechanism of the hidden surface removal test is improved, so that the pixel shader can correctly receive the mask after rasterization, and the defects that the depth / stencil test and the hidden surface removal test of the one rendering pipeline cannot be turned on before the mask enters the pixel shader are avoided, so that the graphics processor has low design complexity and high performance.

[0072] FIGS. 5a and 5b show an exemplary application scenario of the mask transmission method according to an embodiment of the present disclosure.

[0073] In the application scenario shown in FIG. 5a and FIG. 5b, the graphics processor includes a rendering pipeline supporting tile-based deferred rendering, which can be used to render an image including N pixels (N is an integer greater than 1). The rendering pipeline can include a rasterization module (for rasterization processing), a first test module (for depth / stencil test), a second test module (for hidden surface removal test), a pixel shader. The first test module can only complete depth test, or only complete stencil test, or complete depth test and stencil test, and the embodiments of the present disclosure do not make any limitation in this regard.

[0074] In the application scenario shown in FIG. 5a, in the rendering pipeline, after the plurality of primitives are input into the rasterization module after vertex processing, clipping and viewport transformation, one mask (i.e., the first mask described below) is output to the first test module after rasterization is completed, two masks (i.e., the first mask and the second mask described below) are output to the second test module after the first test module completes the depth / stencil test, and one mask (i.e., the fourth mask described below) can be output to the pixel shader after the second test module completes the hidden surface removal test (and splitting), which can be the same as the mask after rasterization (i.e., the first mask described below).

[0075] In the application scenario shown in FIG. 5b, in the rendering pipeline, after the plurality of primitives are input into the rasterization module after vertex processing, clipping and viewport transformation, one mask (i.e., the first mask described below) is output to the first test module after rasterization is completed, two masks (i.e., the first mask and the second mask described below) are output to the second test module after the first test module completes the depth / stencil test, and two masks can be output to the pixel shader after the second test module completes the hidden surface removal test (and splitting), wherein the first mask (i.e., the fourth mask described below) can be the same as the mask after rasterization (i.e., the first mask described below), and the second mask (i.e., the eighth mask described below) can be the same as the mask obtained after rasterization, depth / stencil test and hidden surface removal test according to the prior art.

[0076] The functions of the modules included in the rendering pipelines shown in FIG. 5a and FIG. 5b can be referred to the description of the flow of the mask transmission method below.

[0077] FIG. 6 shows a schematic diagram of the flow of the mask transmission method according to an embodiment of the present disclosure.

[0078] As shown in FIG. 6, in one possible implementation, the present disclosure proposes a mask transmission method, which is applied to a rendering pipeline of a graphics processor, the rendering pipeline including a pixel shader, and the method includes:

[0079] Step S61, rasterize the M primitives respectively to determine M first masks respectively corresponding to the M primitives, M is an integer greater than 1;

[0080] Step S62, perform depth test and / or stencil test on the M first masks respectively to determine M second masks respectively corresponding to the M primitives;

[0081] Step S63, perform hidden surface removal test on the M first masks according to the M second masks to determine a third mask corresponding to the M primitives;

[0082] Step S64, split the third mask to obtain M fourth masks respectively corresponding to the M primitives, the first mask and the fourth mask corresponding to the same primitive are the same;

[0083] Step S65, in response to the first indication, input the M fourth masks to the pixel shader.

[0084] For example, the structure of the rendering pipeline can refer to the examples of FIG. 5a and FIG. 5b.

[0085] Step S61 can be completed by a rasterization module. The M primitives (Primitive 1-Primitive M) received by the rasterization module can be primitives after vertex processing, clipping, and viewport transformation. M can be an integer greater than 1. The rasterization module can rasterize the M primitives respectively to determine M first masks (Mask G1-Mask GM) corresponding to the M primitives. The primitive 1 corresponds to the mask G1, …, and the primitive M corresponds to the mask GM.

[0086] The rendering pipeline is used to render the M primitives to generate an image including N pixels (N is an integer greater than 1), so when rasterizing any primitive in step S61, it can be determined which pixels of the N pixels are covered by the primitive, and which sampling points of the pixels are covered in detail. The first mask corresponding to the primitive determined by the rasterization process can indicate the sampling point information covered by the primitive after the rasterization. Examples of the first mask can refer to the related description of FIG. 7 below.

[0087] The rasterization process can be implemented based on existing technologies, and the specific implementation of the rasterization process will not be described here.

[0088] The rasterization module can output the M first masks (Mask G1-Mask GM) and the starting address of the pixels (not shown) to the first test module. Step S62 can be completed by the first test module.

[0089] The first test module performs step S62, and respectively performs the depth test and / or stencil test on the M first masks (mask G1-mask GM) to determine the M second masks (mask S1-mask SM) corresponding to the M primitives. The mask S1 can be determined by performing the depth test and / or stencil test on the mask G1, the mask SM can be determined by performing the depth test and / or stencil test on the mask GM, and the primitive 1 corresponds to the mask G1, …, the primitive M corresponds to the mask GM, so the primitive 1 corresponds to the mask S1, …, the primitive M corresponds to the mask SM. The examples of the second masks can be referred to the related description of FIG. 7.

[0090] When performing the depth test and / or stencil test on the first mask corresponding to any primitive in step S62, it can be determined whether the coverage of the primitive on each sampling point indicated by the first mask is still valid. The rasterization process determines the sampling point covered by the primitive, and it can be determined that the primitive no longer covers the sampling point when performing the depth test and / or stencil test. At this time, the coverage of the primitive on the sampling point indicated by the first mask can be invalid. Conversely, if the rasterization process determines the sampling point covered by the primitive, it can be determined that the primitive still covers the sampling point when performing the depth test and / or stencil test. At this time, the coverage of the primitive on the sampling point indicated by the first mask can be valid.

[0091] The first test module can determine the second mask corresponding to the primitive according to the first mask corresponding to the primitive and the validity of the coverage of the primitive on each sampling point determined after the depth test and / or stencil test, so that the second mask indicates the sampling point information covered by the primitive after the depth test and / or stencil test.

[0092] The depth test and the stencil test can be implemented based on the prior art, and the specific implementation of the depth test and the stencil test will not be described here.

[0093] The first test module can output the M first masks (mask G1-mask GM) and the M second masks (mask S1-mask SM) to the second test module in two paths respectively. The starting address of the pixel can be output with any one path. Steps S63-S65 can be completed by the second test module.

[0094] The second test module first performs step S63, and performs hidden surface removal test on the M first masks according to the M second masks to determine a third mask D3 corresponding to the M primitives, i.e., the number of the first masks and the second masks is M respectively, and the number of the third mask is 1. The implementation of the hidden surface removal test used in step S63 can be different from the hidden surface removal test in the prior art. For example, when performing step S63 to perform the hidden surface removal test, the pixel-level mask in each first mask can be expanded to the sampling point level to obtain a corresponding fifth mask (the expansion manner is determined by the second mask corresponding to each first mask), and then the fifth masks corresponding to the multiple primitives are covered layer by layer according to the covering order of the primitives, and the covering result of the M fifth masks finally obtained is the third mask D3, so the third mask D3 corresponds to the M primitives. At this time, the third mask D3 can indicate which sampling points each primitive is the top primitive of, and indicate the covering of the primitive on each sampling point in the pixel where the sampling point is located when the primitive is the top primitive of the sampling point. (After the fifth mask covering is completed, when the fifth mask corresponding to a sampling point covered by a certain primitive is still valid, the primitive is the top primitive of the sampling point). For examples of the expansion manner, the fifth mask and the third mask, please refer to the related description of FIG. 7.

[0095] The second test module further performs step S64 to split the third mask D3, and the purpose of the splitting can be to split the part of the third mask D3 related to each primitive to obtain M fourth masks (mask Y1-mask YM) same as the M first masks. The mask Y1 corresponds to the primitive 1, and the mask YM corresponds to the primitive M.

[0096] The user can give an indication of what kind of mask the pixel shader uses for data processing. For example, the first indication can be given when the pixel shader uses the mask after rasterization for data processing. The second test module further performs step S65, and in response to the first indication, can input the M fourth masks same as the M first masks to the pixel shader. At the same time, the starting address (not shown) of the pixel can also be output to the pixel shader. When the pixel shader uses the fourth mask for data processing, the effect can be the same as using the mask after rasterization (the first mask), i.e., the pixel shader can output the color data of N pixels according to the mask Y1-mask YM and the starting address of the pixel. The image to be rendered to the screen can be generated according to the color data.

[0097] If it can be determined in advance that the pixel shader uses the mask after rasterization for data processing, the first indication can also be stored in a specific location in advance, such as in a memory, and after starting the rendering pipeline of the graphics processor, the processor reads the first indication from the memory and outputs it to the rendering pipeline. The embodiments of the present disclosure do not limit the source of the first indication.

[0098] In this case, the graphics processor can make the mask of the input pixel shader consistent with the rasterized mask under the premise of using a single rendering pipeline and retaining early depth / stencil test and hidden surface removal test, so as to be consistent with the capability of a specific application programming interface such as DirectX 11.

[0099] According to the mask transmission method, the rasterization of the M primitives can be completed, and the first mask after rasterization is obtained by performing rasterization processing on the M primitives respectively to determine M first masks corresponding to the M primitives respectively, M being an integer greater than 1; the graphics processor has the function of implementing the depth test and / or the stencil test by performing the depth test and / or the stencil test on the M first masks respectively to determine M second masks corresponding to the M primitives respectively; the graphics processor has the function of implementing the hidden surface removal test by performing the hidden surface removal test on the M first masks according to the M second masks to determine a third mask corresponding to the M primitives, and splitting the third mask to obtain M fourth masks corresponding to the M primitives respectively; the first mask and the fourth mask corresponding to the same primitive are the same, and the M fourth masks are input into the pixel shader in response to the first indication, so that the pixel shader can correctly receive the mask after rasterization. The mask transmission method is executed by a single rendering pipeline, and early depth / stencil test does not need to be closed, the data amount entering the pixel shader is reduced, and the data processing pressure of the graphics processor is reduced; late depth / stencil test does not need to be opened, and the time length of the rendering cycle is reduced; the hidden surface removal test function does not need to be closed, and the performance of the graphics processor is improved. In summary, the mask transmission method improves the mechanism of the hidden surface removal test, ensures that the pixel shader can correctly receive the mask after rasterization, avoids the defect that the depth / stencil test and the hidden surface removal test cannot be opened before the mask enters the pixel shader in the single rendering pipeline, and makes the graphics processor have lower design complexity and higher performance.

[0100] In a possible implementation, the rendering pipeline supports tile-based deferred rendering.

[0101] Since the rendering pipeline retains the function of the hidden surface removal test, the tile-based deferred rendering can be supported. It can be understood that the rendering pipeline can also support other renderings that need the function of the hidden surface removal test and can be implemented by the prior art, and the embodiments of the present disclosure do not limit the specific rendering supported by the rendering pipeline.

[0102] In a possible implementation, the rendering pipeline is used to render M primitives to generate an image including N pixels, each pixel including K sampling points, N and K being integers greater than 1,

[0103] Each first mask includes N masks corresponding to N pixels respectively, and each mask includes K bits;

[0104] Each second mask includes N masks corresponding to N pixels respectively, and each mask includes K bits;

[0105] The third mask includes N groups of masks corresponding to N pixels respectively, and each group of masks includes K masks, and each mask includes K bits.

[0106] Each fourth mask includes N masks corresponding to N pixels respectively, and each mask includes K bits.

[0107] For example, the rendering pipeline can be used to render M primitives to generate an image including N pixels, and each pixel can include K sampling points. K can be an integer greater than 1, such as 2, 4, 6, 8, 16, etc. Embodiments of the present disclosure are not limited to the specific value of K.

[0108] The M primitives correspond to M first masks respectively, so the first masks are primitive-level masks. The primitive includes N pixels, so each first mask can include N masks corresponding to N pixels respectively, and each mask included in the first mask is a pixel-level mask. The pixel includes K sampling points, so when performing the rasterization process in step S61, one sampling point corresponds to one bit of the binary mask, and thus each mask included in the first mask can include K bits.

[0109] The M primitives correspond to M second masks respectively, so the second masks are primitive-level masks. The primitive includes N pixels, so each second mask can include N masks corresponding to N pixels respectively, and each mask included in the second mask is a pixel-level mask. The pixel includes K sampling points, so when performing the depth test and / or stencil test in step S62, one sampling point corresponds to one bit of the binary mask, and thus each mask included in the second mask can include K bits.

[0110] The third mask corresponds to the M primitives, so the third mask is an image-level mask. The primitive includes N pixels, so the third mask can include N groups of masks corresponding to N pixels respectively, and the pixel includes K sampling points, so when performing the hidden surface removal test in step S63, each group of masks of the third mask can include K masks corresponding to K sampling points respectively, that is, each mask included in each group of masks corresponds to a sampling point, so each group of masks is a sampling point-level mask. Each mask included in each group of masks can include K bits.

[0111] The M primitives correspond to M fourth masks respectively, and the fourth masks are primitive-level masks. The primitive includes N pixels, and each fourth mask can include N masks corresponding to N pixels respectively, and each mask included in the fourth mask is a pixel-level mask. The pixel includes K sampling points, and when the splitting in step S64 is performed, one sampling point corresponds to one bit of the binary mask, and thus each mask included in the fourth mask can include K bits.

[0112] FIG. 7 shows an example of masks determined by each step of the mask transmission method and the indicated sampling point coverage according to an embodiment of the present disclosure.

[0113] It is assumed that M = 2, N = 4, and K = 4, that is, the mask transmission method according to the present disclosure is applied to a scenario in which 2 primitives (primitive 1 and primitive 2) are rendered, and the rendered image includes 4 pixels, and each pixel includes 4 sampling points. For the sake of clarity, FIG. 7 only shows the coverage of primitive 1 and primitive 2 on the 4 sampling points of the first pixel.

[0114] Primitive 1 can obtain a mask G1 (first mask) after the rasterization processing of step S61. The mask G1 can include masks G11-G14, and the mask G11 corresponds to the first pixel. Referring to FIG. 7, the mask G11 can include 4 bits, and primitive 1 can cover the 1st-4th sampling points (in the order from bottom to top) of the first pixel after the rasterization processing, and thus the mask G11 can be 1111.

[0115] Primitive 2 can obtain a mask G2 (first mask) after the rasterization of step S61. The mask G2 can include masks G21-G24, and the mask G21 corresponds to the first pixel. Referring to FIG. 7, the mask G21 can include 4 bits, and primitive 2 can cover the 1st, 2nd, and 4th sampling points (in the order from bottom to top) of the first pixel after the rasterization processing, and thus the mask G21 can be 1101.

[0116] The mask G1 (first mask) can obtain a mask S1 (second mask) after the depth test and / or stencil test of step S62. The mask S1 corresponds to primitive 1. The mask S1 can include masks S11-S14, and the mask S11 corresponds to the first pixel. Referring to FIG. 7, the mask S11 can include 4 bits, and the coverage of primitive 1 on the 2nd sampling point of the first pixel becomes invalid after the depth test and / or stencil test, and the coverage of primitive 1 on the 1st, 3rd, and 4th sampling points of the first pixel is still valid (in the order from bottom to top), and thus the mask S11 can be 1011.

[0117] The mask G2 (first mask) can be converted into a mask S2 (second mask) after the depth test and / or stencil test of step S62. The mask S2 corresponds to the primitive 2. The mask S2 can include a mask S21 to a mask S24, wherein the mask S21 corresponds to the first pixel. Referring to FIG. 7, the mask S21 can include 4 bits, and the coverage of the first, second, fourth sampling points of the primitive 2 to the first pixel is still valid (in the order from bottom to top) after the depth test and / or stencil test, and thus the mask S21 can be 1101.

[0118] The mask G1 and the mask G2 (first mask) can be converted into a mask D3 (third mask) after the hidden surface removal test of step S63. The mask D3 corresponds to the primitive 1 and the primitive 2. The mask D3 can include a first group of masks D31 to a fourth group of masks D34, wherein the first group of masks D31 corresponds to the first pixel. Referring to FIG. 7, the first group of masks D31 can include a mask D311 to a mask D314, wherein the mask D311 corresponds to the first sampling point s0 of the first pixel, the mask D312 corresponds to the second sampling point s1 of the first pixel, the mask D313 corresponds to the third sampling point s2 of the first pixel, and the mask D314 corresponds to the fourth sampling point s3 of the first pixel. The masks D311 to D314 can include 4 bits. In the example of FIG. 7, the mask D311 can be 1101, the mask D312 can be 1101, the mask D313 can be 1111, and the mask D314 can be 1101. The mask D3 can be 1101 1101 1111 1101. The exemplary determination of the values of the masks D311 to D314 can be found in the further description of step S63.

[0119] The mask D3 (third mask) can be converted into a mask Y1 and a mask Y2 (fourth mask) after the splitting of step S64. The mask Y1 corresponds to the primitive 1, and the mask Y2 corresponds to the primitive 2. The mask Y1 can include a mask Y11 to a mask Y14, wherein the mask Y11 corresponds to the first pixel. The mask Y11 can include 4 bits, and in the example of FIG. 7, the mask Y11 can be 1111. The mask Y2 can include a mask Y21 to a mask Y24, wherein the mask Y21 corresponds to the first pixel. The mask Y21 can include 4 bits, and in the example of FIG. 7, the mask Y21 can be 1101. The exemplary determination of the values of the masks Y11 and Y21 can be found in the further description of step S63.

[0120] The exemplary implementation of the hidden surface removal test of step S63 is described as follows.

[0121] In one possible implementation, a rendering pipeline is used to render M primitives to generate an image including N pixels, each pixel including K sampling points, N and K are integers greater than 1, and step S63 includes:

[0122] According to the M second masks, the M first masks are processed to obtain M fifth masks, each of which includes N groups of masks corresponding to N pixels respectively, and each group of masks includes K masks, and each mask includes K bits.

[0123] The M fifth masks are subjected to a hidden surface removal test to determine the third mask.

[0124] For example, in step S63, first, the M first masks can be processed according to the M second masks to obtain M fifth masks, so the fifth masks are masks at the primitive level. When the M first masks are processed to obtain the M fifth masks, the pixel-level masks in each first mask can be expanded to the sampling point level, so as to obtain the fifth mask corresponding to the first mask. Each first mask includes N masks corresponding to N pixels respectively, and each fifth mask includes N groups of masks corresponding to N pixels respectively, that is, one mask (pixel level) in the first mask is expanded to one group of masks (sampling point level) in the fifth mask. Each mask in the first mask includes K bits, and the number of masks included in each group of expanded masks can be equal to the number of sampling points of each pixel, that is, each group of masks can include K masks, and each mask can include K bits.

[0125] Still taking FIG. 7 as an example, performing step S63 can process mask G1 (first mask) according to mask S1 (second mask) to obtain mask G_1 (fifth mask). Mask G_1 can include the first group of masks G_11 to the fourth group of masks G_14, where the first group of masks G_11 corresponds to the first pixel. Referring to FIG. 7, the first group of masks G_11 can include mask G_111 to mask G_114, where mask G_111 corresponds to the first sampling point s0 of the first pixel, mask G_112 corresponds to the second sampling point s1 of the first pixel, mask G_113 corresponds to the third sampling point s2 of the first pixel, and mask G_114 corresponds to the fourth sampling point s3 of the first pixel. Masks G_111 to G_114 can include 4 bits. In the example of FIG. 7, mask G_111 can be 1111, mask G_112 can be 0000, mask G_113 can be 1111, and mask G_114 can be 1111. Mask G_11 can be 1111 0000 1111 1111. The exemplary determination manner of the values of masks G_111 to G_114 can be referred to the further description of step S63 below.

[0126] The execution of step S63 can process the mask G2 (the second mask) according to the mask S2 (the first mask) to obtain a mask G_2 (the fifth mask). The mask G_2 can include a first group of masks G_21 to a fourth group of masks G_24, wherein the first group of masks G_21 corresponds to the first pixel. Referring to FIG. 7, the first group of masks G_21 can include a mask G_211 to a mask G_214, wherein the mask G_211 corresponds to the first sampling point s0 of the first pixel, the mask G_212 corresponds to the second sampling point s1 of the first pixel, the mask G_213 corresponds to the third sampling point s2 of the first pixel, and the mask G_214 corresponds to the fourth sampling point s3 of the first pixel. The masks G_211 to G_214 can include 4 bits. In the example of FIG. 7, the mask G_211 can be 1101, the mask G_212 can be 1101, the mask G_213 can be 0000, and the mask G_214 can be 1101. The mask G_21 can be 1101 1101 0000 1101. An exemplary determination manner of the values of the masks G_211 to G_214 can be referred to the further description of step S63 below.

[0127] After the extension is completed, the fifth mask corresponding to the M primitives is taken as an object of the hidden surface removal test, and is processed according to the implementation manner of the hidden surface removal test in the prior art to obtain a third mask. The hidden surface removal test does not change the number of bits of the mask, and therefore the data structure of the fifth mask and the third mask can be the same, and both include N groups of masks, each group of masks includes K masks, and each mask includes K bits. In this case, each mask included in each group of masks in the third mask corresponds to a sampling point, and therefore each group of masks in the third mask is also a sampling point level mask.

[0128] For example, the mask G_1 and the mask G_2 can be taken as objects of the hidden surface removal test, and finally a third mask D3 is obtained. The third mask D3 can include a first group of masks D31 to a fourth group of masks D34, wherein the first group of masks D31 corresponds to the first pixel. Referring to FIG. 7, the first group of masks D31 can include a mask D311 to a mask D314, wherein the mask D311 corresponds to the first sampling point s0 of the first pixel, the mask D312 corresponds to the second sampling point s1 of the first pixel, the mask D313 corresponds to the third sampling point s2 of the first pixel, and the mask D314 corresponds to the fourth sampling point s3 of the first pixel. The masks D311 to D314 can include 4 bits. The mask D311 can be 1101, the mask D312 can be 1101, the mask D313 can be 1111, and the mask D314 can be 1101. The mask D31 can be 1101 1101 1111 1101. An exemplary determination manner of the values of the masks D311 to D314 can be referred to the further description of step S63 below.

[0129] The following describes an exemplary method for extending one mask corresponding to the pixel in the first mask to a group of masks corresponding to the pixel in the fifth mask in combination with FIG. 7.

[0130] In a possible implementation, in step S63, the M first masks are processed to obtain M fifth masks according to the M second masks, including:

[0131] When the tth bit of the jth mask of the ith second mask is equal to the first value, the jth mask of the ith first mask is taken as the tth mask of the jth group of masks of the ith fifth mask, 0 < i ≤ M and is an integer, 0 < j ≤ N and is an integer, and 0 < t ≤ K and is an integer.

[0132] When the tth bit of the jth mask of the ith second mask is equal to the second value, the mask of the K second values is taken as the tth mask of the jth group of masks of the ith fifth mask.

[0133] For example, the ith primitive (0 < i ≤ M and is an integer) corresponds to the ith second mask, the ith first mask, and the ith fifth mask. For example, the 1st primitive (primitive 1) corresponds to the 1st second mask (S1), the 1st first mask (G1), and the 1st fifth mask (G_1). The 2nd primitive (primitive 2) corresponds to the 2nd second mask (S2), the 2nd first mask (G2), and the 2nd fifth mask (G_2).

[0134] The first value may be, for example, a value representing that a sampling point is covered, which may be 1 in the embodiments of the present disclosure. The second value may be, for example, a value representing that a sampling point is not covered, which may be 0 in the embodiments of the present disclosure. It can be understood that the first value and the second value may also be set to other values, as long as the first value represents that a sampling point is covered and the second value represents that a sampling point is not covered, which is not limited in the present disclosure.

[0135] The first pixel is shown in the example of FIG. 7, where j = 1 is taken as an example. When the tth bit of the jth mask of the ith second mask is equal to the first value, the jth mask of the ith first mask is taken as the tth mask of the jth group of masks of the ith fifth mask. For example, when the tth bit of the first mask (mask S11) of the first second mask (S1) is equal to the first value (1), the first mask (G11) of the first first mask (G1) is taken as the tth mask of the first group of masks G_11 of the first fifth mask (G_1). For example, when t = 1, the first bit of the mask S11 is equal to the first value (1), and the mask G11 (1111) is taken as the first mask G_111 of the first group of masks G_11, so the mask G_111 can be 1111. Similarly, when t = 3, the third bit of the mask S11 is equal to the first value (1), and the mask G11 is taken as the third mask G_113 of the first group of masks G_11, so the mask G_113 can be 1111. When t = 4, the fourth bit of the mask S11 is equal to the first value (1), and the mask G11 is taken as the fourth mask G_114 of the first group of masks G_11, so the mask G_114 can be 1111.

[0136] When the tth bit of the jth mask of the ith second mask is equal to the second value, the mask of the K second values is taken as the tth mask of the jth group of masks of the ith fifth mask. For example, when the tth bit is equal to the second value (0), the mask of the four (K = 4) second values (0) is taken as the tth mask of the first group of masks G_11 of the first fifth mask (G_1). For example, when t = 2, the second bit of the mask S11 is equal to the second value (0), and four 0s are taken as the second mask G_112 of the first group of masks G_11, so the mask G_112 can be 0000.

[0137] In this case, the first group of masks G11 of the first fifth mask (G_1) can be 1111 0000 1111 1111.

[0138] Similarly, when the tth bit of the 1st mask (mask S21) of the 2nd second mask (S2) is equal to the 1st numerical value (1), the 1st mask (G21) of the 2nd 1st mask (G2) is taken as the tth mask of the 1st group of masks G_21 of the 2nd 5th mask (G_2), and when the tth bit is equal to the 2nd numerical value (0), the mask of the 4th 2nd numerical value (0) is taken as the tth mask of the 1st group of masks G_21 of the 2nd 5th mask (G_2). Referring to FIG. 7, the mask G21 is 1101, the 1st bit of the mask S21 (1101) is 1, the 2nd bit is 1, the 3rd bit is 0, and the 4th bit is 1, the 1st group of masks G_21 includes the mask G_211 to the mask G_214, and thus the mask G_211 can be 1101, the mask G_212 can be 1101, the mask G_213 can be 0000, and the mask G_214 can be 1101.

[0139] In this case, the 1st group of masks G_21 of the 2nd 5th mask (G_2) can be 1101 1101 0000 1101.

[0140] By analogy, each 1st mask corresponding to each primitive can be expanded into a 5th mask, and the expansion mode of each 1st mask will not be described here.

[0141] In this way, the expansion of the pixel-level mask to the sampling point-level mask can be completed.

[0142] The following describes an exemplary method for performing hidden surface removal testing on M 5th masks according to the prior art.

[0143] In a possible implementation, the hidden surface removal testing is performed on the M 5th masks to determine a 3rd mask, including:

[0144] According to the superposition order of the M primitives, the 5th mask corresponding to the later superposed primitive is used to cover the 5th mask corresponding to the earlier superposed primitive to obtain the 3rd mask.

[0145] For example, the M fifth masks are subjected to the hidden surface removal test, and the third mask can be determined according to the superimposition order of the M primitives, using the fifth mask corresponding to the later superimposed primitive to cover the fifth mask corresponding to the earlier superimposed primitive, to obtain the third mask. When two fifth masks cover each other, two groups of masks corresponding to the same pixel cover each other; when two groups of masks cover each other, the masks corresponding to the same sampling point cover each other. When covering, the mask corresponding to the later superimposed primitive covers the mask corresponding to the earlier superimposed primitive, that is, in the form of overwriting, the mask corresponding to the later superimposed primitive is written to the corresponding storage position of the mask corresponding to the earlier superimposed primitive, and the mask presented after the covering is completed is the third mask. It should be noted that when the masks corresponding to the same sampling point cover each other, the covering operation is valid only when at least one bit of the mask corresponding to the later superimposed primitive is not 0, and the mask corresponding to the earlier superimposed primitive can be completely covered. For example, if the mask corresponding to the later superimposed primitive is 1011 and the mask corresponding to the earlier superimposed primitive is 0111, the superimposed mask is 1011. If each bit of the mask corresponding to the later superimposed primitive is 0, the covering operation of the mask corresponding to the later superimposed primitive is invalid, and the superimposed mask is consistent with the mask corresponding to the earlier superimposed primitive after covering. For example, if the mask corresponding to the later superimposed primitive is 0000 and the mask corresponding to the earlier superimposed primitive is 0111, the superimposed mask is 0111.

[0146] Assume that the primitive 2 is a post-stacking primitive and the primitive 1 is a pre-stacking primitive. The fifth mask (G_2) corresponding to the primitive 2 can be used to cover the fifth mask (G_1) corresponding to the primitive 1. In this case, the first group of masks G_21 of the mask G_2 covers the first group of masks G_11 of the mask G_1 (corresponding to the first pixel). In this case, referring to FIG. 7, the first mask (G_211 = 1101) of the mask G_21 covers the first mask (G_111 = 1111) of the mask G_11 to obtain a mask D311 = 1101, which is the first mask of the first group of masks D31 of the third mask D3 (corresponding to the first sampling point). The second mask (G_212 = 1101) of the mask G_21 covers the second mask (G_112 = 0000) of the mask G_11 to obtain a mask D312 = 1101, which is the second mask of the first group of masks D31 of the third mask D3 (corresponding to the second sampling point). The third mask (G_213 = 0000) of the mask G_21 covers the third mask (G_113 = 1111) of the mask G_11. Since each bit of the post-stacking mask G_21 is 0, the mask G_21 is invalid, and the post-stacking mask is still consistent with the pre-stacking mask G_11, and the third mask D313 = 1111 is obtained, which is the third mask of the first group of masks D31 of the third mask D3 (corresponding to the third sampling point). The fourth mask (G_214 = 1101) of the mask G_21 covers the fourth mask (G_114 = 1111) of the mask G_11 to obtain a mask D314 = 1101, which is the fourth mask of the first group of masks D31 of the third mask D3 (corresponding to the fourth sampling point).

[0147] In this case, the first group of masks D31 of the third mask D3 can be 1101 1101 1111 1101.

[0148] In this way, the M groups of masks corresponding to the same pixel in the M fifth masks are covered, and a group of masks corresponding to the pixel in the third mask is obtained. The N groups of masks obtained by comprehensive covering can obtain the third mask. In this case, the covering method of each two groups of masks corresponding to other pixels will not be described again.

[0149] As can be seen, the third mask includes the same masks as the first mask, and in the above example, D311 = D312 = D314 = G21 and D313 = G11. In this way, the information of the first mask can be retained in the third mask, which facilitates subsequent splitting of the fourth mask according to the third mask.

[0150] Those skilled in the art should understand that the manner of hidden surface removal test in step S63 can also be more, as long as the third mask can include the information of the first mask, and the third mask is the mask obtained through the depth / stencil test and the hidden surface removal test, the specific manner of the hidden surface removal test in step S63 is not limited in the embodiments of the present disclosure.

[0151] In a possible implementation, the rendering pipeline corresponds to a cache, which is used when performing the hidden surface removal test on the M first masks,

[0152] The third mask includes N groups of masks corresponding to N pixels respectively, each group of masks includes K masks, and each mask includes K bits, and N and K are integers greater than 1.

[0153] The cache includes N storage locations, and the jth storage location stores the jth group of masks of the third mask, 0 < j ≤ N and j is an integer.

[0154] For example, the rendering pipeline can correspond to a cache, for example, the cache is located in the second test module. The cache is used when performing the hidden surface removal test on the M first masks, and is specifically used to implement the superposition of the fifth mask. FIG. 8 shows a schematic diagram of the cache according to an embodiment of the present disclosure.

[0155] As shown in FIG. 8, the cache can have N storage locations, each of which corresponds to a pixel. Each storage location can store a mask corresponding to a pixel. Each storage location can include K rows (or K columns), and in the example of FIG. 8, the storage location corresponding to each pixel can include 4 rows. Each row corresponds to a sampling point, that is, each row is used to store a mask corresponding to the sampling point in a group of masks. In the example of FIG. 8, the first row can correspond to the first sampling point s0, the second row can correspond to the second sampling point s1, the third row can correspond to the third sampling point s2, and the fourth row can correspond to the fourth sampling point s3. Each row can store a 4-bit mask.

[0156] After the superposition order of the M primitives is determined, the N groups of masks included in the fifth mask corresponding to the first superimposed primitive are sequentially written to the N storage locations of the cache. The N groups of masks included in the fifth mask corresponding to the second superimposed primitive one by one cover the existing masks in the N storage locations, at this time, the fifth mask corresponding to the second superimposed primitive is completed. In this way, until the fifth mask corresponding to the Mth superimposed primitive is completed, the N groups of masks stored in the N storage locations are the third mask determined by performing the hidden surface removal test on the M fifth masks.

[0157] In this case, only K bits are needed for each sampling point to complete the hidden surface removal test in step S63, and the required cache is also small, and the cost is still much smaller than that of the two-way rendering pipeline, so the normal execution of the function of the hidden surface removal test can be ensured at a small cost.

[0158] Since the mask covers are overwritten, the K masks stored in the storage location corresponding to a pixel can come from different primitives. Therefore, to obtain M fourth masks corresponding to M primitives, the third masks can be split to split out the parts belonging to the same primitive.

[0159] Next, an exemplary way of splitting the third mask in step S64 is described.

[0160] In a possible implementation, the rendering pipeline is used to render M primitives to generate an image including N pixels, each pixel including K sampling points, N and K are integers greater than 1, the third mask includes N groups of masks corresponding to the N pixels respectively, each group of masks includes K masks, and each mask includes K bits;

[0161] Step S64 includes:

[0162] When the ith primitive corresponds to the tth mask of the jth group of masks of the third mask, the tth mask of the jth group of masks of the third mask is taken as the jth mask of the ith fourth mask, 0 < i ≤ M and is an integer, 0 < j ≤ N and is an integer, and 0 < t ≤ K and is an integer;

[0163] When the ith primitive does not correspond to each mask of the jth group of masks of the third mask, the masks of the K second values are taken as the jth mask of the ith fourth mask.

[0164] The correspondence between the tth mask of the jth group of masks of the third mask and the primitive can be determined according to the prior art, which is not described here.

[0165] For example, as shown in FIG. 7, the effective mask (i.e., the mask with K bits not all 0, such as G_111) corresponding to a sampling point in the fifth mask and the mask (such as G11) corresponding to the pixel to which the sampling point belongs in the first mask corresponding to the fifth mask are actually the same. The mask corresponding to the sampling point in the third mask is derived from the mask corresponding to the sampling point in the fifth mask, so if the ith primitive corresponds to the tth mask of the jth group of masks of the third mask, the ith primitive can be considered as the top primitive of the tth sampling point of the jth pixel, and the corresponding mask of the tth mask of the jth group of masks of the third mask in the fifth mask is an effective mask, so the tth mask of the jth group of masks of the third mask can be taken as the jth mask of the ith fourth mask.

[0166] For example, referring to FIG. 7, the first group of masks D31 of the third mask D3 is 1101 1101 1111 1101, in which the first, second, and fourth masks (1101) correspond to the second primitive (primitive 2), and the third mask (1111) corresponds to the first primitive (primitive 1). Therefore, 1101 can be used as the first mask of the second fourth mask (corresponding to primitive 2). 1111 can be used as the first mask of the first fourth mask (corresponding to primitive 1).

[0167] If the ith primitive does not correspond to each mask of the jth group of masks of the third mask, it can be considered that the ith primitive is not the top primitive of the tth sampling point of the jth pixel, and the corresponding mask of the tth mask of the jth group of masks of the third mask in the fifth mask is an invalid mask (all K bits are 0). Therefore, a mask of K second values (for example, 0000) can be used as the jth mask of the ith fourth mask.

[0168] In this way, the fourth mask can be obtained, which is the same as the first mask. This method makes the cost required by the graphics processor smaller.

[0169] Another exemplary way of splitting the third mask in step S64 is described below.

[0170] In a possible implementation, a rendering pipeline is configured to render M primitives to generate an image including N pixels, each pixel including K sampling points, N and K are integers greater than 1, the third mask includes N groups of masks corresponding to the N pixels respectively, each group of masks includes K masks, and each mask includes K bits.

[0171] Step S64 includes:

[0172] When the ith primitive corresponds to the tth mask of the jth group of masks of the third mask, the tth mask of the jth group of masks of the third mask is used as the tth mask of the jth group of masks of the ith seventh mask, 0 < i ≤ M and i is an integer, 0 < j ≤ N and j is an integer, and 0 < t ≤ K and t is an integer.

[0173] When the ith primitive does not correspond to the tth mask of the jth group of masks of the third mask, a mask of K second values is used as the tth mask of the jth group of masks of the ith seventh mask.

[0174] The result of an OR operation of the jth group of masks of the ith seventh mask is used as the jth mask of the ith fourth mask.

[0175] For example, another way of splitting the third mask is the OR operation. When using this way, the third mask is first split to obtain M seventh masks, each of which includes N groups of masks, each group of masks includes K masks, and each mask includes K bits. Each group of masks corresponds to a pixel, and each mask in each group of masks corresponds to a sampling point. FIG. 9 shows a schematic diagram of a seventh mask according to an embodiment of the present disclosure.

[0176] It is assumed that M = 2, N = 4, and K = 4, that is, the mask transmission method according to an embodiment of the present disclosure is applied to a scenario of rendering 2 primitives (primitive 1 and primitive 2), and the rendered image includes 4 pixels, each of which includes 4 sampling points. For the purpose of clarity, FIG. 9 only shows the coverage of primitives 1 and 2 on the 4 sampling points of the first pixel.

[0177] As shown in FIG. 9, the first group of masks D31 of the third mask D3 corresponds to the first pixel, and can be 1101 1101 1111 1101, in which the first, second, and fourth masks (1101) correspond to the second primitive (primitive 2), and the third mask (1111) corresponds to the first primitive (primitive 1). Therefore, 1101 can be used as the first mask P211, the second mask P212, and the fourth mask P214 of the first group of masks P21 (corresponding to the first pixel) of the second seventh mask P2 (corresponding to primitive 2), and the third mask P213 of the first group of masks P21 of the second seventh mask can be 0000. 1111 can be used as the third mask P113 of the first group of masks P11 (corresponding to the first pixel) of the first seventh mask P1 (corresponding to primitive 1), and the first mask P111, the second mask P112, and the fourth mask P114 of the first group of masks of the first seventh mask can be 0000, respectively.

[0178] In this case, the first group of masks P11 of the first seventh mask can be 0000 0000 1111 0000, and the first group of masks P21 of the second seventh mask can be 1101 1101 0000 1101.

[0179] Then, the K masks in the jth group of masks of the ith seventh mask are subjected to an OR operation, and the result of the OR operation is taken as the jth mask of the fourth mask corresponding to the ith primitive. In the example of FIG. 9, the OR operation result of the 1st mask P111=0000, the 2nd mask P112=0000, the 3rd mask P113=1111, and the 4th mask P114=0000 in the 1st group of masks of the 1st seventh mask can be 1111, and thus 1111 can be taken as the 1st mask Y11 (corresponding to the 1st pixel) of the fourth mask Y1 corresponding to the primitive 1. The OR operation result of the 1st mask P211=1101, the 2nd mask P212=1101, the 3rd mask P213=0000, and the 4th mask P214=1101 in the 1st group of masks of the 2nd seventh mask can be 1101, and thus 1101 can be taken as the 1st mask Y21 (corresponding to the 1st pixel) of the fourth mask Y2 corresponding to the primitive 2.

[0180] In this way, the flexibility of the splitting manner of the third mask can be improved.

[0181] Those skilled in the art should understand that there can be more ways of splitting, as long as M fourth masks can be split from the third mask, and the M fourth masks are respectively identical to the M first masks. The embodiments of the present disclosure do not limit the specific manner of splitting the third mask.

[0182] FIG. 10 shows a schematic diagram of an exemplary flow of a mask transmission method according to an embodiment of the present disclosure.

[0183] As shown in FIG. 10, in a possible implementation, the method further includes:

[0184] In step S71, a hidden surface removal test is performed on the M second masks to determine a sixth mask corresponding to the M primitives.

[0185] In step S72, the sixth mask is split to obtain M eighth masks corresponding to the M primitives respectively.

[0186] In step S73, in response to the second indication, the M eighth masks are input to the pixel shader.

[0187] For example, referring to the application scenario of FIG. 5b, the second test module can have two branches, where the first branch can complete the functions described in steps S63-S65 above, and output a fourth mask identical to the first mask to the pixel shader; the second branch can complete the functions described in steps S71-S73, and output a mask (i.e., an eighth mask) after rasterization, depth stencil test, and hidden surface removal test of the primitives according to the prior art method to the pixel shader. The workflow of the first branch can be seen from the relevant description of FIG. 6, which will not be repeated here, and the workflow of the second branch will be introduced below.

[0188] For example, in step S71, the second branch of the second test module can perform hidden surface removal test on the M second masks (masks S1-SM) according to the prior art method, and determine a sixth mask D6 corresponding to the M primitives. When performing step S71 for hidden surface removal test, the second masks corresponding to the primitives can be overlaid layer by layer in the order of coverage of the primitives, and the final coverage result of the M second masks is the sixth mask D6, so the sixth mask D6 corresponds to the M primitives. The sixth mask includes N masks corresponding to N pixels respectively, and each mask includes K bits. At this time, the sixth mask D6 can indicate which sampling points each primitive is the top layer primitive for (when the second mask corresponding to a sampling point is still valid after the coverage between primitives ends, the primitive is the top layer primitive for the sampling point).

[0189] For example, masks S1 and S2 (second masks) can obtain mask D6 (sixth mask) after hidden surface removal test in step 71. Mask D6 corresponds to primitive 1 and primitive 2. Mask D6 can include masks D61-D64, where mask D61 corresponds to the first pixel. In the example of FIG. 7, mask D61 can be 1111, where the first, second, and fourth bits come from mask S2 and thus correspond to primitive 2, and the third bit comes from mask S1 and thus corresponds to primitive 1.

[0190] The second branch of the second test module performs step S72 again to split the sixth mask D6. The purpose of the splitting can be to split the part of the sixth mask D6 related to each primitive. After the depth test and / or stencil test and hidden surface removal test, M eighth masks (mask Y_1 to mask Y_M) are obtained. The primitive 1 corresponds to the mask Y_1, and the primitive M corresponds to the mask Y_M. The eighth mask can include N masks, each mask corresponding to a pixel, and each mask including K bits. Taking the mask D61 corresponding to the first pixel in the mask D6 in FIG. 7 or FIG. 9 as an example, after the splitting, the first mask Y_11 in the eighth mask Y_1 corresponding to the primitive 1 and the first mask Y_21 in the eighth mask Y_2 corresponding to the primitive 2 can be obtained. Since the first, second and fourth bits of the mask D61 correspond to the primitive 2, and the third bit corresponds to the primitive 1, the mask Y_11 can be 0010, and the mask Y_21 can be 1101.

[0191] The way of splitting the sixth mask to obtain the mask corresponding to other pixels is similar to the splitting of the mask Y_11, and will not be described here again.

[0192] The first mask and the eighth mask corresponding to each primitive can be the same or different. If the second mask corresponding to a primitive is the same as the first mask, and the primitive is the top primitive of all sampling points covered after the depth / stencil test of the primitive, the eighth mask corresponding to the primitive is also the same as the first mask. If the second mask corresponding to a primitive is different from the first mask, the eighth mask corresponding to the primitive is also different from the first mask. If the second mask corresponding to a primitive is the same as the first mask, but the primitive is not the top primitive of all sampling points covered after the depth / stencil test of the primitive, the eighth mask corresponding to the primitive is different from the first mask.

[0193] The user can give a second indication when the pixel shader uses the mask after the hidden surface removal test according to the prior art to perform data processing. The second branch of the second test module performs step S73 again in response to the second indication, and can input the M eighth masks to the pixel shader. At the same time, the starting address of the pixel can also be output to the pixel shader. The pixel shader uses the eighth mask and the starting address of the pixel to perform data processing, and outputs the color data of N pixels. According to the color data, an image to be rendered to the screen can be generated.

[0194] If it can be determined in advance that the pixel shader uses the mask after the hidden surface removal test according to the prior art to perform data processing, the second indication can also be stored in a specific location, such as a memory, in advance, and after starting the rendering pipeline of the graphics processor, the processor reads the second indication from the memory and outputs it to the rendering pipeline. The embodiments of the present disclosure do not limit the source of the second indication.

[0195] In this case, the graphics processor can output one of the masks consistent with the rasterized mask to the pixel shader and another of the masks consistent with the prior art hidden surface removal test to the pixel shader, so that the pixel shader has more choices when using data for shading.

[0196] The disclosure also provides a mask transmission device, and FIG. 11 shows a schematic diagram of the structure of the mask transmission device according to an embodiment of the disclosure.

[0197] As shown in FIG. 11, the device is applied to a rendering pipeline of a graphics processor, the rendering pipeline including a pixel shader, and the device includes:

[0198] A rasterization module 10 is configured to perform rasterization processing on M primitives respectively, determine M first masks respectively corresponding to the M primitives, and M is an integer greater than 1.

[0199] A first test module 20 is configured to perform depth testing and / or stencil testing on the M first masks respectively, determine M second masks respectively corresponding to the M primitives.

[0200] A second test module 30 is configured to perform hidden surface removal testing on the M first masks according to the M second masks, determine a third mask corresponding to the M primitives, split the third mask to obtain M fourth masks respectively corresponding to the M primitives, and input the M fourth masks to the pixel shader in response to a first instruction.

[0201] In a possible implementation, the rendering pipeline is configured to render the M primitives to generate an image including N pixels, each pixel including K sampling points, N and K are integers greater than 1, each first mask includes N masks respectively corresponding to the N pixels, and each mask includes K bits; each second mask includes N masks respectively corresponding to the N pixels, and each mask includes K bits; the third mask includes N groups of masks respectively corresponding to the N pixels, each group of masks includes K masks, and each mask includes K bits; and each fourth mask includes N masks respectively corresponding to the N pixels, and each mask includes K bits.

[0202] In a possible implementation, the rendering pipeline is configured to render the M primitives to generate an image comprising N pixels, each pixel comprising K sample points, N and K being integers greater than 1, and the performing hidden surface removal tests on the M first masks according to the M second masks to determine a third mask corresponding to all of the M primitives comprises: processing the M first masks according to the M second masks to obtain M fifth masks, each fifth mask comprising N groups of masks corresponding to the N pixels respectively, each group of masks comprising K masks, and each mask comprising K bits; and performing hidden surface removal tests on the M fifth masks to determine the third mask.

[0203] In a possible implementation, the processing the M first masks according to the M second masks to obtain M fifth masks comprises: when a t th bit of a j th mask of an i th second mask is equal to a first value, taking a j th mask of an i th first mask as a t th mask of a j th group of masks of an i th fifth mask, 0 < i ≤ M and i is an integer, 0 < j ≤ N and j is an integer, and 0 < t ≤ K and t is an integer; and when the t th bit of the j th mask of the i th second mask is equal to a second value, taking K second-value masks as the t th mask of the j th group of masks of the i th fifth mask.

[0204] In a possible implementation, the performing hidden surface removal tests on the M fifth masks to determine the third mask comprises: according to an order of superposition of the M primitives, using a fifth mask corresponding to a later superpositioned primitive to cover a fifth mask corresponding to an earlier superpositioned primitive to obtain the third mask.

[0205] In a possible implementation, the rendering pipeline is configured to render the M primitives to generate an image comprising N pixels, each pixel comprising K sample points, N and K being integers greater than 1, and the third mask comprises N groups of masks corresponding to the N pixels respectively, each group of masks comprising K masks, and each mask comprising K bits; and the splitting the third mask to obtain M fourth masks corresponding to the M primitives respectively comprises: when an i th primitive corresponds to a t th mask of a j th group of masks of the third mask, taking the t th mask of the j th group of masks of the third mask as a j th mask of an i th fourth mask, 0 < i ≤ M and i is an integer, 0 < j ≤ N and j is an integer, and 0 < t ≤ K and t is an integer; and when the i th primitive does not correspond to each mask of the j th group of masks of the third mask, taking K second-value masks as the j th mask of the i th fourth mask.

[0206] In a possible implementation, the rendering pipeline is configured to render the M primitives to generate an image comprising N pixels, each pixel comprising K samples, N and K being integers greater than 1, the third mask comprises N groups of masks corresponding to the N pixels respectively, each group of masks comprises K masks, and each mask comprises K bits; the splitting the third mask to obtain M fourth masks corresponding to the M primitives respectively comprises: when the i th primitive corresponds to the t th mask of the j th group of masks of the third mask, taking the t th mask of the j th group of masks of the third mask as the t th mask of the j th group of masks of the i th seventh mask, 0 < i ≤ M and being an integer, 0 < j ≤ N and being an integer, and 0 < t ≤ K and being an integer; when the i th primitive does not correspond to the t th mask of the j th group of masks of the third mask, taking a mask of K second values as the t th mask of the j th group of masks of the i th seventh mask; and taking an OR operation result of the j th group of masks of the i th seventh mask as the j th mask of the i th fourth mask.

[0207] In a possible implementation, the second test module is further configured to: perform a hidden surface removal test on the M second masks to determine a sixth mask corresponding to all of the M primitives; split the sixth mask to obtain M eighth masks corresponding to the M primitives respectively; and in response to a second indication, input the M eighth masks to the pixel shader.

[0208] In a possible implementation, the rendering pipeline supports tile-based deferred rendering.

[0209] In a possible implementation, the rendering pipeline corresponds to a buffer, the buffer is used when performing the hidden surface removal test on the M first masks, the third mask comprises N groups of masks corresponding to N pixels respectively, each group of masks comprises K masks, each mask comprises K bits, N and K being integers greater than 1, and the buffer comprises N storage locations, a j th storage location storing a j th group of masks of the third mask, 0 < j ≤ N and being an integer.

[0210] In some embodiments, the apparatus provided by the embodiments of the present disclosure has functions or includes modules that can be used to perform the methods described in the above method embodiments, and the specific implementation can be referred to the description of the above method embodiments. For briefness, details are not described herein.

[0211] The embodiments of the present disclosure also provide a computer-readable storage medium having computer program instructions stored therein, and the computer program instructions are executed by a processor to implement the above method. The computer-readable storage medium can be a volatile or non-volatile computer-readable storage medium.

[0212] The embodiment of the present disclosure further provides an electronic device, comprising: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to implement the above method when executing the instructions stored in the memory.

[0213] The embodiment of the present disclosure further provides a computer program product, comprising computer readable code, or a non-volatile computer readable storage medium carrying computer readable code, when the computer readable code is run in the processor of the electronic device, the processor in the electronic device executes the above method.

[0214] FIG. 12 shows a block diagram of an apparatus 1900 according to an embodiment of the present disclosure. For example, the apparatus 1900 can be provided as an electronic device. Referring to FIG. 12, the apparatus 1900 includes a processing component 1922, which further includes one or more processors, and a memory resource represented by a memory 1932 for storing instructions executable by the processing component 1922, such as an application program. The application program stored in the memory 1932 can include one or more than one module each corresponding to a set of instructions. In addition, the processing component 1922 is configured to execute the instructions to perform the above method.

[0215] The apparatus 1900 can further include a power supply component 1926 configured to perform power management of the apparatus 1900, a wired or wireless network interface 1950 configured to connect the apparatus 1900 to a network, and an input output interface 1958 (I / O interface). The apparatus 1900 can operate based on an operating system stored in the memory 1932, such as Windows Server TM , Mac OS X TM , Unix TM , Linux TM , FreeBSD TM or the like.

[0216] In an exemplary embodiment, a non-volatile computer readable storage medium, such as the memory 1932 including computer program instructions executable by the processing component 1922 of the apparatus 1900 to complete the above method, is also provided.

[0217] The present disclosure can be a system, a method, and / or a computer program product. The computer program product can include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present disclosure.

[0218] Computer readable storage media can be tangible storage media which can retain and store instructions for use by an instruction execution device. Computer readable storage media can be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of computer readable storage media include the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.

[0219] Computer readable program instructions described herein can be downloaded to respective computing / processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and / or a wireless network. The network can comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and / or edge servers. A network adapter card or network interface in each computing / processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing / processing device.

[0220] Computer readable program instructions for carrying out operations of the present disclosure can be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer readable program instructions can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate array (FPGA), or programmable logic array (PLA) can execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present disclosure.

[0221] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0222] These computer readable program instructions can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks. These computer readable program instructions can also be stored in a computer readable storage medium that can include random access memory (RAM), read only memory (ROM), electrically erasable programmable read only memory (EEPROM), flash memory or other data storage device. When the computer readable program instructions are loaded into the computer and other programmable data processing apparatus, a series of operational steps are implemented that provide processes such that the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0223] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus or other device to produce a computer implemented process such that the instructions which execute on the computer, other programmable data processing apparatus, or other device implement the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0224] The flow diagrams and the block diagrams in the drawings are presented to illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flow diagrams and the block diagrams can represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logic functions. In some alternative implementations, the functions noted in the blocks can occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks can sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and / or flow diagrams, and combinations thereof, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and

[0225] Embodiments of the present disclosure have been described above, and the description is intended to be illustrative of the embodiments and not restrictive. Many modifications and variations of the described embodiments are possible and are within the scope of the disclosure. The selection of terms is intended to best describe the principles of the embodiments, practical application, or technical improvements in the art, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A mask transmission method, characterized in that: The method is applied to the rendering pipeline of a graphics processor, and the rendering pipeline includes a pixel shader. The method includes: Performing rasterization processing on M primitives respectively to determine M first masks corresponding to the M primitives respectively, where M is an integer greater than 1; Performing depth testing and / or stencil testing on the M first masks respectively to determine M second masks corresponding to the M primitives respectively; Performing hidden surface removal testing on the M first masks according to the M second masks to determine a third mask corresponding to all of the M primitives; Splitting the third mask to obtain M fourth masks corresponding to the M primitives respectively, and the first mask and the fourth mask corresponding to the same primitive are the same; In response to a first indication, inputting the M fourth masks into the pixel shader.

2. The method according to claim 1, characterized in that The rendering pipeline is used to render the M primitives to generate an image including N pixels, and each pixel includes K sampling points, where N and K are integers greater than 1. Each first mask includes N masks corresponding to the N pixels respectively, and each mask includes K bits; Each second mask includes N masks corresponding to the N pixels respectively, and each mask includes K bits; The third mask includes N groups of masks corresponding to the N pixels respectively, each group of masks includes K masks, and each mask includes K bits; Each fourth mask includes N masks corresponding to the N pixels respectively, and each mask includes K bits.

3. The method according to claim 1, characterized in that The rendering pipeline is used to render the M primitives to generate an image including N pixels, and each pixel includes K sampling points, where N and K are integers greater than 1. The performing hidden surface removal testing on the M first masks according to the M second masks to determine a third mask corresponding to all of the M primitives includes: Processing the M first masks according to the M second masks to obtain M fifth masks, and each fifth mask includes N groups of masks corresponding to the N pixels respectively, each group of masks includes K masks, and each mask includes K bits; Performing hidden surface removal testing on the M fifth masks to determine the third mask.

4. The method according to claim 3, characterized in that The processing the M first masks according to the M second masks to obtain M fifth masks includes: When the t-th bit of the j-th mask of the i-th second mask is equal to a first value, taking the j-th mask of the i-th first mask as the t-th mask of the j-th group of masks of the i-th fifth mask, where 0 < i ≤ M and i is an integer, 0 < j ≤ N and j is an integer, 0 < t ≤ K and t is an integer; When the t-th bit of the j-th mask of the i-th second mask is equal to a second value, taking K masks with the second value as the t-th mask of the j-th group of masks of the i-th fifth mask.

5. The method according to claim 3, characterized in that The performing hidden surface removal testing on the M fifth masks to determine the third mask includes: According to the stacking order of the M primitives, using the fifth mask corresponding to the later-stacked primitive to cover the fifth mask corresponding to the earlier-stacked primitive to obtain the third mask.

6. The method according to claim 1, characterized in that The rendering pipeline is used to render the M primitives to generate an image including N pixels, each pixel including K sampling points, where N and K are integers greater than 1. The third mask includes N groups of masks respectively corresponding to the N pixels, each group of masks including K masks, and each mask including K bits; The splitting of the third mask to obtain M fourth masks respectively corresponding to the M primitives includes: When the i-th primitive corresponds to the t-th mask of the j-th group of masks of the third mask, taking the t-th mask of the j-th group of masks of the third mask as the j-th mask of the i-th fourth mask, where 0 < i ≤ M and i is an integer, 0 < j ≤ N and j is an integer, and 0 < t ≤ K and t is an integer; When the i-th primitive does not correspond to each mask of the j-th group of masks of the third mask, taking K masks of a second value as the j-th mask of the i-th fourth mask.

7. The method according to claim 1, characterized in that The rendering pipeline is used to render the M primitives to generate an image including N pixels, each pixel including K sampling points, where N and K are integers greater than 1. The third mask includes N groups of masks respectively corresponding to the N pixels, each group of masks including K masks, and each mask including K bits; The splitting of the third mask to obtain M fourth masks respectively corresponding to the M primitives includes: When the i-th primitive corresponds to the t-th mask of the j-th group of masks of the third mask, taking the t-th mask of the j-th group of masks of the third mask as the t-th mask of the j-th group of the i-th seventh mask, where 0 < i ≤ M and i is an integer, 0 < j ≤ N and j is an integer, and 0 < t ≤ K and t is an integer; When the i-th primitive does not correspond to the t-th mask of the j-th group of masks of the third mask, taking K masks of a second value as the t-th mask of the j-th group of the i-th seventh mask; Taking the logical OR operation result of the j-th group of masks of the i-th seventh mask as the j-th mask of the i-th fourth mask.

8. The method according to claim 1, characterized in that The method further includes: Performing a hidden surface removal test on the M second masks to determine a sixth mask corresponding to all the M primitives; Splitting the sixth mask to obtain M eighth masks respectively corresponding to the M primitives; In response to a second indication, inputting the M eighth masks into the pixel shader.

9. The method according to claim 1, characterized in that The rendering pipeline supports tile-based deferred rendering.

10. The method according to claim 9, characterized in that The rendering pipeline corresponds to a cache, which is used when performing a hidden surface removal test on the M first masks, The third mask includes N groups of masks respectively corresponding to the N pixels, each group of masks including K masks, and each mask including K bits, where N and K are integers greater than 1; The cache includes N storage locations, and the j-th storage location stores the j-th group of masks of the third mask, where 0 < j ≤ N and j is an integer.

11. A mask transmission device, characterized in that: The apparatus is applied to a rendering pipeline of a graphics processor, the rendering pipeline including a pixel shader, and the apparatus includes: A rasterization module, configured to perform rasterization processing on the M primitives respectively to determine M first masks respectively corresponding to the M primitives, where M is an integer greater than 1; A first testing module is configured to perform a depth test and / or a template test on the M first masks to determine M second masks corresponding to the M primitives. The second testing module is configured to perform a hidden surface removal test on the M first masks based on the M second masks to determine a third mask corresponding to all of the M primitives; split the third mask to obtain M fourth masks corresponding to the M primitives respectively; and input the M fourth masks into the pixel shader in response to the first indication.

12. An electronic device, characterized in that: include: processor; a memory for storing processor-executable instructions; The processor is configured to implement the method according to any one of claims 1 to 10 when executing the instructions stored in the memory.

13. A non-volatile computer-readable storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed by a processor, the method according to any one of claims 1 to 10 is implemented.

14. A computer program product comprising computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code, characterized in that: When the computer-readable code runs in a processor of an electronic device, the processor in the electronic device executes the method according to any one of claims 1 to 10.

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