Method of forming a semiconductor channel and associated apparatus

Abstract

The disclosure provides a method of forming at least one semiconductor channel for a semiconductor device on a semiconductor substrate. The method comprises: defining at least one recess area within a dielectric layer on said semiconductor substrate; etching said at least one recess area in at least on etching step to obtain at least one recess in said layer; and growing 2D material within said recess to form said semiconductor channel; wherein said steps are performed in situ on said semiconductor substrate where the semiconductor device is to be formed.

Description

METHOD OF FORMING A SEMICONDUCTOR CHANNEL AND ASSOCIATED APPARATUSCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority of EP application 24169439.7 which was filed on April 10, 2024 and which is incorporated herein in its entirety by reference.FIELD

[0002] The present invention relates to methods and apparatus usable, for example, in the manufacture of devices by lithographic techniques, and to methods of manufacturing devices using lithographic techniques.BACKGROUND

[0003] A lithographic apparatus is a machine constructed to apply a desired pattern onto a substrate. A lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). A lithographic apparatus may, for example, project a pattern at a patterning device (e.g., a mask) onto a layer of radiation-sensitive material (resist) provided on a substrate.

[0004] To project a pattern on a substrate a lithographic apparatus may use electromagnetic radiation. The wavelength of this radiation determines the minimum size of features which can be formed on the substrate. A lithographic apparatus, which uses extreme ultraviolet (EUV) radiation, having a wavelength within the range 4-20 nm, for example 6.7 nm or 13.5 nm, may be used to form smaller features on a substrate than a lithographic apparatus which uses, for example, radiation with a wavelength of 193 nm.

[0005] As transistor size decreases, forming the transistor entirely in silicon becomes increasingly problematic. When the transistor gate length approaches 14nm and below and / or the transistor channel length approaches 20nm and below, for example, it becomes difficult to ensure a low leakage current and power consumption of a silicon transistor while maintaining performance and reliability.

[0006] To address this, other materials have been proposed to replace silicon for the transistor channel in logic devices. One such class of material may comprise transition metal dichalcogenides (TMDs), e.g., WSe2and MoS2. These are two-dimensional materials (e.g., films or nanosheets) which may enable scaling of gate length down to 5nm.

[0007] It would be desirable to improve on present methods of manufacture of TMDs in a lithography setting, and in particular on present methods of manufacture of TMD-based transistor devices.SUMMARY

[0008] The present disclosure provides a method of forming at least one semiconductor channel for a semiconductor device on a semiconductor substrate, the method comprising: defining at least onerecess area within a dielectric layer on said semiconductor substrate; etching said at least one recess area in at least on etching step to obtain at least one recess in said layer; and growing 2D material within said recess to form said semiconductor channel; wherein said steps are performed in situ on said semiconductor substrate where the semiconductor device is to be formed.

[0009] Other aspects provide a semiconductor device comprising a semiconductor channel formed by performance of said method and an integrated circuit manufacturing apparatus arranged to perform said method.BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments of the invention will now be described, by way of example only, with reference to the accompanying schematic drawings, in which:Figure 1 depicts a lithographic system comprising a lithographic apparatus and a radiation source;Figure 2 depicts a recess for forming a 2D material therein to provide a semiconductor device channel in accordance with methods disclosed herein;Figure 3A, 3B, 3C and 3D depict steps of a first example method for in situ formation of a semiconductor device channel in accordance with methods disclosed herein;Figure 4 depicts a terraced recess are for forming a 2D material therein to provide a semiconductor device channel in accordance with methods disclosed herein; andFigure 5A, 5B, 5C, 5D, 5E, 5F, 5G, 5H, 51 depict steps of a second example method for in situ formation of a semiconductor device channel in accordance with methods disclosed herein.DETAILED DESCRIPTION

[0011] In the present document, the terms "radiation" and "beam" are used to encompass all types of electromagnetic radiation, including ultraviolet radiation (e.g. with a wavelength of 365, 248, 193, 157 or 126 nm) and EUV (extreme ultra-violet radiation, e.g. having a wavelength in the range of about 5-100 nm).

[0012] The term "reticle", "mask" or "patterning device" as employed in this text may be broadly interpreted as referring to a generic patterning device that can be used to endow an incoming radiation beam with a patterned cross-section, corresponding to a pattern that is to be created in a target portion of the substrate. These terms may be used interchangeable and synonymously.

[0013] The term "pellicle" may refer to a protective layer typically positioned in front of the reticle. For detail see, for instance, US patent number US10983431, incorporated herein by reference.

[0014] Figure 1 shows a lithographic system comprising a radiation source SO and a lithographic apparatus LA. The radiation source SO is configured to generate an EUV radiation beam B and to supply the EUV radiation beam B to the lithographic apparatus LA. The lithographic apparatus LA comprises an illumination system IL, a support structure MT configured to support a patterning deviceMA (e.g., a mask), a projection system PS and a substrate table WT configured to support a substrate W.

[0015] The illumination system IL is configured to condition the EUV radiation beam B before the EUV radiation beam B is incident upon the patterning device MA. Thereto, the illumination system IL may include a facetted field mirror device 10 and a facetted pupil mirror device 11. The faceted field mirror device 10 and faceted pupil mirror device 11 together provide the EUV radiation beam B with a desired cross-sectional shape and a desired intensity distribution. The illumination system IL may include other mirrors or devices in addition to, or instead of, the faceted field mirror device 10 and faceted pupil mirror device 11.

[0016] After being thus conditioned, the EUV radiation beam B interacts with the patterning device MA. As a result of this interaction, a patterned EUV radiation beam B’ is generated. The projection system PS is configured to project the patterned EUV radiation beam B’ onto the substrate W. For that purpose, the projection system PS may comprise a plurality of mirrors 13,14 which are configured to project the patterned EUV radiation beam B’ onto the substrate W held by the substrate table WT. The projection system PS may apply a reduction factor to the patterned EUV radiation beam B’, thus forming an image with features that are smaller than corresponding features on the patterning device MA. For example, a reduction factor of 4 or 8 may be applied. Although the projection system PS is illustrated as having only two mirrors 13,14 in Figure 1, the projection system PS may include a different number of mirrors (e.g., six or eight mirrors).

[0017] The substrate W may include previously formed patterns. Where this is the case, the lithographic apparatus LA aligns the image, formed by the patterned EUV radiation beam B’, with a pattern previously formed on the substrate W.

[0018] A relative vacuum, i.e. a small amount of gas (e.g. hydrogen) at a pressure well below atmospheric pressure, may be provided in the radiation source SO, in the illumination system IL, and / or in the projection system PS.

[0019] The radiation source SO shown in Figure 1 is, for example, of a type which may be referred to as a laser produced plasma (LPP) source. A laser system 1, which may, for example, include a CO2 laser, is arranged to deposit energy via a laser beam 2 into a fuel, such as tin (Sn) which is provided from, e.g., a fuel emitter 3. Although tin is referred to in the following description, any suitable fuel may be used. The fuel may, for example, be in liquid form, and may, for example, be a metal or alloy. The fuel emitter 3 may comprise a nozzle configured to direct tin, e.g. in the form of droplets, along a trajectory towards a plasma formation region 4. The laser beam 2 is incident upon the tin at the plasma formation region 4. The deposition of laser energy into the tin creates a tin plasma 7 at the plasma formation region 4. Radiation, including EUV radiation, is emitted from the plasma 7 during deexcitation and recombination of electrons with ions of the plasma.

[0020] The EUV radiation from the plasma is collected and focused by a collector 5. Collector 5 comprises, for example, a near-normal incidence radiation collector 5 (sometimes referred to moregenerally as a normal -incidence radiation collector). The collector 5 may have a multilayer mirror structure which is arranged to reflect EUV radiation (e.g., EUV radiation having a desired wavelength such as 13.5 nm). The collector 5 may have an ellipsoidal configuration, having two focal points. A first one of the focal points may be at the plasma formation region 4, and a second one of the focal points may be at an intermediate focus 6, as discussed below.

[0021] The laser system 1 may be spatially separated from the radiation source SO. Where this is the case, the laser beam 2 may be passed from the laser system 1 to the radiation source SO with the aid of a beam delivery system (not shown) comprising, for example, suitable directing mirrors and / or a beam expander, and / or other optics. The laser system 1, the radiation source SO and the beam delivery system may together be considered to be a radiation system.

[0022] Radiation that is reflected by the collector 5 forms the EUV radiation beam B. The EUV radiation beam B is focused at intermediate focus 6 to form an image at the intermediate focus 6 of the plasma present at the plasma formation region 4. The image at the intermediate focus 6 acts as a virtual radiation source for the illumination system IL. The radiation source SO is arranged such that the intermediate focus 6 is located at or near to an opening 8 in an enclosing structure 9 of the radiation source SO.

[0023] Although Figure 1 depicts the radiation source SO as a laser produced plasma (LPP) source, any suitable source such as a discharge produced plasma (DPP) source or a free electron laser (FEL) may be used to generate EUV radiation.

[0024] Transition metal dichalcogenides (TMDs), such as for example Tungsten Diselenide WSe2 and Molybdenum Disulfide M0S2, are examples of materials which are candidates for replacing silicon in forming transistor channels for post-silicon transistors (e.g., Complementary Metal-Oxide- Semiconductor CMOS devices). TMDs may be formed as a two-dimensional material (e.g., a film or nanosheet); for example, the two-dimensional material may comprise a thickness of less than 4 atomic layers (i.e., less than 3nm where a thickness of a monolayer is approximately between 0.6-0.8nm depending on the actual TMD material; e.g., the thickness of a WSe2 monolayer is about 0.8nm and the thickness of a M0S2 monolayer is about 0.7nm). Such TMDs enable aggressive scaling of gate length down to 5nm and therefore may be suitable for the next generation of logic devices.

[0025] Currently, TMDs are grown via various techniques for logic devices (both front-end-of- line FEOL and back-end-of-line BEOL). In some cases, the TMDs are grown directly on the target substrate (amorphous / pattemed) via a suitable deposition process such as Metal-Organic Chemical Vapour Deposition (MOCVD). Alternatively, TMDs may be grown offline on a crystalline substrate, e.g., sapphire, and then transferred to the target substrate. In either case, after growth (and where applicable, transfer), the TMD film is patterned in a patterning step to create the channel structures, e.g., structures of about tens of nanometers.

[0026] There are a number of challenges involved in both growth and patterning of the TMD film according to present methods. Growing the TMD material on amorphous wafers results in apolycrystalline and granular film with low mobility. Layer transfer is presently unsuitable for high- volume manufacture and is subject to many issues such as inter alia contamination and wrinkling. The thermal budget for growing TMD film on a substrate is limited to 400C and the quality of the grown 2D film is highly affected by the growth temperature . Also, due to lack of adhesion forces at the surface, patterning and etching steps can lead to mechanical instability, and the resulting structures are prone to residues and delamination.

[0027] It has been demonstrated (e.g., Wan et al. Wafer-scale single-orientation 2D layers by atomic edge-guided epitaxial growth; Chem. Soc. Rev., 2022, 51, 803, incorporated herein by reference) that 2D material growth may be initiated by a step edge due to a difference in bonding energy between an edge atom and a surface atom.

[0028] The methods disclosed herein comprise an area-selective 2D material growth approach, which obviates the need for lithography and etching steps on the grown film. This is achieved by creating at least one step edge by litho-etch steps, e.g., more specifically by performing high-resolution (e.g., EUV) patterning and shallow etching (e.g., atomic layer etch). As such, this method may be performed, and therefore the TMD film grown, directly on the product substrate (e.g., the wafer on which the final IC product is formed), and in particular directly at the intended location of the active channel(s) (i.e., such that no transfer step is necessary).

[0029] Figure 2 schematically illustrates an etched recess 200, having been etched within a layer of dielectric 205 (e.g., an oxide or more specifically a silicon dioxide SiCL, Aluminum Oxide AI2O3 or hafnium dioxide HfC layer). The etched recess 200 provides at least one (e.g., in this example four) step edges 210 directly within the dielectric substrate 205. The etched recess 200 limits the growth area of the grown film to within the recess. This may prevent different grains joining and creating a grain boundary. The step edges 210 will promote preferential growth of the film material in the direction indicated by arrows 230, i.e., perpendicularly away from the step edge 210 into the recess 200.

[0030] The etched recess may for example be rectangular (e.g., including square) in shape and have dimensions x*y*h, where h is the etch depth. The etch depth h may be fewer than 5 atomic layers or fewer than 4 atomic layers (e.g., 1, 2 or 3 atomic layers) and / or up to 4nm or 3nm. This depth may be achieved by atomic layer etching, for example.

[0031] The recess area dimensions x and y are defined by the channel size, e.g., they are the same as the dimensions of the channel (or channels). For example, each of the substrate plane dimensions x and y may respectively be (optionally a different one of) smaller than 5pm, smaller than 1pm, smaller than 500nm, smaller than 300nm, smaller than 200nm, smaller than lOOnm or smaller than 50nm, for example. By way of a specific example (for a single channel), the y dimension may be between 60nm and lOOnm, between 70nm and 90nm or about 80nm and the x dimension may be between lOnm and 30nm, between 15nm and 25nm or about 20nm. The recess may be formed to comprise a single transistor channel or a plurality of transistor channels in parallel.

[0032] Figure 3 illustrates the steps of a method for locally growing 2D material (e.g., TMD film) for providing one or more semiconductor device channels (e.g., transistor channels). Step A shows a substrate 305 comprising a dielectric layer 310 and resist layer 315 undergoing an exposure step. A portion or recess area 320 of the resist layer 315 is exposed to radiation 325 using a lithography process. For example, such an exposure step may be performed on an EUV lithography apparatus, e.g., an apparatus as illustrated in Figure 1, so as to achieve the required dimensions. Step B is an etching step where an upper portion 330 (e.g., the first 1-3 atomic layers) of the dielectric layer 310 corresponding to the exposed resist is etched. Step C shows the result of the etching step, where the etched dielectric layer 310’ comprises an etched recess 300. Step D shows the result of growing 2D material 345 (e.g., a TMD film) within the recess 300 (e.g., from one or more step edges 350 at the periphery of the recess 300).

[0033] In the embodiment illustrated in Figure 3, because the growth substrate is a dielectric and of amorphous nature, the grown 2D crystals may have random orientations, which leads to large performance variability between fabricated devices on the same wafer. To address this, in an optional embodiment, it is proposed to control the direction of the crystal growth by mimicking terraces that are formed on sapphire substrate during TMD layer growth.

[0034] Such a method may comprise forming the at least one recess as a plurality of terrace structures. For example, the plurality of terrace structures may define a plurality of tilted (with respect to the substrate plane) terrace surfaces which are substantially parallel to each other and / or non-parallel with the substrate plane. Each of the terraces may be between lOnm and 50nm wide, between lOnm and 40nm, between lOnm and 30nm or in the region of 20 nm wide, with atomic steps between them.

[0035] Figure 4 is a schematic illustration of such terraced recesses from side-on and isometrically from above. Substrate 405 comprises dielectric layer 410. A plurality of angled recesses 400 forming terraces 435 have been formed within the dielectric layer 410. As the TMD film layer 445 grows, it will follow the direction of terraces 435 and therefore grow in a unique direction away from step edge 450, as indicated by arrows 430.

[0036] The terraces may be formed by a combination of two litho-etch processes, where each respective etch is performed at an etch angle with respect to the substrate plane normal. For example, the two etch steps may be performed at a positive etch angle and a negative etch angle with magnitude between 1 and 89 degrees with respect to said normal. As such, a first etch step may be performed at a first etch angle 0i and a second etch step may be performed at a second etch angle 02. The first etch angle 0i may be between 1 and 89 degrees, between 70 and 89 degrees or between 75 and 85 degrees with respect to the substrate normal and the second etch angle 02 may be between -1 and -89, between -40 and -60 degrees, between -45 and -55 degrees (it may be appreciated that whichever angle direction is positive is arbitrary). Angled etching concepts are described, for example, in Sung-Woon Cho et al 2014 ECS J. Solid State Sci. Technol. 3 Q215, incorporated herein by reference.

[0037] Figure 5 illustrates the steps of a method for locally growing 2D material (e.g., TMD film) and fabricating one or more semiconductor device channels using terrace structures. Step A shows a first exposure step. A substrate 505 comprising a dielectric layer 510 and resist layer 515 is shown. First regions 520 of a recess area within the resist layer 515 are exposed to radiation 525 using a lithography process. For example, such an exposure step may be performed on an EUV lithography apparatus, e.g., an apparatus as illustrated in Figure 1. Step B is a first directional etching step where upper portions 530 (e.g., comprising the first 1 to 10 atomic layers, the first 1 to 5 atomic layers, the first 1 to 4 atomic layers or the first 1 to 3 atomic layers) of the dielectric layer 510 corresponding to the resist exposed in step A are etched. This etching is performed at a first etch angle 0i; i.e., in the direction indicated by arrows 535a. Step C shows the result of the first etching step, where the etched dielectric layer 510’ comprises etched slopes or terrace regions 500.

[0038] Step D shows a second exposure step following deposition of another layer of resist 520’ onto the etched dielectric layer 510’. Second regions 520’ of a recess area within the resist layer 515, e.g., corresponding to unetched portions 530’ of etched dielectric layer 510’, are exposed to radiation 525 using a (e.g., EUV) lithography process. Step E shows a second directional etch step, where second upper portions 530’ of the dielectric layer 510’ corresponding to the resist exposed at step D are etched (in the direction indicated by arrows 530b) at a second etch angle 02. Step F shows the result of the second etching step, where the (twice) etched dielectric layer 510” comprises etched recesses or terraces 500’. Each etched recess or terrace 500’ may have a maximum depth between 3 to 10 atomic layers or 3 to 5 atomic layers and a minimum depth of between 1 to 5 atomic layers or between 1 to 3 atomic layers. At one end of the terraced region comprising etched recess / terraces 500’ is a step edge 550 from which growth of TMD material 545 (step G) begins and grows in the direction of the slopes of the terraces 500’ . As before, the grown TMD material 545 may have a thickness up to 3 atomic layers and / or 3nm.

[0039] At step H, gate dielectric 555 and gate material 560 (e.g., metal) is deposited over the grown TMD material 545, after which further processing steps may be performed, to remove the recessed oxide layer 510” and replace it with a further gate dielectric layer 565. Such processing steps may include selective lateral etch and dielectric fill steps. The result of these processing steps is shown in step I, which shows the resultant semiconductor device channel 545 (formed of the 2D material), dielectric layers 555, 565, gate material 560 on a substrate (e.g., wafer) 505.

[0040] In a nanosheet structure, these steps can be repeated for all nanosheets of 2D material.

[0041] Such an approach provides an area-selective deposition of 2D materials for a transistor channel and a controlled crystalline direction on a poly crystalline substrate (rather than a poly crystalline film). The grown 2D material can easily be integrated into a nanosheet structure. As such, it is possible to locally control the growth location of 2D TMD material so as to create a semiconductor channel between two terminals on a substrate. Such approaches obviate the need for performing lithography and etch on the fragile 2D layer and / or covering the full wafer with the 2D TMD material.

[0042] Depending on the dimension and the density of the terraces, direct-self assembly (DSA) can also be used as complementary to EUV lithography to create miniature patterns. As such, the exposure step(s) described above may include or be replaced by direct-self assembly steps.

[0043] In addition to the methods described above, the concepts herein also relate to an integrated circuit manufacturing apparatus comprising a lithographic apparatus and an etching apparatus which is configured for performance of the methods disclosed herein. The lithographic apparatus may be an EUV lithographic apparatus for example.

[0044] Further embodiments of the invention are disclosed in the list of numbered clauses below:1. A method of forming at least one semiconductor channel for a semiconductor device on a semiconductor substrate, the method comprising: defining at least one recess area within a dielectric layer on said semiconductor substrate; etching said at least one recess area in at least on etching step to obtain at least one recess in said layer; and growing 2D material within said recess to form said semiconductor channel; wherein said steps are performed in situ on said semiconductor substrate where the semiconductor device is to be formed.2. A method according to clause 1, wherein said at least one recess comprises at least one step edge, and said growing 2D material within said recess comprises growing the 2D material from said at least one step edge.3. A method according to clause 1 or 2, wherein the grown 2D material has a thickness fewer than four atomic layers.4. A method according to any preceding clause, wherein the dimensions of said at least one recess area are substantially the same as that of the at least one semiconductor channel being formed.5. A method according to any preceding clause, wherein the grown 2D material comprises at least one transition metal dichalcogenide material.6. A method according to any preceding clause, wherein the dielectric layer comprises an amorphous material.7. A method according to any preceding clause, wherein said defining at least one recess area comprises exposing said at least one recess area in at least one lithographic exposure step.8. A method according to clause 7, wherein said lithographic process comprises an EUV lithographic process using exposure radiation having a wavelength between 4nm and 20nm.9. A method according to any preceding clause, wherein said defining and etching steps are performed to form a plurality of recesses defining a plurality of terrace structures.10. A method according to clause 9, wherein said terrace structures comprise terrace surfaces aligned non-parallel with a substrate plane defined by a surface of said substrate.11. A method according to clause 10, wherein said terrace surfaces comprise a plurality of mutually parallel terrace surfaces.12. A method according to any of clauses 9 to 11, wherein said etching steps comprise at least a first directional etch.13. A method according to clause 12, wherein said first directional etch is performed at a first angle between 1 and 89 degrees with respect to a normal to the substrate plane.14. A method according to clause 12, wherein said first directional etch is performed at a first angle between 75 and 85 degrees with respect to a normal to the substrate plane.15. A method according to clause 12, 13 or 14, wherein said defining and etching steps comprise a first lithographic exposure step to expose first regions within said recess area, a first directional etch step to etch the exposed first regions, a second lithographic exposure step to expose second regions within said recess area and a second directional etch step to etch the exposed second regions.16. A method according to clause 15, wherein said second directional etch is performed at a second angle between -1 and -89 degrees with respect to a normal to the substrate plane.17. A method according to clause 15, wherein said second directional etch is performed at a second angle between -45 and -55 degrees with respect to a normal to the substrate plane.18. A method according to any of clauses 9 to 17, wherein each said terrace structures is between lOnm and 40nm wide.19. A method according to any preceding clause, wherein said etching step comprises an atomic etching step to define said at least one recess with a maximum depth of fewer than ten atomic layers.20. A method according to any preceding clause, wherein said etching step comprises an atomic etching step to define said at least one recess with a maximum depth of fewer than five atomic layers.21. A method according to any preceding clause, wherein said defining at least one recess area comprises defining the at least one recess area using a direct-self assembly process.22. A method according to any preceding clause, wherein said semiconductor device comprises a transistor.23. A method according to any preceding clause, comprising forming said at least one semiconductor channel between two electrodes.24. A method according to any preceding clause, wherein said etching comprises atomic layer etching.25. A method according to any preceding clause, wherein said recess area comprises one or both dimensions in the substrate plane which is smaller than 1pm.26. A method according to any preceding clause, wherein said recess area comprises one or both dimensions in the substrate plane which is smaller than 500nm.27. A method according to any preceding clause, wherein said recess area comprises one or both dimensions in the substrate plane which is smaller than lOOnm.28. A method according to any preceding clause, comprising adding a gate dielectric and gate material over said semiconductor channel to form a semiconductor device.29. A semiconductor device comprising a semiconductor channel formed by performance of the method of any of clauses 1 to 27.30. A semiconductor device manufactured by performance of the method of clause 28.31. An integrated circuit manufacturing apparatus comprising: a lithographic apparatus; and an etching apparatus; said integrated circuit manufacturing apparatus being operable to perform the method of any of clauses 1 to 28.

[0045] Although specific reference may be made in this text to the use of lithographic apparatus in the manufacture of ICs, it should be understood that the lithographic apparatus described herein may have other applications. Possible other applications include the manufacture of integrated optical systems, guidance and detection patterns for magnetic domain memories, flat -panel displays, liquidcrystal displays (LCDs), thin-film magnetic heads, etc.

[0046] Although specific reference may be made in this text to embodiments of the invention in the context of a lithographic apparatus, embodiments of the invention may be used in other apparatus. Embodiments of the invention may form part of a mask inspection apparatus, a metrology apparatus, or any apparatus that measures or processes an object such as a wafer (or other substrate) or mask (or other patterning device). These apparatuses may be generally referred to as lithographic tools. Such a lithographic tool may use vacuum conditions or ambient (non-vacuum) conditions.

[0047] Although specific reference may have been made above to the use of embodiments of the invention in the context of optical lithography, it will be appreciated that the invention, where the context allows, is not limited to optical lithography and may be used in other applications, for example imprint lithography.

[0048] While specific embodiments of the invention have been described above, it will be appreciated that the invention may be practiced otherwise than as described. The descriptions above are intended to be illustrative, not limiting. Thus it will be apparent to one skilled in the art that modifications may be made to the invention as described without departing from the scope of the claims set out below.

Claims

CLAIMS1 . A method of forming at least one semiconductor channel for a semiconductor device on a semiconductor substrate, the method comprising: defining at least one recess area within a dielectric layer on said semiconductor substrate; etching said at least one recess area in at least one etching step to obtain at least one recess in said layer; and growing 2D material within said recess to form said semiconductor channel, wherein said steps are performed in situ on said semiconductor substrate where the semiconductor device is to be formed.

2. A method as claimed in claim 1, wherein said at least one recess comprises at least one step edge, and said growing 2D material within said recess comprises growing the 2D material from said at least one step edge.

3. A method as claimed in claim 1 , wherein the grown 2D material has a thickness fewer than four atomic layers.

4. A method as claimed in claim 1, wherein the dimensions of said at least one recess area are substantially the same as that of the at least one semiconductor channel being formed.

5. A method as claimed in claim 1, wherein the grown 2D material comprises at least one transition metal dichalcogenide material.

6. A method as claimed in claim 1, wherein the dielectric layer comprises an amorphous material.

7. A method as claimed in claim 1, wherein said defining at least one recess area comprises exposing said at least one recess area in at least one lithographic exposure step.

8. A method as claimed in claim 7, wherein said lithographic process comprises an EUV lithographic process using exposure radiation having a wavelength between 4nm and 20nm.

9. A method as claimed in claim 1, wherein said defining and etching steps are performed to form a plurality of recesses defining a plurality of terrace structures.

10. A method as claimed in claim 9, wherein said terrace structures comprise terrace surfaces aligned non-parallel with a substrate plane defined by a surface of said substrate.

11. A method as claimed in claim 9, wherein said etching steps comprise at least a first directional etch.

12. A method as claimed in claim 1, wherein said defining and etching steps comprise a first lithographic exposure step to expose first regions within said recess area, a first directional etch step to etch the exposed first regions, a second lithographic exposure step to expose second regions within said recess area and a second directional etch step to etch the exposed second regions.

13. A method as claimed in claim 1 , comprising adding a gate dielectric and gate material over said semiconductor channel to form a semiconductor device.

14. A semiconductor device comprising a semiconductor channel formed by performance of the method of claim 1.

15. A semiconductor device manufactured by performance of the method of claim 13.

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