Semiconductor device

Abstract

Provided is a semiconductor device having a small occupancy area. This semiconductor device comprises a first transistor, a second transistor, and a first insulating layer. The first transistor has a first conductive layer, a second conductive layer, and a first oxide semiconductor layer. The second transistor has a third conductive layer, a second conductive layer, and a second oxide semiconductor layer. The first insulating layer is positioned on the first conductive layer and on the third conductive layer and has an end portion contacting the upper surface of the first conductive layer and an end portion contacting the upper surface of the third conductive layer. The second conductive layer is positioned on the first insulating layer. The first oxide semiconductor layer has an end portion contacting the upper surface of the first conductive layer, an end portion contacting the side surface of the first insulating layer, an end portion contacting the side surface of the second conductive layer, and an end portion contacting the upper surface. The second oxide semiconductor layer has an end portion contacting the upper surface of the third conductive layer, an end portion contacting the side surface of the first insulating layer, an end portion contacting the side surface of the second conductive layer, and an end portion contacting the upper surface.

Description

Semiconductor Devices

[0001] BACKGROUND OF THE INVENTION 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device and a manufacturing method thereof. 2. Description of the Related Art One embodiment of the present invention relates to a transistor and a manufacturing method thereof.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device (for example, a touch sensor), an input / output device (for example, a touch panel), a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be semiconductor devices and each may have a semiconductor device.

[0004] Semiconductor devices including transistors are widely used in electronic devices. For example, in display devices, pixel size can be reduced by reducing the area occupied by a transistor, and resolution can be increased. Therefore, miniaturized transistors are in demand.

[0005] As devices requiring high-definition display devices, devices for virtual reality (VR), augmented reality (AR), substitutional reality (SR), and mixed reality (MR) are being actively developed.

[0006] 2. Description of the Related Art As display devices, for example, light-emitting devices having organic electroluminescence (EL) elements or light-emitting diodes (LEDs) have been developed.

[0007] Patent Document 1 discloses a high-definition display device using organic EL elements.

[0008] International Publication No. 2016 / 038508

[0009] An object of one embodiment of the present invention is to provide a semiconductor device including a micro-sized transistor. Another object is to provide a semiconductor device including a transistor with a short channel length. Another object is to provide a semiconductor device including a transistor with high on-state current. Another object is to provide a semiconductor device including a transistor with high field-effect mobility. Another object is to provide a semiconductor device including a transistor with favorable electrical characteristics. Another object is to provide a semiconductor device that operates at high speed. Another object is to provide a semiconductor device with a small occupation area. Another object is to provide a semiconductor device with low wiring resistance. Another object is to provide a semiconductor device or display device with low power consumption. Another object is to provide a highly reliable transistor, semiconductor device, or display device. Another object is to provide a high-resolution display device. Another object is to provide a method for manufacturing a semiconductor device or display device with high productivity. Another object is to provide a novel transistor, semiconductor device, or display device, or a manufacturing method thereof.

[0010] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0011] One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, and a first insulating layer. The first transistor includes a first conductive layer, a second conductive layer, and a first oxide semiconductor layer. The second transistor includes a third conductive layer, a second conductive layer, and a second oxide semiconductor layer. The first insulating layer is located over the first conductive layer and the third conductive layer. The first insulating layer has an end portion in contact with a top surface of the first conductive layer and an end portion in contact with a top surface of the third conductive layer. The second conductive layer is located over the first insulating layer. The first oxide semiconductor layer has an end portion in contact with a top surface of the first conductive layer, an end portion in contact with a side surface of the first insulating layer, an end portion in contact with a side surface of the second conductive layer, and an end portion in contact with a top surface of the second conductive layer. The second oxide semiconductor layer has an end in contact with the top surface of the third conductive layer, an end in contact with the side surface of the first insulating layer, an end in contact with the side surface of the second conductive layer, and an end in contact with the top surface of the second conductive layer.

[0012] In the above-described semiconductor device, the first transistor preferably includes a gate insulating layer and a first gate electrode. The second transistor preferably includes a gate insulating layer and a second gate electrode. The gate insulating layer is preferably located on the first oxide semiconductor layer and the second oxide semiconductor layer. The first gate electrode preferably has a region facing a side surface of the first insulating layer with the gate insulating layer and the first oxide semiconductor layer interposed therebetween. The second gate electrode preferably has a region facing a side surface of the first insulating layer with the gate insulating layer and the second oxide semiconductor layer interposed therebetween.

[0013] In the above-described semiconductor device, the gate insulating layer preferably has a region in contact with a side surface of the first insulating layer.

[0014] One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, and a first insulating layer. The first transistor includes a first conductive layer, a second conductive layer, a first oxide semiconductor layer, a gate insulating layer, and a first gate electrode. The second transistor includes a third conductive layer, a second conductive layer, a second oxide semiconductor layer, a gate insulating layer, and a second gate electrode. The first insulating layer is located over the first conductive layer and the third conductive layer. The first insulating layer has an end portion in contact with a top surface of the first conductive layer and an end portion in contact with a top surface of the third conductive layer. The second conductive layer is located over the first insulating layer. The first oxide semiconductor layer has regions in contact with a top surface of the first conductive layer, a side surface of the first insulating layer, and a top surface and a side surface of the second conductive layer. The second oxide semiconductor layer has a region in contact with an upper surface of the third conductive layer, a side surface of the first insulating layer, and an upper surface and a side surface of the second conductive layer. The gate insulating layer has a region in contact with an upper surface and a side surface of the first oxide semiconductor layer, an upper surface and a side surface of the second oxide semiconductor layer, and a side surface of the first insulating layer. The first gate electrode has a region facing a side surface of the first insulating layer with the gate insulating layer and the first oxide semiconductor layer interposed therebetween. The second gate electrode has a region facing a side surface of the first insulating layer with the gate insulating layer and the second oxide semiconductor layer interposed therebetween.

[0015] In the above-described semiconductor device, the top surface shape of the second conductive layer preferably matches or substantially matches the top surface shape of the first insulating layer.

[0016] In the above-described semiconductor device, the gate insulating layer preferably has a region in contact with the upper surface of the first insulating layer.

[0017] The aforementioned semiconductor device preferably includes a second insulating layer. The second insulating layer preferably has a region in contact with the lower surface of the first conductive layer and the lower surface of the third conductive layer. The first insulating layer preferably includes a third insulating layer and a fourth insulating layer on the third insulating layer. The second insulating layer preferably includes silicon, nitrogen, and hydrogen. The third insulating layer preferably includes silicon and nitrogen. The fourth insulating layer preferably includes silicon and oxygen.

[0018] In the above-described semiconductor device, the second insulating layer preferably has a region containing more hydrogen than the third insulating layer.

[0019] In the above-described semiconductor device, the first oxide semiconductor layer and the second oxide semiconductor layer preferably contain indium.

[0020] In the above-described semiconductor device, the first conductive layer and the third conductive layer preferably contain indium and oxygen, respectively.

[0021] One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, and an insulating layer. The first transistor includes a first conductive layer, a second conductive layer, and a first oxide semiconductor layer. The second transistor includes a third conductive layer, a fourth conductive layer, and a second oxide semiconductor layer. The insulating layer is located over the first conductive layer and the third conductive layer. The insulating layer has a first side surface in contact with a top surface of the first conductive layer and a second side surface in contact with a top surface of the third conductive layer. The first side surface faces the second side surface. The second conductive layer has a region overlapping with the first conductive layer with the insulating layer interposed therebetween. The first oxide semiconductor layer has an end portion in contact with a top surface of the first conductive layer, an end portion in contact with the first side surface, an end portion in contact with a side surface of the second conductive layer, and an end portion in contact with a top surface of the second conductive layer. The fourth conductive layer has a region overlapping with the third conductive layer with an insulating layer interposed therebetween. The second oxide semiconductor layer has an end portion in contact with a top surface of the third conductive layer, an end portion in contact with a second side surface, an end portion in contact with a side surface of the fourth conductive layer, and an end portion in contact with a top surface of the fourth conductive layer.

[0022] In the above-described semiconductor device, at least a part of a region of the first oxide semiconductor layer in contact with the first side surface is preferably opposed to a region of the second oxide semiconductor layer in contact with the second side surface when viewed from above.

[0023] In the above-described semiconductor device, a region of the first oxide semiconductor layer in contact with the first side surface is preferably not opposed to a region of the second oxide semiconductor layer in contact with the second side surface when viewed from above.

[0024] In the semiconductor device described above, the first transistor preferably has a region adjacent to the second transistor in a direction in which the first side surface extends in a top view.

[0025] In the above-described semiconductor device, the first transistor preferably includes a gate insulating layer and a first gate electrode. The second transistor preferably includes a gate insulating layer and a second gate electrode. The gate insulating layer is preferably located on the first oxide semiconductor layer and the second oxide semiconductor layer. The first gate electrode preferably has a region facing the first side surface with the gate insulating layer and the first oxide semiconductor layer interposed therebetween. The second gate electrode preferably has a region facing the second side surface with the gate insulating layer and the second oxide semiconductor layer interposed therebetween.

[0026] In the above-described semiconductor device, the gate insulating layer preferably has a region in contact with the first side surface and a region in contact with the second side surface.

[0027] In the semiconductor device described above, the gate insulating layer preferably has a region in contact with the upper surface of the insulating layer.

[0028] In the above-described semiconductor device, the first oxide semiconductor layer and the second oxide semiconductor layer preferably contain indium.

[0029] In the above-described semiconductor device, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer preferably contain indium and oxygen.

[0030] According to one embodiment of the present invention, a semiconductor device including a micro-sized transistor can be provided. Alternatively, a semiconductor device including a transistor with a short channel length can be provided. Alternatively, a semiconductor device including a transistor with high on-state current can be provided. Alternatively, a semiconductor device including a transistor with high field-effect mobility can be provided. Alternatively, a semiconductor device including a transistor with favorable electrical characteristics can be provided. Alternatively, a semiconductor device that operates at high speed can be provided. Alternatively, a semiconductor device with a small occupation area can be provided. Alternatively, a semiconductor device with low wiring resistance can be provided. Alternatively, a semiconductor device or display device with low power consumption can be provided. Alternatively, a highly reliable transistor, semiconductor device, or display device can be provided. Alternatively, a high-resolution display device can be provided. Alternatively, a method for manufacturing a semiconductor device or display device with high productivity can be provided. Alternatively, a novel transistor, semiconductor device, or display device, or a manufacturing method thereof can be provided.

[0031] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0032] FIG. 1A is a top view showing an example of a semiconductor device. FIG. 1B is an equivalent circuit diagram of the semiconductor device. FIG. 1C is a cross-sectional view showing an example of a semiconductor device. FIGS. 2A and 2B are cross-sectional views showing an example of a semiconductor device. FIGS. 3A and 3B are perspective views showing an example of a semiconductor device. FIGS. 4A and 4B are cross-sectional views showing an example of a semiconductor device. FIG. 5A is a cross-sectional view showing an example of a semiconductor device. FIG. 5B is a top view showing an example of a semiconductor device. FIGS. 6A and 6B are cross-sectional views showing an example of a semiconductor device. FIGS. 7A and 7B are cross-sectional views showing an example of a semiconductor device. FIG. 8A is a top view showing an example of a semiconductor device. FIG. 8B is a cross-sectional view showing an example of a semiconductor device. FIGS. 9A and 9B are perspective views showing an example of a semiconductor device. FIGS. 10A to 10C are cross-sectional views showing an example of a semiconductor device. FIG. 11A is a top view showing an example of a semiconductor device. FIG. 11B is an equivalent circuit diagram of the semiconductor device. FIG. 11C is a cross-sectional view showing an example of a semiconductor device. FIG. 12 is a cross-sectional view showing an example of a semiconductor device. FIGS. 13A and 13B are perspective views showing an example of a semiconductor device. 14A and 14B are cross-sectional views showing an example of a semiconductor device. FIG. 15A is a top view showing an example of a semiconductor device. FIG. 15B is an equivalent circuit diagram of the semiconductor device. FIG. 15C is a cross-sectional view showing an example of a semiconductor device. FIG. 16 is a cross-sectional view showing an example of a semiconductor device. FIG. 17A is a top view showing an example of a semiconductor device. FIG. 17B is an equivalent circuit diagram of the semiconductor device. FIG. 17C is a cross-sectional view showing an example of a semiconductor device. FIG. 18A is a top view showing an example of a semiconductor device. FIG. 18B is an equivalent circuit diagram of the semiconductor device. FIG. 18C is a cross-sectional view showing an example of a semiconductor device. FIGS. 19A and 19B are equivalent circuit diagrams of the semiconductor device. FIG. 20A is a top view showing an example of a semiconductor device. FIG. 20B is a cross-sectional view showing an example of a semiconductor device. FIGS. 21A and 21B are perspective views showing an example of a semiconductor device. FIG. 22A is a top view showing an example of a semiconductor device. FIG. 22B is a cross-sectional view showing an example of a semiconductor device. FIG. 23A is a top view showing an example of a semiconductor device. FIG. 23B is a cross-sectional view showing an example of a semiconductor device. 24A and 24B are equivalent circuit diagrams of the semiconductor device.FIG. 25A is a top view showing an example of a semiconductor device. FIG. 25B is a cross-sectional view showing an example of a semiconductor device. FIGS. 26A and 26B are perspective views showing an example of a semiconductor device. FIG. 27A is a top view showing an example of a semiconductor device. FIGS. 27B and 27C are cross-sectional views showing an example of a semiconductor device. FIGS. 28A and 28B are perspective views showing an example of a semiconductor device. FIG. 29A is a top view showing an example of a semiconductor device. FIGS. 29B and 29C are cross-sectional views showing an example of a semiconductor device. FIGS. 30A and 30B are perspective views showing an example of a semiconductor device. FIG. 31A is a top view showing an example of a semiconductor device. FIG. 31B is a perspective view showing an example of a semiconductor device. FIG. 32A is a top view showing an example of a semiconductor device. FIG. 32B is a cross-sectional view showing an example of a semiconductor device. FIGS. 33A and 33B are cross-sectional views showing an example of a semiconductor device. FIGS. 34A and 34B are perspective views showing an example of a semiconductor device. FIG. 35A is a top view showing an example of a semiconductor device. FIG. 35B is a cross-sectional view showing an example of a semiconductor device. FIG. 36A is a top view showing an example of a semiconductor device. FIG. 36B is a cross-sectional view showing an example of a semiconductor device. FIGS. 37A to 37C are cross-sectional views showing an example of a semiconductor device. FIGS. 38A and 38B are cross-sectional views showing an example of a semiconductor device. FIG. 39 is a perspective view showing an example of a semiconductor device. FIG. 40 is a top view showing an example of a semiconductor device. FIG. 41 is a perspective view showing an example of a semiconductor device. FIG. 42 is a top view showing an example of a semiconductor device. FIGS. 43A to 43E are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIGS. 44A to 44D are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIGS. 45A and 45B are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIGS. 46A to 46D are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIG. 47 is a perspective view showing an example of a display device. FIGS. 48A and 48B are cross-sectional views showing an example of a display device. FIG. 49 is a cross-sectional view showing an example of a display device. FIGS. 50A to 50C are cross-sectional views showing an example of a display device. FIGS. 51A and 51B are cross-sectional views showing an example of a display device. Fig. 52 is a cross-sectional view showing an example of a display device, and Fig. 53A to Fig. 53C are cross-sectional views showing an example of a display device.Fig. 54 is a cross-sectional view showing an example of a display device. Figs. 55A and 55B are cross-sectional views showing an example of a display device. Figs. 56A to 56D are views showing an example of an electronic device. Figs. 57A to 57F are views showing an example of an electronic device. Figs. 58A to 58G are views showing an example of an electronic device.

[0033] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0034] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0035] For ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0036] In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or the order of stacking). Furthermore, the ordinal numbers assigned to components in one part of this specification may not match the ordinal numbers assigned to the same components in other parts of this specification or in the claims.

[0037] The terms "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0038] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing switching operations to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0039] The functions of "source" and "drain" may be interchanged when transistors of different polarities are used or when the direction of current changes during circuit operation. For this reason, the terms "source" and "drain" may be used interchangeably in this specification. The source and drain of a transistor may be appropriately referred to as the source terminal and drain terminal, or the source electrode and drain electrode, depending on the situation.

[0040] The terms "gate" and "back gate" can be used interchangeably. Therefore, in this specification and the like, the terms "gate" and "back gate" can be used interchangeably. Note that the names of the gate and back gate of a transistor can be appropriately changed to gate electrode and back gate electrode, etc., depending on the situation.

[0041] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as an object. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; note that wiring is not a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements. Note that A, B, and C, which will be described later, represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0042] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no electrical signal is exchanged or an interaction of electrical potential occurs between A and B, it can still be defined that "A and B are indirectly connected" as long as there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B.

[0043] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, and cases where a gate insulating film of a transistor is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0044] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another transistor from a power supply, GND, etc.

[0045] In this specification, unless otherwise specified, the on-state current refers to the drain current (also referred to as Id) when a transistor is in an on state (also referred to as a conductive state). Unless otherwise specified, the on state refers to a state in which the voltage between the gate and the source (also referred to as gate voltage, Vg or Vgs) is equal to or higher than a threshold voltage (also referred to as Vth) for an n-channel transistor, or a state in which the voltage is equal to or lower than the threshold voltage for a p-channel transistor.

[0046] In this specification and the like, unless otherwise specified, the off-state current refers to a leakage current between the source and drain when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state refers to a state in which the voltage between the gate and the source is lower than the threshold voltage in an n-channel transistor, and higher than the threshold voltage in a p-channel transistor.

[0047] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0048] In this specification, the top surface shape of a component refers to the contour shape of the component as viewed from above (also referred to as a plan view). The top surface view refers to a view from the normal direction of the surface on which the component is formed or the surface of a support (e.g., a substrate) on which the component is formed.

[0049] In this specification, the phrase "top surface shapes that match or approximately match" refers to at least a portion of the contours of stacked layers overlapping. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer. In these cases, the phrase "top surface shapes that match or approximately match" may also be used. Furthermore, when the top surface shapes match or approximately match, it can also be said that "edges match or approximately match" or "edges are aligned or approximately aligned."

[0050] In this specification and the like, a tapered shape refers to a shape in which at least a part of a side surface of a structure is inclined with respect to a substrate surface or a surface to be formed. The angle formed between the inclined side surface and the substrate surface or the surface to be formed is sometimes referred to as a taper angle.

[0051] In this specification, etc., a device fabricated using a metal mask or an FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. In addition, in this specification, etc., a device fabricated without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure. Because devices with an MML structure can be manufactured without using a metal mask, they can exceed the upper limit of resolution due to the alignment accuracy of the metal mask. Furthermore, devices with an MML structure can eliminate the need for equipment for manufacturing metal masks and a metal mask cleaning process. Furthermore, devices with an MML structure are suitable for mass production because they can keep manufacturing costs low.

[0052] In this specification and the like, a structure in which different light-emitting layers are formed for light-emitting elements (also referred to as light-emitting devices) with different emission wavelengths is sometimes referred to as an SBS (Side By Side) structure. The SBS structure allows the materials and configuration to be optimized for each light-emitting element, increasing the degree of freedom in selecting materials and configurations and making it easier to improve brightness and reliability.

[0053] In this specification and the like, holes or electrons may be referred to as "carriers." For example, in a light-emitting element, a hole injection layer or an electron injection layer may be referred to as a "carrier injection layer," a hole transport layer or an electron transport layer may be referred to as a "carrier transport layer," and a hole block layer or an electron block layer may be referred to as a "carrier block layer." Note that the above-mentioned carrier injection layer, carrier transport layer, and carrier block layer may not be clearly distinguishable. Furthermore, one layer may have two or three functions among the carrier injection layer, carrier transport layer, and carrier block layer.

[0054] In this specification and the like, a light-emitting element has an EL layer between a pair of electrodes. The EL layer has at least a light-emitting layer. Here, examples of layers (also referred to as functional layers) included in the EL layer include a light-emitting layer, a carrier injection layer (a hole injection layer and an electron injection layer), a carrier transport layer (a hole transport layer and an electron transport layer), and a carrier block layer (a hole block layer and an electron block layer). In this specification and the like, a light-receiving element (also referred to as a light-receiving device) has at least an active layer that functions as a photoelectric conversion layer between a pair of electrodes. In this specification and the like, one of the pair of electrodes may be referred to as a pixel electrode, and the other as a common electrode.

[0055] In this specification and the like, a step disconnection refers to a phenomenon in which a layer, a film, or an electrode is separated due to the shape of the surface on which it is formed (for example, a step or the like).

[0056] In this specification and the like, the term "island-like" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated.

[0057] In this specification and the like, the sacrificial layer (which may also be referred to as a mask layer) is located above at least the light-emitting layer (more specifically, a layer that is processed into an island shape among the layers that make up the EL layer), and has the function of protecting the light-emitting layer during the manufacturing process.

[0058] In this specification and the like, flexibility refers to the property of an object being soft and bendable, i.e., the property of an object being able to deform in response to an external force applied to the object, regardless of whether or not the object has elasticity or the ability to return to its original shape before deformation.

[0059] For example, a flexible electronic device can deform in response to an external force. A flexible electronic device can be used while fixed in a deformed state, or can be used after repeatedly deforming. A flexible display device (also referred to as a flexible display device, flexible display device, flexible display, etc.) can deform in response to an external force. A flexible display device can be used while fixed in a deformed state, or can be used after repeatedly deforming, or can be used in an undeformed state. A flexible battery (also referred to as a flexible battery, flexible battery, flexible battery, etc.) can deform in response to an external force. A flexible battery can be used while fixed in a deformed state, or can be used after repeatedly deforming, or can be used in an undeformed state. A flexible substrate (also referred to as a flexible substrate, flexible substrate, etc.) can deform in response to an external force. A flexible substrate can be used while fixed in a deformed state, or can be used after repeatedly deforming, or can be used in an undeformed state. Note that the above phrase "deform in response to an external force" refers to deformation by an average adult's hand without requiring excessive force. Flexibility can be quantified as deformation of an object due to an external force using a testing machine (such as a tensile testing machine or a compression testing machine) capable of measuring stress-strain.

[0060] In this specification, when an object is described as having flexibility, it means that at least a part of the object has flexibility. In other words, a flexible object may have a non-flexible part (also called a hard part).

[0061] In this specification, when two objects are deformed by the same external force, the object that deforms more is said to be the object with higher flexibility. Also, when a first part and a second part of an object are deformed by the same external force, the part that deforms more is said to be the part with higher flexibility.

[0062] Embodiment 1 In this embodiment, a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 1A to 35B. FIG.

[0063] One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, and a first insulating layer.

[0064] The first transistor includes a first conductive layer, a second conductive layer, and a first oxide semiconductor layer, and the first conductive layer functions as one of a source electrode and a drain electrode, and the second conductive layer functions as the other of the source electrode and the drain electrode.

[0065] The second transistor includes a third conductive layer, a second conductive layer, and a second oxide semiconductor layer, and in the second transistor, the third conductive layer functions as one of a source electrode and a drain electrode, and the second conductive layer functions as the other of the source electrode and the drain electrode.

[0066] The first insulating layer is located on the first conductive layer and the third conductive layer. The first insulating layer has an end in contact with a top surface of the first conductive layer and an end in contact with a top surface of the third conductive layer. The second conductive layer is located on the first insulating layer. The first oxide semiconductor layer has an end in contact with a top surface of the first conductive layer, an end in contact with a side surface of the first insulating layer, an end in contact with a side surface of the second conductive layer, and an end in contact with a top surface of the second conductive layer. The second oxide semiconductor layer has an end in contact with a top surface of the third conductive layer, an end in contact with a side surface of the first insulating layer, an end in contact with a side surface of the second conductive layer, and an end in contact with a top surface of the second conductive layer.

[0067] A region of the first oxide semiconductor layer in contact with the first conductive layer functions as one of a source region and a drain region of the first transistor, and a region of the first oxide semiconductor layer in contact with the second conductive layer functions as the other of the source region and the drain region. In the first oxide semiconductor layer, a channel formation region of the first transistor is located between the source region and the drain region.

[0068] A region of the second oxide semiconductor layer in contact with the third conductive layer functions as one of a source region and a drain region of the second transistor, and a region of the second oxide semiconductor layer in contact with the second conductive layer functions as the other of the source region and the drain region. In the second oxide semiconductor layer, a channel formation region of the second transistor is located between the source region and the drain region.

[0069] The channel length of the first transistor can be controlled by the thickness of the first insulating layer sandwiched between the first conductive layer and the second conductive layer. Similarly, the channel length of the second transistor can be controlled by the thickness of the first insulating layer sandwiched between the second conductive layer and the third conductive layer. That is, the channel lengths of these transistors are not affected by the exposure performance of the exposure equipment used for fabrication. Therefore, the channel length of the transistor can be made shorter than the minimum dimension that the exposure equipment can expose (hereinafter also referred to as the minimum dimension). By shortening the channel length, the transistor can have a large on-state current. Therefore, a semiconductor device that operates at high speed can be obtained. Furthermore, since the source electrode, the oxide semiconductor layer, and the drain electrode can be provided overlapping with each other, the area occupied by the transistor can be reduced. Therefore, the area occupied by the semiconductor device including the transistor can be reduced.

[0070] The second conductive layer functions as the other of the source and drain electrodes of the first transistor and also functions as the other of the source and drain electrodes of the second transistor. That is, the other of the source and drain of the first transistor is connected to the other of the source and drain of the second transistor. By sharing the second conductive layer between the first transistor and the second transistor, the area occupied by the circuit can be reduced, resulting in a compact semiconductor device.

[0071] <Configuration Example 1> [Configuration Example 1-1] A semiconductor device according to one embodiment of the present invention will be described. FIG. 1A shows a top view (also referred to as a plan view) of a semiconductor device 10. FIG. 1B shows an equivalent circuit diagram of the semiconductor device 10. FIG. 1C shows a cross-sectional view of the section taken along dashed dotted line A1-A2 in FIG. 1A, FIG. 2A shows a cross-sectional view of the section taken along dashed dotted line B1-B2, and FIG. 2B shows a cross-sectional view of the section taken along dashed dotted line B3-B4. Note that some of the components of the semiconductor device 10 (such as a gate insulating layer) are omitted in FIG. 1A. As with FIG. 1A, some of the components are omitted in the top views of the semiconductor device in the following drawings.

[0072] The semiconductor device 10 includes a transistor 100, a transistor 200, an insulating layer 110, and an insulating layer 109. The insulating layer 109 is provided over a substrate 102, and the transistors 100 and 200 are provided over the insulating layer 109.

[0073] The transistor 100 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112a, and a conductive layer 112b. In the transistor 100, the conductive layer 104 functions as a gate electrode, and the insulating layer 106 functions as a gate insulating layer. The conductive layer 112a functions as one of a source electrode and a drain electrode, and the conductive layer 112b functions as the other. A region of the semiconductor layer 108 that overlaps with the gate electrode between the source electrode and the drain electrode via the gate insulating layer functions as a channel formation region. A region of the semiconductor layer 108 that is in contact with the source electrode functions as a source region, and a region that is in contact with the drain electrode functions as a drain region.

[0074] The transistor 200 can have a similar structure to that of the transistor 100. The transistor 200 includes a conductive layer 204, an insulating layer 106, a semiconductor layer 208, a conductive layer 212a, and a conductive layer 112b. In the transistor 200, the conductive layer 204 functions as a gate electrode, and the insulating layer 106 functions as a gate insulating layer. The conductive layer 212a functions as one of a source electrode and a drain electrode, and the conductive layer 112b functions as the other. A region of the semiconductor layer 208 that overlaps with the gate electrode between the source electrode and the drain electrode via the gate insulating layer functions as a channel formation region. A region of the semiconductor layer 208 that is in contact with the source electrode functions as a source region, and a region that is in contact with the drain electrode functions as a drain region.

[0075] The conductive layer 112b functions as the other of the source electrode and the drain electrode of the transistor 100 and also functions as the other of the source electrode and the drain electrode of the transistor 200. By sharing the conductive layer 112b between the transistors 100 and 200, the area occupied by the circuit can be reduced, and a small-sized semiconductor device can be provided.

[0076] The other of the source and the drain of the transistor 100 is connected to the other of the source and the drain of the transistor 200. Note that although the transistors 100 and 200 are both n-channel transistors in FIG. 1B , one embodiment of the present invention is not limited to this. One or both of the transistors 100 and 200 can be p-channel transistors. Alternatively, a structure without one of the transistors 100 and 200 is also possible.

[0077] A perspective view of the semiconductor device 10 is shown in FIG. 3A. A perspective view in which the conductive layer 104, the conductive layer 204, and the insulating layer 106 are omitted from FIG. 3A is shown in FIG. 3B. In FIGS. 3A and 3B, some of the insulating layers are shown transparently and their outlines are indicated by dashed lines. In the perspective views of the semiconductor device in the following drawings, similar to FIG. 3A etc., some of the insulating layers are shown transparently and their outlines are indicated by dashed lines.

[0078] The conductive layer 112a and the conductive layer 212a are provided over the insulating layer 109, the insulating layer 110 is provided over the conductive layer 112a and the conductive layer 212a, and the conductive layer 112b is provided over the insulating layer 110. The conductive layer 112a and the conductive layer 212a each have a region in contact with the insulating layer 109. The insulating layer 110 has a region in contact with the conductive layer 112a, the conductive layer 212a, and the conductive layer 112b. The insulating layer 110 has a region sandwiched between the conductive layer 112a and the conductive layer 112b and a region sandwiched between the conductive layer 212a and the conductive layer 112b. The conductive layer 112a has a region overlapping with the conductive layer 112b with the insulating layer 110 interposed therebetween. The conductive layer 212a has a region overlapping with the conductive layer 112b with the insulating layer 110 interposed therebetween.

[0079] The conductive layer 212a can be formed in the same process as the conductive layer 112a. For example, a conductive film to become the conductive layer 112a and the conductive layer 212a is formed and then processed to form the conductive layer 112a and the conductive layer 212a. By forming the conductive layer 112a and the conductive layer 212a in the same process, manufacturing costs can be reduced. Alternatively, the conductive layer 112a and the conductive layer 212a can be formed in different processes. By forming the conductive layer 112a and the conductive layer 212a in different processes, different materials can be used for the conductive layer 112a and the conductive layer 212a, thereby widening the range of material selection.

[0080] As shown in FIG. 1C , the insulating layer 110 has an end 31 in contact with the upper surface of the conductive layer 112a and an end 31a in contact with the upper surface of the conductive layer 212a. In the insulating layer 110, the region where the side surface of the insulating layer 110 and the upper surface of the conductive layer 112a contact corresponds to the end 31, and the region where the side surface of the insulating layer 110 and the upper surface of the conductive layer 212a contact corresponds to the end 31a. The conductive layer 112a has a region where the insulating layer 110 is provided and a region where the insulating layer 110 is not provided. The conductive layer 212a has a region where the insulating layer 110 is provided and a region where the insulating layer 110 is not provided. The insulating layer 110 also has a side 77 on the conductive layer 112a and a side 77a on the conductive layer 212a. The lower end of the side 77 corresponds to the end 31, and the lower end of the side 77a corresponds to the end 31a.

[0081] The semiconductor layer 108 is provided over the conductive layer 112a, the conductive layer 112b, and the insulating layer 110. The semiconductor layer 108 has a region in contact with the top surface and side surface of the conductive layer 112b, a side surface (here, the side surface 77) of the insulating layer 110, and the top surface of the conductive layer 112a. The semiconductor layer 108 is connected to the conductive layer 112a and also connected to the conductive layer 112b. The semiconductor layer 108 has a shape that follows the shapes of the top surface and side surface of the conductive layer 112b, the side surface 77, and the top surface of the conductive layer 112a. The semiconductor layer 108 is provided across a region over the conductive layer 112a where the insulating layer 110 is provided and a region over the conductive layer 112a where the insulating layer 110 is not provided.

[0082] The semiconductor layer 108 has a first region in contact with the conductive layer 112a, a second region in contact with the side surface 77, and a third region in contact with the conductive layer 112b. The first region is in contact with the second region, and the second region is in contact with the third region. It can also be said that the first region is continuous with the second region, and the second region is continuous with the third region. In the transistor 100, the first region functions as one of a source region and a drain region, and the third region functions as the other of the source region and the drain region. A channel formation region is located in the second region.

[0083] A semiconductor layer 208 is provided over the conductive layer 212a, the conductive layer 112b, and the insulating layer 110. The semiconductor layer 208 has a region in contact with the top surface and side surface of the conductive layer 112b, a side surface (here, the side surface 77a) of the insulating layer 110, and the top surface of the conductive layer 212a. The semiconductor layer 208 is connected to the conductive layer 212a and also connected to the conductive layer 112b. The semiconductor layer 208 has a shape that follows the shapes of the top surface and side surface of the conductive layer 112b, the side surface 77a, and the top surface of the conductive layer 212a. The semiconductor layer 208 is provided across a region over the conductive layer 212a where the insulating layer 110 is provided and a region over the conductive layer 212a where the insulating layer 110 is not provided.

[0084] The semiconductor layer 208 has a fourth region in contact with the conductive layer 212a, a fifth region in contact with the side surface 77a, and a sixth region in contact with the conductive layer 112b. The fourth region is in contact with the fifth region, and the fifth region is in contact with the sixth region. It can also be said that the fourth region is continuous with the fifth region, and the fifth region is continuous with the sixth region. In the transistor 200, the fourth region functions as one of a source region and a drain region, and the sixth region functions as the other of the source region and the drain region. A channel formation region is located in the fifth region.

[0085] Fig. 4A shows a cross-sectional view of the cut surface taken along dashed dotted line C1-C2 in Fig. 1C, and Fig. 4B shows a cross-sectional view of the cut surface taken along dashed dotted line D1-D2 in Fig. 1C. Fig. 4A is a cross-sectional view in a plane including the channel formation region of transistor 100 and the channel formation region of transistor 200, and Fig. 4B is a cross-sectional view in a plane including the other of the source and drain regions of transistor 100 and the other of the source and drain regions of transistor 200. Fig. 5A shows an enlarged view of Fig. 1C.

[0086] 2A , 4A, and 4B , the semiconductor layer 108 has an end 33 in contact with the top surface of the conductive layer 112a, an end 37 in contact with the side surface 77, an end 39 in contact with the side surface of the conductive layer 112b, and an end 35 in contact with the top surface of the conductive layer 112b. The end 33 is an end on the surface of the semiconductor layer 108 that is in contact with the top surface of the conductive layer 112a. The end 37 is an end on the surface of the semiconductor layer 108 that is in contact with the side surface 77. The end 39 is an end on the surface of the semiconductor layer 108 that is in contact with the side surface of the conductive layer 112b. The end 35 is an end on the surface of the semiconductor layer 108 that is in contact with the top surface of the conductive layer 112b.

[0087] 2B, 4A, and 4B, the semiconductor layer 208 has an end 33a in contact with the upper surface of the conductive layer 212a, an end 37a in contact with the side surface 77a, an end 39a in contact with the side surface of the conductive layer 112b, and an end 35a in contact with the upper surface of the conductive layer 112b. The end 33a is an end on the surface of the semiconductor layer 208 that is in contact with the upper surface of the conductive layer 212a. The end 37a is an end on the surface of the semiconductor layer 208 that is in contact with the side surface 77a. The end 39a is an end on the surface of the semiconductor layer 208 that is in contact with the side surface of the conductive layer 112b. The end 35a is an end on the surface of the semiconductor layer 208 that is in contact with the upper surface of the conductive layer 112b.

[0088] The semiconductor layer 208 can be formed in the same process as the semiconductor layer 108. For example, semiconductor films that will become the semiconductor layers 108 and 208 are formed and then processed to form the semiconductor layers 108 and 208. Forming the semiconductor layers 108 and 208 in the same process can reduce manufacturing costs. Alternatively, the semiconductor layers 108 and 208 can be formed in different processes. Forming the semiconductor layers 108 and 208 in different processes allows different materials to be used for the semiconductor layers 108 and 208, thereby widening the range of material selection.

[0089] The semiconductor material used for the semiconductor layer 108 and the semiconductor layer 208 is not particularly limited. For example, a semiconductor made of a single element or a compound semiconductor can be used. Examples of semiconductors made of a single element include silicon and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Other examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors (OS: Oxide Semiconductor). Note that these semiconductor materials may contain impurities as dopants.

[0090] The crystallinity of the semiconductor material used for the semiconductor layer 108 and the semiconductor layer 208 is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) can be used. The use of a single crystal semiconductor or a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0091] The semiconductor layer 108 and the semiconductor layer 208 can each be made of, for example, silicon. Examples of silicon include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low temperature polysilicon (LTPS). A transistor using amorphous silicon for its channel formation region can be formed on a large glass substrate and manufactured at low cost. A transistor using polycrystalline silicon for its channel formation region has high field-effect mobility and can operate at high speed. A transistor using microcrystalline silicon for its channel formation region has higher field-effect mobility than a transistor using amorphous silicon and can operate at high speed. Note that a transistor using silicon for its channel formation region may be referred to as a Si transistor, and a transistor using LTPS for its channel formation region may be referred to as an LTPS transistor.

[0092] The semiconductor layer 108 and the semiconductor layer 208 each preferably contain a metal oxide (also referred to as an oxide semiconductor) that exhibits semiconductor characteristics. A transistor using an oxide semiconductor (hereinafter referred to as an OS transistor) has extremely high field-effect mobility compared to a transistor using amorphous silicon. Furthermore, an OS transistor has an extremely low off-state current and can hold charge accumulated in a capacitor connected in series with the transistor for a long period of time. Furthermore, the use of an OS transistor can reduce the power consumption of a semiconductor device. When an oxide semiconductor is used for a semiconductor layer, the semiconductor layer can be referred to as an oxide semiconductor layer or a metal oxide layer.

[0093] The insulating layer 110 can be an inorganic insulating layer, an organic insulating layer, or both. Examples of materials that can be used for the organic insulating layer include acrylic resin and polyimide resin. The insulating layer 110 preferably includes one or more inorganic insulating layers. Examples of materials that can be used for the inorganic insulating layer include oxides, nitrides, oxynitrides, and nitride oxides. Examples of oxides include silicon oxide, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, cerium oxide, gallium zinc oxide, and hafnium aluminate. Examples of nitrides include silicon nitride and aluminum nitride. Examples of oxynitrides include silicon oxynitride, aluminum oxynitride, gallium oxynitride, yttrium oxynitride, and hafnium oxynitride. Examples of nitride oxides include silicon nitride oxide and aluminum nitride oxide.

[0094] In this specification and the like, an oxynitride refers to a material having a composition in which oxygen is contained in a larger amount than nitrogen, and a nitride oxide refers to a material having a composition in which nitrogen is contained in a larger amount than oxygen.

[0095] The insulating layer 110 has a region in contact with the semiconductor layer 108 and a region in contact with the semiconductor layer 208. When a metal oxide is used for the semiconductor layer 108, at least a part of the region of the insulating layer 110 in contact with the semiconductor layer 108 preferably contains oxygen in order to improve the interfacial characteristics between the semiconductor layer 108 and the insulating layer 110. Specifically, the region of the insulating layer 110 in contact with the channel formation region of the semiconductor layer 108 preferably contains oxygen. One or more of an oxide and an oxynitride can be suitably used for the region of the insulating layer 110 in contact with the channel formation region of the semiconductor layer 108. Similarly, at least a part of the region of the insulating layer 110 in contact with the semiconductor layer 208 preferably contains oxygen.

[0096] When a metal oxide is used for the semiconductor layer 108, it is preferable that at least a part of the region of the insulating layer 110 in contact with the semiconductor layer 108 releases oxygen when heat is applied. As a result, oxygen is supplied from the insulating layer 110 to the semiconductor layer 108, and oxygen vacancies (V Ｏ : Oxygen Vacancy), and defects in which hydrogen enters an oxygen vacancy (hereinafter referred to as V Ｏ Similarly, it is preferable that at least a part of the region of the insulating layer 110 in contact with the semiconductor layer 208 releases oxygen when heat is applied.

[0097] The insulating layer 106, which functions as a gate insulating layer of the transistor 100 and a gate insulating layer of the transistor 200, is provided to cover the semiconductor layer 108 and the semiconductor layer 208. The insulating layer 106 has regions in contact with the top surface and side surface of the semiconductor layer 108, the top surface and side surface of the semiconductor layer 208, the side surface 77, and the side surface 77a. The insulating layer 106 also has regions in contact with the top surface and side surface of the conductive layer 112a, the top surface and side surface of the conductive layer 212a, the top surface and side surface of the conductive layer 112b, and the top surface of the insulating layer 109.

[0098] 4A , the insulating layer 110 has, on a side surface 77, a region 70 where the semiconductor layer 108 is provided and a region 72 where the semiconductor layer 108 is not provided. In the region 70, the semiconductor layer 108 is in contact with the insulating layer 110. The insulating layer 106 has a region facing the side surface 77 with the semiconductor layer 108 interposed therebetween. On the other hand, in the region 72, the insulating layer 106 is in contact with the insulating layer 110. Furthermore, the insulating layer 110 has, on a side surface 77a, a region 70a where the semiconductor layer 208 is provided and a region 72a where the semiconductor layer 208 is not provided. In the region 70a, the semiconductor layer 208 is in contact with the insulating layer 110. The insulating layer 106 has a region facing the side surface 77a with the semiconductor layer 208 interposed therebetween. On the other hand, in the region 72a, the insulating layer 106 is in contact with the insulating layer 110.

[0099] The conductive layer 104, which functions as a gate electrode of the transistor 100, is provided over the insulating layer 106 and has a region in contact with the top surface of the insulating layer 106. The conductive layer 104 has a region overlapping with the semiconductor layer 108 with the insulating layer 106 interposed therebetween. The conductive layer 104 also has a region facing the side surface 77 with the insulating layer 106 and the semiconductor layer 108 interposed therebetween. The conductive layer 104 is provided to cover at least the region in contact with the side surface 77 of the semiconductor layer 108. This allows the region to function as a channel formation region of the transistor 100.

[0100] The conductive layer 204 functioning as the gate electrode of the transistor 200 is provided over the insulating layer 106 and has a region in contact with the top surface of the insulating layer 106. The conductive layer 204 has a region overlapping with the semiconductor layer 208 with the insulating layer 106 interposed therebetween. The conductive layer 204 also has a region facing the side surface 77a with the insulating layer 106 and the semiconductor layer 208 interposed therebetween. The conductive layer 204 is provided to cover at least the region in contact with the side surface 77a of the semiconductor layer 208. This allows the region to function as a channel formation region of the transistor 200.

[0101] The conductive layer 204 can be formed in the same process as the conductive layer 104. For example, conductive films to become the conductive layers 104 and 204 are formed and then processed to form the conductive layers 104 and 204. By forming the conductive layers 104 and 204 in the same process, manufacturing costs can be reduced. Alternatively, the conductive layers 104 and 204 can be formed in different processes. By forming the conductive layers 104 and 204 in different processes, different materials can be used for the conductive layers 104 and 204, thereby widening the range of material selection.

[0102] Note that the conductive layer 104 may cover the entire semiconductor layer 108. Covering the semiconductor layer 108 with the conductive layer 104 can prevent the semiconductor layer 108 from being damaged when a layer is formed over the transistor 100. Similarly, the conductive layer 204 may cover the entire semiconductor layer 208.

[0103] A step can be formed between a region over the conductive layer 112a where the insulating layer 110 and the conductive layer 112b are provided and a region over the conductive layer 112a where the insulating layer 110 and the conductive layer 112b are not provided, and the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 are provided along the step. Similarly, a step can be formed between a region over the conductive layer 212a where the insulating layer 110 and the conductive layer 112b are provided and a region over the conductive layer 212a where the insulating layer 110 and the conductive layer 112b are not provided, and the semiconductor layer 208, the insulating layer 106, and the conductive layer 204 are provided along the step.

[0104] In each of the transistors 100 and 200, a source electrode and a drain electrode are located at different heights with respect to the surface of the substrate 102, and a drain current flows perpendicular to or approximately perpendicular to the surface of the substrate 102. In other words, the drain current flows vertically in the transistors 100 and 200. Therefore, the transistor of one embodiment of the present invention can be referred to as a vertical channel transistor, a vertical transistor, or a VFET (Vertical Field Effect Transistor).

[0105] The channel length of the transistor 100 can be controlled by the thickness of the insulating layer 110 provided between the conductive layer 112a and the conductive layer 112b. The channel length of the transistor 200 can be controlled by the thickness of the insulating layer 110 provided between the conductive layer 212a and the conductive layer 112b. Therefore, a transistor having a channel length shorter than the minimum exposure dimension of an exposure apparatus used to manufacture the transistor can be manufactured with high precision. Furthermore, the characteristic variation among multiple transistors is also reduced. This stabilizes the operation of the semiconductor device 10, thereby improving its reliability. Furthermore, reduced characteristic variation of transistors increases the degree of freedom in circuit design, allowing the operating voltage of the semiconductor device to be lowered. This reduces the power consumption of the semiconductor device.

[0106] In the transistor of one embodiment of the present invention, a source electrode, a semiconductor layer, and a drain electrode can be provided so as to overlap with each other; therefore, the area occupied by the transistor can be significantly reduced compared to a so-called planar transistor in which the semiconductor layer is arranged in a planar shape.

[0107] The conductive layer 112a, the conductive layer 112b, the conductive layer 212a, the conductive layer 104, and the conductive layer 204 can each function as a wiring. The transistor 100 and the transistor 200 can be provided in a region where these wirings overlap. That is, in a circuit including the transistor 100, the transistor 200, and the wiring, the area occupied by the transistor 100, the transistor 200, and the wiring can be reduced. Therefore, a semiconductor device with a small area can be provided.

[0108] For example, when the semiconductor device of one embodiment of the present invention is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, and a high-resolution display device can be obtained.Furthermore, when the semiconductor device of one embodiment of the present invention is applied to a driver circuit of a display device (for example, one or both of a gate line driver circuit and a source line driver circuit), the area occupied by the driver circuit can be reduced, and a display device with a narrow frame can be obtained.

[0109] The insulating layer 109 is provided between the transistor 100, the transistor 200, and the insulating layer 110 and the substrate 102. The insulating layer 109 has regions in contact with the conductive layer 112a, the conductive layer 212a, the insulating layer 110, and the insulating layer 106. The insulating layer 109 can be formed using any of the materials listed for the insulating layer 110.

[0110] The insulating layer 109 preferably has a barrier property. The insulating layer 109 is preferably made of a material through which impurities (e.g., water and hydrogen) contained in the substrate 102 do not easily diffuse. This can prevent impurities from diffusing from the substrate 102 to the transistor 100 and the transistor 200.

[0111] In this specification and the like, a barrier film refers to a film having barrier properties. The barrier properties refer to one or both of a function of making it difficult for a target substance to diffuse and thereby suppressing the substance from permeating the film (also referred to as low permeability) and a function of capturing or fixing the substance (also referred to as gettering). For example, an insulating layer having barrier properties can be referred to as a barrier insulating layer.

[0112] The insulating layer 109 functioning as a barrier film can be formed using, for example, one or more of an oxide containing one or both of aluminum and hafnium, an oxide containing magnesium, an oxide containing gallium, a nitride containing aluminum, a nitride containing silicon, and a nitride oxide containing silicon. Specifically, the insulating layer 109 can be formed using, for example, one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, aluminum nitride, silicon nitride, and silicon nitride oxide.

[0113] The insulating layer 109 preferably has a region in contact with the bottom surface of the conductive layer 112a and the bottom surface of the conductive layer 212a. The insulating layer 109 preferably contains impurities (e.g., water and hydrogen) that reduce the electrical resistance of the semiconductor layer 108 and the semiconductor layer 208, and is preferably made of a material that releases the impurities. The impurities released from the insulating layer 109 diffuse into a region of the conductive layer 112a that is in contact with the insulating layer 109. The impurities diffused into the conductive layer 112a diffuse into a region of the semiconductor layer 108 that is in contact with the conductive layer 112a, thereby allowing the region to contain the impurities and reduce the electrical resistance of the region. Similarly, the impurities released from the insulating layer 109 diffuse into a region of the conductive layer 212a that is in contact with the insulating layer 109. The impurities diffused into the conductive layer 212a diffuse into a region of the semiconductor layer 208 that is in contact with the conductive layer 212a, thereby allowing the region to contain the impurities and reduce the electrical resistance of the region. That is, it is possible to reduce the electrical resistance of one of the source region and the drain region of the transistor 100 and the transistor 200. Therefore, a transistor with a large on-state current can be obtained, and a semiconductor device that operates at high speed can be provided.

[0114] When a metal oxide is used for the semiconductor layer 108 and the semiconductor layer 208, the impurities released from the insulating layer 109 preferably contain hydrogen. When hydrogen contained in the insulating layer 109 diffuses into the semiconductor layer 108 through the conductive layer 112a, a region of the semiconductor layer 108 in contact with the conductive layer 112a contains hydrogen, increasing the carrier concentration of the region. Similarly, when hydrogen contained in the insulating layer 109 diffuses into the semiconductor layer 208 through the conductive layer 212a, a region of the semiconductor layer 208 in contact with the conductive layer 212a contains hydrogen, increasing the carrier concentration of the region. That is, the electrical resistance of one of the source region and the drain region of the transistor 100 and the transistor 200 can be reduced. The insulating layer 109 preferably contains, for example, silicon and hydrogen. Typically, silicon nitride containing hydrogen can be used as the insulating layer 109.

[0115] It is more preferable that the insulating layer 109 be formed using a material that releases impurities that reduce the electrical resistance of the conductive layers 112a and 212a, thereby reducing the electrical resistance of the conductive layers 112a and 212a.

[0116] The conductive layer 112a and the conductive layer 212a can each be formed using, for example, a conductive metal oxide (also referred to as an oxide conductor). Examples of oxide conductors (OC) include indium oxide, zinc oxide, In—Sn oxide (ITO), In—Zn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Sn—Si oxide (also referred to as ITO containing silicon, ITSO), zinc oxide to which gallium is added, and In—Ga—Zn oxide. In particular, oxide conductors containing indium have high conductivity and can therefore be suitably used for the conductive layer 112a and the conductive layer 212a.

[0117] When a metal oxide is used for the conductive layer 112a and the conductive layer 212a, the impurities released from the insulating layer 109 preferably contain hydrogen. The impurities released from the insulating layer 109 diffuse into the conductive layer 112a and the conductive layer 212a, and the conductive layer 112a and the conductive layer 212a each contain the impurity. This increases the carrier concentration of the conductive layer 112a and the conductive layer 212a, thereby reducing the electrical resistance. Furthermore, the conductive layer 112a and the conductive layer 212a can function as wirings, enabling a semiconductor device with low wiring resistance to be obtained. Note that the impurities that reduce the electrical resistance of the conductive layer 112a and the conductive layer 212a can be the same as the impurities that reduce the electrical resistance of the semiconductor layer 108 and the semiconductor layer 208. Alternatively, these impurities can be different from each other. It is more preferable that the conductive layer 112a and the conductive layer 212a each easily transmit impurities. It is more preferable that the conductive layer 112a and the conductive layer 212a each be less likely to adsorb impurities.

[0118] The thickness T109 of the insulating layer 109 is preferably 5 nm to 100 nm, more preferably 10 nm to 100 nm, even more preferably 20 nm to 100 nm, and even more preferably 20 nm to 50 nm. As shown in FIG. 5A , the thickness T109 can be the shortest distance between the surface on which the insulating layer 109 is formed (here, the upper surface of the substrate 102) and the upper surface of the insulating layer 109 in a cross-sectional view.

[0119] When the thickness T109 is large and the amount of impurities released from the insulating layer 109 is too large, the amount of impurities diffusing into the semiconductor layer 108 and the semiconductor layer 208 increases, and oxygen vacancies (V Ｏ ) and V Ｏ The amount of H is the oxygen vacancy (V Ｏ ) and V ＯOn the other hand, if the thickness T109 is small, the amount of impurities diffused into the conductive layer 112a, the conductive layer 212a, the semiconductor layer 108, and the semiconductor layer 208 will be small, and the electrical resistance of the conductive layer 112a, the electrical resistance of the conductive layer 212a, one of the source region and drain region of the semiconductor layer 108, and one of the source region and drain region of the semiconductor layer 208 may become high. By setting the thickness T109 within the above range, oxygen deficiency (V Ｏ ) and V Ｏ It is possible to suppress an increase in H and to lower the electrical resistance of these. The thickness T109 is not limited to the above range.

[0120] The insulating layer 109 is preferably provided in at least the region where the conductive layer 112a and the conductive layer 212a are provided. As shown in FIG. 6A , the insulating layer 109 can be configured so that its edges are aligned or substantially aligned with the edges of the conductive layer 112a and the conductive layer 212a. For example, an insulating film to be the insulating layer 109 and a conductive film to be the conductive layer 112a and the conductive layer 212a are formed and processed using the same mask layer, thereby forming the insulating layer 109, the conductive layer 112a, and the conductive layer 212a. Processing the insulating film and the conductive film in the same process can reduce manufacturing costs. The insulating layer 110 has regions in contact with the side surfaces of the insulating layer 109, the top and side surfaces of the conductive layer 112a, the top and side surfaces of the conductive layer 212a, and the top surface of the substrate 102.

[0121] If the amount of impurities released from the insulating layer 109 is too large, there is a risk that the amount of impurities diffusing into the channel formation region of the semiconductor layer 108 and the semiconductor layer 208 will be large. By providing the insulating layer 109 in a part of the substrate 102 and not providing the insulating layer 109 in the other part, the area of ​​the region where the insulating layer 109 is provided can be adjusted. This makes it possible to adjust the amount of impurities released from the insulating layer 109. By reducing the area of ​​the region where the insulating layer 109 is provided, the amount of impurities released from the insulating layer 109 is reduced, and the amount of impurities diffusing into the channel formation region can be reduced.

[0122] As shown in FIG. 6B , the end of the insulating layer 109 may not be aligned with the end of the conductive layer 112a or the end of the conductive layer 212a. The insulating layer 109 may have a region that protrudes beyond the end of the conductive layer 112a and a region that protrudes beyond the end of the conductive layer 212a. The end of the conductive layer 112a and the end of the conductive layer 212a are in contact with the top surface of the insulating layer 109. This structure reduces the step between the formation surfaces of layers (e.g., the insulating layer 110) formed on the conductive layer 112a and the insulating layer 109 and the conductive layer 212a and the insulating layer 109, thereby improving the coverage of the layers. This can prevent defects such as discontinuities or voids in the layers.

[0123] The structure of the insulating layer 109 shown here can be applied to other structure examples. Also, a structure in which the insulating layer 109 is not provided may be used.

[0124] The insulating layer 110 preferably has a stacked structure. Fig. 1C and other figures show an example in which the insulating layer 110 includes an insulating layer 110a, an insulating layer 110b on the insulating layer 110a, and an insulating layer 110c on the insulating layer 110b. The insulating layer 110a, the insulating layer 110b, and the insulating layer 110c can each be made of the materials listed for the insulating layer 110.

[0125] A region of the semiconductor layer 108 in contact with the insulating layer 110b functions as a channel formation region of the transistor 100. A region of the semiconductor layer 208 in contact with the insulating layer 110b functions as a channel formation region of the transistor 200. The insulating layer 110b preferably contains oxygen, and is preferably formed using one or more of the above-described oxides and oxynitrides. The insulating layer 110b preferably contains, for example, silicon and oxygen. Typically, one or both of silicon oxide and silicon oxynitride can be preferably used for the insulating layer 110b.

[0126] In the following, the semiconductor layer 108 may be used as an example for description. For the semiconductor layer 208, the description of the semiconductor layer 108 can be referred to.

[0127] It is more preferable to use a material that releases oxygen when heat is applied for the insulating layer 110b. When heat is applied during the manufacturing process of the semiconductor device 10, the insulating layer 110b releases oxygen, which allows oxygen to be supplied to the semiconductor layer 108 and the semiconductor layer 208. By supplying oxygen from the insulating layer 110b to the semiconductor layer 108 and the semiconductor layer 208, particularly to the channel formation region of the semiconductor layer 108 and the channel formation region of the semiconductor layer 208, oxygen vacancies (V Ｏ ) is repaired, and oxygen vacancies (V Ｏ ) can be reduced. Ｏ H can be reduced. Therefore, a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0128] For example, oxygen can be supplied to the insulating layer 110b by heat treatment in an oxygen-containing atmosphere or plasma treatment in an oxygen-containing atmosphere. Alternatively, oxygen can be supplied to the insulating layer 110b by forming a film on the top surface of the insulating layer 110b by a sputtering method in an oxygen-containing atmosphere. Then, the film can be removed. Note that a method for supplying oxygen to the insulating layer 110b will be specifically described in Embodiment 2.

[0129] The insulating layer 110b is preferably formed by a sputtering method or a plasma-enhanced chemical vapor deposition (PECVD) method. In particular, by forming the insulating layer 110b by a sputtering method without using a gas containing a hydrogen element (e.g., hydrogen gas or ammonia gas) in the film formation gas, a film with an extremely low hydrogen content can be obtained. Therefore, hydrogen can be prevented from being supplied to the channel formation region, and the electrical characteristics of the transistor can be stabilized.

[0130] The insulating layer 110a is provided between the insulating layer 110b and the conductive layer 112a. The insulating layer 110c is provided between the insulating layer 110b and the conductive layer 112b. The insulating layer 110a and the insulating layer 110c preferably release small amounts of impurities (e.g., hydrogen and water) from themselves. Furthermore, the insulating layer 110a and the insulating layer 110c preferably are impermeable to substances. The insulating layer 110a and the insulating layer 110c can also be said to function as barrier films. Specifically, the insulating layer 110a and the insulating layer 110c preferably are impermeable to impurities. This can prevent impurities contained in the insulating layer 110a and the insulating layer 110c from diffusing into the channel formation region. Therefore, a highly reliable transistor can be obtained, exhibiting favorable electrical characteristics.

[0131] The insulating layer 110a and the insulating layer 110c are preferably made of a material that is difficult for oxygen to permeate. This can prevent oxygen contained in the insulating layer 110b from diffusing to the conductive layer 112a through the insulating layer 110a and to the conductive layer 212a through the insulating layer 110a. Similarly, it can prevent oxygen contained in the insulating layer 110b from diffusing to the conductive layer 112b through the insulating layer 110c. This increases the amount of oxygen supplied from the insulating layer 110b to the channel formation region of the semiconductor layer 108 and the channel formation region of the semiconductor layer 208, thereby reducing oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. Therefore, a transistor with good electrical characteristics and high reliability can be obtained. Furthermore, the conductive layers 112a, 112b, and 212a can be prevented from being oxidized by oxygen contained in the insulating layer 110b, which can prevent the electrical resistance of these layers from increasing. Therefore, a transistor with high on-state current can be obtained.

[0132] The insulating layer 110a and the insulating layer 110c can each be made of the materials listed above for the barrier film. For example, the insulating layer 110a and the insulating layer 110c can each be made of one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, aluminum nitride, silicon nitride, and silicon nitride oxide. The insulating layer 110a and the insulating layer 110c can each be made of the same material. Alternatively, the insulating layer 110a and the insulating layer 110c can each be made of different materials.

[0133] In this specification and the like, different materials refer to materials in which some or all of the constituent elements are different, or materials in which the constituent elements are the same but the composition is different.

[0134] One or more of the insulating layers 110a, 110b, and 110c can have a stacked structure. For example, the insulating layer 110c can have a stacked structure of an aluminum oxide film and a silicon nitride film over the aluminum oxide film.

[0135] The thickness T110c of the insulating layer 110c is preferably 3 nm to 500 nm, more preferably 5 nm to 400 nm, even more preferably 10 nm to 300 nm, even more preferably 20 nm to 300 nm, even more preferably 50 nm to 300 nm, even more preferably 100 nm to 300 nm, even more preferably 100 nm to 200 nm. As shown in FIG. 5A , the thickness T110c can be the shortest distance between the surface on which the insulating layer 110c is formed (here, the upper surface of the insulating layer 110b) and the upper surface of the insulating layer 110c in a cross-sectional view.

[0136] The thickness T110c is preferably a value that at least functions as a barrier film against oxygen. The thickness T110c can be thinner than the thickness T110a. If the thickness T110c of the insulating layer 110c is thick, the amount of impurities released from the insulating layer 110c increases, which may result in a larger amount of impurities diffusing into the channel formation region. On the other hand, if the thickness T110c is thin, oxygen contained in the insulating layer 110b may diffuse to the conductive layer 112b via the insulating layer 110c, which may result in a reduced amount of oxygen supplied to the channel formation region. By setting the thickness T110c within the above range, the amount of oxygen supplied to the channel formation region can be increased, and oxygen vacancies (V Ｏ ) and V Ｏ This can reduce H. Furthermore, it is possible to prevent the conductive layer 112b from being oxidized by oxygen contained in the insulating layer 110b, which would otherwise increase the electrical resistance of the conductive layer 112b. Note that the thickness T110c is not limited to the above range.

[0137] The thickness T110a of the insulating layer 110a is preferably 3 nm to 500 nm, more preferably 5 nm to 400 nm, even more preferably 10 nm to 300 nm, even more preferably 20 nm to 300 nm, even more preferably 50 nm to 300 nm, even more preferably 100 nm to 300 nm, even more preferably 100 nm to 250 nm, even more preferably 150 nm to 250 nm. As shown in FIG. 5A , the thickness T110a can be the shortest distance between the surface on which the insulating layer 110a is formed (e.g., the upper surface of the conductive layer 112a) and the upper surface of the insulating layer 110a in a cross-sectional view.

[0138] If the thickness T110a of the insulating layer 110a is small, oxygen contained in the insulating layer 110b may diffuse to the conductive layer 112a side through the insulating layer 110a, and the amount of oxygen supplied to the channel formation region may decrease. On the other hand, if the thickness T110a is large, the amount of impurities released from the insulating layer 110a may increase, and the amount of impurities diffusing into the channel formation region may increase. By setting the thickness T110a within the above range, the amount of oxygen supplied to the channel formation region can be increased, and oxygen vacancies (V Ｏ) and V Ｏ This can reduce the thickness T110a. In addition, it is possible to prevent the conductive layer 112a from being oxidized by oxygen contained in the insulating layer 110b, which would otherwise increase the electrical resistance of the conductive layer 112a. The thickness T110a is not limited to the above range.

[0139] The thickness T110a can be made thicker than the thickness T110c. When the region of the semiconductor layer 108 in contact with the insulating layer 110a functions as a source region or a drain region, the distance from the source region or the drain region to the gate electrode can be made more uniform by making the thickness T110a thicker. This makes it possible to make the electric field of the gate electrode applied to the channel formation region more uniform.

[0140] At least one of the region of the semiconductor layer 108 in contact with the insulating layer 110a and the region of the semiconductor layer 108 in contact with the insulating layer 110c can be a region having lower electrical resistance than the channel formation region (hereinafter also referred to as a low-resistance region). This region can also be referred to as a region having a higher carrier concentration or a higher oxygen defect density than the channel formation region. By using a material that releases impurities (e.g., water and hydrogen) for the insulating layer 110a, the region of the semiconductor layer 108 in contact with the insulating layer 110a contains impurities, and this region can be a low-resistance region. The semiconductor layer 108 can have a low-resistance region between the region in contact with the conductive layer 112a (one of the source region and the drain region) and the channel formation region. Similarly, by using a material that releases impurities for the insulating layer 110c, the region of the semiconductor layer 108 in contact with the insulating layer 110c contains impurities, and this region can be a low-resistance region. The semiconductor layer 108 may have a low-resistance region between a region in contact with the conductive layer 112b (the other of the source and drain regions) and the channel formation region. The low-resistance region may function as a buffer region for reducing the drain electric field. Note that the low-resistance region may also function as a source region or a drain region.

[0141] Note that impurities released from the insulating layer 110a may diffuse into the channel formation region via the insulating layer 110b or via one of the source region and the drain region of the semiconductor layer 108. Similarly, impurities released from the insulating layer 110c may diffuse into the channel formation region via the insulating layer 110b or via the other of the source region and the drain region of the semiconductor layer 108. However, oxygen is supplied from the insulating layer 110b to at least the region of the semiconductor layer 108 that is in contact with the insulating layer 110b, and therefore oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. This suppresses the shift of the threshold voltage, and a transistor having both a small cutoff current and a large on-state current can be obtained. Therefore, a semiconductor device having both low power consumption and high performance can be obtained. Note that the drain current flowing when the gate voltage (Vg) is 0 V may be referred to as the cutoff current.

[0142] However, if the amount of impurities released from the insulating layer 110a and the insulating layer 110c becomes too large, the impurities contained in the semiconductor layer 108 increase. As a result, oxygen vacancies (V Ｏ ) and V Ｏ The amount of H is the oxygen vacancy (V Ｏ ) and V Ｏ The amount of H may be greater than the amount of H. Even when a material that releases impurities is used for the insulating layer 110a and the insulating layer 110c, it is more preferable that the amount of released impurities is small.

[0143] The insulating layer 110a has a region in contact with the top surface and side surfaces of the conductive layer 112a and a region in contact with the top surface of the insulating layer 109. This can prevent impurities contained in the insulating layer 109 and the conductive layer 112a from diffusing into the channel formation region of the semiconductor layer 108 through the insulating layer 110b.

[0144] Note that impurities released from the insulating layer 109 may diffuse into the channel formation region via the conductive layer 112a and one of the source region and the drain region of the semiconductor layer 108. However, oxygen is supplied from the insulating layer 110b to at least the region of the semiconductor layer 108 that is in contact with the insulating layer 110b, and therefore oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. This suppresses a shift in threshold voltage, enabling a transistor with both a small cutoff current and a large on-state current. Therefore, a semiconductor device with both low power consumption and high performance can be provided.

[0145] The insulating layer 109 preferably has a region with a higher hydrogen content than the insulating layer 110a. The hydrogen content of the insulating layer 110 can be analyzed by, for example, secondary ion mass spectrometry (SIMS).

[0146] The amount of released hydrogen can be adjusted by differentiating the deposition conditions for the insulating layer 109 and the insulating layer 110a. Specifically, the insulating layer 109 and the insulating layer 110a can be made different from each other in one or more of the deposition power (deposition power density), deposition pressure, deposition gas type, deposition gas flow rate ratio, deposition temperature, and distance between the substrate and the electrode. For example, by making the deposition power density of the insulating layer 109 lower than the deposition power density of the insulating layer 110a, the hydrogen content in the insulating layer 109 can be made higher than the hydrogen content in the insulating layer 110a. This can increase the amount of hydrogen released from the insulating layer 109 due to heat applied to the insulating layer 109.

[0147] The deposition gas used to form the insulating layer 109 preferably contains more hydrogen than the deposition gas used to form the insulating layer 110a. Specifically, when a silicon nitride film or a silicon nitride oxide film is formed for each of the insulating layer 109 and the insulating layer 110a by a PECVD method, the ratio of the flow rate of ammonia gas to the total flow rate of the deposition gas used to form the insulating layer 109 (hereinafter also referred to as the ammonia flow rate ratio) is preferably higher than the ammonia flow rate ratio of the deposition gas used to form the insulating layer 110a. By forming the insulating layer 109 under the condition of a high ammonia flow rate ratio, the hydrogen content in the insulating layer 109 can be increased. Furthermore, the amount of hydrogen released from the insulating layer 109 due to heat applied to the insulating layer 109 can be increased.

[0148] The film density of the insulating layer 110a is preferably higher than that of the insulating layer 109. This can prevent hydrogen contained in the insulating layer 109 from diffusing into the channel formation region of the semiconductor layer 108 through the insulating layers 110a and 110b. The film density can be evaluated by, for example, Rutherford backscattering spectrometry (RBS) or X-ray reflectivity (XRR). The difference in film density can sometimes be evaluated by a cross-sectional transmission electron microscope (TEM) image. In TEM observation, a high film density results in a dense (dark) transmission electron (TE) image, whereas a low film density results in a faint (bright) transmission electron (TE) image. Therefore, in a TE image, the insulating layer 110a may appear denser (darker) than the insulating layer 109. Even when the same material is used for the insulating layer 109 and the insulating layer 110a, the film densities are different, and therefore, in a cross-sectional TEM image, the boundary between them may be observed as a difference in contrast.

[0149] Note that although the insulating layer 110 has a three-layer stacked structure here, one embodiment of the present invention is not limited to this. The insulating layer 110 preferably includes at least the insulating layer 110b. A structure without one or both of the insulating layer 110a and the insulating layer 110c is also possible. Alternatively, the insulating layer 110 may have a stacked structure of four or more layers.

[0150] As shown in Fig. 7A, the insulating layer 110 can have a five-layer stacked structure. Fig. 7A shows a configuration in which the insulating layer 110 has an insulating layer 110d, an insulating layer 110a on the insulating layer 110d, an insulating layer 110b on the insulating layer 110a, an insulating layer 110c on the insulating layer 110b, and an insulating layer 110e on the insulating layer 110c.

[0151] The insulating layer 110d and the insulating layer 110e can each be made of the same material as the insulating layer 109. For example, a silicon nitride film or a silicon nitride oxide film can be preferably used for the insulating layer 110d and the insulating layer 110e. The insulating layer 110d and the insulating layer 110e can each be made of the same material. Alternatively, the insulating layer 110d and the insulating layer 110e can each be made of different materials.

[0152] The insulating layer 110d is provided between the insulating layer 110a and the conductive layer 112a and the conductive layer 212a. The insulating layer 110d is provided so as to cover the conductive layer 112a, the conductive layer 212a, and the insulating layer 109. The insulating layer 110d has regions in contact with the top surface and side surface of the conductive layer 112a, the top surface and side surface of the conductive layer 212a, the top surface of the insulating layer 109, the side surface of the semiconductor layer 108, and the side surface of the semiconductor layer 208.

[0153] The insulating layer 110e is provided between the conductive layer 112b and the insulating layer 110c. The insulating layer 110e has regions in contact with the top surface of the insulating layer 110c, the bottom surface of the conductive layer 112b, the side surfaces of the semiconductor layer 108, and the side surfaces of the semiconductor layer 208.

[0154] The insulating layers 110d and 110e are preferably made of a material that releases impurities (e.g., water and hydrogen) that reduce the electrical resistance of the semiconductor layer 108 and the semiconductor layer 208, respectively. This allows the region of the semiconductor layer 108 in contact with the insulating layer 110d to be a low-resistance region. The semiconductor layer 108 can have a low-resistance region between the region in contact with the conductive layer 112a (one of the source and drain regions) and the channel formation region. Similarly, by using a material that releases impurities for the insulating layer 110e, the region of the semiconductor layer 108 in contact with the insulating layer 110e contains impurities, making this region a low-resistance region. The semiconductor layer 108 can have a low-resistance region between the region in contact with the conductive layer 112b (the other of the source and drain regions) and the channel formation region. Providing a low-resistance region between the source or drain region and the channel formation region can suppress hot carrier degradation. Note that these low-resistance regions may function as source or drain regions.

[0155] When the region of the semiconductor layer 108 in contact with the insulating layer 110d functions as a source region or a drain region, the distance from the source region to the gate electrode and the distance from the drain region to the gate electrode of the semiconductor layer 108 can be made more uniform, thereby making the electric field of the gate electrode applied to the channel formation region more uniform.

[0156] When a metal oxide is used for the semiconductor layer 108, it is more preferable that the impurities released from the insulating layers 110d and 110e include hydrogen. The hydrogen reacts with oxygen that is bonded to the metal atoms of the metal oxide to form water, which causes oxygen deficiency (V Ｏ ) is formed. Furthermore, oxygen vacancies (V Ｏ ) with hydrogen atoms (V Ｏ H) functions as a donor, generating electrons as carriers. This increases the carrier concentration in the region of the semiconductor layer 108 that is in contact with the insulating layer 110d and the region that is in contact with the insulating layer 110e, thereby reducing the electrical resistance.

[0157] For the semiconductor layer 208, the description of the semiconductor layer 108 can be referred to.

[0158] The insulating layer 110d preferably has a region containing more hydrogen than the insulating layer 110a. The film density of the insulating layer 110a is more preferably higher than that of the insulating layer 110d. For the insulating layer 110d and the insulating layer 110a, the description of the insulating layer 109 and the insulating layer 110a can be referred to.

[0159] Similarly, the insulating layer 110e preferably has a region containing more hydrogen than the insulating layer 110c. The film density of the insulating layer 110c is more preferably higher than that of the insulating layer 110e. For the insulating layers 110e and 110c, the descriptions of the insulating layers 109 and 110a can be referred to.

[0160] The insulating layer 110d is preferably made of a material that releases impurities that reduce the electrical resistance of the conductive layer 112a. This can reduce the electrical resistance of the conductive layer 112a. Similarly, the insulating layer 110e is preferably made of a material that releases impurities that reduce the electrical resistance of the conductive layer 112b. This can reduce the electrical resistance of the conductive layer 112b. For example, when a metal oxide is used for the conductive layers 112a and 112b, the impurities preferably contain hydrogen. This increases the carrier concentration of the conductive layers 112a and 112b, thereby reducing their electrical resistance. The conductive layers 112a and 112b can each function as wirings, thereby providing a semiconductor device with low wiring resistance.

[0161] Note that the insulating layer 110 may be omitted from either or both of the insulating layer 110d and the insulating layer 110e. For example, as shown in FIG. 7B, the insulating layer 110 may be formed of four layers: the insulating layer 110a, the insulating layer 110b, the insulating layer 110c, and the insulating layer 110e.

[0162] The configuration of the insulating layer 110 shown here can also be applied to other configuration examples.

[0163] [Semiconductor Layer 108, Semiconductor Layer 208] Metal oxides that can be used for the semiconductor layer 108 and the semiconductor layer 208 will be specifically described. In the following, the semiconductor layer 108 and the transistor 100 will be used as examples in some cases. For the semiconductor layer 208 and the transistor 200, the descriptions of the semiconductor layer 108 and the transistor 100 can be referred to.

[0164] Examples of metal oxides include indium oxide (also referred to as indium oxide, IO), gallium oxide (also referred to as gallium oxide), and zinc oxide (also referred to as zinc oxide). The metal oxide preferably contains at least indium. The metal oxide preferably contains one or both of indium and zinc. The metal oxide preferably contains one or more elements selected from indium, element M, and zinc. The element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from gallium, aluminum, tin, and yttrium, and even more preferably one or more of gallium, aluminum, and tin. These elements are more preferred because they have a high bond energy with oxygen and an ionic radius similar to that of indium or zinc. Furthermore, tin is more preferred because it is tetravalent and can increase carrier mobility. In this specification, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification may also include metalloid elements.

[0165] The semiconductor layer 108 may be formed of, for example, indium oxide, indium zinc oxide (In—Zn oxide, also referred to as IZO (registered trademark)), indium tin oxide (In—Sn oxide, also referred to as ITO), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium tungsten oxide (In—W oxide, also referred to as IWO), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al—Z), or the like. Examples of usable materials include indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as AZO), indium tin zinc oxide (In-Sn-Zn oxide, also referred to as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO, IGZAO, or IAGZO). Alternatively, examples of usable materials include indium tin oxide containing silicon (ITSO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide).

[0166] Note that the metal oxide may contain one or more metal elements having a higher period number in the periodic table instead of or in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide. Therefore, the presence of a metal element having a higher period number may improve the field-effect mobility of a transistor. Examples of metal elements having a higher period number include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0167] The metal oxide may contain one or more nonmetallic elements. The nonmetallic elements in the metal oxide may increase the carrier concentration or narrow the band gap, thereby increasing the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0168] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the field-effect mobility of the transistor can be increased, and a transistor with a large on-state current can be realized.

[0169] In this specification and the like, the ratio of the number of indium atoms to the sum of the numbers of atoms of all contained metal elements may be referred to as the indium content. The same applies to other metal elements. When a plurality of elements are contained as the element M, the sum of the ratios of the number of atoms of the element M to the sum of the numbers of atoms of all contained metal elements can be referred to as the content of the element M.

[0170] By increasing the zinc content in the metal oxide, the metal oxide can be made highly crystalline, which can suppress the diffusion of impurities in the metal oxide, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0171] By increasing the content of element M in the metal oxide, it is possible to obtain a metal oxide with a large band gap. Ｏ ) is suppressed, the formation of oxygen vacancies (V Ｏ ) can be suppressed, and a shift in the threshold voltage of the transistor can be suppressed. As a result, the cutoff current can be reduced, and the transistor can be a normally-off transistor. In addition, the transistor can have a small off-state current. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

[0172] The electrical characteristics and reliability of a transistor vary depending on the composition of the metal oxide used in the semiconductor layer 108. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, a semiconductor device that has both excellent electrical characteristics and high reliability can be obtained.

[0173] When the metal oxide is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of the element M. Examples of atomic ratios of metal elements in such In-M-Zn oxides include In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:1, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M Examples of suitable compositions include In:M:Zn = 5:1:9, In:M:Zn = 6:1:6, In:M:Zn = 10:1:1, In:M:Zn = 10:1:3, In:M:Zn = 10:1:4, In:M:Zn = 10:1:6, In:M:Zn = 10:1:7, In:M:Zn = 10:1:8, In:M:Zn = 5:2:5, In:M:Zn = 10:1:10, In:M:Zn = 20:1:10, In:M:Zn = 40:1:10, and compositions in the vicinity thereof. Note that a composition in the vicinity includes a range of ±30% of the desired atomic ratio. Increasing the atomic ratio of indium in the metal oxide can increase the on-state current or field-effect mobility of the transistor.

[0174] The atomic ratio of In in the In-M-Zn oxide can be less than the atomic ratio of the element M. Examples of atomic ratios of metal elements in such In-M-Zn oxide include In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, In:M:Zn=1:3:6, and compositions close to these. By increasing the ratio of the number of M atoms in the metal oxide, oxygen deficiency (V Ｏ ) can be suppressed.

[0175] When the element M contains a plurality of elements, the atomic ratio of the element M can be the sum of the atomic ratios of these elements.

[0176] By using a material with a high indium content for the semiconductor layer 108, the on-state current or the field-effect mobility of the transistor can be increased. Ｏ) can be suppressed. The content of element M (the ratio of the number of atoms of element M to the sum of the number of atoms of all contained metal elements) is preferably 0.1% to 25%, more preferably 0.1% to 20%, even more preferably 0.1% to 10%, even more preferably 0.1% to 8%, even more preferably 0.1% to 6%, and even more preferably 0.1% to 4%. This allows for a transistor with excellent electrical characteristics. For example, it is preferable to use a metal oxide having a ratio of In:M:Zn=40:1:10 or a metal oxide having a similar ratio. The element M is preferably one or more of the above elements, and more preferably one or more selected from aluminum, gallium, tin, and yttrium. Specifically, metal oxides having a ratio of In:Sn:Zn=40:1:10 or a metal oxide having a similar ratio can be suitably used. Alternatively, metal oxides having a ratio of In:Al:Zn=40:1:10 or a metal oxide having a similar ratio can be suitably used.

[0177] Here, when a polycrystalline metal oxide is used for the semiconductor layer 108, crystal grain boundaries become recombination centers, and carriers are captured, which may reduce the on-state current of the transistor. Furthermore, when a polycrystalline metal oxide is used for the semiconductor layer 108, the surface of the semiconductor layer 108 may become uneven. This increases the step on the surface where a layer (e.g., the insulating layer 106) formed on the semiconductor layer 108 is to be formed, which may cause defects such as discontinuities or voids in the layer. When a metal oxide having a composition that easily results in a polycrystalline structure is used for the semiconductor layer 108, it is preferable to include an element that inhibits crystallization. This prevents the semiconductor layer 108 from becoming polycrystalline, resulting in a transistor with a large on-state current. Furthermore, the coverage of a layer (e.g., the insulating layer 106) formed on the semiconductor layer 108 can be improved, which may prevent defects such as discontinuities or voids in the layer.

[0178] For example, compared to indium tin oxide (ITO), indium tin oxide (ITSO) containing silicon is less likely to form a polycrystalline structure, and therefore can be suitably used for the semiconductor layer 108. When ITSO is used, the silicon content (the ratio of the number of silicon atoms to the sum of the numbers of atoms of all metal elements contained) is preferably 1% to 20%, more preferably 3% to 20%, even more preferably 3% to 15%, and even more preferably 5% to 15%. As the atomic ratio of metal elements, for example, In:Sn:Si=45:5:4, In:Sn:Si=95:5:8, and metal oxides in the vicinity thereof can be suitably used. When indium tin oxide (ITSO) containing silicon is used for the semiconductor layer 108, it is preferable that the ITSO have crystallinity. Note that the semiconductor layer 108 may have an amorphous region or may be amorphous.

[0179] A metal oxide not containing element M can be used for the semiconductor layer 108. When the metal oxide is an In-Zn oxide, the atomic ratio of the metal elements can be, for example, In:Zn = 1:1, In:Zn = 2:1, In:Zn = 1:2, In:Zn = 3:1, In:Zn = 3:2, In:Zn = 2:3, In:Zn = 4:1, In:Zn = 4:3, In:Zn = 5:1, In:Zn = 5:2, In:Zn = 5:3, In:Zn = 5:4, In:Zn = 5:6, In:Zn = 5:7, In:Zn = 5:8, In:Zn = 5:9, In:Zn = 7:1, In:Zn = 10:1, In:Zn = 10:3, In:Zn = 10:7, and compositions in the vicinity thereof. Furthermore, it is more preferable that the atomic ratio of In is equal to or greater than the atomic ratio of Zn. By increasing the atomic ratio of indium in the metal oxide, the on-state current or field-effect mobility of the transistor can be increased.

[0180] The composition of the semiconductor layer 108 can be analyzed by, for example, Energy Dispersive X-ray Spectrometry (EDX), X-ray Photoelectron Spectroscopy (XPS), or Electron Spectrometry for Chemical Analysis (ESCA), Inductively Coupled Plasma-Mass Spectrometry (ICP-MS), or Inductively Coupled Plasma-Atomic Emission Spectroscopy (ICP-AES). Spectrometry) can be used. Alternatively, a combination of these techniques can be used for analysis. It is preferable to separate the peaks of the spectrum obtained by the analysis and identify and quantify the elements. Note that for elements with low content, the actual content and the content obtained by analysis may differ due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content, it may be difficult to quantify the content of element M, or element M may be below the detection limit.

[0181] The metal oxide film can be preferably formed by sputtering or atomic layer deposition (ALD). When the metal oxide film is formed by sputtering, the composition of the formed metal oxide film may differ from the composition of the sputtering target. In particular, the zinc content in the formed metal oxide film may decrease to about 50% of the zinc content in the sputtering target.

[0182] It is preferable to use a crystalline metal oxide for the semiconductor layer 108. Examples of the structure of a crystalline metal oxide include a c-axis aligned crystal (CAAC) structure, a polycrystalline structure, and a nanocrystalline (nc) structure. By using a crystalline metal oxide, the density of defect states in the semiconductor layer 108 can be reduced, and a highly reliable semiconductor device can be realized.

[0183] The semiconductor layer 108 is preferably formed using a CAAC-OS or an nc-OS.

[0184] The CAAC-OS has a plurality of layered crystals. The c-axes of the crystals are oriented in the normal direction to the surface where the semiconductor layer 108 is formed. The semiconductor layer 108 preferably has layered crystals parallel or approximately parallel to the surface where the semiconductor layer 108 is formed. For example, the semiconductor layer 108 preferably has layered crystals parallel or approximately parallel to the top surface of the conductive layer 112b in a region in contact with the top surface of the conductive layer 112b and layered crystals parallel or approximately parallel to the side surface of the conductive layer 112b in a region in contact with the side surface of the conductive layer 112b. In particular, the semiconductor layer 108 preferably has layered crystals parallel or approximately parallel to the side surface 77 of the insulating layer 110, which is the surface where the semiconductor layer 108 is formed. With this structure, the layered crystals of the semiconductor layer 108 are formed parallel or approximately parallel to the channel length direction of the transistor 100, thereby enabling the transistor to have a large on-state current.

[0185] By using a metal oxide with high crystallinity for the channel formation region, the density of defect states in the channel formation region can be reduced, while by using a metal oxide with low crystallinity, a transistor capable of passing a large current can be realized.

[0186] The higher the substrate temperature during deposition of a metal oxide film, the higher the crystallinity of the resulting metal oxide film. The substrate temperature during deposition can be adjusted, for example, by the temperature of the stage on which the substrate is placed during deposition. Furthermore, the higher the oxygen flow rate ratio of the deposition gas used for deposition or the oxygen partial pressure in the processing chamber, the higher the crystallinity of the resulting metal oxide film.

[0187] The crystallinity of the semiconductor layer 108 can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, the analysis can be performed by combining a plurality of these techniques.

[0188] When a metal oxide is used for the semiconductor layer 108, V ＯIt is preferable to reduce H as much as possible to obtain high-purity intrinsic or substantially high-purity intrinsic. Ｏ To obtain a metal oxide with a sufficiently reduced amount of H, impurities such as water and hydrogen in the metal oxide must be removed (sometimes referred to as dehydration or dehydrogenation treatment), and oxygen must be supplied to the metal oxide to eliminate oxygen deficiency (V Ｏ It is important to repair the Ｏ By using a metal oxide in which impurities such as H are sufficiently reduced in a channel formation region of a transistor, stable electrical characteristics can be obtained. Ｏ ) is sometimes referred to as oxygenation treatment.

[0189] When a metal oxide is used for the semiconductor layer 108, the carrier concentration in the channel formation region is 1×10 １８ cm −３ Preferably, it is 1×10 or less. １７ cm −３ More preferably, it is less than 1×10 １６ cm −３ More preferably, it is less than 1×10 １３ cm −３ More preferably, it is less than 1×10 １２ cm −３ It is more preferable that the carrier concentration in the channel formation region is less than 1×10. −９ cm −３ It can be said that:

[0190] OS transistors exhibit little change in electrical characteristics due to radiation exposure, i.e., have high radiation resistance, and therefore can be suitably used in environments where radiation may be incident. It can also be said that OS transistors have high reliability against radiation. For example, OS transistors can be suitably used in pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton rays, and neutron rays).

[0191] The semiconductor layer 108 may include a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals bonds. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-state current can be provided.

[0192] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (an element belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as the channel formation region of a transistor include molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) etc.

[0193] The semiconductor layer 108 can have a stacked structure including two or more metal oxide layers. The two or more metal oxide layers included in the semiconductor layer 108 can have the same or substantially the same composition. By using a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs. When the two or more metal oxide layers included in the semiconductor layer 108 have the same or substantially the same composition, the boundary (interface) between these metal oxide layers may not be clearly identified.

[0194] 5A and 5B , the channel lengths and channel widths of the transistor 100 and the transistor 200 will be described. FIG. 5B is a top view of the semiconductor device 10. Here, a region of the semiconductor layer 108 in contact with the side surface of the insulating layer 110b is described as a channel formation region of the transistor 100, and a region of the semiconductor layer 208 in contact with the side surface of the insulating layer 110b is described as a channel formation region of the transistor 200.

[0195] In FIG. 5A , the channel length L100 of the transistor 100 and the channel length L200 of the transistor 200 are indicated by dashed double-headed arrows. The channel length L100 of the transistor 100 corresponds to the length of the region where the semiconductor layer 108 and the side surface of the insulating layer 110b meet in a cross-sectional view. That is, the channel length L100 is determined by the thickness T110b of the insulating layer 110b and the angle θ110b between the side surface of the insulating layer 110b facing the semiconductor layer 108 and the surface on which the insulating layer 110b is to be formed (here, the upper surface of the insulating layer 110a). Therefore, the channel length L100 can be set to a value smaller than the minimum exposure dimension of the exposure tool, enabling the realization of a fine-sized transistor. Specifically, this allows the realization of a transistor with an extremely short channel length that could not be realized with conventional exposure tools used in the mass production of flat panel displays (e.g., minimum dimensions of approximately 2 μm or 1.5 μm). Furthermore, it is possible to realize a transistor having a channel length of less than 10 nm without using the extremely expensive exposure equipment used in cutting-edge LSI technology. The same applies to the channel length L200.

[0196] The channel length L100 and the channel length L200 may each be, for example, 5 nm or more, 7 nm or more, or 10 nm or more, and may be less than 3 μm, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less. For example, the channel length L100 may be 100 nm or more and 1 μm or less.

[0197] By shortening the channel length L100, the on-state current of the transistor 100 can be increased. By shortening the channel length L200, the on-state current of the transistor 200 can be increased. By using the transistors 100 and 200, a circuit capable of high-speed operation can be manufactured. Furthermore, the area occupied by the circuit can be reduced. Therefore, a small-sized semiconductor device can be obtained. For example, when the semiconductor device of one embodiment of the present invention is applied to a large display device or a high-resolution display device, even if the number of wirings is increased, signal delay in each wiring can be reduced, and display unevenness can be suppressed. Furthermore, since the area occupied by the circuit can be reduced, the frame of the display device can be narrowed.

[0198] By adjusting the thickness T110b and angle θ110b of the insulating layer 110b, the channel length L100 and the channel length L200 can be controlled.

[0199] The thickness T110b of the insulating layer 110b can be, for example, 5 nm or more, 7 nm or more, or 10 nm or more, and can be less than 3 μm, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less.

[0200] The side surface of the insulating layer 110 facing the semiconductor layer 108 and the side surface facing the semiconductor layer 208 preferably have a tapered shape. The angle θ110b is preferably less than 90 degrees. By reducing the angle θ110b, the coverage of the layers (e.g., the semiconductor layer 108 and the semiconductor layer 208) formed on the insulating layer 110 can be improved. Furthermore, when the angle θ110b is 90 degrees or less, the smaller the angle θ110b, the longer the channel lengths L100 and L200 can be, and the larger the angle θ110b, the shorter the channel lengths L100 and L200 can be.

[0201] The angle θ110b can be, for example, 30 degrees or more, 35 degrees or more, 40 degrees or more, 45 degrees or more, 50 degrees or more, 55 degrees or more, 60 degrees or more, 65 degrees or more, or 70 degrees or more, and can be less than 90 degrees, 85 degrees or less, or 80 degrees or less. The angle θ110b can also be 75 degrees or less, 70 degrees or less, 65 degrees or less, or 60 degrees or less.

[0202] 1C and the like, the angle θ110b is shown as being less than 90 degrees, but this is not a limitation of one embodiment of the present invention. The angle θ110b may also be set to 90 degrees or approximately 90 degrees. This allows the channel lengths L100 and L200 to be shortened and the area occupied by the semiconductor device to be reduced.

[0203] 1C and other figures show a configuration in which the side surfaces 77 and 77a are linear in cross section, but this is not a limitation of one aspect of the present invention. In cross section, the side surfaces 77 may be curved. Alternatively, the side surfaces 77 may include both linear and curved regions. The same applies to the side surfaces 77a.

[0204] The top surface shape of the conductive layer 112b preferably coincides with or substantially coincides with that of the insulating layer 110. FIG. 1A and other figures illustrate a configuration in which the top surface shape of the conductive layer 112b coincides with that of the insulating layer 110. The conductive layer 112b and the insulating layer 110 can be formed using the same mask layer. For example, an insulating film that will become the insulating layer 110 and a conductive film that will become the conductive layer 112b on the insulating film are formed, and a mask layer (e.g., a resist mask) is formed on the conductive film. Then, by processing the conductive film and the insulating film using the mask layer as a mask, the conductive layer 112b and the insulating layer 110 can be formed with top surface shapes that coincide with or substantially coincide with each other. Processing the insulating film that will become the insulating layer 110 and the conductive film that will become the conductive layer 112b in the same process can reduce manufacturing costs. Note that although the top surface shapes of the conductive layer 112b and the insulating layer 110 are shown as rectangular in FIG. 1A and other figures, these top surface shapes are not particularly limited. In addition, in FIG. 1C and other figures, the side surface 77 and the side surface 77a are shown separately, but the side surfaces of the insulating layer 110 may be continuously connected, making it difficult to distinguish between the side surface 77 and the side surface 77a.

[0205] It is preferable that there is no step between the side surface of the conductive layer 112b facing the semiconductor layer 108 and the side surface 77a, and that the surface is flat (i.e., the two surfaces are flush). Similarly, it is preferable that there is no step between the side surface of the conductive layer 112b facing the semiconductor layer 208 and the side surface 77a, and that the surface is flat. This can improve the coverage of the insulating layer 110 and the layers (e.g., the semiconductor layer 108 and the semiconductor layer 208) provided on the conductive layer 112b. Note that a configuration may also be adopted in which the side surface of the conductive layer 112b facing the semiconductor layer 108 and the side surface 77 are discontinuous, and the side surface of the conductive layer 112b facing the semiconductor layer 208 and the side surface 77a are discontinuous. Furthermore, a configuration in which the top surface shape of the conductive layer 112b does not match the top surface shape of the insulating layer 110 may also be adopted.

[0206] Here, it is preferable that the conductive layer 112b does not have a region in contact with the side surface (e.g., the side surface 77 and the side surface 77a) of the insulating layer 110. If the conductive layer 112b is also in contact with the side surface 77, the channel length L100 of the transistor 100 becomes shorter than the length of the side surface of the insulating layer 110b, which may make it difficult to control the channel length L100. The same applies to the side surface 77a and the transistor 200. Therefore, it is preferable that the top surface shape of the conductive layer 112b and the top surface shape of the insulating layer 110 match or approximately match, or that the insulating layer 110 encompasses the conductive layer 112b in a top view.

[0207] 5B , the channel width W100 of the transistor 100 and the channel width W200 of the transistor 200 are each indicated by a double-arrowed, two-dot chain line. The channel width W100 is the width of the region where the semiconductor layer 108 and the conductive layer 104 overlap in a direction perpendicular to the channel length direction. The channel width W200 is the width of the region where the semiconductor layer 208 and the conductive layer 204 overlap in a direction perpendicular to the channel length direction.

[0208] When the semiconductor layer 108, the semiconductor layer 208, the conductive layer 104, and the conductive layer 204 are formed using lithography, the channel widths W100 and W200 are equal to or larger than the minimum dimensions that can be exposed by an exposure apparatus. The channel widths W100 and W200 are, for example, 20 nm or more, 50 nm or more, 100 nm or more, 200 nm or more, 500 nm or more, or 1 μm or more, and can be less than 500 μm, 200 μm or less, 100 μm or less, 50 μm or less, 20 μm or less, 10 μm or less, or 5 μm or less. While FIG. 5B and other figures show a configuration in which the channel widths W100 and W200 are the same, one embodiment of the present invention is not limited thereto. The channel widths W100 and W200 can be different from each other.

[0209] Note that although the example described here is a structure in which the region of the semiconductor layer 108 in contact with the insulating layer 110b functions as the channel formation region of the transistor 100 and the region of the semiconductor layer 208 in contact with the insulating layer 110b functions as the channel formation region of the transistor 200, one embodiment of the present invention is not limited to this. The region of the semiconductor layer 108 in contact with the insulating layer 110a may also function as the channel formation region of the transistor 100, and the region of the semiconductor layer 208 in contact with the insulating layer 110a may also function as the channel formation region of the transistor 200. Similarly, the region of the semiconductor layer 108 in contact with the insulating layer 110c and the region of the semiconductor layer 208 in contact with the insulating layer 110c may also function as channel formation regions.

[0210] Although FIG. 1A and the like illustrate a structure in which the semiconductor layer 108 and the semiconductor layer 208 are provided on different side surfaces (here, the side surface 77 and the side surface 77a) of the insulating layer 110, one embodiment of the present invention is not limited to this.

[0211] 8A to 9B, the semiconductor layer 108 and the semiconductor layer 208 can be provided on the same side of the insulating layer 110. FIG. 8A is a top view of the semiconductor device 10, and FIG. 8B is a cross-sectional view of the cut surface taken along dashed dotted line A1-A2 shown in FIG. 8A. FIG. 9A is a perspective view of the semiconductor device 10. FIG. 9B is a perspective view in which the conductive layer 104, the conductive layer 204, and the insulating layer 106 are omitted from FIG. 9A.

[0212] The semiconductor layer 108 has a region in contact with the top surface and side surface of the conductive layer 112b, the side surface 77, and the top surface of the conductive layer 112a. The semiconductor layer 208 has a region in contact with the top surface and side surface of the conductive layer 112b, the side surface 77, and the top surface of the conductive layer 212a.

[0213] There is no particular limitation on the side surfaces of the insulating layer 110 on which the semiconductor layer 108 and the semiconductor layer 208 are provided. Therefore, the degree of freedom in the layout of the semiconductor layer 108 and the semiconductor layer 208 can be increased, and the area occupied by the semiconductor device can be reduced.

[0214] [Conductive Layer 112a, Conductive Layer 112b, Conductive Layer 212a, Conductive Layer 104, Conductive Layer 204] The conductive layers 112a, 112b, 212a, 104, and 204 can each have a single-layer structure or a stacked structure of two or more layers. Materials that can be used for these conductive layers include, for example, one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, as well as alloys containing one or more of the aforementioned metals. For these conductive layers, conductive materials with low electrical resistivity, such as one or more of copper, silver, gold, and aluminum, can be preferably used. Copper and aluminum are particularly preferred due to their excellent mass productivity.

[0215] An oxide conductor can be used for each of the conductive layers 112a, 112b, 212a, 104, and 204. The above description can be referred to for the oxide conductor.

[0216] When oxygen vacancies are formed in a metal oxide having semiconductor properties and hydrogen is added to the oxygen vacancies, a donor level is formed near the conduction band. As a result, the metal oxide becomes electrically conductive, and the conductivity of the metal oxide increases. The metal oxide that has become electrically conductive can be called an oxide conductor.

[0217] The conductive layer 112a, the conductive layer 112b, the conductive layer 212a, the conductive layer 104, and the conductive layer 204 can each have a stacked structure of a conductive film containing the oxide conductor (metal oxide) and a conductive film containing a metal or an alloy. By using a conductive film containing a metal or an alloy, wiring resistance can be reduced.

[0218] A Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) can be applied to each of the conductive layer 112a, the conductive layer 112b, the conductive layer 212a, the conductive layer 104, and the conductive layer 204. By using a Cu-X alloy film, it can be processed by wet etching, thereby reducing manufacturing costs.

[0219] Note that the conductive layer 112a, the conductive layer 112b, the conductive layer 212a, the conductive layer 104, and the conductive layer 204 can be formed using the same material, or at least one of them can be formed using a different material.

[0220] The conductive layer 112a has a region in contact with the semiconductor layer 108, the conductive layer 212a has a region in contact with the semiconductor layer 208, and the conductive layer 112b has a region in contact with the semiconductor layer 108 and the semiconductor layer 208. When a metal oxide is used for the semiconductor layer 108 and the semiconductor layer 208, if a metal that is easily oxidized (e.g., aluminum) is used for these conductive layers, an insulating oxide (e.g., aluminum oxide) may be formed between the conductive layer 112a or the conductive layer 112b and the semiconductor layer 108, and between the conductive layer 212a or the conductive layer 112b and the semiconductor layer 208, which may hinder conduction therebetween. Therefore, it is preferable to use a conductive material that is not easily oxidized, a conductive material that maintains low electrical resistance even when oxidized, or an oxide conductor for these conductive layers.

[0221] For the conductive layer 112a, the conductive layer 112b, and the conductive layer 212a, it is preferable to use, for example, titanium, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel. These are preferable because they are conductive materials that are resistant to oxidation or materials that maintain low electrical resistance even when oxidized. Note that when the conductive layer 112a or the conductive layer 112b has a stacked structure, it is preferable to use a conductive material that is resistant to oxidation for at least the layer in contact with the semiconductor layer 108. Similarly, when the conductive layer 212a or the conductive layer 112b has a stacked structure, it is preferable to use a conductive material that is resistant to oxidation for at least the layer in contact with the semiconductor layer 208.

[0222] The conductive layer 112a, the conductive layer 112b, and the conductive layer 212a can each be made of any of the above-mentioned oxide conductors. Specifically, oxide conductors such as indium oxide, zinc oxide, ITO, In—Zn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, ITSO, and zinc oxide to which gallium has been added can be used. In particular, oxide conductors containing indium have high conductivity and can therefore be suitably used for the conductive layer 112a, the conductive layer 112b, and the conductive layer 212a.

[0223] The conductive layer 112a, the conductive layer 112b, and the conductive layer 212a may each be made of a nitride conductor, such as tantalum nitride or titanium nitride.

[0224] The conductive layer 112a, the conductive layer 112b, the conductive layer 212a, the conductive layer 104, and the conductive layer 204 can each have a single-layer structure or a stacked structure of two or more layers.

[0225] When the conductive layer 112a, the conductive layer 112b, and the conductive layer 212a have a stacked structure, the first conductive layer in contact with one or more of the semiconductor layer 108 and the semiconductor layer 208 is preferably made of a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, or an oxide conductor. For example, ITO or ITSO can be suitably used for the first conductive layer. On the other hand, the material used for the second conductive layer that is not in contact with either the semiconductor layer 108 or the semiconductor layer 208 is not particularly limited. For example, the second conductive layer is preferably made of a material having lower electrical resistivity than the first conductive layer. This can reduce the electrical resistance of the conductive layer 112a, the conductive layer 112b, and the conductive layer 212a. For example, copper or tungsten can be suitably used for the second conductive layer.

[0226] The extending direction of the conductive layer 112a, the conductive layer 112b, the conductive layer 212a, the conductive layer 104, and the conductive layer 204 is not particularly limited.

[0227] [Insulating Layer 106] The insulating layer 106 preferably has one or more inorganic insulating layers. The insulating layer 106 can be made of the same material as that used for the insulating layer 110.

[0228] The insulating layer 106 has regions in contact with the semiconductor layer 108, the semiconductor layer 208, the conductive layer 112a, the conductive layer 212a, the conductive layer 112b, the conductive layer 104, and the insulating layer 110. When a metal oxide is used for the semiconductor layer 108 and the semiconductor layer 208, any of the above-described oxides and oxynitrides is preferably used for at least a film in contact with the semiconductor layer 108 and the semiconductor layer 208 among films constituting the insulating layer 106. When the insulating layer 106 has a single-layer structure, silicon oxide, silicon oxynitride, or aluminum oxide can be suitably used for the insulating layer 106.

[0229] Note that in a miniaturized transistor, a thin gate insulating layer may result in a large leakage current. By using a material with a high relative dielectric constant (also referred to as a high-k material) for the gate insulating layer, a low voltage can be achieved during transistor operation while maintaining the physical film thickness. Examples of high-k materials that can be used for the insulating layer 106 include gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium.

[0230] 1C and the like, the insulating layer 106 has a single-layer structure, but one embodiment of the present invention is not limited to this. The insulating layer 106 can have a stacked structure of two or more layers. 10A to 10C show a structure in which the insulating layer 106 has a two-layer structure of an insulating layer 106a and an insulating layer 106b over the insulating layer 106a.

[0231] When the insulating layer 106 has a stacked structure, the insulating layers on the semiconductor layer 108 side and the semiconductor layer 208 side (the insulating layer 106a here) are preferably made of oxide or oxynitride. For example, the insulating layer 106a can be preferably made of one or more of silicon oxide, silicon oxynitride, and aluminum oxide. Alternatively, the insulating layer 106a can be made of nitride or nitride oxide. For example, aluminum nitride can be preferably used for the insulating layer 106a.

[0232] At least one of the layers constituting the insulating layer 106 preferably functions as a barrier film. By providing the barrier film, it is possible to suppress the diffusion of metal components contained in the conductive layer 104 and the conductive layer 204 and impurities (e.g., water and hydrogen) contained in layers formed over the transistor 100 and the transistor 200 to the semiconductor layer 108 and the semiconductor layer 208 through the insulating layer 106. Furthermore, it is possible to suppress the diffusion of oxygen contained in the insulating layer 110b to the conductive layer 104 side and the conductive layer 204 side through the insulating layer 106. As a result, the amount of oxygen supplied from the insulating layer 110b to the channel formation region of the semiconductor layer 108 and the channel formation region of the semiconductor layer 208 increases, and oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. Therefore, a transistor with good electrical characteristics and high reliability can be obtained. Furthermore, the conductive layer 104 and the conductive layer 204 can be prevented from being oxidized by oxygen contained in the insulating layer 110b, which can prevent the electrical resistance of these conductive layers from increasing. As a result, a transistor with good electrical characteristics and high reliability can be obtained. The above-mentioned materials can be used as the barrier film. For example, one or more of silicon nitride, aluminum oxide, and aluminum nitride can be suitably used for one or more layers constituting the insulating layer 106.

[0233] When the insulating layer 106 has a stacked-layer structure, for example, silicon oxynitride can be used for the insulating layer 106a and silicon nitride can be used for the insulating layer 106b. Alternatively, silicon oxynitride can be used for the insulating layer 106a and aluminum oxide can be used for the insulating layer 106b. Alternatively, silicon oxynitride can be used for the insulating layer 106a and aluminum nitride can be used for the insulating layer 106b. Alternatively, aluminum oxide can be used for the insulating layer 106a and silicon oxynitride can be used for the insulating layer 106b. Alternatively, aluminum oxide can be used for the insulating layer 106a and silicon nitride can be used for the insulating layer 106b. Alternatively, aluminum nitride can be used for the insulating layer 106a and silicon oxynitride can be used for the insulating layer 106b.

[0234] Although an example in which the insulating layer 106 has a stacked structure of two layers is shown here, one embodiment of the present invention is not limited to this. The insulating layer 106 can also have a stacked structure of three or more layers.

[0235] The configuration of the insulating layer 106 shown here can also be applied to other configuration examples.

[0236] [Substrate 102] There are no significant limitations on the material of the substrate 102, but it must have at least heat resistance sufficient to withstand subsequent heat treatment. For example, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, or a resin substrate can be used as the substrate 102. Alternatively, a substrate on which a semiconductor element is provided can be used as the substrate 102. A substrate on which an insulating film is formed on the surface can be used as the substrate 102. The shape of the substrate 102 is not particularly limited, and can be, for example, circular or rectangular.

[0237] A flexible substrate can be used as the substrate 102, and the transistors 100 and 200 can be formed directly on the flexible substrate. Alternatively, a peeling layer can be provided between the substrate 102 and the transistors 100 and 200. By providing the peeling layer, after a semiconductor device is partially or entirely completed thereon, the semiconductor device can be separated from the substrate 102 and transferred to another substrate. In this case, the transistors 100 and 200 can also be transferred to a substrate with low heat resistance or a flexible substrate.

[0238] The following describes a configuration example of a semiconductor device that is partially different from the configuration example described above. Note that, in the following, descriptions of parts that overlap with the configuration example described above may be omitted. Furthermore, in the drawings shown below, parts that have the same functions as the configuration example described above may be hatched with the same pattern and may not be assigned reference numerals.

[0239] [Configuration Example 1-2] FIG. 11A shows a top view of a semiconductor device 10A according to one embodiment of the present invention. FIG. 11B shows an equivalent circuit diagram of the semiconductor device 10A. FIG. 11C shows a cross-sectional view of the cut surface taken along dashed dotted line A1-A2 in FIG. 11A. FIG. 2A can be referred to for a cross-sectional view of the cut surface taken along dashed dotted line B1-B2 in FIG. 11A. FIG. 12 shows a cross-sectional view of the cut surface taken along dashed dotted line B3-B4.

[0240] The semiconductor device 10A includes a transistor 100, a transistor 200, an insulating layer 110, an insulating layer 210, and an insulating layer 109.

[0241] The transistor 100 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112a, and a conductive layer 112b. The above description of the transistor 100 can be referred to.

[0242] The transistor 200 includes a conductive layer 204, an insulating layer 106, a semiconductor layer 208, a conductive layer 112a, and a conductive layer 212b. In the transistor 200, the conductive layer 204 functions as a gate electrode, and the insulating layer 106 functions as a gate insulating layer. The conductive layer 112a functions as one of a source electrode and a drain electrode, and the conductive layer 212b functions as the other electrode.

[0243] The conductive layer 112a functions as one of a source electrode and a drain electrode of the transistor 100 and also functions as one of a source electrode and a drain electrode of the transistor 200. By sharing the conductive layer 112a between the transistors 100 and 200, the area occupied by the circuit can be reduced, and a small-sized semiconductor device can be provided.

[0244] One of the source and the drain of the transistor 100 is connected to one of the source and the drain of the transistor 200. Note that although the transistors 100 and 200 are both n-channel transistors in FIG. 11B, one embodiment of the present invention is not limited thereto. One or both of the transistors 100 and 200 can be p-channel transistors.

[0245] A perspective view of the semiconductor device 10A is shown in Fig. 13A. A perspective view in which the conductive layer 104, the conductive layer 204, and the insulating layer 106 are omitted from Fig. 13A is shown in Fig. 13B.

[0246] The conductive layer 112a is provided over the insulating layer 109, and the insulating layer 110 and the insulating layer 210 are provided over the conductive layer 112a. The conductive layer 112b is provided over the insulating layer 110, and the conductive layer 212b is provided over the insulating layer 210. The insulating layer 110 is in contact with the conductive layer 112a and the conductive layer 112b and has a region sandwiched between the conductive layer 112a and the conductive layer 112b. The insulating layer 210 is in contact with the conductive layer 112a and the conductive layer 212b and has a region sandwiched between the conductive layer 112a and the conductive layer 212b. The conductive layer 112a has a region overlapping with the conductive layer 112b with the insulating layer 110 interposed therebetween and a region overlapping with the conductive layer 212b with the insulating layer 210 interposed therebetween.

[0247] The insulating layer 210 can be described in the description of the insulating layer 110. The insulating layer 210 can be formed using the same materials as those for the insulating layer 110. The insulating layer 210 can be formed in the same process as the insulating layer 110.

[0248] The insulating layer 210 preferably has a stacked structure. Fig. 11C and other figures show an example in which the insulating layer 210 has an insulating layer 210a, an insulating layer 210b on the insulating layer 210a, and an insulating layer 210c on the insulating layer 210b. The description of the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c can be referred to for the insulating layer 210a, the insulating layer 110b, and the insulating layer 210c, and therefore detailed description thereof will be omitted.

[0249] For the conductive layer 212b, the description of the conductive layer 112b can be referred to. The conductive layer 212b can be formed using any of the materials listed for the conductive layer 112b. The conductive layer 212b can be formed in the same process as the conductive layer 112b.

[0250] As described above, the top surface shape of the conductive layer 112b preferably matches or substantially matches the top surface shape of the insulating layer 110. Similarly, the top surface shape of the conductive layer 212b preferably matches or substantially matches the top surface shape of the insulating layer 210. The conductive layer 112b, the insulating layer 110, the conductive layer 212b, and the insulating layer 210 can be formed using the same mask layer. For example, an insulating film that will become the insulating layer 110 and the insulating layer 210, and a conductive film that will become the conductive layer 112b and the conductive layer 212a on the insulating film are formed, and a mask layer (e.g., a resist mask) is formed on the conductive film. Then, by processing the conductive film and the insulating film using the mask layer as a mask, the conductive layer 112b and the insulating layer 110 that have the same or substantially the same top surface shape can be formed, and the conductive layer 212b and the insulating layer 210 that have the same or substantially the same top surface shape can be formed. By processing the insulating film that will become the insulating layer 110 and the insulating layer 210 and the conductive film that will become the conductive layer 112b and the conductive layer 212b in the same process, manufacturing costs can be reduced. Note that, although the top surface shapes of the conductive layer 112b and the insulating layer 110, and the conductive layer 212b and the insulating layer 210 are shown as rectangles in Figure 11A and other figures, these top surface shapes are not particularly limited. Note that parts of the conductive layer 112b, the insulating layer 110, the conductive layer 212b, and the insulating layer 210 can also be formed in different processes.

[0251] 11C , insulating layer 110 has an end 31 in contact with the upper surface of conductive layer 112a, and insulating layer 210 has an end 41 in contact with the upper surface of conductive layer 112a. Conductive layer 112a has a region where insulating layer 110 is provided, a region where insulating layer 210 is provided, and a region where neither insulating layer 110 nor insulating layer 210 is provided. Insulating layer 110 has a side surface 77 on conductive layer 112a, and insulating layer 210 has a side surface 87 on conductive layer 112a. The lower end of side surface 77 becomes end surface 31, and the lower end of side surface 87 becomes end surface 41.

[0252] The semiconductor layer 108 is provided over the conductive layers 112a and 112b and the insulating layer 110. For the semiconductor layer 108, the above description can be referred to.

[0253] A semiconductor layer 208 is provided over the conductive layer 112a, the conductive layer 212b, and the insulating layer 210. The semiconductor layer 208 has a region in contact with the top surface and side surface of the conductive layer 212b, a side surface (here, the side surface 87) of the insulating layer 210, and the top surface of the conductive layer 112a. The semiconductor layer 208 is connected to the conductive layer 112a and also connected to the conductive layer 212b. The semiconductor layer 208 has a shape that follows the shapes of the top surface and side surface of the conductive layer 212b, the side surface 87, and the top surface of the conductive layer 112a. The semiconductor layer 208 is provided across a region over the conductive layer 112a where the insulating layer 210 is provided and a region over the conductive layer 112a where neither the insulating layer 210 nor the insulating layer 110 is provided.

[0254] The semiconductor layer 208 has a fourth region in contact with the conductive layer 112a, a fifth region in contact with the side surface 87, and a sixth region in contact with the conductive layer 212b. The fourth region is in contact with the fifth region, and the fifth region is in contact with the sixth region. It can also be said that the fourth region is continuous with the fifth region, and the fifth region is continuous with the sixth region. In the transistor 200, the fourth region functions as one of a source region and a drain region, and the sixth region functions as the other of the source region and the drain region. A channel formation region is located in the fifth region.

[0255] 14A shows a cross-sectional view of the cut surface taken along dashed dotted line C1-C2 in FIG. 11C , and FIG. 14B shows a cross-sectional view of the cut surface taken along dashed dotted line D1-D2 in FIG. 14A is a cross-sectional view in a plane including the channel formation region of transistor 100 and the channel formation region of transistor 200, and FIG. 14B is a cross-sectional view in a plane including the other of the source and drain regions of transistor 100 and the other of the source and drain regions of transistor 200.

[0256] 12 , 14A, and 14B , the semiconductor layer 208 has an end 43 in contact with the upper surface of the conductive layer 212a, an end 47 in contact with the side surface 87, an end 49 in contact with the side surface of the conductive layer 212b, and an end 45 in contact with the upper surface of the conductive layer 212b. The end 43 is an end on the surface of the semiconductor layer 208 that is in contact with the upper surface of the conductive layer 112a. The end 47 is an end on the surface of the semiconductor layer 208 that is in contact with the side surface 87. The end 49 is an end on the surface of the semiconductor layer 208 that is in contact with the side surface of the conductive layer 212b. The end 45 is an end on the surface of the semiconductor layer 208 that is in contact with the upper surface of the conductive layer 212b.

[0257] 14A , the insulating layer 210 has, on a side surface 87, a region 80 where the semiconductor layer 208 is provided and a region 82 where the semiconductor layer 208 is not provided. In the region 80, the semiconductor layer 208 contacts the insulating layer 210. The insulating layer 106 has a region facing the side surface 87 with the semiconductor layer 208 interposed therebetween. On the other hand, in the region 82, the insulating layer 106 contacts the insulating layer 210.

[0258] In the semiconductor device 10A, the semiconductor layer 208 is provided in contact with the conductive layer 112a, the side surface 87, and the conductive layer 212b. The insulating layer 210, the side surface 87, the end 41, the end 43, the end 45, the end 47, the end 49, the region 80, and the region 82 in the semiconductor device 10A correspond to the insulating layer 110, the side surface 77a, the end 31a, the end 33a, the end 35a, the end 37a, the end 39a, the region 70a, and the region 72a in the semiconductor device 10 (see FIGS. 1B, 2B, 4A, and 4B).

[0259] [Configuration Example 1-3] FIG. 15A shows a top view of a semiconductor device 10B according to one embodiment of the present invention. FIG. 15B shows an equivalent circuit diagram of the semiconductor device 10B. FIG. 15C shows a cross-sectional view of the cut surface taken along dashed dotted line A1-A2 in FIG. 15A. FIG. 2A can be referred to for a cross-sectional view of the cut surface taken along dashed dotted line B1-B2 in FIG. 15A. FIG. 16 shows a cross-sectional view of the cut surface taken along dashed dotted line B3-B4.

[0260] The semiconductor device 10B includes a transistor 100, a transistor 200, an insulating layer 110, an insulating layer 210, and an insulating layer 109.

[0261] The transistor 100 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112a, and a conductive layer 112b. The above description of the transistor 100 can be referred to.

[0262] The transistor 200 includes a conductive layer 204, an insulating layer 106, a semiconductor layer 208, a conductive layer 212a, and a conductive layer 212b. In the transistor 200, the conductive layer 204 functions as a gate electrode, and the insulating layer 106 functions as a gate insulating layer. The conductive layer 212a functions as one of a source electrode and a drain electrode, and the conductive layer 212b functions as the other electrode.

[0263] The insulating layer 106 has an opening 149 that reaches the conductive layer 112a. The conductive layer 204 is provided to cover the opening 149. The conductive layer 204 is in contact with the conductive layer 112a in the opening 149 and is connected to the conductive layer 112a.

[0264] One of the source and the drain of the transistor 100 is connected to the gate of the transistor 200. Note that although the transistors 100 and 200 are both n-channel transistors in FIG. 15B, one embodiment of the present invention is not limited thereto. One or both of the transistors 100 and 200 can be p-channel transistors.

[0265] Although the structure in which one of the source and the drain of the transistor 100 is connected to the gate of the transistor 200 is shown, one embodiment of the present invention is not limited to this. The other of the source and the drain of the transistor 100 can be connected to the gate of the transistor 200. For example, an opening that reaches the conductive layer 112b is provided in the insulating layer 106, and the conductive layer 204 is provided to cover the opening. As a result, the conductive layer 204 can be in contact with and connected to the conductive layer 112b in the opening.

[0266] The configuration of the opening 149 and the conductive layer 204 shown here can also be applied to other configuration examples.

[0267] [Configuration Example 1-4] FIG. 17A shows a top view of a semiconductor device 10C according to one embodiment of the present invention. FIG. 17B shows an equivalent circuit diagram of the semiconductor device 10C. FIG. 17C shows a cross-sectional view of the cut surface taken along dashed dotted line A1-A2 in FIG. 17A. For a cross-sectional view of the cut surface taken along dashed dotted line B1-B2 in FIG. 17A, refer to FIG. 2A.

[0268] The semiconductor device 10C includes a transistor 100, a capacitor 150, an insulating layer 110, an insulating layer 210, and an insulating layer 109.

[0269] The transistor 100 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112a, and a conductive layer 112b. The above description of the transistor 100 can be referred to.

[0270] The capacitor 150 includes a conductive layer 112a, an insulating layer 106 over the conductive layer 112a, and a conductive layer 104C over the insulating layer 106. The conductive layer 112a, the insulating layer 106, and the conductive layer 104C overlap with each other. The conductive layer 112a and the conductive layer 104C function as a pair of electrodes of the capacitor 150, and the insulating layer 106 sandwiched between the pair of electrodes functions as a dielectric of the capacitor 150.

[0271] The conductive layer 104C can be formed in the same process as the conductive layer 104. The conductive layer 112a functions as one of a source electrode and a drain electrode of the transistor 100 and also functions as one of a pair of electrodes of the capacitor 150. When the conductive layer 112a is shared by the transistor 100 and the capacitor 150, the area occupied by the circuit can be reduced, and a small-sized semiconductor device can be provided.

[0272] One of the source and the drain of the transistor 100 is connected to one of a pair of electrodes of the capacitor 150. Note that although the transistor 100 is an n-channel transistor in FIG. 17B, one embodiment of the present invention is not limited thereto. The transistor 100 can also be a p-channel transistor.

[0273] An example of a configuration different from the semiconductor device 10C is shown in FIG. 18A. FIG. 18A is a top view of the semiconductor device 10D. FIG. 18B shows an equivalent circuit diagram of the semiconductor device 10D. FIG. 18C shows a cross-sectional view of the cut surface taken along dashed dotted line A1-A2 in FIG. 18A. For a cross-sectional view of the cut surface taken along dashed dotted line B1-B2 in FIG. 18A, refer to FIG. 2A.

[0274] The semiconductor device 10D includes a transistor 100, a capacitor 150A, an insulating layer 110, an insulating layer 210, and an insulating layer 109.

[0275] The transistor 100 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112a, and a conductive layer 112b. The above description of the transistor 100 can be referred to.

[0276] The capacitor 150A includes a conductive layer 112b, an insulating layer 106 over the conductive layer 112b, and a conductive layer 104C over the insulating layer 106. The conductive layer 112b, the insulating layer 106, and the conductive layer 104C overlap with each other in some regions. The conductive layer 112b and the conductive layer 104C function as a pair of electrodes of the capacitor 150A, and the insulating layer 106 sandwiched between the pair of electrodes functions as a dielectric of the capacitor 150A.

[0277] The conductive layer 112b functions as the other of the source electrode and drain electrode of the transistor 100 and also functions as one of a pair of electrodes of the capacitor 150A. By sharing the conductive layer 112b between the transistor 100 and the capacitor 150A, the area occupied by the circuit can be reduced, and a small-sized semiconductor device can be provided.

[0278] The other of the source and the drain of the transistor 100 is connected to one of a pair of electrodes of the capacitor 150A. Note that although the transistor 100 is an n-channel transistor in FIG. 18B, one embodiment of the present invention is not limited to this. The transistor 100 can also be a p-channel transistor.

[0279] 17A to 18C show the configuration in which the source or drain of the transistor 100 is connected to a capacitor, the connection between the transistor and the capacitor is not limited to this. Furthermore, the capacitor connected to the transistor 100 is not limited to the configuration of the capacitor 150 or the capacitor 150A.

[0280] 19A illustrates an equivalent circuit diagram of a semiconductor device 20 according to one embodiment of the present invention. The semiconductor device 20 includes transistors 100_1 to 100_p (p is an integer of 2 or greater). The transistors 100_1 to 100_p are connected in series and share a gate. The semiconductor device 20 can be regarded as a single transistor.

[0281] 19A illustrates the transistors 100_1 to 100_p as n-channel transistors, one embodiment of the present invention is not limited to this. The transistors 100_1 to 100_p can also be p-channel transistors.

[0282] A specific description will be given taking as an example the case where the number of transistors connected in series (p) is 4. FIG. 19B shows an equivalent circuit diagram of a semiconductor device 20 according to one embodiment of the present invention. FIG. 20A shows a top view of the semiconductor device 20. FIG. 20B shows a cross-sectional view of the cut surface taken along dashed dotted line A1-A2 in FIG. 20A. FIG. 21A shows a perspective view of the semiconductor device 20. FIG. 21B shows a perspective view in which the conductive layer 104 and the insulating layer 106 are omitted from FIG. 21A.

[0283] The semiconductor device 20 includes transistors 100_1 to 100_4. The structure of the transistor 100 or the transistor 200 described above can be applied to each of the transistors 100_1 to 100_4.

[0284] 20A and other figures show a configuration in which the transistors 100_1 to 100_4 are arranged in one row and four columns, the arrangement of the transistors is not particularly limited. For example, the transistors 100_1 to 100_4 may be arranged in two rows and two columns.

[0285] The transistor 100_1 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108_1, a conductive layer 112a, and a conductive layer 112b. The conductive layer 112a functions as one of a source electrode and a drain electrode of the transistor 100_1, and the conductive layer 112b functions as the other.

[0286] The transistor 100_2 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108_2, a conductive layer 112b, and a conductive layer 112c. The conductive layer 112c functions as one of a source electrode and a drain electrode of the transistor 100_2, and the conductive layer 112b functions as the other. The conductive layer 112b is shared by the transistors 100_1 and 100_2. That is, the other of the source electrode and the drain electrode of the transistor 100_1 is connected to the other of the source electrode and the drain electrode of the transistor 100_2.

[0287] The transistor 100_3 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108_3, a conductive layer 112c, and a conductive layer 112d. The conductive layer 112c functions as one of a source electrode and a drain electrode of the transistor 100_3, and the conductive layer 112d functions as the other. The conductive layer 112c is shared by the transistors 100_2 and 100_3. That is, one of the source electrode and the drain electrode of the transistor 100_2 is connected to one of the source electrode and the drain electrode of the transistor 100_3.

[0288] The transistor 100_4 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108_4, a conductive layer 112d, and a conductive layer 112e. The conductive layer 112d functions as one of a source electrode and a drain electrode of the transistor 100_4, and the conductive layer 112e functions as the other. The conductive layer 112d is shared by the transistors 100_3 and 100_4. That is, the other of the source electrode and the drain electrode of the transistor 100_3 is connected to the other of the source electrode and the drain electrode of the transistor 100_4.

[0289] The conductive layer 112a, the conductive layer 112c, and the conductive layer 112e are provided over the insulating layer 109. The conductive layer 112a, the conductive layer 112c, and the conductive layer 112e can be formed in the same process. For the conductive layer 112c and the conductive layer 112e, the description of the conductive layer 112a can be referred to.

[0290] The insulating layer 110 is provided over the conductive layer 112a and the conductive layer 112c, and the conductive layer 112b is provided over the insulating layer 110. The insulating layer 210 is provided over the conductive layer 112c and the conductive layer 112e, and the conductive layer 112d is provided over the insulating layer 210. The insulating layer 110 and the insulating layer 210 can be formed in the same process. The conductive layer 112b and the conductive layer 112d can also be formed in the same process. For the conductive layer 112d, refer to the description of the conductive layer 112b.

[0291] The insulating layer 110 has an end portion in contact with the top surface of the conductive layer 112a and an end portion in contact with the top surface of the conductive layer 112c. The insulating layer 210 has an end portion in contact with the top surface of the conductive layer 112c and an end portion in contact with the top surface of the conductive layer 112e.

[0292] The semiconductor layer 108_1 is provided over the conductive layer 112a, the conductive layer 112b, and the insulating layer 110. The semiconductor layer 108_1 has a region in contact with the top surface and side surfaces of the conductive layer 112b, the side surfaces of the insulating layer 110, and the top surface of the conductive layer 112a.

[0293] The semiconductor layer 108_2 is provided over the conductive layer 112c, the conductive layer 112b, and the insulating layer 110. The semiconductor layer 108_2 has a region in contact with the top surface and side surfaces of the conductive layer 112b, the side surfaces of the insulating layer 110, and the top surface of the conductive layer 112c.

[0294] The semiconductor layer 108_3 is provided over the conductive layer 112c, the conductive layer 112d, and the insulating layer 210. The semiconductor layer 108_3 has a region in contact with the top surface and side surfaces of the conductive layer 112d, the side surfaces of the insulating layer 210, and the top surface of the conductive layer 112c.

[0295] The semiconductor layer 108_4 is provided over the conductive layers 112e and 112d and the insulating layer 210. The semiconductor layer 108_4 has a region in contact with the top surface and side surfaces of the conductive layer 112d, the side surfaces of the insulating layer 210, and the top surface of the conductive layer 112e.

[0296] The semiconductor layers 108_1 to 108_4 can be formed in the same process. The description of the semiconductor layer 108 and the semiconductor layer 208 can be referred to for the semiconductor layers 108_1 to 108_4.

[0297] An insulating layer 106 is provided over the semiconductor layers 108_1 to 108_4. The insulating layer 106 functions as a gate insulating layer of the transistors 100_1 to 100_4. The insulating layer 106 has a region in contact with the top surface and side surface of the semiconductor layer 108_1, the top surface and side surface of the semiconductor layer 108_2, the top surface and side surface of the semiconductor layer 108_3, the top surface and side surface of the semiconductor layer 108_4, the top surface of the conductive layer 112a, the top surface of the conductive layer 112b, the top surface of the conductive layer 112c, the top surface of the conductive layer 112d, the top surface of the conductive layer 112e, the side surface of the insulating layer 110, and the side surface of the insulating layer 210.

[0298] A conductive layer 104 is provided over the insulating layer 106. The conductive layer 104 functions as a gate electrode of the transistors 100_1 to 100_4. The conductive layer 104 has a region facing a side surface of the insulating layer 110 with the insulating layer 106 and the semiconductor layer 108_1 interposed therebetween and a region facing a side surface of the insulating layer 110 with the insulating layer 106 and the semiconductor layer 108_2 interposed therebetween. The conductive layer 104 also has a region facing a side surface of the insulating layer 210 with the insulating layer 106 and the semiconductor layer 108_3 interposed therebetween and a region facing a side surface of the insulating layer 210 with the insulating layer 106 and the semiconductor layer 108_4 interposed therebetween.

[0299] When the semiconductor device 20 is regarded as a single transistor, the channel length of the transistor is the sum of the channel lengths of the transistors 100_1 to 100_4. For example, if the channel length of each of the transistors 100_1 to 100_4 is L100, the semiconductor device 20 can be regarded as a transistor having a channel length of "L100×4" (see FIG. 5A). The semiconductor device 20, which is composed of p transistors, can be regarded as a transistor having a channel length of "L100×p". Note that the semiconductor device 20 can be regarded as a transistor having a channel width of W100 (see FIG. 5B). By connecting multiple transistors in series, the channel length is increased, thereby improving saturation. Furthermore, the channel lengths can be varied by adjusting the number (p) of transistors connected in series. The number (p) of transistors connected in series can be determined so as to achieve a desired saturation.

[0300] In this specification and the like, a small change in current in the saturation region in the Id-Vd characteristics of a transistor may be expressed as "high saturation."

[0301] 20A and the like illustrate a structure in which the semiconductor layer is separated among the transistors 100_1 to 100_4 (here, the semiconductor layer is separated into the semiconductor layers 108_1 to 108_4), but one embodiment of the present invention is not limited to this. A semiconductor layer can be shared by a plurality of transistors.

[0302] 22A and 22B , the transistors 100_1 and 100_2 can share the semiconductor layer 108_1, and the transistors 100_3 and 100_4 can share the semiconductor layer 108_3. The semiconductor layer 108_1 has a region in contact with the top surface of the conductive layer 112a, the top surface and side surface of the conductive layer 112b, the top surface of the conductive layer 112c, and the side surface of the insulating layer 110. The semiconductor layer 108_3 has a region in contact with the top surface of the conductive layer 112c, the top surface and side surface of the conductive layer 112d, the top surface of the conductive layer 112e, and the side surface of the insulating layer 210. Sharing the semiconductor layer between the transistors 100_1 and 100_2 eliminates the need for a space between the semiconductor layer of the transistor 100_1 and the semiconductor layer of the transistor 100_2 (see the semiconductor layer 108_1 and the semiconductor layer 108_2 in FIGS. 20A and 20B ). The same applies to the transistors 100_3 and 100_4. Therefore, a semiconductor device occupying a small area can be provided.

[0303] 23A and 23B , the semiconductor layer 108_1 can be shared by the transistors 100_1 to 100_4. The semiconductor layer 108_1 has a region in contact with a top surface of the conductive layer 112a, a top surface and side surfaces of the conductive layer 112b, a top surface of the conductive layer 112c, a top surface and side surfaces of the conductive layer 112d, a top surface of the conductive layer 112e, a side surface of the insulating layer 110, and a side surface of the insulating layer 210. Sharing the semiconductor layer among the transistors 100_1 to 100_4 eliminates the need for spaces between the semiconductor layer of the transistor 100_1 and the semiconductor layer of the transistor 100_2, between the semiconductor layer of the transistor 100_2 and the semiconductor layer of the transistor 100_3, and between the semiconductor layer of the transistor 100_3 and the semiconductor layer of the transistor 100_4 (see the semiconductor layers 108_1 to 108_4 in FIGS. 20A and 20B ). Therefore, the semiconductor device can occupy a small area.

[0304] Note that the configuration of the semiconductor device 20 can be applied to other configuration examples. For example, in the semiconductor devices 10 to 10D described above, the semiconductor device 20 can be applied to one or both of the transistor 100 and the transistor 200.

[0305] 24A illustrates an equivalent circuit diagram of a semiconductor device 30 according to one embodiment of the present invention. The semiconductor device 30 includes transistors 100_1 to 100_q (q is an integer of 2 or greater). The transistors 100_1 to 100_q are connected in parallel and share a gate. The semiconductor device 30 can be regarded as a single transistor.

[0306] 24A illustrates the transistors 100_1 to 100_q as n-channel transistors, one embodiment of the present invention is not limited to this. The transistors 100_1 to 100_p can also be q-channel transistors.

[0307] A specific description will be given taking as an example the case where the number (q) of transistors connected in parallel is 4. FIG. 24B shows an equivalent circuit diagram of a semiconductor device 30 which is one embodiment of the present invention. FIG. 25A shows a top view of the semiconductor device 30. FIG. 25B shows a cross-sectional view of the cut surface taken along dashed dotted line A1-A2 in FIG. 25A. FIG. 26A shows a perspective view of the semiconductor device 30. FIG. 26B shows a perspective view in which the conductive layer 104 and the insulating layer 106 are omitted from FIG. 26A.

[0308] The semiconductor device 30 includes transistors 100_1 to 100_4. The structure of the transistor 100 or the transistor 200 described above can be applied to each of the transistors 100_1 to 100_4.

[0309] 25A and other figures show a configuration in which the transistors 100_1 to 100_4 are arranged in one row and four columns, the arrangement of the transistors is not particularly limited. For example, the transistors 100_1 to 100_4 may be arranged in two rows and two columns.

[0310] The transistors 100_1 to 100_4 each include a conductive layer 104, an insulating layer 106, a conductive layer 112a, and a conductive layer 112b. In each of the transistors 100_1 to 100_4, the conductive layer 112a functions as one of a source electrode and a drain electrode, and the conductive layer 112b functions as the other. The transistor 100_1 includes a semiconductor layer 108_1, the transistor 100_2 includes a semiconductor layer 108_2, the transistor 100_3 includes a semiconductor layer 108_3, and the transistor 100_4 includes a semiconductor layer 108_4.

[0311] The conductive layer 112a is shared by the transistors 100_1 to 100_4. That is, one of the source electrode and one of the drain electrode of the transistors 100_1 to 100_4 are connected to each other. The conductive layer 112b is shared by the transistors 100_1 to 100_4. That is, the other of the source electrode and one of the drain electrode of the transistors 100_1 to 100_4 are connected to each other.

[0312] A conductive layer 112a is provided over the insulating layer 109. An insulating layer 110 is provided over the conductive layer 112a, and a conductive layer 112b is provided over the insulating layer 110.

[0313] Semiconductor layers 108_1 to 108_4 are provided over the conductive layer 112a, the conductive layer 112b, and the insulating layer 110. The semiconductor layers 108_1 to 108_4 each have a region in contact with the top surface and side surfaces of the conductive layer 112b, the side surfaces of the insulating layer 110, and the top surface of the conductive layer 112a. Note that the semiconductor layers 108_1 to 108_4 may be collectively referred to as semiconductor layers 108.

[0314] An insulating layer 106 is provided over the semiconductor layers 108_1 to 108_4. The insulating layer 106 functions as a gate insulating layer for the transistors 100_1 to 100_4. The insulating layer 106 has a region in contact with the top surface and side surface of the semiconductor layer 108_1, the top surface and side surface of the semiconductor layer 108_2, the top surface and side surface of the semiconductor layer 108_3, the top surface and side surface of the semiconductor layer 108_4, the top surface of the conductive layer 112a, the top surface of the conductive layer 112b, and the side surface of the insulating layer 110.

[0315] A conductive layer 104 is provided over the insulating layer 106. The conductive layer 104 functions as a gate electrode of the transistors 100_1 to 100_4. The conductive layer 104 has a region facing a side surface of the insulating layer 110 with the insulating layer 106 and the semiconductor layer 108_1 interposed therebetween. The conductive layer 104 has a region facing a side surface of the insulating layer 110 with the insulating layer 106 and the semiconductor layer 108_2 interposed therebetween. The conductive layer 104 also has a region facing a side surface of the insulating layer 110 with the insulating layer 106 and the semiconductor layer 108_3 interposed therebetween. The conductive layer 104 has a region facing a side surface of the insulating layer 110 with the insulating layer 106 and the semiconductor layer 108_4 interposed therebetween.

[0316] When the semiconductor device 30 is regarded as a single transistor, the channel width of the transistor is the sum of the channel widths of the transistors 100_1 to 100_4. For example, if the channel length of each of the transistors 100_1 to 100_4 is represented by a channel width W100, the semiconductor device 30 can be regarded as a transistor having a channel width of "W100 x 4" (see FIG. 5B). The semiconductor device 30, which is configured with q transistors, can be regarded as a transistor having a channel width of "W100 x q". Note that the semiconductor device 30 can be regarded as a transistor having a channel length L100 (see FIG. 5A). Connecting multiple transistors in parallel increases the channel width, thereby increasing the on-state current. Furthermore, the channel width can be varied by adjusting the number (q) of transistors connected in parallel. The number (q) of transistors connected in parallel can be determined so as to achieve a desired on-state current.

[0317] 25A and the like illustrate a structure in which the semiconductor layer is separated for the transistors 100_1 to 100_4 (here, the semiconductor layer is separated into the semiconductor layers 108_1 to 108_4). By separating the semiconductor layer for each transistor, the area of ​​each semiconductor layer can be reduced. This can prevent the semiconductor layer from generating heat due to a current flowing through the transistor. Therefore, a highly reliable semiconductor device can be obtained.

[0318] Note that the configuration of the semiconductor device 30 can be applied to other configuration examples. For example, in the semiconductor devices 10 to 10D described above, the semiconductor device 30 can be applied to one or both of the transistor 100 and the transistor 200.

[0319] The semiconductor device 20 can be applied to each transistor included in the semiconductor device 30. That is, a configuration can be achieved in which a group of series-connected transistors are further connected in parallel (hereinafter also referred to as series-parallel connection).

[0320] <Configuration Example 2> FIG. 27A shows a top view of a semiconductor device 40 according to one embodiment of the present invention. FIG. 27B shows a cross-sectional view of the cut surface taken along dashed dotted line B1-B2 in FIG. 27A , and FIG. 27C shows a cross-sectional view of the cut surface taken along dashed dotted line B3-B4 in FIG. 1C can be referred to for the cross-sectional view of the cut surface taken along dashed dotted line A1-A2. FIG. 1B can be referred to for an equivalent circuit diagram of the semiconductor device 40.

[0321] Fig. 28A shows a perspective view of the semiconductor device 40. Fig. 28B shows a perspective view in which the conductive layer 104, the conductive layer 204, and the insulating layer 106 are omitted from Fig. 28A.

[0322] The semiconductor device 40 includes a transistor 100, a transistor 200, an insulating layer 110, and an insulating layer 109. The semiconductor device 40 differs from the semiconductor device 10 shown in FIG. 1A and the like mainly in that the insulating layer 106 is in contact with the top surface of the insulating layer 110.

[0323] 27A and other figures show a configuration in which the top surface shape of the conductive layer 112b does not match the top surface shape of the insulating layer 110. Some ends of the conductive layer 112b contact the top surface of the insulating layer 110. The insulating layer 110 has a region that protrudes beyond the conductive layer 112b. When viewed from above, it is preferable that the insulating layer 110 encompasses the conductive layer 112b. As shown in FIGS. 27B and 27C , the insulating layer 110 has a region on its top surface where the conductive layer 112b is provided and a region where the conductive layer 112b is not provided. In the region where the conductive layer 112b is not provided, the insulating layer 106 contacts the top surface of the insulating layer 110.

[0324] For example, an insulating film that will become the insulating layer 110 is formed, an island-shaped conductive layer that will become the conductive layer 112b is formed on the insulating film, and a mask layer (e.g., a resist mask) is formed on the conductive layer and the insulating film. Then, the conductive layer and the insulating film are processed using the mask layer as a mask to form the conductive layer 112b and the insulating layer 110. As shown in FIG. 1C , it is preferable that there is no step between the side surface of the conductive layer 112b facing the semiconductor layer 108 and the side surface 77, and that the two surfaces are flush with each other. Similarly, it is preferable that there is no step between the side surface of the conductive layer 112b facing the semiconductor layer 208 and the side surface 77a, and that the side surface of the conductive layer 112b facing the semiconductor layer 108 and the side surface 77a are flat. It is also possible to configure the side surface of the conductive layer 112b facing the semiconductor layer 108 to be discontinuous with the side surface 77, and the side surface of the conductive layer 112b facing the semiconductor layer 208 to be discontinuous with the side surface 77a.

[0325] By forming the insulating layer 110 using a mask layer different from that of the conductive layer 112b, the degree of freedom in the layout of the insulating layer 110 can be increased. For example, by increasing the area where the insulating layer 110 is provided, the amount of oxygen supplied from the insulating layer 110 (e.g., the insulating layer 110b) to the semiconductor layer 108 and the semiconductor layer 208 can be increased. As a result, oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced.

[0326] 27A and the like illustrate a structure in which two transistors (here, the transistor 100 and the transistor 200) are provided in the insulating layer 110; however, one embodiment of the present invention is not limited to this. Three or more transistors can be provided in the insulating layer 110. For example, a plurality of transistors each having a semiconductor layer in contact with the side surface 77 can be provided. Similarly, a plurality of transistors each having a semiconductor layer in contact with the side surface 77a can be provided. Alternatively, a transistor can be provided which has a semiconductor layer in contact with a side surface of the insulating layer 110 that is different from both the side surface 77 and the side surface 77a.

[0327] Note that the structures of the conductive layer 112b and the insulating layer 110 shown here can be applied to other structure examples.

[0328] <Configuration Example 3> FIG. 29A shows a top view of a semiconductor device 40A according to one embodiment of the present invention. FIG. 29B shows a cross-sectional view of the cut surface taken along dashed dotted line A1-A2 in FIG. 29A , and FIG. 29C shows a cross-sectional view of the cut surface taken along dashed dotted line B3-B4 in FIG. 27B can be referred to for a cross-sectional view of the cut surface taken along dashed dotted line B1-B2. FIG. 11B can be referred to for an equivalent circuit diagram of the semiconductor device 40A.

[0329] 30A and 30B are perspective views of the semiconductor device 40A, in which the conductive layer 104, the conductive layer 204, and the insulating layer 106 shown in FIG.

[0330] The semiconductor device 40A includes a transistor 100, a transistor 200, an insulating layer 110, and an insulating layer 109. The semiconductor device 40A differs mainly from the semiconductor device 10A shown in FIG. 11A and the like in that the insulating layer 110 has a groove (slit).

[0331] The insulating layer 110 has a slit 137 that reaches the conductive layer 112a and the insulating layer 109. As shown in FIG. 29B , the insulating layer 110 is divided by the slit 137, and the insulating layer 110 has a pair of side surfaces (side surface 77 and side surface 77a) that face each other across the slit 137. The side surface 77 includes a region located on the conductive layer 112a and a region located on the insulating layer 109. Similarly, the side surface 77a includes a region located on the conductive layer 112a and a region located on the insulating layer 109. The insulating layer 110 has an end portion 31 and an end portion 31a that contact the upper surface of the conductive layer 112a. On the conductive layer 112a, the lower end of the side surface 77 is the end portion 31, and the lower end of the side surface 77a is the end portion 31a. A conductive layer 112b and a conductive layer 212b are provided on the insulating layer 110.

[0332] The semiconductor layer 108 and the semiconductor layer 208 are provided so as to cover part of the slit 137. The semiconductor layer 108 has regions in contact with the side surface 77, the top and side surfaces of the conductive layer 112b, and the top surface of the conductive layer 112a. The semiconductor layer 208 has regions in contact with the side surface 77a, the top and side surfaces of the conductive layer 212b, and the top surface of the conductive layer 112a.

[0333] The insulating layer 106 is provided over the semiconductor layer 108 and the semiconductor layer 208, and the conductive layer 104 and the conductive layer 204 are provided over the insulating layer 106. The conductive layer 104 has a region facing the side surface 77 with the insulating layer 106 and the semiconductor layer 108 interposed therebetween. The conductive layer 204 has a region facing the side surface 77a with the insulating layer 106 and the semiconductor layer 208 interposed therebetween.

[0334] 29A and the like illustrate a structure in which two transistors (here, the transistor 100 and the transistor 200) are provided in the insulating layer 110; however, one embodiment of the present invention is not limited to this. Three or more transistors can be provided in the insulating layer 110. For example, a plurality of transistors each having a semiconductor layer in contact with the side surface 77 can be provided. Similarly, a plurality of transistors each having a semiconductor layer in contact with the side surface 77a can be provided. Alternatively, a transistor can be provided which has a semiconductor layer in contact with a side surface of the insulating layer 110 that is different from both the side surface 77 and the side surface 77a.

[0335] 29A and other drawings show the slit 137 extending in one direction, but this is not a limitation of one aspect of the present invention. The shape of the top surface of the slit 137 is not particularly limited.

[0336] Although Figure 29A and other figures illustrate a structure in which the insulating layer 110 is divided by the slit 137, one embodiment of the present invention is not limited to this. An example structure different from that of Figure 29A is shown in Figure 31A. Figure 31A is a top view of a semiconductor device 40A. For a cross-sectional view of the cut surface taken along dashed dotted line A1-A2 in Figure 31A, see Figure 29B. For a cross-sectional view of the cut surface taken along dashed dotted line B1-B2, see Figure 27B. For a cross-sectional view of the cut surface taken along dashed dotted line B3-B4, see Figure 29C. For an equivalent circuit diagram of the semiconductor device 40A, see Figure 11B. Figure 31B shows a perspective view of the semiconductor device 40A in which the conductive layer 104, the conductive layer 204, and the insulating layer 106 are omitted. As shown in Figures 31A and 31B, a structure in which the insulating layer 110 is not divided by the slit 137 is possible. The semiconductor layer 108 and the semiconductor layer 208 can be provided on the side surfaces (here, the side surfaces 77 and 77 a ) of the insulating layer 110 formed by the slits 137 .

[0337] The configuration of the insulating layer 110 and the slits 137 shown here can also be applied to other configuration examples.

[0338] <Configuration Example 4> FIG. 32A shows a top view of a semiconductor device 40B according to one embodiment of the present invention. FIG. 32B shows a cross-sectional view of the section taken along dashed dotted line A1-A2 in FIG. 32A , FIG. 33A shows a cross-sectional view of the section taken along dashed dotted line B1-B2, and FIG. 33B shows a cross-sectional view of the section taken along dashed dotted line B3-B4. FIG. 1B can be referred to for an equivalent circuit diagram of the semiconductor device 40B. FIG. 34A shows a perspective view of the semiconductor device 40B. FIG. 34B shows a perspective view in which the conductive layer 104, the conductive layer 204, and the insulating layer 106 are omitted from FIG. 34A .

[0339] The semiconductor device 40B includes a transistor 100A, a transistor 200A, an insulating layer 110, and an insulating layer 109. The semiconductor device 40B differs from the semiconductor device 10 shown in FIG. 1C and the like mainly in that the conductive layer 112b and the insulating layer 110 have openings.

[0340] The conductive layer 112b and the insulating layer 110 have an opening 141 that reaches the conductive layer 112a and an opening 241 that reaches the conductive layer 212a. The opening 141 includes an opening in the conductive layer 112b and an opening in the insulating layer 110. It can also be said that the side surface of the conductive layer 112b, the side surface 77a of the insulating layer 110, and the top surface of the conductive layer 112a are exposed in the opening 141. Similarly, the opening 241 includes an opening in the conductive layer 112b and an opening in the insulating layer 110. It can also be said that the side surface of the conductive layer 112b, the side surface 77a, and the top surface of the conductive layer 212a are exposed in the opening 241.

[0341] The semiconductor layer 108 is provided so as to cover a part of the opening 141. The semiconductor layer 108 is provided so as to cross the opening 141. The semiconductor layer 108 has a region in contact with the top surface and side surface of the conductive layer 112b, the side surface 77, and the top surface of the conductive layer 112a.

[0342] The semiconductor layer 208 is provided so as to cover a part of the opening 241. The semiconductor layer 208 is provided so as to cross the opening 241. The semiconductor layer 208 has regions in contact with the top surface and side surface of the conductive layer 112b, the side surface 77a, and the top surface of the conductive layer 212a.

[0343] An insulating layer 106 is provided over the semiconductor layer 108 and the semiconductor layer 208. A conductive layer 104 and a conductive layer 204 are provided over the insulating layer 106. The semiconductor layer 108, the insulating layer 106, and the conductive layer 104 each have a region located within the opening 141. The semiconductor layer 208, the insulating layer 106, and the conductive layer 204 each have a region located within the opening 241.

[0344] The semiconductor layer 108 has a region 74 and a region 74a in contact with the side surface 77. The region 74 and the region 74a each function as a channel formation region of the transistor 100A. The conductive layer 104 has a region facing the side surface 77 with the region 74 and the insulating layer 106 interposed therebetween, and also has a region facing the side surface 77 with the region 74a and the insulating layer 106 interposed therebetween.

[0345] The semiconductor layer 208 has a region 84 and a region 84a in contact with the side surface 77a. The region 84 and the region 84a each function as a channel formation region of the transistor 200A. The conductive layer 204 has a region facing the side surface 77a with the region 84 and the insulating layer 106 interposed therebetween, and a region facing the side surface 77a with the region 84a and the insulating layer 106 interposed therebetween.

[0346] The channel lengths and channel widths of the transistor 100A and the transistor 200A will be described with reference to FIGS. 35A and 35B.

[0347] 35B, the channel length L100 of the transistor 100A and the channel length L200 of the transistor 200A are indicated by dashed double-headed arrows. The channel length L100 can be explained by referring to the above description, and therefore a detailed explanation will be omitted. The channel length L200 can be explained by referring to the description of the channel length L100.

[0348] 35A , in the transistor 100A, a width W1 of the region where the semiconductor layer 108 and the conductive layer 104 overlap in the region 74 and a width W2 of the region where the semiconductor layer 108 and the conductive layer 104 overlap in the region 74a are indicated by double-dot-dashed arrows in a direction perpendicular to the channel length direction. The channel width W100 of the transistor 100A is the sum of the width W1 and the width W2.

[0349] 35A , in the transistor 200A, the width W3 of the region where the semiconductor layer 208 and the conductive layer 204 overlap in the region 84 and the width W4 of the region where the semiconductor layer 208 and the conductive layer 204 overlap in the direction perpendicular to the channel length direction are indicated by double-arrowed dashed lines. The channel width W200 of the transistor 200A is the sum of the width W3 and the width W4. Note that although the widths W1 to W4 are the same in FIG. 35A and other drawings, one embodiment of the present invention is not limited to this. One or more of the widths W1 to W4 may be different.

[0350] 35A and other figures show a configuration in which the top surface shapes of the openings 141 and 241 are rectangular with rounded corners, but one embodiment of the present invention is not limited thereto. The top surface shapes of the openings 141 and 241 are not limited thereto and may be, for example, a circle, an ellipse, a triangle, a square (including a rectangle, a diamond, and a square), a polygon such as a pentagon, or a shape with rounded corners of these polygons. The polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles equal to or less than 180 degrees). By forming the top surface shapes of the openings 141 and 241 as circular, the processing accuracy when forming the openings 141 and 241 can be improved, and the openings 141 and 241 can be formed with a fine size. In this specification and other documents, a circle is not limited to a perfect circle. 35A and the like show a structure in which the top surface shape of the opening 141 is the same as the top surface shape of the opening 241, but this is not a limitation of one embodiment of the present invention. The top surface shape of the opening 141 may be different from the top surface shape of the opening 241.

[0351] The opening 141 is provided only in the semiconductor layer 108 and a region near it, the opening 241 is provided only in the semiconductor layer 208 and a region near it, and the insulating layer 110 is provided in the remaining region. Therefore, the area of ​​the region where the insulating layer 110 is provided can be increased, and unevenness caused by the region where the insulating layer 110 is provided and the region where it is not provided can be reduced. This improves the coverage of layers provided over the transistor 100A, the transistor 200A, and the insulating layer 110, and suppresses defects such as discontinuities or voids in the layers.

[0352] The configurations of the openings 141 and 241 shown here can also be applied to other configuration examples.

[0353] <Configuration Example 5> A top view of a semiconductor device 42 according to one embodiment of the present invention is shown in FIG. 36A . FIG. 36B shows a cross-sectional view of the section taken along dashed dotted line A1-A2 in FIG. 36A , and FIG. 37A shows a cross-sectional view of the section taken along dashed dotted line A3-A4 in FIG. 37B shows a cross-sectional view of the section taken along dashed dotted line B1-B2, and FIG. 37C shows a cross-sectional view of the section taken along dashed dotted line B3-B4. FIG. 38A shows a cross-sectional view of the section taken along dashed dotted line B5-B6, and FIG. 38B shows a cross-sectional view of the section taken along dashed dotted line B7-B8.

[0354] The semiconductor device 42 includes a transistor 100, a transistor 107, a transistor 200, a transistor 207, an insulating layer 110, and an insulating layer 109. The semiconductor device 42 is different from the semiconductor device 40A shown in FIG. 29A and the like mainly in that the semiconductor device 42 includes a transistor 107 and a transistor 207. The semiconductor layers of the transistors 100 and 107 are in contact with the side surfaces 77a. The semiconductor layers of the transistors 200 and 207 are in contact with the side surfaces 77a.

[0355] The transistor 100 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112a, and a conductive layer 112b. The transistor 200 includes a conductive layer 204, an insulating layer 106, a semiconductor layer 208, a conductive layer 212a, and a conductive layer 212b. The above descriptions of the transistors 100 and 200 can be referred to.

[0356] The transistor 107 includes a conductive layer 104A, an insulating layer 106, a semiconductor layer 108A, a conductive layer 112aA, and a conductive layer 112bA. In the transistor 107, the conductive layer 104A functions as a gate electrode, and the insulating layer 106 functions as a gate insulating layer. The conductive layer 112aA functions as one of a source electrode and a drain electrode, and the conductive layer 112bA functions as the other. The transistor 107 has a structure similar to that of the transistor 100. For the conductive layer 104A, the insulating layer 106, the semiconductor layer 108A, the conductive layer 112aA, and the conductive layer 112bA, the descriptions of the conductive layer 104, the insulating layer 106, the semiconductor layer 108, the conductive layer 112a, and the conductive layer 112b can be referred to.

[0357] The transistor 207 includes a conductive layer 204A, an insulating layer 106, a semiconductor layer 208A, a conductive layer 212aA, and a conductive layer 212bA. In the transistor 207, the conductive layer 204A functions as a gate electrode, and the insulating layer 106 functions as a gate insulating layer. The conductive layer 212aA functions as one of a source electrode and a drain electrode, and the conductive layer 212bA functions as the other. The transistor 207 has a structure similar to that of the transistor 200. For the conductive layer 204A, the insulating layer 106, the semiconductor layer 208A, the conductive layer 212aA, and the conductive layer 212bA, the descriptions of the conductive layer 204, the insulating layer 106, the semiconductor layer 208, the conductive layer 212a, and the conductive layer 212b can be referred to.

[0358] FIG. 39 is a perspective view of the semiconductor device 42. FIG. 39 selectively illustrates the semiconductor layers, source and drain electrodes, insulating layer 110, insulating layer 109, and substrate 102 of the transistor 100, transistor 107, transistor 200, and transistor 207. The insulating layer 110 is located over the conductive layer 112a, the conductive layer 112aA, the conductive layer 212a, and the conductive layer 212aA, and has a slit 137 reaching these conductive layers. The side surface 77 is in contact with the top surface of the conductive layer 112a and the top surface of the conductive layer 112aA. The side surface 77a is in contact with the top surface of the conductive layer 212a and the top surface of the conductive layer 212aA. The semiconductor layer 108A is provided in contact with the conductive layer 112aA, the side surface 77, and the conductive layer 112bA. The semiconductor layer 208A is provided in contact with the conductive layer 212aA, the side surface 77a, and the conductive layer 212bA.

[0359] By providing multiple transistors (here, the transistors 100 and 107) having semiconductor layers in contact with the side surface 77 and multiple transistors (here, the transistors 200 and 207) having semiconductor layers in contact with the side surface 77a, the number of transistors per unit area can be increased, thereby making it possible to provide a semiconductor device with a small occupation area.

[0360] 36 and other figures show a configuration in which, in a top view, the positions of the semiconductor layer 108 and the semiconductor layer 208 are aligned, and the positions of the semiconductor layer 108A and the semiconductor layer 208A are aligned in a direction perpendicular to the direction in which the slit 137 extends. It is preferable that at least a portion of the region in contact with the side surface 77 of the semiconductor layer 108 faces the region in contact with the side surface 77a of the semiconductor layer 208 in a top view. It is preferable that at least a portion of the region in contact with the side surface 77 of the semiconductor layer 10A8 faces the region in contact with the side surface 77a of the semiconductor layer 208A in a top view. The direction in which the slit 137 extends can also be referred to as the direction in which the side surface 77 extends or the direction in which the side surface 77a extends.

[0361] One embodiment of the present invention is not limited thereto, and the position of the semiconductor layer 108 can be shifted from the position of the semiconductor layer 208. Furthermore, the position of the semiconductor layer 108A can be shifted from the position of the semiconductor layer 208A.

[0362] 36 and the like illustrate a structure in which the channel widths of the transistor 100, the transistor 107, the transistor 200, and the transistor 207 are the same, but one embodiment of the present invention is not limited to this. The channel widths of these transistors can be made different from each other.

[0363] An example of a configuration different from semiconductor device 42 is shown in Fig. 40. Fig. 40 is a top view of semiconductor device 42A. For a cross-sectional view of the cut surface taken along dashed dotted line A1-A2 shown in semiconductor device 42A, see Fig. 36B, and for a cross-sectional view of the cut surface taken along dashed dotted line A3-A4, see Fig. 37A. For cross-sectional views of the cut surfaces taken along dashed dotted line B1-B2, dashed dotted line B3-B4, dashed dotted line B5-B6, and dashed dotted line B7-B8, see Figs. 37B to 38B.

[0364] 41 is a perspective view of the semiconductor device 42A. FIG. 41 excerpts the semiconductor layers, source and drain electrodes, insulating layer 110, insulating layer 109, and substrate 102 of the transistor 100, the transistor 107, the transistor 200, and the transistor 207.

[0365] As shown in FIG. 40 , in a top view, the positions of the semiconductor layer 108 and the semiconductor layer 208 may not be aligned in a direction perpendicular to the direction in which the side surface 77 extends, and the positions of the semiconductor layer 108A and the semiconductor layer 208A may not be aligned. FIG. 40 also shows a configuration in which the position of the semiconductor layer 208 is not aligned with the position of the semiconductor layer 108A. In other words, the positions of the semiconductor layer 108 and the semiconductor layer 208 are misaligned in a direction perpendicular to the direction in which the side surface 77 extends, and the positions of the semiconductor layer 108A and the semiconductor layer 208A are misaligned. It is also possible to say that the position of the semiconductor layer 208 is misaligned with the position of the semiconductor layer 108A. It is preferable that the region of the semiconductor layer 108 that contacts the side surface 77a does not face the region of the semiconductor layer 208 that contacts the side surface 77a in a top view. It is preferable that the region of semiconductor layer 10A8 that contacts side surface 77 does not face the region of semiconductor layer 208A that contacts side surface 77a in top view. This configuration allows the distance between the semiconductor layers to be increased, which may prevent processing defects from occurring when forming the semiconductor layers (here, semiconductor layer 108, semiconductor layer 108A, semiconductor layer 208, and semiconductor layer 208A). Similarly, processing defects may also be prevented when forming a conductive layer by processing the same film.

[0366] An example configuration different from semiconductor device 42A is shown in FIG. 42 . FIG. 42 is a top view of semiconductor device 42B. For a cross-sectional view of the cut surface taken along dashed dotted line A1-A2 shown in semiconductor device 42B, refer to FIG. 36B , and for a cross-sectional view of the cut surface taken along dashed dotted line A3-A4, refer to FIG. 37A . Note that to avoid cluttering the drawing, dashed dotted line B1-B2, dashed dotted line B3-B4, dashed dotted line B5-B6, and dashed dotted line B7-B8 are omitted from FIG. 42 , but for cross-sectional views of these cut surfaces, refer to FIGS. 37B to 38B .

[0367] 42 , the transistor 100 can be configured to have a region adjacent to the transistor 200 in the direction in which the side surface 77 extends, as viewed from above. For example, the semiconductor layer 108 has a region facing the semiconductor layer 208 in the direction in which the side surface 77 extends, as viewed from above. The conductive layer 112a has a region facing the conductive layer 212a in the direction in which the side surface 77 extends, as viewed from above. Similarly, the transistor 200 has a region adjacent to the transistor 107, and the transistor 107 has a region adjacent to the transistor 207. This allows the width of the slit 137 to be reduced, thereby increasing the number of transistors per unit area. This allows for a semiconductor device with a small occupation area.

[0368] 36A to 42 do not show connections between transistors, but the transistors can also be connected. The above description can be referred to for the connections between transistors. Furthermore, the number of transistors included in the semiconductor device of one embodiment of the present invention is not particularly limited.

[0369] The transistor arrangement shown here can also be applied to other configuration examples.

[0370] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0371] 43A to 46D , a method for manufacturing a semiconductor device according to one embodiment of the present invention will be described. Note that with regard to materials and formation methods of elements, descriptions of parts similar to those described in Embodiment 1 may be omitted.

[0372] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting semiconductor devices can be formed using methods such as sputtering, chemical vapor deposition (CVD), vacuum evaporation, pulsed laser deposition (PLD), and atomic layer deposition (ALD). CVD methods include plasma enhanced chemical vapor deposition (PECVD) and thermal CVD. One type of thermal CVD method is metal organic chemical vapor deposition (MOCVD).

[0373] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed by wet film formation methods such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.

[0374] When processing a thin film that constitutes a semiconductor device, a lithography method or the like can be used. Alternatively, the thin film can be processed by a nanoimprint method, a sandblasting method, a lift-off method, or the like. Furthermore, an island-shaped thin film can be directly formed by a film formation method using a shielding mask such as a metal mask.

[0375] There are two typical lithography methods: one is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0376] In lithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other examples include ultraviolet light, KrF laser light, and ArF laser light. Exposure can also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure. An electron beam can also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0377] The thin film can be etched by one or more of dry etching, wet etching, and sandblasting.

[0378] 43A to 45B show cross-sectional views taken along dashed line A1-A2 in FIG.

[0379] First, the insulating layer 109 is formed over the substrate 102. The insulating layer 109 can be formed by a sputtering method or a PECVD method.

[0380] Next, a conductive film to be the conductive layer 112a and the conductive layer 212a is formed over the insulating layer 109, and then processed to form the conductive layer 112a and the conductive layer 212a (FIG. 43A). The conductive film can be preferably formed by sputtering.

[0381] Subsequently, an insulating film 110af that will become the insulating layer 110a and an insulating film 110bf that will become the insulating layer 110b are formed on the conductive layer 112a and the conductive layer 212a (FIG. 43B).

[0382] The insulating films 110af and 110bf can be preferably formed by sputtering or PECVD. After forming the insulating film 110af, it is preferable to form the insulating film 110bf without exposing the surface of the insulating film 110af to the atmosphere. This can prevent impurities from the atmosphere from adhering to the surface of the insulating film 110af. Examples of such impurities include water and organic substances. For example, after forming the insulating film 110af, it is preferable to form the insulating film 110bf consecutively using the same apparatus.

[0383] The substrate temperature during deposition of the insulating film 110af and the insulating film 110bf is preferably 180° C. or higher and 450° C. or lower, more preferably 200° C. or higher and 450° C. or lower, further preferably 250° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 400° C. or lower, further preferably 350° C. or higher and 400° C. or lower. By setting the substrate temperature within the above-described range during deposition of the insulating film 110af and the insulating film 110bf, the amount of impurities (e.g., water and hydrogen) released from the insulating film itself can be reduced, and diffusion of the impurities into the semiconductor layer 108 and the semiconductor layer 208 can be suppressed. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be obtained.

[0384] Since the insulating films 110af and 110bf are formed before the semiconductor layers 108 and 208, there is no need to worry about oxygen being desorbed from the semiconductor layers 108 and 208 due to the heat applied during the formation of the insulating films 110af and 110bf.

[0385] After the insulating films 110af and 110bf are formed, heat treatment is preferably performed. By performing the heat treatment, impurities (for example, water and hydrogen) can be removed from the insulating films 110af and the insulating films 110bf and from their surfaces.

[0386] After the insulating film 110bf is formed, oxygen is preferably supplied to the insulating film 110bf. By supplying oxygen to the insulating film 110bf (later the insulating layer 110b), oxygen can be later supplied from the insulating layer 110b to the semiconductor layer 108 and the semiconductor layer 208, and oxygen vacancies and V in the semiconductor layer 108 and the semiconductor layer 208 can be reduced. Ｏ H can be reduced. Therefore, a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0387] As a method for supplying oxygen, for example, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used. For the plasma treatment, an apparatus that converts oxygen gas into plasma by high frequency power can be suitably used. Examples of apparatus that convert gas into plasma by high frequency power include a PECVD apparatus, a plasma etching apparatus, and a plasma ashing apparatus. The plasma treatment is preferably carried out in an atmosphere containing oxygen. For example, oxygen, nitrous oxide (N ２ O), nitrogen dioxide (NO ２ It is preferable to perform the plasma treatment in an atmosphere containing one or more of carbon monoxide, carbon dioxide, and / or arsenic. The amount of oxygen supplied can be adjusted by, for example, the power and treatment time in the plasma treatment. Fig. 43C schematically shows with arrows how oxygen is supplied to the insulating film 110bf.

[0388] After the insulating film 110bf is formed, nitrogen is preferably supplied to the insulating film 110bf. The nitrogen supply method can be referred to the description of the oxygen supply method described above. As a nitrogen supply method, plasma treatment in an atmosphere containing nitrogen can be suitably used. For example, nitrogen, dinitrogen monoxide (N ２ O), and nitrogen dioxide (NO ２ The amount of nitrogen supplied can be adjusted by, for example, the power and processing time in the plasma processing.

[0389] In the insulating layer (here, the insulating film 110bf or the later insulating layer 110b), nitrogen reacts with oxygen to form nitrogen oxide (NO Ｘ, X is a real number greater than 0). ２ O, NO and NO ２ In the insulating layer, the nitrogen oxide forms a level, which is located within the band gap of the metal oxide. ２ The transition level where the charge of the indium oxide changes between the 0 state and the -1 state is located within the band gap of the indium oxide. ２ When the metal oxide diffuses to the interface between the insulating layer and the semiconductor layer having the metal oxide or near the interface, the level traps electrons. As a result, negative charges (also referred to as negative fixed charges) are formed at the interface between the insulating layer and the semiconductor layer or near the interface, which can increase the threshold voltage of the transistor in the positive direction. This allows the transistor to be a normally-off transistor, resulting in a semiconductor device with low power consumption.

[0390] Increasing the amount of nitrogen oxide can increase the threshold voltage to the positive side. However, if the amount of nitrogen oxide is too large, the threshold voltage may fluctuate greatly when a positive potential (positive bias) is applied to the gate of the transistor, which may result in reduced reliability. Therefore, it is preferable to use a nitrogen oxide amount within a range that does not affect reliability.

[0391] The amount of nitrogen oxides can be evaluated, for example, by measuring the amount of desorption in thermal desorption spectrometry (TDS) or the amount of electron spin in electron spin resonance (ESR). In TDS, NO (mass-to-charge ratio (m / z) = 30), N ２ O (m / z=44), and NO ２ The amount of NO (m / z = 46) desorbed can be evaluated. ２ In some cases, it may be difficult to quantify the amount of NO and N released. ２ By evaluating the amount of O released, ２ In ESR, the amount of NO can be evaluated. ２Since the N atom has 7 electrons and the O atom has 8 electrons, the ESR signal derived from NO ２ The molecule has an open-shell structure. Therefore, the neutral NO ２ Since the molecule has a lone electron, it can be measured by ESR. １４ Since N has a nuclear spin of 1, １４ The peak of the ESR signal related to N is split into three. At this time, the split width of the ESR signal is the hyperfine coupling constant.

[0392] The order of the treatment for supplying oxygen and the treatment for supplying nitrogen is not particularly limited. Oxygen can be supplied after nitrogen is supplied. Nitrogen can also be supplied after oxygen is supplied. Alternatively, oxygen and nitrogen can be supplied in the same treatment. For example, oxygen and nitrogen can be supplied by performing a plasma treatment in an atmosphere containing nitrogen and oxygen. For example, dinitrogen monoxide (N ２ By carrying out a plasma treatment using nitrogen oxides, nitrogen oxides can be efficiently produced, which is preferable.

[0393] After the insulating film 110bf is formed, it is preferable to perform the plasma treatment without exposing the surface of the insulating film 110bf to the atmosphere. For example, when a PECVD apparatus is used to form the insulating film 110bf, it is preferable to perform the plasma treatment in the PECVD apparatus. This can improve productivity. Specifically, after the insulating film 110bf is formed in the PECVD apparatus, it is preferable to perform the plasma treatment in the PECVD apparatus without exposing the surface of the insulating film 110bf to the atmosphere. ２ O plasma treatment can be performed.

[0394] Next, it is preferable to form the film 130 on the insulating film 110bf (FIG. 43D). The film 130 can be formed by a sputtering method. By forming the film 130 in an atmosphere containing oxygen, oxygen can be supplied to the insulating film 110bf.

[0395] The conductivity of the film 130 does not matter. At least one of an insulating film, a semiconductor film, and a conductive film can be used as the film 130. For example, aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide (ITO), or silicon-containing indium tin oxide (ITSO) can be used as the film 130.

[0396] The film 130 is preferably made of an oxide material containing one or more of the same elements as those of the semiconductor layer 108 and the semiconductor layer 208. In particular, it is preferable to use a metal oxide that can be used for the semiconductor layer 108 and the semiconductor layer 208.

[0397] During the deposition of the film 130, the amount of oxygen supplied to the insulating film 110bf can be increased by increasing the oxygen flow rate of the deposition gas introduced into the processing chamber of the deposition apparatus or the oxygen partial pressure in the processing chamber. The oxygen flow rate or oxygen partial pressure is, for example, preferably 50% to 100%, more preferably 60% to 100%, even more preferably 70% to 100%, still more preferably 80% to 100%, and even more preferably 90% to 100%. In particular, it is preferable to set the oxygen flow rate to 100% and the oxygen partial pressure as close to 100% as possible.

[0398] By forming the film 130 by sputtering in an oxygen-containing atmosphere in this manner, oxygen can be supplied to the insulating film 110bf during the formation of the film 130, and oxygen desorption from the insulating film 110bf can be prevented. As a result, a large amount of oxygen can be trapped in the insulating film 110bf. Then, a large amount of oxygen can be supplied to the semiconductor layer 108 and the semiconductor layer 208 by subsequent heat treatment. As a result, oxygen vacancies and V in the semiconductor layer 108 and the semiconductor layer 208 can be reduced. Ｏ H can be reduced, and a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0399] Heat treatment is preferably performed after the film 130 is formed. By performing heat treatment after the film 130 is formed, oxygen can be effectively supplied from the film 130 to the insulating film 110bf.

[0400] The temperature of the heat treatment is preferably 150° C. or higher and lower than the strain point of the substrate, more preferably 200° C. or higher and 450° C. or lower, further preferably 250° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 400° C. or lower, and further preferably 350° C. or higher and 400° C. or lower. The heat treatment can be performed in an atmosphere containing one or more of a noble gas, nitrogen, or oxygen. As the nitrogen-containing atmosphere or the oxygen-containing atmosphere, dry air (CDA: Clean Dry Air) can be used. Note that the content of hydrogen, water, and the like in the atmosphere is preferably as low as possible. As the atmosphere, it is preferable to use a high-purity gas with a dew point of −60° C. or lower, preferably −100° C. or lower. Using an atmosphere containing as little hydrogen, water, and the like as possible can prevent hydrogen, water, and the like from being taken into the insulating films 110af and 110bf as much as possible. The heat treatment can be performed using an oven, a rapid thermal annealing (RTA) device, etc. By using an RTA device, the heat treatment time can be shortened.

[0401] After the film 130 is formed or after the heat treatment, oxygen can be further supplied to the insulating film 110bf through the film 130. Oxygen can be supplied by, for example, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment. The above description of the plasma treatment can be referred to, and therefore, detailed description thereof will be omitted.

[0402] Next, the film 130 is removed ( FIG. 43E ). There are no particular limitations on the method for removing the film 130, but wet etching is preferably used. By using wet etching, etching of the insulating film 110bf can be suppressed when removing the film 130. This prevents the thickness of the insulating film 110bf from becoming thin, and allows the thickness of the insulating layer 110b to be made uniform.

[0403] The process of supplying oxygen to the insulating film 110bf is not limited to the above-described method. For example, oxygen radicals, oxygen atoms, oxygen atomic ions, or oxygen molecular ions can be supplied to the insulating film 110bf by ion doping, ion implantation, or plasma treatment. Alternatively, a film that suppresses oxygen desorption can be formed on the insulating film 110bf, and then oxygen can be supplied to the insulating film 110bf through the film. The film is preferably removed after oxygen is supplied. The film that suppresses oxygen desorption can be a conductive film or a semiconductor film containing one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten.

[0404] Next, an insulating film 110cf that will become the insulating layer 110c is formed on the insulating film 110bf (FIG. 44A). For the formation of the insulating film 110cf, the description regarding the formation of the insulating film 110af can be referred to.

[0405] When an oxide or oxynitride is used for the insulating layer 110c, the insulating film 110cf can be formed in an oxygen-containing atmosphere to supply oxygen to the insulating film 110bf. The insulating film 110cf can be preferably formed by sputtering. For example, the insulating film 110cf can be formed by sputtering using an aluminum target in an oxygen-containing atmosphere. When forming the insulating film 110cf, the amount of oxygen supplied to the insulating film 110bf can be increased by increasing the oxygen flow rate of the deposition gas introduced into the treatment chamber of the deposition apparatus or the oxygen partial pressure in the treatment chamber. The oxygen flow rate or oxygen partial pressure is preferably, for example, 50% to 100%, more preferably 60% to 100%, even more preferably 70% to 100%, even more preferably 80% to 100%, and even more preferably 90% to 100%. In particular, it is preferable to set the oxygen flow rate ratio to 100% and the oxygen partial pressure to as close to 100% as possible.

[0406] By forming the insulating film 110cf in an oxygen-containing atmosphere, oxygen can be supplied to the insulating film 110bf during the formation of the insulating film 110cf, and oxygen desorption from the insulating film 110bf can be prevented. As a result, a large amount of oxygen can be trapped in the insulating film 110bf. Then, a large amount of oxygen can be supplied to the semiconductor layer 108 and the semiconductor layer 208 by subsequent heat treatment. As a result, oxygen vacancies and V in the semiconductor layer 108 and the semiconductor layer 208 can be reduced. Ｏ H can be reduced, and a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0407] Heat treatment can also be performed after the insulating film 110cf is formed. By performing heat treatment after the insulating film 110cf is formed, oxygen can be effectively supplied from the insulating film 110cf to the insulating film 110bf.

[0408] Next, a conductive film 112bf that will become the conductive layer 112b is formed on the insulating film 110cf (FIG. 44B). The conductive film 112bf can be formed by sputtering.

[0409] Next, the conductive film 112bf, the insulating film 110cf, the insulating film 110bf, and the insulating film 110af are processed to form the conductive layer 112b, the insulating layer 110c, the insulating layer 110b, and the insulating layer 110a ( FIG. 44C ). This results in the insulating layer 110 having the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c. The conductive layer 112b can be preferably formed by wet etching, for example. The insulating layer 110 can be preferably formed by dry etching, for example.

[0410] The conductive layer 112b and the insulating layer 110 can be formed using, for example, the same resist mask. After forming the insulating film to be the insulating layer 110 and the conductive film 112bf, a resist mask is formed over the conductive film 112bf, and the conductive film 112bf and the insulating film are processed using the resist mask, thereby forming the conductive layer 112b and the insulating layer 110. By using the same resist mask to form the conductive layer 112b and the insulating layer 110, productivity can be improved. Furthermore, the top surface shapes of the conductive layer 112b and the insulating layer 110 can be made to match or approximately match. Note that different resist masks can also be used to form the conductive layer 112b and the insulating layer 110.

[0411] Next, a metal oxide film 108f to be the semiconductor layer 108 and the semiconductor layer 208 is formed so as to cover the conductive layer 112a, the conductive layer 212a, the conductive layer 112b, and the insulating layer 110 ( FIG. 44D ). The metal oxide film 108f is provided in contact with the upper surface of the conductive layer 112a, the upper surface of the conductive layer 212a, the upper surface and side surfaces of the conductive layer 112b, and the side surfaces of the insulating layer 110.

[0412] The metal oxide film 108f is preferably formed by a sputtering method using a metal oxide target. Alternatively, the metal oxide film 108f is preferably formed by an ALD method. By using the ALD method, a metal oxide film can be formed with high coverage on the side surfaces of the insulating layer 110 and the conductive layer 112b. Furthermore, the ALD method allows easy control of the film formation rate, and thus allows thin films to be formed with high yield. Therefore, the ALD method is particularly suitable when the metal oxide film 108f is thin. Furthermore, instead of the sputtering method and the ALD method, a CVD method can be used to form the metal oxide film 108f.

[0413] The metal oxide film 108f is preferably a dense film with as few defects as possible. Furthermore, the metal oxide film 108f is preferably a high-purity film in which impurities including hydrogen are reduced as much as possible. In particular, it is preferable to use a crystalline metal oxide film as the metal oxide film 108f.

[0414] Oxygen gas is preferably used when the metal oxide film 108f is formed. By using oxygen gas, oxygen can be suitably supplied to the insulating layer 110. For example, when an oxide or an oxynitride is used for the insulating layer 110b, oxygen can be suitably supplied to the insulating layer 110b.

[0415] By supplying oxygen to the insulating layer 110b, oxygen is supplied to the semiconductor layer 108 and the semiconductor layer 208 in a later process, and oxygen vacancies and V in the semiconductor layer 108 and the semiconductor layer 208 are eliminated. Ｏ H can be reduced.

[0416] When forming the metal oxide film 108f, a mixture of oxygen gas and an inert gas (e.g., helium gas, argon gas, xenon gas, etc.) can be used. Note that the higher the oxygen flow rate ratio or oxygen partial pressure of the deposition gas when forming the metal oxide film, the higher the crystallinity of the metal oxide film, and thus a highly reliable transistor can be realized. On the other hand, the lower the oxygen flow rate ratio or oxygen partial pressure, the lower the crystallinity and the higher the electrical conductivity of the metal oxide film, and thus a transistor with a large on-state current can be realized.

[0417] Here, if the oxygen flow rate ratio or oxygen partial pressure is high, the metal oxide film may become polycrystalline. In the case of a polycrystalline metal oxide film, the grain boundaries may become recombination centers, trapping carriers and reducing the on-state current of the transistor. Therefore, it is preferable to adjust the oxygen flow rate ratio or oxygen partial pressure so that the metal oxide film 108f does not become polycrystalline. Because the ease with which a metal oxide film becomes polycrystalline varies depending on the composition of the metal oxide film, it is preferable to adjust the oxygen flow rate ratio or oxygen partial pressure depending on the composition of the metal oxide film 108f. However, one embodiment of the present invention is not limited thereto, and a polycrystalline metal oxide can be used. When the grain boundaries of a polycrystalline metal oxide film do not affect the transistor characteristics, a transistor using a polycrystalline metal oxide can have higher reliability than a transistor using a metal oxide with low crystallinity.

[0418] The higher the substrate temperature during deposition of the metal oxide film, the higher the crystallinity and density of the metal oxide film, which allows for a highly reliable transistor. On the other hand, the lower the substrate temperature, the lower the crystallinity and electrical conductivity of the metal oxide film, which allows for a high on-state current of the transistor.

[0419] The substrate temperature during deposition of the metal oxide film 108f is preferably from room temperature (e.g., 25° C.) to 250° C., more preferably from room temperature to 200° C., and even more preferably from room temperature to 140° C. For example, setting the substrate temperature from room temperature to 140° C. is preferable because it increases productivity. Furthermore, by depositing the metal oxide film at room temperature or without heating the substrate, the crystallinity can be reduced.

[0420] Note that if the substrate temperature is too high, the metal oxide film may have a polycrystalline structure. It is preferable to set the substrate temperature depending on the composition of the material used for the metal oxide film 108f.

[0421] When the ALD method is used, it is preferable to use a film formation method such as a thermal ALD method or PEALD (Plasma Enhanced ALD). The thermal ALD method is preferable because it exhibits extremely high coverage. The PEALD method is preferable because it not only exhibits high coverage but also allows low-temperature film formation.

[0422] The metal oxide film can be formed by, for example, the ALD method using a precursor containing the constituent metal element and an oxidizing agent.

[0423] For example, when forming an In—Ga—Zn oxide film, three precursors, i.e., a precursor containing indium, a precursor containing gallium, and a precursor containing zinc, can be used, or two precursors, i.e., a precursor containing indium and a precursor containing gallium and zinc, can be used.

[0424] Examples of indium-containing precursors include triethylindium, trimethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) chloride, (3-(dimethylamino)propyl)dimethylindium, and [1,1,1-trimethyl-N-(trimethylsilyl)amido]-indium.

[0425] Gallium-containing precursors include, for example, trimethylgallium, triethylgallium, gallium trichloride, tris(dimethylamido)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, and diethylchlorogallium.

[0426] Precursors containing aluminum include, for example, aluminum chloride and trimethylaluminum.

[0427] Tin-containing precursors include, for example, tin(IV) chloride and tetrakis(dimethylamido)tin.

[0428] Precursors containing zinc include, for example, dimethylzinc, diethylzinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), and zinc chloride.

[0429] Oxidizing agents include, for example, ozone, oxygen, and water.

[0430] The composition of the resulting film can be controlled by adjusting one or more of the types of source gases, the flow rate ratio of the source gases, the time for which the source gases are flowed, and the order in which the source gases are flowed. By adjusting these, the composition of the metal oxide film 108f can be controlled. Furthermore, by adjusting these, it is possible to form a metal oxide film 108f whose composition changes continuously.

[0431] Before forming the metal oxide film 108f, it is preferable to perform at least one of a treatment for removing water, hydrogen, organic substances, and the like adsorbed on the surface of the insulating layer 110 and a treatment for supplying oxygen into the insulating layer 110. For example, heat treatment can be performed at a temperature of 70° C. or higher and 200° C. or lower in a reduced pressure atmosphere. Alternatively, plasma treatment can be performed in an atmosphere containing oxygen. Alternatively, dinitrogen monoxide (N ２ By performing plasma treatment in an atmosphere containing an oxidizing gas such as nitrous oxide (NO), oxygen can be supplied to the insulating layer 110. By performing plasma treatment containing nitrous oxide gas, oxygen can be supplied while organic substances on the surface of the insulating layer 110 are suitably removed. After such treatment, it is preferable to form the metal oxide film 108f continuously without exposing the surface of the insulating layer 110 to the air.

[0432] In addition, when the semiconductor layer 108 and the semiconductor layer 208 have a stacked structure, it is preferable to form a metal oxide film first, and then form the next metal oxide film in succession without exposing the surface of the first metal oxide film to the air.

[0433] When the semiconductor layer 108 and the semiconductor layer 208 have a stacked structure, all of the layers constituting the semiconductor layer 108 and the semiconductor layer 208 can be deposited by the same method (for example, sputtering or ALD). Alternatively, different deposition methods can be used for each layer. For example, the first metal oxide layer can be deposited by sputtering, and the second metal oxide layer can be deposited by ALD.

[0434] Subsequently, the metal oxide film 108f is processed into an island shape to form the semiconductor layer 108 and the semiconductor layer 208 (FIG. 45A).

[0435] The semiconductor layer 108 and the semiconductor layer 208 can be preferably formed by wet etching. At this time, a part of the conductive layer 112b in a region that does not overlap with either the semiconductor layer 108 or the semiconductor layer 208 may be etched and thinned. In a configuration in which the top surface shape of the conductive layer 112b does not match the top surface shape of the insulating layer 110, as shown in FIG. 27A and the like, a part of the insulating layer 110 in a region that does not overlap with either the semiconductor layer 108 or the conductive layer 112b may be etched and thinned. For example, the insulating layer 110c of the insulating layer 110 may be removed by etching, exposing the surface of the insulating layer 110b. Note that, in etching the metal oxide film 108f, using a material with a high etching selectivity for the insulating layer 110c can prevent the insulating layer 110c from becoming thin.

[0436] Heat treatment is preferably performed after the metal oxide film 108f is formed or after the metal oxide film 108f is processed into the semiconductor layer 108 and the semiconductor layer 208. The heat treatment can remove hydrogen and water contained in the metal oxide film 108f, or the semiconductor layer 108 and the semiconductor layer 208, or adsorbed to the surfaces thereof. Furthermore, the heat treatment may improve the film quality of the metal oxide film 108f or the semiconductor layer 108 and the semiconductor layer 208 (for example, reduce defects or improve crystallinity).

[0437] By the heat treatment, oxygen can also be supplied from the insulating layer 110b to the metal oxide film 108f or the semiconductor layer 108 and the semiconductor layer 208. In this case, it is more preferable to perform the heat treatment before processing into the semiconductor layer 108 and the semiconductor layer 208. The above description can be referred to for the heat treatment, and therefore detailed description thereof will be omitted.

[0438] Note that this heat treatment does not have to be performed if it is not necessary. Alternatively, the heat treatment may be omitted here and may be combined with a heat treatment performed in a later step. Furthermore, a process in which heat is applied in a later step (e.g., a film formation step) may also serve as this heat treatment.

[0439] Subsequently, the insulating layer 106 is formed to cover the semiconductor layer 108, the semiconductor layer 208, the conductive layer 112b, and the insulating layer 110 (FIG. 45B). The insulating layer 106 can be formed by, for example, a PECVD method, a sputtering method, or an ALD method.

[0440] When a metal oxide is used for the semiconductor layer 108 and the semiconductor layer 208, the insulating layer 106 preferably functions as a barrier film that suppresses oxygen diffusion. When the insulating layer 106 functions as a barrier film, oxygen is suppressed from being released from the semiconductor layer 108 and the semiconductor layer 208, and oxygen vacancies (V Ｏ In addition, oxygen contained in the semiconductor layer 108 and the semiconductor layer 208 is prevented from diffusing into the conductive layer 104 and the conductive layer 204 through the insulating layer 106, thereby preventing the conductive layer 104 and the conductive layer 204 from being oxidized. As a result, a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0441] By increasing the temperature during deposition of the insulating layer 106 that functions as a gate insulating layer, the insulating layer can have fewer defects. However, if the temperature during deposition of the insulating layer 106 is high, oxygen is released from the semiconductor layer 108 and the semiconductor layer 208, causing oxygen vacancies and V in the semiconductor layer 108 and the semiconductor layer 208. Ｏ H may increase. The substrate temperature during deposition of the insulating layer 106 is preferably 180° C. or higher and 450° C. or lower, more preferably 200° C. or higher and 450° C. or lower, further preferably 250° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 450° C. or lower, and further preferably 300° C. or higher and 400° C. or lower. By setting the substrate temperature during deposition of the insulating layer 106 within the above range, defects in the insulating layer 106 can be reduced and oxygen can be prevented from being released from the semiconductor layer 108 and the semiconductor layer 208. Therefore, a transistor exhibiting favorable electrical characteristics and high reliability can be obtained.

[0442] Before forming the insulating layer 106, it is preferable to perform plasma treatment on the surfaces of the semiconductor layer 108 and the semiconductor layer 208. The plasma treatment can reduce impurities such as water adsorbed on the surfaces of the semiconductor layer 108 and the semiconductor layer 208. Therefore, impurities at the interfaces between the semiconductor layer 108 and the insulating layer 106 and the semiconductor layer 208 can be reduced, and a highly reliable transistor can be realized. This is particularly suitable when the surfaces of the semiconductor layer 108 and the semiconductor layer 208 are exposed to the air between the formation of the semiconductor layer 108 and the semiconductor layer 208 and the formation of the insulating layer 106. The plasma treatment can be performed in an atmosphere of oxygen, ozone, nitrogen, nitrous oxide, argon, or the like, for example. It is also preferable that the plasma treatment and the formation of the insulating layer 106 are performed successively without exposure to the air.

[0443] Subsequently, the conductive layer 104 is formed on the insulating layer 106 (FIG. 1C). The conductive film that becomes the conductive layer 104 can be preferably formed by, for example, a sputtering method, a thermal CVD method (including an MOCVD method), or an ALD method.

[0444] Through the above steps, the semiconductor device 10 of one embodiment of the present invention can be manufactured.

[0445] <Manufacturing Method Example 2> An example of a manufacturing method of the semiconductor device 40B shown in Figures 32A to 35B will be described. Figures 46A to 46D show cross-sectional views taken along dashed line A1-A2 shown in Figure 32A.

[0446] First, the steps up to the formation of the conductive film 112bf are performed in the same manner as in Manufacturing Method Example 1. For the steps up to the formation of the conductive film 112bf, the description of FIGS.

[0447] Next, the conductive film 112bf is processed to form a conductive layer 112B (FIG. 46A). The conductive layer 112B will later become the conductive layer 112b. The conductive layer 112B can be preferably formed by, for example, wet etching.

[0448] Next, portions of the conductive layer 112B, the insulating film 110af, the insulating film 110bf, and the insulating film 110cf are removed to form an opening 141 reaching the conductive layer 112a and an opening 241 reaching the conductive layer 212a ( FIG. 46B ). This forms the conductive layer 112b and the insulating layer 110. For example, wet etching can be suitably used to form the conductive layer 112b. For example, dry etching can be suitably used to form the insulating layer 110.

[0449] Subsequently, a metal oxide film 108f that will become the semiconductor layer 108 and the semiconductor layer 208 is formed so as to cover the opening 141 (FIG. 46C). The above description can be referred to for the formation of the metal oxide film 108f.

[0450] Next, the metal oxide film 108f is processed into an island shape to form the semiconductor layer 108 and the semiconductor layer 208 (FIG. 46D). For the formation of the semiconductor layer 108 and the semiconductor layer 208 and subsequent steps, the description in <Manufacturing Method Example 1> can be referred to.

[0451] Through the above steps, the semiconductor device 40B of one embodiment of the present invention can be manufactured.

[0452] Embodiment 3 In this embodiment, a display device of one embodiment of the present invention will be described with reference to FIGS.

[0453] The display device of this embodiment can be a high-resolution display device or a large-sized display device. Therefore, the display device of this embodiment can be used as a display unit for electronic devices having relatively large screens, such as television devices, desktop or notebook computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound reproduction devices.

[0454] The display device of the present embodiment can be a high-definition display device, and can therefore be used, for example, as a display unit for a wristwatch-type or bracelet-type information terminal (wearable device), as well as a display unit for a wearable device that can be worn on the head, such as a head-mounted display (HMD) for VR, or a glasses-type AR device.

[0455] The semiconductor device of one embodiment of the present invention can be used for a display device or a module including the display device. Examples of the module including the display device include a module in which a connector such as a flexible printed circuit (hereinafter referred to as FPC) or a tape carrier package (TCP) is attached to the display device, and a module in which an integrated circuit (IC) is mounted by a chip-on-glass (COG) method, a chip-on-film (COF) method, or the like.

[0456] The display device of this embodiment may have a function as a touch panel. For example, various detection elements (also referred to as sensor elements) that can detect the proximity or contact of a detection target such as a finger can be applied to the display device.

[0457] Examples of sensor types include a capacitance type, a resistive film type, a surface acoustic wave type, an infrared type, an optical type, and a pressure-sensitive type.

[0458] The capacitance type includes, for example, a surface capacitance type and a projected capacitance type. The projected capacitance type includes, for example, a self-capacitance type and a mutual capacitance type. The mutual capacitance type is preferred because it enables simultaneous multi-point detection.

[0459] Examples of touch panels include out-cell, on-cell, and in-cell types. Note that an in-cell touch panel is a type in which electrodes constituting a detection element are provided on one or both of a substrate supporting a display element and an opposing substrate.

[0460] <Display Device 50A> FIG. 47 shows a perspective view of the display device 50A.

[0461] The display device 50A has a configuration in which a substrate 152 and a substrate 151 are bonded together. In Fig. 47, the substrate 152 is indicated by a dashed line.

[0462] The display device 50A has a display portion 162, a connection portion 140, a circuit portion 164, a conductive layer 165, etc. Fig. 47 shows an example in which an IC 173 and an FPC 172 are mounted on the display device 50A. Therefore, the configuration shown in Fig. 47 can also be said to be a display module having the display device 50A, an IC, and an FPC.

[0463] The connection portion 140 is provided on the outside of the display portion 162. The connection portion 140 can be provided along one side or multiple sides of the display portion 162. There may be one or multiple connection portions 140. FIG. 47 shows an example in which the connection portion 140 is provided so as to surround the four sides of the display portion 162. The connection portion 140 connects the common electrode of the display element and the conductive layer, and can supply a potential to the common electrode.

[0464] The circuit portion 164 includes, for example, a scan line driver circuit (also referred to as a gate driver). Alternatively, the circuit portion 164 may include both a scan line driver circuit and a signal line driver circuit (also referred to as a source driver).

[0465] The conductive layer 165 has a function of supplying signals and power to the display portion 162 and the circuit portion 164. The signals and power are input to the conductive layer 165 from the outside through the FPC 172 or are input to the conductive layer 165 from the IC 173.

[0466] 47 shows an example in which an IC 173 is provided on a substrate 151 by a COG method. The IC 173 may be, for example, an IC having one or both of a scanning line driver circuit and a signal line driver circuit. The display device 50A and the display module may be configured without an IC. The IC may also be mounted on an FPC by a COF method or the like.

[0467] The semiconductor device of one embodiment of the present invention can be applied to, for example, one or both of the display portion 162 and the circuit portion 164 of the display device 50A. An oxide semiconductor (OS) can be suitably used for a channel formation region of a transistor included in the display device. By using an OS transistor, the display device can have low power consumption. Furthermore, the semiconductor device of one embodiment of the present invention can be used for both the display portion 162 and the circuit portion 164, that is, all of the transistors included in the display device can be OS transistors. By using OS transistors for all of the transistors included in the display device in this manner, an effect of reducing manufacturing costs can be obtained.

[0468] For example, when the semiconductor device of one embodiment of the present invention is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, resulting in a high-resolution display device. Furthermore, when the semiconductor device of one embodiment of the present invention is applied to a driver circuit of a display device (e.g., one or both of a gate line driver circuit and a source line driver circuit), the area occupied by the driver circuit can be reduced, resulting in a display device with a narrow frame. Furthermore, since the semiconductor device of one embodiment of the present invention has good electrical characteristics, its use in a display device can improve the reliability of the display device.

[0469] The display section 162 is an area in the display device 50A that displays an image, and has a plurality of periodically arranged pixels 201. Fig. 47 shows an enlarged view of one pixel 201.

[0470] The pixel arrangement in the display device of this embodiment is not particularly limited, and various methods can be applied, such as a stripe arrangement, an S-stripe arrangement, a matrix arrangement, a delta arrangement, a Bayer arrangement, and a pentile arrangement.

[0471] 47 includes a sub-pixel 11R that emits red light, a sub-pixel 11G that emits green light, and a sub-pixel 11B that emits blue light. Note that the number of sub-pixels included in one pixel is not particularly limited.

[0472] Each of the sub-pixels 11R, 11G, and 11B includes a display element and a circuit that controls the driving of the display element.

[0473] Various elements can be used as the display element, including, for example, a liquid crystal element and a light-emitting element. Other examples include shutter-type or optical interference-type MEMS (Micro Electro Mechanical Systems) elements, display elements that employ a microcapsule method, an electrophoresis method, an electrowetting method, or an electronic liquid powder (registered trademark) method, etc. Furthermore, a QLED (Quantum-dot LED) that uses a light source and color conversion technology using quantum dot materials may also be used.

[0474] Examples of display devices using liquid crystal elements include transmissive liquid crystal display devices, reflective liquid crystal display devices, and semi-transmissive liquid crystal display devices.

[0475] Examples of modes that can be used in display devices using liquid crystal elements include vertical alignment (VA) mode, Fringe Field Switching (FFS) mode, In-Plane-Switching (IPS) mode, Twisted Nematic (TN) mode, Axially Symmetric Aligned Micro-cell (ASM) mode, Optically Compensated Birefringence (OCB) mode, Ferroelectric Liquid Crystal (FLC) mode, Anti-Ferroelectric Liquid Crystal (AFLC) mode, and Electrically Compensated Birefringence (ECB) mode. Examples of the VA mode include a Multi-Domain Vertical Alignment (MVA) mode, a Patterned Vertical Alignment (PVA) mode, and an Advanced Super View (ASV) mode.

[0476] Examples of liquid crystal materials that can be used in liquid crystal elements include thermotropic liquid crystals, low-molecular-weight liquid crystals, polymer liquid crystals, polymer-dispersed liquid crystals (PDLCs), polymer network liquid crystals (PNLCs), ferroelectric liquid crystals, and antiferroelectric liquid crystals. These liquid crystal materials exhibit cholesteric phases, smectic phases, cubic phases, chiral nematic phases, isotropic phases, blue phases, and the like, depending on the conditions. Furthermore, either positive-type or negative-type liquid crystals may be used as the liquid crystal material, and the type can be selected depending on the mode or design to be applied.

[0477] Examples of the light-emitting element include self-luminous light-emitting elements such as LEDs (Light Emitting Diodes), OLEDs (Organic LEDs), semiconductor lasers, etc. Examples of the LED that can be used include mini LEDs and micro LEDs.

[0478] Examples of light-emitting substances that the light-emitting element has include fluorescent substances (fluorescent materials), phosphorescent substances (phosphorescent materials), substances that exhibit thermally activated delayed fluorescence (thermally activated delayed fluorescence: TADF materials), and inorganic compounds (quantum dot materials, etc.).

[0479] The light-emitting element can emit light of infrared, red, green, blue, cyan, magenta, yellow, white, etc. Furthermore, the color purity can be improved by providing the light-emitting element with a microcavity structure.

[0480] One of a pair of electrodes included in the light-emitting element functions as an anode, and the other electrode functions as a cathode.

[0481] Note that the display device of one embodiment of the present invention may be any of a top-emission type that emits light in a direction opposite to a substrate on which a light-emitting element is formed, a bottom-emission type that emits light toward a substrate on which a light-emitting element is formed, and a dual-emission type that emits light to both sides.

[0482] Figure 48A shows an example of a cross section of the display device 50A when a portion of the area including the FPC 172, a portion of the circuit section 164, a portion of the display section 162, a portion of the connection section 140, and a portion of the area including the end portion are cut away.

[0483] 48A includes transistors 205D, 205R, 205G, and 205B, a light-emitting element 130R, a light-emitting element 130G, and a light-emitting element 130B between a substrate 151 and a substrate 152. The light-emitting element 130R is a display element included in the sub-pixel 11R that emits red light, the light-emitting element 130G is a display element included in the sub-pixel 11G that emits green light, and the light-emitting element 130B is a display element included in the sub-pixel 11B that emits blue light.

[0484] The display device 50A employs an SBS structure, which allows the materials and configuration to be optimized for each light-emitting element, increasing the degree of freedom in the selection of materials and configurations and facilitating improvements in brightness and reliability.

[0485] The display device 50A is a top emission type, which allows transistors and the like to be arranged overlapping the light emitting region of the light emitting element, thereby enabling a higher pixel aperture ratio than a bottom emission type.

[0486] The transistor 205D, the transistor 205R, the transistor 205G, and the transistor 205B are all formed over a substrate 151. These transistors can be manufactured in the same process. Note that the transistors 205D, the transistor 205R, the transistor 205G, and the transistor 205B may have different structures.

[0487] In this embodiment, an example in which OS transistors are used as the transistors 205D, 205R, 205G, and 205B will be described. The transistors according to one embodiment of the present invention can be used as the transistors 205D, 205R, 205G, and 205B. That is, the display device 50A includes the transistor according to one embodiment of the present invention in both the display portion 162 and the circuit portion 164. By using the transistor according to one embodiment of the present invention in the display portion 162, the pixel size can be reduced, leading to higher resolution. Furthermore, by using the transistor according to one embodiment of the present invention in the circuit portion 164, the area occupied by the circuit portion 164 can be reduced, leading to a narrower frame. The description of the previous embodiment can be referred to for the transistor according to one embodiment of the present invention.

[0488] 48A illustrates an example in which the structure of the transistor 100 illustrated in FIG. 1C and the like is applied to the transistor 205D, and the structure of the semiconductor device 20 illustrated in FIG. 20B and the like is applied to the transistors 205R, 205G, and 205B. Here, the same hatching pattern is applied to multiple layers obtained by processing the same conductive film.

[0489] The transistor 205D includes a conductive layer 104 functioning as a gate, an insulating layer 106 functioning as a gate insulating layer, conductive layers 112a and 112b functioning as a source and a drain, and a semiconductor layer 108 having a metal oxide. The semiconductor layer 108 has a region in contact with a side surface of the insulating layer 110.

[0490] The transistor 205R, the transistor 205G, and the transistor 205B each include a transistor 100_2 and a transistor 100_3, respectively, in which the number (p) of transistors connected in series is 2 (see FIGS. 19A to 20B ). The transistor 205R, the transistor 205G, and the transistor 205B each include a conductive layer 104 functioning as a gate, an insulating layer 106 functioning as a gate insulating layer, conductive layers 112b to 112d functioning as sources and drains, and semiconductor layers 108_2 and 108_3 having metal oxide. The semiconductor layer 108 has a region in contact with a side surface of the insulating layer 110, and the semiconductor layer 208 has a region in contact with a side surface of the insulating layer 210.

[0491] The transistors 205R, 205G, and 205B function as drive transistors that control the current flowing through the light-emitting elements 130R, 130G, and 130B, for example. By applying the configuration of the semiconductor device 20 to the drive transistors, the channel length can be increased, and saturation can be improved. Therefore, even if the source-drain voltage of these transistors is changed, the change in source-drain current is small, and therefore the light emission brightness of the light-emitting elements 130R, 130G, and 130B can be stabilized.

[0492] Note that the transistor included in the display device of this embodiment is not limited to the transistor of one embodiment of the present invention. For example, the display device may include a combination of the transistor of one embodiment of the present invention and a transistor having another structure.

[0493] The display device of this embodiment may include, for example, one or more of a planar transistor, a staggered transistor, and an inverted staggered transistor. The transistor included in the display device of this embodiment may be either a top-gate transistor or a bottom-gate transistor. Alternatively, gates may be provided above and below a semiconductor layer in which a channel is formed.

[0494] The display device of this embodiment may have a Si transistor.

[0495] To increase the emission luminance of a light-emitting element included in a pixel circuit, it is necessary to increase the amount of current flowing through the light-emitting element. To achieve this, it is necessary to increase the source-drain voltage of a driving transistor included in the pixel circuit. Since an OS transistor has a higher withstand voltage between its source and drain than a Si transistor, a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as the driving transistor included in a pixel circuit, it is possible to increase the amount of current flowing through the light-emitting element and increase the emission luminance of the light-emitting element.

[0496] When a transistor operates in a saturation region, an OS transistor can reduce the change in source-drain current with respect to a change in gate-source voltage compared to a Si transistor. Therefore, by using an OS transistor as a driving transistor included in a pixel circuit, the current flowing between the source and drain can be precisely controlled by changing the gate-source voltage, thereby controlling the amount of current flowing to a light-emitting element. This allows a pixel circuit to have a larger number of gray levels.

[0497] In terms of the saturation of the current that flows when a transistor operates in a saturation region, an OS transistor can pass a more stable current (saturation current) than a Si transistor, even when the source-drain voltage gradually increases. Therefore, by using an OS transistor as a driving transistor, a stable current can be passed to a light-emitting element, even when the current-voltage characteristics of the light-emitting element vary. In other words, when an OS transistor operates in a saturation region, the change in the source-drain current is small even when the source-drain voltage is changed, and therefore the light-emitting luminance of the light-emitting element can be stabilized.

[0498] The transistors included in the circuit portion 164 and the transistors included in the display portion 162 may have the same structure or different structures. The transistors included in the circuit portion 164 may all have the same structure or may have two or more types. Similarly, the transistors included in the display portion 162 may all have the same structure or may have two or more types.

[0499] All the transistors included in the display portion 162 may be OS transistors, all the transistors included in the display portion 162 may be Si transistors, or some of the transistors included in the display portion 162 may be OS transistors and the rest may be Si transistors.

[0500] For example, by using both an LTPS transistor and an OS transistor in the display portion 162, a display device with low power consumption and high driving capability can be realized. A structure in which an LTPS transistor and an OS transistor are combined is sometimes referred to as LTPO. Note that a more preferable example is a structure in which an OS transistor is used as a transistor that functions as a switch for controlling conduction / non-conduction between wirings, and an LTPS transistor is used as a transistor for controlling current.

[0501] For example, one of the transistors included in the display portion 162 functions as a transistor for controlling a current flowing to a light-emitting element and can also be called a driving transistor. One of the source and drain of the driving transistor is connected to a pixel electrode of the light-emitting element. It is preferable to use an LTPS transistor as the driving transistor. This can increase the current flowing to the light-emitting element in the pixel circuit.

[0502] On the other hand, another transistor included in the display portion 162 functions as a switch for controlling pixel selection / non-selection and can also be called a selection transistor. The gate of the selection transistor is connected to a gate line, and one of the source and drain is connected to a source line (signal line). An OS transistor is preferably used as the selection transistor. This allows the gradation of a pixel to be maintained even when the frame frequency is significantly low (for example, 1 fps or less), and therefore power consumption can be reduced by stopping the driver when displaying a still image.

[0503] An insulating layer 218 is provided to cover the transistors 205D, 205R, 205G, and 205B, and an insulating layer 235 is provided over the insulating layer 218.

[0504] The insulating layer 218 preferably functions as a protective layer for the transistor. The insulating layer 218 is preferably made of a material through which impurities such as water and hydrogen are less likely to diffuse. This allows the insulating layer 218 to function as a barrier film. With such a structure, diffusion of impurities from the outside into the transistor can be effectively suppressed, and the reliability of the display device can be improved.

[0505] The insulating layer 218 preferably includes one or more inorganic insulating layers. The insulating layer 218 can be made of the same material as that used for the insulating layer 110.

[0506] The insulating layer 235 preferably functions as a planarization layer, and is preferably an organic insulating film. Materials that can be used for the organic insulating film include acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene-based resin, phenolic resin, and precursors of these resins. The insulating layer 235 may also have a laminated structure of an organic insulating film and an inorganic insulating film. The outermost layer of the insulating layer 235 preferably functions as an etching protection layer. This prevents recesses from being formed in the insulating layer 235 during processing of the pixel electrodes 111R, 111G, 111B, etc. Alternatively, recesses may be formed in the insulating layer 235 during processing of the pixel electrodes 111R, 111G, 111B, etc. Note that the pixel electrodes 111R, 111G, and 111B may be collectively referred to as pixel electrodes 111.

[0507] On the insulating layer 235, the light emitting elements 130R, 130G, and 130B are provided.

[0508] The light-emitting element 130R has a pixel electrode 111R on the insulating layer 235, an EL layer 113R on the pixel electrode 111R, and a common electrode 115 on the EL layer 113R. The light-emitting element 130R shown in Fig. 48A emits red light (R). The EL layer 113R has a light-emitting layer that emits red light.

[0509] The light-emitting element 130G has a pixel electrode 111G on the insulating layer 235, an EL layer 113G on the pixel electrode 111G, and a common electrode 115 on the EL layer 113G. The light-emitting element 130G shown in Fig. 48A emits green light (G). The EL layer 113G has a light-emitting layer that emits green light.

[0510] The light-emitting element 130B has a pixel electrode 111B on the insulating layer 235, an EL layer 113B on the pixel electrode 111B, and a common electrode 115 on the EL layer 113B. The light-emitting element 130B shown in Fig. 48A emits blue light (B). The EL layer 113B has a light-emitting layer that emits blue light.

[0511] 48A, the EL layers 113R, 113G, and 113B are all shown with the same thickness, but this is not limited to this. The EL layers 113R, 113G, and 113B may have different thicknesses. For example, it is preferable to set the thickness of the EL layers 113R, 113G, and 113B so that the optical path length increases the intensity of the light emitted by each layer. This allows for a microcavity structure to be realized, and the color purity of the light emitted from each light-emitting element to be improved.

[0512] The pixel electrode 111R is connected to the conductive layer 112d of the transistor 205R in an opening provided in the insulating layer 106, the insulating layer 218, and the insulating layer 235. Similarly, the pixel electrode 111G is connected to the conductive layer 112d of the transistor 205G, and the pixel electrode 111B is connected to the conductive layer 112d of the transistor 205B.

[0513] Ends of each of the pixel electrodes 111R, 111G, and 111B are covered with an insulating layer 237. The insulating layer 237 functions as a partition wall. The insulating layer 237 can be formed in a single layer structure or a stacked layer structure using one or both of an inorganic insulating material and an organic insulating material. For example, the materials that can be used for the insulating layer 218 and the insulating layer 235 can be used for the insulating layer 237. The insulating layer 237 can electrically insulate the pixel electrode and the common electrode. Furthermore, the insulating layer 237 can electrically insulate adjacent light-emitting elements from each other.

[0514] The insulating layer 237 is provided at least in the display unit 162. The insulating layer 237 may be provided not only in the display unit 162 but also in the connection unit 140 and the circuit unit 164. Furthermore, the insulating layer 237 may be provided up to the edge of the display device 50A.

[0515] The common electrode 115 is a continuous film provided in common to the light-emitting elements 130R, 130G, and 130B. The common electrode 115 shared by the plurality of light-emitting elements is connected to a conductive layer 123 provided in the connection portion 140. For the conductive layer 123, it is preferable to use a conductive layer formed from the same material and in the same process as the pixel electrodes 111R, 111G, and 111B.

[0516] In a display device according to one embodiment of the present invention, a conductive film that transmits visible light is preferably used for the pixel electrode and the common electrode, which are electrodes from which light is extracted, and a conductive film that reflects visible light is preferably used for the electrode from which light is not extracted.

[0517] A conductive film that transmits visible light may also be used for the electrode on the side from which light is not extracted. In this case, it is preferable to place the electrode between the reflective layer and the EL layer. In other words, the light emitted from the EL layer may be reflected by the reflective layer and extracted from the display device.

[0518] Materials for forming the pair of electrodes of the light-emitting element can include metals, alloys, electrically conductive compounds, and mixtures thereof, as appropriate. Specific examples of such materials include metals such as aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium, and neodymium, as well as alloys containing these metals in combination. Other examples of such materials include indium tin oxide (In-Sn oxide, also referred to as ITO), In-Si-Sn oxide (also referred to as ITSO), indium zinc oxide (In-Zn oxide), and In-W-Zn oxide. Other examples of such materials include aluminum-containing alloys (aluminum alloys), such as an alloy of aluminum, nickel, and lanthanum (Al-Ni-La), and silver-containing alloys, such as an alloy of silver and magnesium and an alloy of silver, palladium, and copper (Ag-Pd-Cu, also referred to as APC). Other examples of the material include elements belonging to Group 1 or 2 of the periodic table (e.g., lithium, cesium, calcium, and strontium) that are not exemplified above, rare earth metals such as europium and ytterbium, alloys containing appropriate combinations of these, and graphene.

[0519] The light-emitting element preferably has a micro-optical resonator (microcavity) structure. Therefore, one of the pair of electrodes of the light-emitting element is preferably an electrode that is transparent and reflective to visible light (semi-transmissive / semi-reflective electrode), and the other is preferably an electrode that is reflective to visible light (reflective electrode). By having the light-emitting element have a microcavity structure, the light emitted from the light-emitting layer can be resonated between both electrodes, thereby intensifying the light emitted from the light-emitting element.

[0520] The light transmittance of the transparent electrode is 40% or more. For example, it is preferable to use an electrode having a visible light (light with a wavelength of 400 nm or more and less than 750 nm) transmittance of 40% or more for the transparent electrode of the light-emitting element. The visible light reflectance of the semi-transmissive / semi-reflective electrode is 10% or more and 95% or less, preferably 30% or more and 80% or less. The visible light reflectance of the reflective electrode is 40% or more and 100% or less, preferably 70% or more and 100% or less. In addition, the electrical resistivity of these electrodes is 1×10 −２ Preferably, it is Ωcm or less.

[0521] The EL layers 113R, 113G, and 113B are each provided in an island shape. In FIG. 48A , the ends of adjacent EL layers 113R and 113G overlap, the ends of adjacent EL layers 113G and 113B overlap, and the ends of adjacent EL layers 113R and 113B overlap. When forming island-shaped EL layers using a fine metal mask, the ends of adjacent EL layers may overlap as shown in FIG. 48A , but this is not limited to this. That is, adjacent EL layers may not overlap but may be spaced apart. Furthermore, the display device may have both regions where adjacent EL layers overlap and regions where adjacent EL layers do not overlap but are spaced apart.

[0522] Each of the EL layers 113R, 113G, and 113B includes at least a light-emitting layer. The light-emitting layer includes one or more light-emitting materials. As the light-emitting material, a material that emits light of a color such as blue, purple, blue-purple, green, yellow-green, yellow, orange, or red is appropriately used. Furthermore, a material that emits near-infrared light can also be used as the light-emitting material.

[0523] The light-emitting material may include a fluorescent material, a phosphorescent material, a TADF material, and a quantum dot material.

[0524] The light-emitting layer may contain one or more organic compounds (host materials, assist materials, etc.) in addition to a light-emitting substance (guest material). As the one or more organic compounds, one or both of a substance with high hole-transport properties (hole-transport material) and a substance with high electron-transport properties (electron-transport material) can be used. Furthermore, as the one or more organic compounds, a bipolar substance (a substance with high electron-transport properties and hole-transport properties) or a TADF material can be used.

[0525] The light-emitting layer preferably includes, for example, a phosphorescent material and a hole-transporting material and an electron-transporting material that are a combination that easily forms an exciplex. This configuration allows efficient emission using Exciplex-Triple Energy Transfer (ExTET), which is energy transfer from the exciplex to the light-emitting material (phosphorescent material). By selecting a combination that forms an exciplex that emits light that overlaps with the wavelength of the lowest-energy absorption band of the light-emitting material, energy transfer becomes smooth and light emission can be achieved efficiently. This configuration allows for high efficiency, low-voltage operation, and a long lifetime of the light-emitting element.

[0526] In addition to the light-emitting layer, the EL layer may include one or more of a layer containing a substance with high hole-injecting properties (hole-injecting layer), a layer containing a hole-transporting material (hole-transporting layer), a layer containing a substance with high electron-blocking properties (electron-blocking layer), a layer containing a substance with high electron-injecting properties (electron-injecting layer), a layer containing an electron-transporting material (electron-transporting layer), and a layer containing a substance with high hole-blocking properties (hole-blocking layer).In addition, the EL layer may include one or both of a bipolar substance and a TADF material.

[0527] The light-emitting element can be made of either a low-molecular-weight compound or a high-molecular-weight compound, and may contain an inorganic compound. The layers constituting the light-emitting element can be formed by a method such as a vapor deposition method (including a vacuum vapor deposition method), a transfer method, a printing method, an inkjet method, or a coating method.

[0528] The light-emitting element may have a single structure (a structure having only one light-emitting unit) or a tandem structure (a structure having multiple light-emitting units). The light-emitting unit has at least one light-emitting layer. The tandem structure is a structure in which multiple light-emitting units are connected in series via a charge-generating layer. When a voltage is applied between a pair of electrodes, the charge-generating layer injects electrons into one of the two light-emitting units and holes into the other. The tandem structure allows the light-emitting element to emit light with high brightness. Furthermore, the tandem structure can reduce the current required to achieve the same brightness compared to a single structure, thereby improving reliability. The tandem structure can also be called a stack structure.

[0529] In Figure 48A, when a light-emitting element with a tandem structure is used, it is preferable that EL layer 113R has a structure having multiple light-emitting units that emit red light, EL layer 113G has a structure having multiple light-emitting units that emit green light, and EL layer 113B has a structure having multiple light-emitting units that emit blue light.

[0530] A protective layer 131 is provided on the light-emitting elements 130R, 130G, and 130B. The protective layer 131 and the substrate 152 are bonded via an adhesive layer 142. A light-shielding layer 117 is provided on the substrate 152. For example, a solid sealing structure or a hollow sealing structure can be applied to seal the light-emitting elements. In FIG. 48A , the space between the substrates 152 and 151 is filled with the adhesive layer 142, and a solid sealing structure is applied. Alternatively, the space may be filled with an inert gas (such as nitrogen or argon), and a hollow sealing structure may be applied. In this case, the adhesive layer 142 may be provided so as not to overlap with the light-emitting elements. Alternatively, the space may be filled with a resin different from the frame-shaped adhesive layer 142.

[0531] The protective layer 131 is preferably provided in at least the display portion 162 and is provided so as to cover the entire display portion 162. The protective layer 131 is preferably provided so as to cover not only the display portion 162 but also the connection portion 140 and the circuit portion 164. The protective layer 131 is also preferably provided up to the edge of the display device 50A. Meanwhile, in the connection portion 197, a region where the protective layer 131 is not provided is generated in order to connect the FPC 172 and the conductive layer 166.

[0532] By providing the protective layer 131 on the light emitting elements 130R, 130G, and 130B, the reliability of the light emitting elements can be improved.

[0533] The protective layer 131 can have a single-layer structure or a stacked structure of two or more layers. The conductivity of the protective layer 131 does not matter. The protective layer 131 can be formed using at least one of an insulating film, a semiconductor film, and a conductive film.

[0534] The protective layer 131 has an inorganic film, which can prevent the common electrode 115 from being oxidized, suppress impurities (moisture, oxygen, etc.) from entering the light-emitting element, and so on, thereby suppressing deterioration of the light-emitting element and improving the reliability of the display device.

[0535] The protective layer 131 preferably includes one or more inorganic insulating layers. The protective layer 131 can be made of a material that can be used for the insulating layer 110. In particular, the protective layer 131 is preferably made of a nitride or a nitride oxide, and more preferably made of a nitride.

[0536] The protective layer 131 may be an inorganic film containing ITO, In—Zn oxide, Ga—Zn oxide, Al—Zn oxide, IGZO, or the like. The inorganic film preferably has high resistance, specifically, preferably has higher resistance than the common electrode 115. The inorganic film may further contain nitrogen.

[0537] When light emitted from the light-emitting element is extracted through the protective layer 131, it is preferable that the protective layer 131 has high transparency to visible light. For example, ITO, IGZO, and aluminum oxide are preferable because they are inorganic materials that have high transparency to visible light.

[0538] For example, a stacked structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film, or a stacked structure of an aluminum oxide film and an IGZO film on the aluminum oxide film can be used as the protective layer 131. By using such a stacked structure, impurities (water, oxygen, etc.) can be prevented from entering the EL layer side.

[0539] Furthermore, the protective layer 131 may have an organic film. For example, the protective layer 131 may have both an organic film and an inorganic film. Examples of organic films that can be used for the protective layer 131 include the organic insulating films that can be used for the insulating layer 235.

[0540] A connection portion 197 is provided in a region of the substrate 151 where the substrate 152 does not overlap. In the connection portion 197, the conductive layer 165 is connected to the FPC 172 via the conductive layer 166 and the connection layer 242. In this example, the conductive layer 165 is a conductive layer obtained by processing the same conductive film as the conductive layer 112b. In this example, the conductive layer 166 is a conductive layer obtained by processing the same conductive film as the pixel electrodes 111R, 111G, and 111B. The connection portion between the conductive layer 165 and the conductive layer 166 can have the same structure as the connection portion between the pixel electrode 111 and the conductive layer 112b. Specifically, FIG. 48A shows an example in which an opening is provided above the conductive layer 165, and the conductive layer 166 is in contact with the upper surface of the conductive layer 165 through the opening. The conductive layer 166 is exposed on the upper surface of the connection portion 197. This allows the connection portion 197 and the FPC 172 to be connected via the connection layer 242.

[0541] The display device 50A is a top-emission type. Light emitted by the light-emitting elements is emitted toward the substrate 152. The substrate 152 is preferably made of a material that is highly transparent to visible light. The pixel electrodes 111R, 111G, and 111B contain a material that reflects visible light, and the counter electrode (common electrode 115) contains a material that transmits visible light.

[0542] It is preferable to provide a light-shielding layer 117 on the surface of the substrate 152 facing the substrate 151. The light-shielding layer 117 can be provided between adjacent light-emitting elements, in the connection section 140, in the circuit section 164, and the like.

[0543] A colored layer such as a color filter may be provided on the surface of the substrate 152 on the substrate 151 side or on the protective layer 131. When a color filter is provided over the light-emitting element, the color purity of light emitted from the pixel can be increased.

[0544] The colored layer is a colored layer that selectively transmits light in a specific wavelength range and absorbs light in other wavelength ranges. For example, a red (R) color filter that transmits light in the red wavelength range, a green (G) color filter that transmits light in the green wavelength range, and a blue (B) color filter that transmits light in the blue wavelength range can be used. Each colored layer can be made of one or more of a metal material, a resin material, a pigment, and a dye. The colored layers are formed at desired positions by a printing method, an inkjet method, an etching method using lithography, or the like.

[0545] Various optical members can be arranged on the outside of the substrate 152 (the surface opposite to the substrate 151). Examples of optical members include a polarizing plate, a retardation plate, a light diffusion layer (such as a diffusion film), an anti-reflection layer, and a light-collecting film. In addition, a surface protection layer such as an anti-static film that suppresses the adhesion of dust, a water-repellent film that makes it difficult for dirt to adhere, a hard coat film that suppresses the occurrence of scratches during use, or an impact absorbing layer may be arranged on the outside of the substrate 152. For example, a glass layer or a silica layer (SiO ｘ The surface protection layer can be preferably formed of a material such as DLC (diamond-like carbon), aluminum oxide (AlO ｘ), polyester-based materials, or polycarbonate-based materials may also be used. Note that it is preferable to use a material with high transmittance to visible light for the surface protection layer. It is also preferable to use a material with high hardness for the surface protection layer.

[0546] The substrate 151 and the substrate 152 can each be made of glass, quartz, ceramics, sapphire, resin, metal, alloy, semiconductor, or the like. A material that transmits light is used for the substrate on the side from which light from the light-emitting element is extracted. When a flexible material is used for the substrate 151 and the substrate 152, the flexibility of the display device can be increased, and a flexible display can be realized. Furthermore, a polarizing plate may be used for at least one of the substrates 151 and 152.

[0547] Substrate 151 and substrate 152 can be made of polyester resin such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbo...

Claims

a first transistor, a second transistor, and a first insulating layer; the first transistor includes a first conductive layer, a second conductive layer, and a first oxide semiconductor layer; the second transistor includes a third conductive layer, the second conductive layer, and a second oxide semiconductor layer; the first insulating layer is located on the first conductive layer and on the third conductive layer; the first insulating layer has an end portion in contact with an upper surface of the first conductive layer and an end portion in contact with an upper surface of the third conductive layer; the second conductive layer is located on the first insulating layer; the first oxide semiconductor layer has an end portion in contact with a top surface of the first conductive layer, an end portion in contact with a side surface of the first insulating layer, an end portion in contact with a side surface of the second conductive layer, and an end portion in contact with a top surface of the second conductive layer; the second oxide semiconductor layer has an end portion in contact with a top surface of the third conductive layer, an end portion in contact with a side surface of the first insulating layer, an end portion in contact with a side surface of the second conductive layer, and an end portion in contact with the top surface of the second conductive layer. 　 In claim 1, the first transistor has a gate insulating layer and a first gate electrode; the second transistor has the gate insulating layer and a second gate electrode; the gate insulating layer is located on the first oxide semiconductor layer and the second oxide semiconductor layer; the first gate electrode has a region facing a side surface of the first insulating layer with the gate insulating layer and the first oxide semiconductor layer interposed therebetween; the second gate electrode has a region facing a side surface of the first insulating layer with the gate insulating layer and the second oxide semiconductor layer interposed therebetween. 　 In claim 2, The semiconductor device, wherein the gate insulating layer has a region in contact with a side surface of the first insulating layer. 　 a first transistor, a second transistor, and a first insulating layer; the first transistor includes a first conductive layer, a second conductive layer, a first oxide semiconductor layer, a gate insulating layer, and a first gate electrode; the second transistor includes a third conductive layer, the second conductive layer, a second oxide semiconductor layer, the gate insulating layer, and a second gate electrode; the first insulating layer is located on the first conductive layer and on the third conductive layer; the first insulating layer has an end portion in contact with an upper surface of the first conductive layer and an end portion in contact with an upper surface of the third conductive layer; the second conductive layer is located on the first insulating layer; the first oxide semiconductor layer has a region in contact with an upper surface of the first conductive layer, a side surface of the first insulating layer, and an upper surface and a side surface of the second conductive layer; the second oxide semiconductor layer has a region in contact with an upper surface of the third conductive layer, a side surface of the first insulating layer, and an upper surface and a side surface of the second conductive layer; the gate insulating layer has a region in contact with an upper surface and a side surface of the first oxide semiconductor layer, an upper surface and a side surface of the second oxide semiconductor layer, and a side surface of the first insulating layer; the first gate electrode has a region facing a side surface of the first insulating layer with the gate insulating layer and the first oxide semiconductor layer interposed therebetween; the second gate electrode has a region facing a side surface of the first insulating layer with the gate insulating layer and the second oxide semiconductor layer interposed therebetween. 　 In any one of claims 1 to 4, A semiconductor device, wherein the top surface shape of the second conductive layer coincides or substantially coincides with the top surface shape of the first insulating layer. 　 In any one of claims 2 to 4, The semiconductor device, wherein the gate insulating layer has a region in contact with an upper surface of the first insulating layer. 　 In any one of claims 1 to 4, a second insulating layer; the second insulating layer has a region in contact with a lower surface of the first conductive layer and a lower surface of the third conductive layer; the first insulating layer has a third insulating layer and a fourth insulating layer on the third insulating layer; the second insulating layer comprises silicon, nitrogen, and hydrogen; the third insulating layer comprises silicon and nitrogen; The fourth insulating layer comprises silicon and oxygen. In claim 7 The semiconductor device, wherein the second insulating layer has a region having a higher hydrogen content than the third insulating layer. 　 In any one of claims 1 to 4, The semiconductor device, wherein the first oxide semiconductor layer and the second oxide semiconductor layer each contain indium. 　 In any one of claims 1 to 4, The semiconductor device, wherein the first conductive layer and the third conductive layer each contain indium and oxygen.

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