Communication system and communication method

Abstract

The present disclosure relates to a communication system and a communication method that can enable transmitting audio data using the MIPI A-PHY standard. According to the present invention, a transmission device divides a clock signal required for transmission of audio data according to the I2S standard according to a predetermined N value, generates an Audio packet in which a count result obtained by counting a frequency division clock signal obtained by the division in accordance with a predetermined transmission reference frequency is stored in an Audio payload, stores the Audio packet in an Audio packet according to the A-PHY standard, and transmits the Audio packet via an A-PHY network. A reception device then receives the Audio packet via the A-PHY network, acquires the count result stored in the Audio payload of the Audio packet, refers to a predetermined reception reference frequency on the basis of the count result, and restores the clock signal. The present technology can be applied to, for example, a communication system that transmits I2S SDATA using the MIPI A-PHY standard.

Description

Communication system and communication method

[0001] The present disclosure relates to a communication system and a communication method, and more particularly to a communication system and a communication method that are capable of transmitting audio data using the MIPI A-PHY standard.

[0002] In recent years, developments have been underway to transmit audio data captured by microphones and acceleration information from acceleration sensors to a vehicle's ECU (Electronic Control Unit). For example, transmitting audio data to a vehicle's ECU is expected to be used as input for sound source localization, quickly alerting the user to an emergency vehicle approaching from a direction that is out of the blind spot of the in-vehicle camera. Furthermore, if acceleration information from an acceleration sensor could be transmitted to the ECU as road noise information, like audio data, the ECU could generate an anti-phase road noise cancellation signal, which could be used to create a quieter and more comfortable in-vehicle environment.

[0003] One of the standards defined by the MIPI (Mobile Industry Processor Interface) Alliance is the A-PHY (Automotive PHY) standard (see, for example, Non-Patent Document 1). The A-PHY standard is a standard that mainly relates to the physical layer and data link layer of a Serializer Deserializer (SerDes) for automotive applications. For the protocol adaptation layer above the data link layer, there is also a protocol-specific PAL (Protocol Adaptation Layer) standard (see, for example, Non-Patent Document 2).

[0004] MIPI Alliance Specification for A-PHY, version 1.1, MIPI Alliance, Inc., 9 August 2021.A-PHY Protocol Adaptation Layer Specification for I2C, version1.0, MIPI Alliance, Inc., 29 September 2020

[0005] Incidentally, the MIPI A-PHY standard (ver. 1.1) disclosed in the above-mentioned Non-Patent Documents 1 and 2, and the PAL standard for individual protocol adaptation layers, do not standardize audio packets used in PAL-Audio, which transmits audio data in accordance with standards such as I2S (Inter-IC Sound).

[0006] The present disclosure has been made in light of such circumstances, and enables audio data to be transmitted in accordance with a standard such as I2S using the MIPI A-PHY standard (i.e., PAL Audio standardization of MIPI A-PHY).

[0007] A communication system according to one aspect of the present disclosure includes a transmitting device that divides a clock signal required for transmitting audio data in accordance with the I2S standard in accordance with a predetermined N value, counts the divided clock signal obtained by the division in accordance with a predetermined transmission reference frequency, generates an Audio packet having the count result stored in the Audio payload, stores the Audio packet in an Audio packet conforming to the A-PHY standard, and transmits the Audio packet via an A-PHY network, and a receiving device that receives the A-Packet via the A-PHY network, obtains the count result stored in the Audio payload of the Audio packet stored in the A-Packet, and restores the clock signal by referring to a predetermined reception reference frequency based on the count result.

[0008] A communication method according to one aspect of the present disclosure includes: dividing a clock signal required for transmitting audio data in accordance with the I2S standard in accordance with a predetermined N value; counting the divided clock signal obtained by the division in accordance with a predetermined transmission reference frequency; generating an Audio packet having the count result stored in the Audio payload; storing the Audio packet in an A-Packet in accordance with the A-PHY standard; and transmitting the A-Packet via an A-PHY network; receiving the A-Packet via the A-PHY network; obtaining the count result stored in the Audio payload of the Audio packet stored in the A-Packet; and restoring the clock signal based on the count result by referring to a predetermined reception reference frequency.

[0009] In one aspect of the present disclosure, a clock signal required for transmitting audio data in accordance with the I2S standard is divided in frequency according to a predetermined N value, the divided clock signal obtained by the division is counted in accordance with a predetermined transmission reference frequency to generate an Audio packet having the count result stored in the Audio payload, the Audio packet is stored in an A-Packet conforming to the A-PHY standard and transmitted via an A-PHY network, the A-Packet is then received via the A-PHY network, the count result stored in the Audio payload of the Audio packet stored in the A-Packet is obtained, and the clock signal is restored based on the count result by referring to the predetermined reception reference frequency.

[0010] 26. FIG. 27 is a block diagram showing an example of a communication system using an A-PHY network as a crosspoint of an I2S bus. FIG. 28 is a block diagram showing an example of the configuration of a first embodiment of a communication system to which the present technology is applied. FIG. 29 is a block diagram showing an example of the configuration of the ECU and A-PHY deserializer of FIG. 2. FIG. 30 is a diagram showing an example of data written to the PAL_I2S master-side register of FIG. 3, and an example of a PMC result(M) packetized by the A-Packet constructor of FIG. 3. FIG. 31 is a diagram explaining how to calculate the BCLK_Div value and PMC_result(M) value shown in FIG. 3. FIG. 29 is a diagram showing an example of the configuration of an Audio packet included in an A-Packet payload in the first embodiment. FIG. 29 is a block diagram showing an example of the configuration of the A-PHY serializer of FIG. 2. FIG. 29 is a block diagram showing an example of the configuration of the ADC device of FIG. 2. FIG. 29 is a diagram showing an example of data written to the PAL_I2S slave-side register of FIG. 7, an example of a PMC result(M) included in an Audio packet decoded by the A-Packet deconstructor of FIG. 7, and an example of an Audio Master Clock (MCK) restored by the MCK generator of FIG. 26. FIG. 29 is a block diagram showing an example of the configuration of the BCLK generator of FIG. 7. FIG. 11 is a diagram for explaining how to obtain BCLK_Div and BCLK in the BCLK generator of FIG. 10. FIG. 12 is a diagram for explaining the Audio header of an Audio packet. FIG. 13 is a diagram for explaining an example of a Start timestamp in I2S mode. FIG. 14 is a diagram for explaining an example of a Start timestamp in I2S Left justified mode. FIG. 15 is a diagram for explaining an example of a Start timestamp in I2S Right justified mode. FIG. 16 is a diagram for explaining an example of a Start timestamp in TDM4 pulse mode. FIG. 17 is a diagram for explaining an example of a Start timestamp in TDM4 nopulse mode. FIG. 18 is a diagram for explaining the Audio payload of an Audio packet. FIG. 19 is a diagram for explaining the format of I2S data for each SDBW.26. FIG. 27 is a diagram showing a detailed example of audio transmission setting information written to the PAL_I2S slave-side register of FIG. 7 or FIG. 26. FIG. 28 is a block diagram showing a configuration example of a second embodiment of a communication system to which the present technology is applied. FIG. 29 is a block diagram showing a configuration example of an ECU and A-PHY serializer of FIG. 21. FIG. 29 is a diagram explaining how to calculate the PMC Value in FIG. 22. FIG. 30 is a diagram showing a configuration example of an Audio packet in the second embodiment. FIG. 31 is a block diagram showing a modified example of PAL-Audio (ISAM) equipped with an MCK generator. FIG. 32 is a block diagram showing a configuration example of the A-PHY deserializer of FIG. 21. FIG. 33 is a block diagram showing a configuration example of the DAC device of FIG. 21. FIG. 34 is a block diagram showing a configuration example of the MCK generator of FIG. 26. FIG. 35 is a diagram explaining how to calculate MCK_Div and BCLK in the MCK generator of FIG. 28.

[0011] Hereinafter, specific embodiments to which the present technology is applied will be described in detail with reference to the drawings.

[0012] <Example of A-PHY Network> First, with reference to FIG. 1, an example of a communication system using an A-PHY network as a crosspoint of an I2S bus will be described.

[0013] 1, a first I2S bus 11-1 and a second I2S bus 11-2 are configured using an A-PHY network as a crosspoint. The A-PHY network is configured by connecting an I2S adaptation layer (ISAM) natively connected to an I2S master device, which is an I2S adaptation layer connected to a native I2S master, and an I2S adaptation layer (ISAS) natively connected to an I2S slave device, which are connected in accordance with the MIPI A-PHY (PAL Audio described herein) standard.

[0014] The first I2S bus 11-1 is configured with an I2S master 21-1, an ISAM 22-1, an ISAS 23-1, and an ISAS 23-2, and I2S slaves 24-1 to 24-4. The I2S master 21-1 is connected to the ISAM 22-1 and the I2S slave 24-1 via I2S, and the ISAM 22-1 is connected to the ISAS 23-1 and the ISAS 23-2 via an A-PHY network. The ISAS 23-1 is connected to the I2S slaves 24-2 and 24-3 via I2S, and the ISAS 23-2 is connected to the I2S slave 24-4 via I2S.

[0015] Therefore, just as the I2S master 21-1 communicates with the I2S slave 24-1 in accordance with the I2S standard, it can also communicate with the I2S slaves 24-2 and 24-3 via the ISAM 22-1 and ISAS 23-1. Similarly, the I2S master 21-1 can communicate with the I2S slave 24-4 via the ISAM 22-1 and ISAS 23-2.

[0016] The second I2S bus 11-2 is configured with an I2S master 21-2, an ISAM 22-2, an ISAS 23-3, and I2S slaves 24-5 to 24-7. The I2S master 21-2 is connected to the ISAM 22-2 and the I2S slave 24-5 via I2S, and the ISAM 22-2 is connected to the ISAS 23-3 via the A-PHY network. The ISAS 23-3 is connected to the I2S slaves 24-6 and 24-7 via I2S.

[0017] Therefore, the I2S master 21-2 can communicate with the I2S slave 24-6 and the I2S slave 24-7 via the ISAM 22-2 and the ISAS 23-3, just as it can communicate with the I2S slave 24-5 in accordance with the I2S standard.

[0018] The I2S master 21 and the I2S slave 24 are native I2S, and the ISAM 22 and ISAS 23 are I2S adaptation layers. The ISAM 22 functions as an I2S slave between the I2S master 21 and the ISAS 23, and the I2S slave 24 functions as an I2S master between the I2S master 21 and the ISAS 23.

[0019] <First Configuration Example of Communication System> A configuration example of a first embodiment of a communication system to which the present technology is applied will be described with reference to FIGS. 2 to 20 .

[0020] FIG. 2 is a block diagram showing an example of the configuration of the communication system 101.

[0021] 2, the communication system 101 includes an ECU 102, an A-PHY deserializer 103, an A-PHY serializer 104, and an ADC (Analog to Digital Converter) device 105-1 and an ADC device 105-2. A microphone 106-1 and a microphone 106-2 are connected to the ADC device 105-1 and the ADC device 105-2, respectively.

[0022] The ECU 102 and the A-PHY deserializer 103 are connected in accordance with the I2C (Inter-Integrated Circuit) and I2S standards. The A-PHY deserializer 103 and the A-PHY serializer 104 are connected via an A-PHY network. The A-PHY serializer 104 and the ADC devices 105-1 and 105-2 are connected in accordance with the I2C and I2S standards, respectively.

[0023] 2, the A-PHY serializer 104 and the ADC devices 105-1 and 105-2 are on the source side, and the ECU 102 and the A-PHY deserializer 103 are on the sink side. Audio packets conforming to the I2S standard that store audio data of sounds picked up by the microphones 106-1 and 106-2 are stored in the A-Packet payload of an A-Packet and transmitted from the source side to the sink side.

[0024] The ECU 102 is, for example, an electronic control unit mounted on an automobile, and in the communication system 101, has a function as an I2C and I2S master.

[0025] The A-PHY deserializer 103 receives an A-Packet containing an Audio packet transmitted from the source side via the A-PHY network, extracts audio data conforming to the I2S standard from the A-Packet, and supplies it to the ECU 102.

[0026] The A-PHY serializer 104 generates an A-Packet in which the audio data supplied from the ADC device 105-1 and the ADC device 105-2 is stored in the A-Packet payload, and transmits the A-Packet to the sink side via the A-PHY network.

[0027] The ADC device 105-1 and the ADC device 105-2 have functions as I2C and I2S slaves, respectively, and supply audio data obtained by AD converting analog sound signals input from the microphones 106-1 and 106-2 to the A-PHY serializer 104. Note that the ADC device 105-1 and the ADC device 105-2 have the same configuration, and when there is no need to distinguish between them, they will be simply referred to as the ADC device 105.

[0028] The microphones 106-1 and 106-2 collect sounds, convert them into electrical signals, and supply the analog sound signals to the ADC devices 105-1 and 105-2, respectively. Note that the microphones 106-1 and 106-2 have the same configuration, and when there is no need to distinguish between them, they will be simply referred to as the microphones 106.

[0029] Additionally, in the communication system 101, A-Packets storing I2C packets and CFS (Clock Forwarding Service) A-Packets storing frequency offsets are transmitted and received via the A-PHY network. For example, the A-PHY network can use CFS A-Packets to synchronize the time of a Running Time-Based Counter (RTBC), which is the reference time for executing processing.

[0030] An A-Packet is composed of an A-Packet header, an A-Packet payload, and an A-Packet tail, and for example, the Adaptation Type (e.g., 4'b0111) included in the A-Packet header indicates that an Audio packet (Audio header (I2S) and Audio payload (I2S)) is stored in the A-Packet payload. For example, the Adaptation Type (7), which is reserved in the MIPI A-PHY standard (ver1.1), can be assigned to indicate that audio data is stored in the A-Packet payload.

[0031] FIG. 3 is a block diagram showing an example of the configuration of the ECU 102 and the A-PHY deserializer 103.

[0032] As shown in FIG. 3, the ECU 102 includes an I2C master 201 and an I2S master 202 .

[0033] The I2C master 201 communicates with the I2C slaves 221 and 231 of the A-PHY deserializer 103 in accordance with the I2C standard and controls the communication. In I2C, serial data SDA is transmitted and received in accordance with a serial clock SCL output from the I2C master 201. For example, the I2C master 201 can write audio transmission setting information, which contains various information required for audio transmission, to a PAL_I2S master-side register 232 of the A-PHY deserializer 103.

[0034] The I2S master 202 communicates with the I2S slave 247 of the A-PHY deserializer 103 in accordance with the I2S standard and controls this communication. For example, the I2S master 202 supplies the I2S slave 247 with an LRCLK, which is a clock signal for distinguishing between the L channel and R channel of SDATA, and a BCLK, which is a clock signal required for transmitting SDATA, and acquires SDATA (I2S data: audio data conforming to the I2S standard) transmitted from the I2S slave 247.

[0035] The A-PHY deserializer 103 is configured to include a PAL-I2C 211 , a PAL-Audio 212 , a data link layer 213 , and a PHY layer 214 .

[0036] The PAL-I2C 211 has an I2C slave 221 and functions as an I2C adaptation layer (ICAM) that is natively connected to an I2C master device. The I2C slave 221 communicates with the I2C master 201 in accordance with the I2C standard under communication control by the I2C master 201.

[0037] The PAL-Audio 212 includes an I2C slave 231, a PAL_I2S master side register 232, a controller 233, and a PAL_I2S encoder 234, and functions as, for example, an ISAM (see FIG. 1).

[0038] The I2C slave 231 communicates with the I2C master 201 in accordance with the I2C standard under the control of the I2C master 201. For example, the I2C slave 231 writes audio transmission setting information to the PAL_I2S master-side register 232 under the control of the I2C master 201.

[0039] In the PAL_I2S master side register 232, for example, audio transmission setting information (e.g., TxREFCK_INFO: 250 MHz, RxREFCK_INFO: 500 MHz, SDBW (I2S Data Bit Width): 32, Number of channels: 8, LRCLK (=fs): 48 MHz, K value: 512, N value: 768) as shown in FIG. 4 is written.

[0040] The controller 233 controls the PAL_I2S encoder 234 based on the audio transmission setting information in the PAL_I2S master-side register 232. For example, the controller 233 supplies an N value (=768) obtained from the audio transmission setting information to a BCLK divider 241 of the PAL_I2S encoder 234. The controller 233 also supplies parameters obtained from the audio transmission setting information (e.g., parameters other than the N value of the audio transmission setting information shown in FIG. 20 , which will be described later, such as the number of channels and SDBW) to an A-Packet constructor 243 and an A-Packet deconstructor 246 of the PAL_I2S encoder 234.

[0041] The PAL_I2S encoder 234 has a BCLK divider 241, a PMC 242, an A-Packet constructor 243, an I2S encode FIFO 244, an I2S decode FIFO 245, an A-Packet deconstructor 246, and an I2S slave 247. The PAL_I2S encoder 234 encodes the SDATA supplied from the data link layer 213 and supplies it to the ECU 102.

[0042] The BCLK divider 241 divides the BCLK output from the I2S master 202 in accordance with the N value supplied from the controller 233, and supplies BCLK_Div obtained by this division to the PMC 242. For example, as shown in FIG. 5 , if the BCLK is 12.288 MHz and the N value is 768, the BCLK divider 241 supplies 16 KHz (= 12.288 MHz / 768) obtained as BCLK_Div to the PMC 242.

[0043] The PMC 242 counts BCLK_Div supplied from the BCLK divider 241 in accordance with TxREFCK (=250 MHz) supplied from the running time base counter 251, and supplies the resulting PMC_result(M) to the A-Packet constructor 243. For example, as shown in FIG. 5 , if BCLK_Div is 16 kHz and TxREFCK is 250 MHz, the PMC 242 supplies 15625 (=16 kHz@62500 ns / 250 MHz@4 ns) calculated as PMC_result(M) to the A-Packet constructor 243.

[0044] The A-Packet constructor 243 generates an audio packet consisting of an audio header and audio payload to be stored in the A-Packet payload in accordance with the RTBC supplied from the running time base counter 251 of the data link layer 213, the LRCLK and BCLK supplied from the I2S master 202, the PMC_result(M) (=15625) supplied from the PMC 242, and parameters (I2S master mode and target clock select) supplied from the controller 233, and writes the generated audio packet to the I2S encode FIFO 244. As shown in A of Fig. 6, the audio header includes an audio type, a CRC type, a time stamp type, an I2S packet type, and an audio packet ID, and the audio payload includes a data length, a 3-byte PMC_result[17:0], and a 4-byte CRC32.

[0045] Here, in the communication system 101, audio data is not transmitted from the ECU 102, but PMC_result(M), which is required to restore BCLK, needs to be transmitted to the A-PHY serializer 104. Therefore, PMC_result[17:0]=15625 (see FIG. 18, which will be described later) is stored in the Audio payload of the Audio packet generated by the A-Packet constructor 243 (see A in FIG. 6), and (1) is set in the I2S packet type of the Audio header (see FIG. 12, which will be described later).

[0046] 21, in order to transmit audio data from the ECU 102, the A-Packet constructor 243 generates an Audio payload in which SDATA is stored and writes an Audio packet (see FIG. 24) consisting of an Audio header and Audio payload to the I2S encode FIFO 244. Hereinafter, the Audio packet written to the I2S encode FIFO 244 (the same applies to the Audio packet written to the I2S decode FIFO 245 described later) will also be referred to as W_SDATA.

[0047] The I2S encode FIFO 244 stores W_SDATA (i.e., audio packets) supplied from the A-Packet constructor 243 in accordance with I2S_WCLK, a write clock signal supplied from the A-Packet constructor 243. The I2S encode FIFO 244 then outputs the audio packets in the order they were input in accordance with I2S_RCLK, a read clock signal supplied from the frame constructor 252 of the data link layer 213. Hereinafter, audio packets read from the I2S encode FIFO 244 (as well as audio packets read from the I2S decode FIFO 245, described later) will also be referred to as R_SDATA.

[0048] The I2S decode FIFO 245 stores W_SDATA (i.e., audio packets) supplied from the frame decoder 253 in accordance with I2S_WCLK, which is a write clock signal supplied from the frame decoder 253 of the data link layer 213. The I2S decode FIFO 245 then outputs the audio packets in the order they were input, in accordance with I2S_RCLK, which is a read clock signal supplied from the A-Packet decoder 246.

[0049] The A-Packet deconstructor 246 reads the audio packet (audio header and audio payload) stored in the A-Packet payload from the I2S decode FIFO 245. As shown in B of Fig. 6, the audio header includes an audio type, a CRC type, a time stamp type, an I2S packet type, and an audio packet ID, and the audio payload includes a time stamp, a data length, and 255 bytes of I2S data.

[0050] The A-Packet deconstructor 246 extracts the I2S data stored in the audio payload for each SDBW (see FIG. 19 , which will be described later) in accordance with BCLK based on information in the audio header (see FIG. 12 , which will be described later), the RTBC supplied from the running time base counter 251, the LRCLK and BCLK supplied from the I2S master 202, and parameters (Number of channels and SDBW) supplied from the controller 233, and supplies this as SDATA to the I2S slave 247. Note that if the Time Stamp Type in the audio header is set to (2) (see FIG. 12 , which will be described later), the A-Packet deconstructor 246 starts outputting SDATA when the value of the Time Stamp in the audio payload matches the RTBC supplied from the running time base counter 251.

[0051] The I2S slave 247 performs communication with the I2S master 202 in accordance with the I2S standard in accordance with communication control by the I2S master 202. For example, the I2S slave 247 transmits SDATA supplied from the A-Packet deconstructor 246 to the I2S master 202 in accordance with the LRCLK and BCLK supplied from the I2S master 202. For example, the I2S slave 247 transmits SDATA to the I2S master 202 in accordance with the BCLK.

[0052] The data link layer 213 has a running time base counter 251, a frame constructor 252, and a frame deconstructor 253, and performs data link layer processing.

[0053] The running time base counter 251 supplies the A-Packet constructor 243 and the A-Packet deconstructor 246 with an RTBC for achieving time synchronization with the A-PHY serializer 104. The running time base counter 251 also supplies the PMC 242 with TxREFCK, which is a clock signal that the PMC 242 references to obtain PMC_result(M).

[0054] The frame constructor 252 stores the R_SDATA (i.e., Audio packet) read from the I2S encoding FIFO 244 in the A-Packet payload as shown in FIG. 2 above to construct (packetize) an A-Packet, and supplies it to the uplink 261 of the PHY layer 214.

[0055] If the Adaptation Type included in the A-Packet header of the A-Packet supplied from the downlink 262 of the PHY layer 214 indicates (7), the frame deconstructor 253 writes the Audio packet stored in the A-Packet payload to the I2S decode FIFO 245 of the PAL-Audio 212. Here, in the communication system 101, SDATA consisting of audio data for two channels, the microphone 106-1 and the microphone 106-2, is stored in the A-Packet payload.

[0056] The PHY layer 214 has an uplink 261 and a downlink 262, and performs physical layer processing. In the communication system 101, the uplink 261 is the transmitting side (Tx), and the downlink 262 is the receiving side (Rx). In the PHY layer 214, the uplink 261 transmits A-Packets supplied from the frame constructor 252 to the A-PHY network, and the downlink 262 receives A-Packets transmitted from the A-PHY network and supplies them to the frame deconstructor 253.

[0057] The ECU 102 and the A-PHY deserializer 103 are configured as described above.

[0058] The A-PHY deserializer 103 divides the BCLK required for transmitting SDATA according to the N value, counts the BCLK_Div obtained by this division according to TxREFCK, and generates an Audio packet in which the count result PMC_result(M) is stored in the Audio payload.The A-PHY deserializer 103 can then store this Audio packet in an Audio packet conforming to the A-PHY standard and transmit it via the A-PHY network.

[0059] FIG. 7 is a block diagram showing an example of the configuration of the A-PHY serializer 104.

[0060] As shown in FIG. 7, the A-PHY serializer 104 includes a PHY layer 301 , a data link layer 302 , a PAL-I2C 303 , and a PAL-Audio 304 .

[0061] The PHY layer 301 has an uplink 311 and a downlink 312, and performs physical layer processing. In the communication system 101, the uplink 311 is the receiving side (Rx), and the downlink 312 is the transmitting side (Tx). In the PHY layer 301, the uplink 311 receives an A-Packet transmitted from the A-PHY network and supplies it to a frame deconstructor 321 in the data link layer 302, and the downlink 312 transmits the A-Packet supplied from the frame constructor 323 in the data link layer 302 to the A-PHY network.

[0062] The data link layer 302 has a frame deconstructor 321, a running time base counter 322, and a frame constructor 323, and performs data link layer processing.

[0063] The frame decoder 321 determines the supply destination of the A-Packet according to the Adaptation Type included in the A-Packet header of the A-Packet supplied from the uplink 311. For example, if the Adaptation Type indicates (7), the frame decoder 321 writes the Audio packet stored in the A-Packet payload to the I2S decoder FIFO 351 of the PAL-Audio 304. In this case, as described above, in the communication system 101, PMC_result (see A in FIG. 6 described above) is stored in the A-Packet payload.

[0064] Furthermore, if the Adaptation Type indicates (5), the frame decoder 321 writes the I2C packet stored in the A-Packet payload to the I2C decode FIFO 331. In this case, the payload of the I2C packet stores, for example, audio transmission setting information and ADC setting information.

[0065] The running time base counter 322 supplies the RTBC for achieving time synchronization with the A-PHY deserializer 103 to the A-Packet deconstructor 352 and the A-Packet constructor 354, and supplies the RxREFCK to the BCLK generator 344. For example, in the data link layer 302, the running time base counter 322 can be synchronized with the running time base counter 251 based on the A-Packet received by the frame deconstructor 321.

[0066] The frame constructor 323 reads R_SDATA (i.e., Audio packets) from the I2S encoding FIFO 355 of the PAL-Audio 304, stores the Audio packets in the A-Packet payload as shown in FIG. 2 above, constructs (packetizes) an A-Packet, and supplies it to the downlink 312.

[0067] The PAL-I2C 303 has an I2C decode FIFO 331, a PAL-I2C decoder 332, and an I2C master 333, and functions as an I2C adaptation layer (ICAS) that is natively connected to an I2C save device.

[0068] The I2C decode FIFO 331 stores I2C_WDATA (e.g., audio transmission setting information and ADC setting information stored in the payload of the I2C packet) supplied from the frame deconstructor 321 in accordance with I2C_WCLK, which is a write clock signal supplied from the frame deconstructor 321. Then, the I2C decode FIFO 331 outputs I2C_RDATA (e.g., audio transmission setting information and ADC setting information stored in the payload of the I2C packet) in the order in which it was input in accordance with I2C_RCLK, which is a read clock signal supplied from the PAL-I2C decoder 332.

[0069] The PAL-I2C decoder 332 reads the I2C_RDATA from the I2C decode FIFO 331 and supplies it to the I2C master 333 .

[0070] The I2C master 333 communicates with the I2C slave 341 of the PAL-Audio 304 and the I2C slave 361 of the ADC device 105 in Fig. 8 in accordance with the I2C standard, and controls the communication. For example, the I2C master 333 can write audio transmission setting information (see Fig. 20 , described later) to a PAL_I2S slave-side register 342 of the PAL-Audio 304 via the I2C slave 341. The I2C master 333 can also transmit ADC setting information to the ADC device 105 in Fig. 8.

[0071] The PAL-Audio 304 includes an I2C slave 341, a PAL_I2S slave register 342, a slave controller 343, a BCLK generator 344, and a PAL_I2S encoder / decoder 345, and functions as, for example, an ISAS (see FIG. 1).

[0072] The I2C slave 341 communicates with the I2C master 333 in accordance with the I2C standard under the control of the I2C master 333. For example, the I2C slave 341 can write audio transmission setting information (see FIG. 20 , which will be described later) to the PAL_I2S slave-side register 342 under the control of the I2C master 333.

[0073] The PAL_I2S slave side register 342 is written with, for example, audio transmission setting information such as that shown in FIG. 9 (e.g., TxREFCK_INFO: 250 MHz, RxREFCK_INFO: 500 MHz, SDBW (I2S Data Bit Width): 32, Number of channels: 8, LRCLK (=fs): 48 MHz, K value: 512, N value: 768).

[0074] The slave-side controller 343 controls the BCLK generator 344 and the PAL_I2S encoder / decoder 345 based on the audio transmission setting information in the PAL_I2S slave-side register 342. For example, the slave-side controller 343 writes the N value, SDBW, number of channels, TxREFCK_INFO, RxREFCK_INFO, and the like obtained from the audio transmission setting information to the BCLK generator 344. The slave-side controller 343 also writes necessary parameters (number of channels and SDBW) from the audio transmission setting information in the PAL_I2S slave-side register 342 to the A-Packet deconstructor 352, I2S master 353, and A-Packet constructor 354 of the PAL_I2S encoder / decoder 345.

[0075] The BCLK generator 344 generates BCLK and LRCLK based on RxREFCK supplied from the running time base counter 322, PMC_result(M) (=15625) supplied from the A-Packet deconstructor 352 of the PAL_I2S encoder / decoder 345, and parameters supplied from the slave-side controller 343. The BCLK generator 344 then supplies BCLK and LRCLK to the A-Packet deconstructor 352 of the PAL_I2S encoder / decoder 345, the I2S master 353, and the A-Packet constructor 354. The detailed configuration of the BCLK generator 344 will be described later with reference to FIG. 10.

[0076] The PAL_I2S encoder / decoder 345 has an I2S decoder FIFO 351, an A-Packet deconstructor 352, an I2S master 353, an A-Packet constructor 354, and an I2S encode FIFO 355. The PAL_I2S encoder / decoder 345 decodes the SDATA supplied from the data link layer 302 and encodes the SDATA supplied from the ADC device 105 in FIG. 8.

[0077] The I2S decoder FIFO 351 stores the W_SDATA (i.e., audio packets) supplied from the frame decoder 321 in accordance with I2S_WCLK, which is a write clock signal supplied from the frame decoder 321. The I2S decoder FIFO 351 then outputs the audio packets in the order they were input in accordance with I2S_RCLK, which is a read clock signal supplied from the A-Packet decoder 352.

[0078] The A-Packet deconstructor 352 reads an Audio packet from the I2S decoder FIFO 351. The A-Packet deconstructor 352 then analyzes the Audio header to determine the contents stored in the Audio payload of the Audio packet. As described above, in the communication system 101, only the PMC_result(M) (see A in FIG. 6 described above) required to restore the BCLK is stored in the A-Packet payload. Therefore, the A-Packet deconstructor 352 obtains the PMC_result(M) (= 15625) stored in the A-Packet payload and supplies it to the BCLK generator 344.

[0079] In the communication system 101A described later with reference to FIG. 21, I2S data is stored in the audio payload of an audio packet to transmit audio data from the ECU 102. In this case, the A-Packet deconstructor 352 extracts the I2S data stored in the audio payload for each SDBW (see FIG. 19 described later) in accordance with the BCLK based on the information in the audio header (see FIG. 12 described later), the RTBC supplied from the running time base counter 322, the LRCLK and BCLK supplied from the BCLK generator 344, and parameters (number of channels and SDBW) supplied from the slave-side controller 343, and supplies the extracted data as SDATA to the I2S master 353. In addition, if the time stamp type in the audio header is set to (2) (see FIG. 12 described later), output of the SDATA begins when the value of the time stamp in the audio payload matches the RTBC supplied from the running time base counter 322.

[0080] The I2S master 353 communicates with the I2S slave 362 of the ADC device 105 in FIG. 8 in accordance with the I2S standard and controls this communication. For example, the I2S master 353 transmits the LRCLK and BCLK supplied from the BCLK generator 344 to the I2S slave 362. When SDATA corresponding to the LRCLK and BCLK is transmitted from the I2S slave 362, the I2S master 353 acquires the SDATA and supplies it to the A-Packet constructor 354. For example, the I2S master 353 supplies the SDATA to the A-Packet constructor 354 in accordance with the BCLK. Note that in the communication system 101, the I2S master 353 operates in a receive mode in which it receives SDATA from the ADC device 105, according to the setting value of the I2S master mode in FIG. 20.

[0081] The A-Packet constructor 354 stores the SDATA supplied from the I2S master 353 in the Audio payload based on the RTBC supplied from the running time base counter 322, the LRCLK and BCLK supplied from the BCLK generator 344, and the parameters (Number of channels and SDBW) supplied from the slave-side controller 343, generates an Audio packet consisting of an Audio header and Audio payload as shown in B of Figure 6 above, and writes it to the I2S encode FIFO 355.

[0082] The I2S encode FIFO 355 stores the W_SDATA (i.e., audio packets) supplied from the A-Packet constructor 243 in accordance with I2S_WCLK, which is a write clock signal supplied from the A-Packet constructor 243. The I2S encode FIFO 355 then outputs the audio packets in the order they were input in accordance with I2S_RCLK, which is a read clock signal supplied from the frame constructor 323.

[0083] The A-PHY serializer 104 is configured as described above.

[0084] The A-PHY serializer 104 receives an Audio packet via the A-PHY network, obtains the PMC_result(M) stored in the Audio payload of the Audio packet, and can restore BCLK by referring to RxREFCK based on the PMC_result(M).

[0085] FIG. 8 is a block diagram showing an example of the configuration of the ADC device 105.

[0086] As shown in FIG. 8, the ADC device 105 includes an I2C slave 361, an I2S slave 362, and an AD converter 363, and the AD converter 363 is provided with a register 364.

[0087] The I2C slave 361 communicates with the I2C master 333 in accordance with the I2C standard under the control of the I2C master 333. For example, the I2C slave 361 can write ADC setting information to the register 364 under the control of the I2C master 333.

[0088] The I2S slave 362 communicates with the I2S master 353 in accordance with the I2S standard in accordance with communication control by the I2S master 353. For example, the I2S slave 362 converts audio data supplied from the AD converter 363 into SDATA in accordance with the I2S standard in accordance with the LRCLK and BCLK transmitted from the I2S master 353, and transmits the SDATA to the I2S master 353. The SDATA is made up of audio data for two channels, the microphone 106-1 and the microphone 106-2.

[0089] The AD converter 363 converts the analog audio signal supplied from the microphone 106 into an AD signal in accordance with the ADC setting information of the register 364 , and supplies the audio data obtained by the AD conversion to the I2S slave 362 .

[0090] The ADC device 105 is configured as described above.

[0091] FIG. 10 is a block diagram showing an example of the configuration of the BCLK generator 344.

[0092] As shown in FIG. 10, the BCLK generator 344 includes a controller register 371 , a TxREFCK generator 372 , a TxREFCK divider 373 , a BCLK generator core 374 , and an LRCLK generator 375 .

[0093] The slave-side controller 343 writes audio transmission setting information shown in FIG. 20, which will be described later, into the controller register 371 .

[0094] The TxREFCK generator 372 generates TxREFCK (=RxREFCK / (RxREFCK_INFO / TxREFCK_INFO)) by dividing or multiplying RxREFCK in accordance with TxREFCK_INFO and RxREFCK_INFO of the controller register 371, and supplies the generated TxREFCK to the TxREFCK generator 372. For example, if TxREFCK_INFO is 250 MHz, RxREFCK_INFO is 500 MHz, and RxREFCK is 500 MHz, the TxREFCK generator 372 generates a TxREFCK of 250 MHz (=500 MHz / (500 MHz / 250 MHz)). Note that if TxREFCK and RxREFCK are equal, it is not necessary for the TxREFCK generator 372 to generate TxREFCK, and the RxREFCK INFO field and TxREFCK INFO field of the controller register 371 are also not necessary.

[0095] The TxREFCK divider 373 divides the TxREFCK supplied from the TxREFCK generator 372 by the PMC_result(M) supplied from the A-Packet deconstructor 352 to restore BCLK_Div (=TxREFCK / PMC_result(M)), and supplies it to the BCLK generator core 374. For example, as shown in FIG. 11, if TxREFCK is 250 MHz and PMC_result(M) is 15625, the TxREFCK divider 373 restores BCLK_Div of 16 kHz (=250 MHz / 15625).

[0096] The BCLK generator core 374 multiplies BCLK_Div supplied from the TxREFCK divider 373 by the N value supplied from the controller register 371 to restore BCLK (=BCLK_Div × N), which it supplies to the LRCLK generator 375 and also outputs to the outside. For example, as shown in Figure 11, if BCLK_Div is 16 kHz and the N value is 768, the BCLK generator core 374 restores a BCLK of 12.288 MHz (=16 kHz × 768).

[0097] The LRCLK generator 375 divides the BCLK supplied from the BCLK generator core 374 by parameters (SDBW and Number of channels) supplied from the controller register 371 to restore LRCLK (=BCLK / (SDBW × ch)), and outputs it to the outside. For example, if BCLK is 12.288 MHz, SDBW is 32, and the Number of channels is 8, the LRCLK generator 375 restores an LRCLK of 48 kHz (=12.288 MHz / (32 × 8)).

[0098] The BCLK generator 344 is configured as described above.

[0099] The communication system 101 configured as described above utilizes RTBC that uses the time synchronization function of the A-PHY network, and can store SDATA (I2S data: audio data that conforms to the I2S standard) in A-Packets and transmit it via the A-PHY network.

[0100] The flow of data in the communication system 101 will now be described.

[0101] First, the ADC devices 105-1 and 105-2 require ADC setting information for AD conversion of analog sound signals input from the microphones 106-1 and 106-2, respectively. Therefore, the I2C master 201 of the ECU 102 transmits the ADC setting information as I2C data to the I2C slaves 361-1 and 361-2 via the PAL-I2C 211 functioning as an ICAM and the PAL-I2C 303 functioning as an ICAS. The I2C slave 361-1 receives the I2C data and writes the ADC setting information to the register 364-1, and the I2C slave 361-2 receives the I2C data and writes the ADC setting information to the register 364-2.

[0102] Before transmitting via I2S, the ECU 102 writes necessary information from among the audio transmission setting information (see FIG. 20 , which will be described later) to the PAL_I2S master side register 232 and the PAL_I2S slave side register 342 via the PAL-I2C 211 functioning as an ICAM and the PAL-I2C 303 functioning as an ICAS. Note that the ECU 102 may write the audio transmission setting information via the PAL-I2C 211 and the PAL-I2C 303, or may use a method such as PAL-SPI.

[0103] The PAL-Audio 212 measures the BCLK of the I2S signal received from the I2S master 202 using RTBC, converts it into A-Packets, and supplies them to the frame constructor 252. The PAL-Audio 212 also restores the I2S data of the microphones 106-1 and 106-2 supplied from the frame deconstructor 253, and transmits it to the I2S master 202 as SDATA.

[0104] When transmitting data received from the PAL-Audio 212 to the A-PHY serializer 104 , the frame constructor 252 stores the received data in the A-Packet payload to construct an A-Packet, and supplies it to the uplink 261 .

[0105] When the frame decoder 253 receives an A-Packet from the downlink 262, it references the Adaptation Type in the A-Packet header, and if the Adaptation Type indicates (7), it supplies the Audio packet stored in the A-Packet payload to the PAL-Audio 212, which functions as an ISAM.

[0106] The uplink 261 of the PHY layer 214 transmits an A-Packet to the uplink 311 of the A-PHY serializer 104 via the A-PHY network. The downlink 262 of the PHY layer 214 receives the A-Packet transmitted from the downlink 312 of the A-PHY serializer 104 via the A-PHY network.

[0107] The uplink 311 of the PHY layer 301 receives an A-Packet transmitted from the uplink 261 of the A-PHY deserializer 103 via the A-PHY network, and supplies the A-Packet to the frame deconstructor 321. The downlink 312 of the PHY layer 301 transmits the A-Packet supplied from the frame constructor 323 to the downlink 262 of the A-PHY deserializer 103 via the A-PHY network.

[0108] When the frame decoder 321 receives an A-Packet from the uplink 311, it refers to the Adaptation Type in the A-Packet header, and if the Adaptation Type indicates (7), it supplies the Audio packet stored in the A-Packet payload to the PAL-Audio 304, which functions as an ISAS.

[0109] When transmitting data received from the PAL-Audio 304 to the A-PHY deserializer 103 , the frame constructor 323 stores the received data in the A-Packet payload to construct an A-Packet, and supplies it to the downlink 312 .

[0110] The PAL-Audio 304 restores an I2S signal from the A-Packet supplied from the frame deconstructor 321 and transmits the I2S signal to the I2S slave 362-1 and the I2S slave 362-2. Furthermore, when the PAL-Audio 304 receives SDATA from the I2S slave 362-1 and the I2S slave 362-2, it generates an Audio packet to be stored in the A-Packet payload and supplies it to the frame constructor 323.

[0111] In the communication system 101, the above-described data flow enables the transmission of audio transmission setting information using I2C, the transmission of BCLK as an A-Packet, and the transmission of SDATA (I2S Data) via the A-PHY network. Note that, similar to the communication system 101 AD converting an analog audio signal input from the microphone 106 and transmitting it using I2S, the communication system 101 can also AD convert an analog acceleration signal input from an acceleration sensor (not shown) and transmit it using I2S.

[0112] FIG. 12 shows an example of the format of the Audio header.

[0113] The Audio header is 6 bytes if the Audio type is "1" (I2S) and the Timestamp type is "1" or "2", and is 2 bytes in all other cases.

[0114] The presentation timestamp can be used to set a future time when synchronizing audio and video data on multiple channels.

[0115] The relationship between the Start timestamp and the RTBC will be described with reference to FIGS.

[0116] 13 to 17 show examples of the start timestamp in each I2S mode.

[0117] FIG. 13 is a diagram showing an example of a start timestamp in the I2S mode.

[0118] As shown in FIG. 13, in the I2S mode, SDATA starts one bit later than the timing at which LRCLK falls, and the Start timestamp is set at the timing shown in the figure.

[0119] FIG. 14 is a diagram showing an example of a start timestamp in the I2S left justified mode.

[0120] As shown in FIG. 14, in the I2S left justified mode, SDATA starts in synchronization with the falling edge of LRCLK, and the Start timestamp is set at the timing shown in the figure.

[0121] FIG. 15 is a diagram showing an example of a Start timestamp in the I2S Right justified mode.

[0122] As shown in FIG. 15, in the I2S Right justified mode, SDATA starts so that it ends in synchronization with the falling edge of LRCLK, and the Start timestamp is set at the timing shown in the figure.

[0123] FIG. 16 is a diagram showing an example of a start timestamp in the TDM4 pulse mode.

[0124] As shown in FIG. 16, in the TDM4 pulse mode, SDATA of four channels is transmitted within fs [Hz] from the timing when 1-bit LRCLK rises, and the Start timestamp is set at the timing shown in the figure.

[0125] FIG. 17 is a diagram showing an example of a Start timestamp in TDM4 nopulse mode.

[0126] As shown in FIG. 17, in the TDM4 nopulse mode, SDATA of four channels is transmitted within fs [Hz] from the timing when LRCLK rises, and the Start timestamp is set at the timing shown in the figure.

[0127] FIG. 18 is a diagram showing an example of an Audio payload of an Audio packet.

[0128] As shown in FIG. 18, the Audio payload of the Audio packet stores the Data length, a 3-byte PMC_result[17:0], and a 4-byte CRC32.

[0129] FIG. 19 is a diagram showing an example of I2S data for each SDBW (I2S Data Bit Width).

[0130] As shown in FIG. 19, SDBW is set to 8 bits, 12 bits, 16 bits, 20 bits, 24 bits, and 32 bits.

[0131] Fig. 20 is a diagram showing a detailed example of audio transmission setting information written to the PAL_I2S slave-side register of Fig. 7 or Fig. 26. Note that only necessary information out of the information shown in Fig. 20 is written to the PAL_I2S master-side register 232 of Fig. 3 or Fig. 22.

[0132] For example, the I2S master mode and target clock select are always stored in the PAL_I2S master side register 232. The SDBW and number of channels may be stored in the PAL_I2S master side register 232. The coefficient K may be stored in the PAL_I2S master side register 232. The divisor N is always stored in the PAL_I2S master side register 232. When TxREFCK ≠ RxREFCK, TxREFCK_INFO and RxREFCK_INFO are always stored in the PAL_I2S slave side register 342.

[0133] <Second Configuration Example of Communication System> A configuration example of a second embodiment of a communication system to which the present technology is applied will be described with reference to FIGS. 21 to 29 .

[0134] FIG. 21 is a block diagram showing an example of the configuration of a communication system 101A.

[0135] 21, a communication system 101A includes an ECU 102A, an A-PHY serializer 104A, an A-PHY deserializer 103A, and digital-to-analog converter (DAC) devices 107-1 and 107-2. Speakers 108-1 and 108-2 are connected to the DAC devices 107-1 and 107-2, respectively.

[0136] The ECU 102A and the A-PHY serializer 104A are connected in accordance with the I2C and I2S standards. The A-PHY serializer 104A and the A-PHY deserializer 103A are connected via an A-PHY network. The A-PHY deserializer 103A and the DAC device 107-1 and the DAC device 107-2 are connected in accordance with the I2C and I2S standards, respectively.

[0137] 21, the ECU 102A and A-PHY serializer 104A are on the source side, and the A-PHY deserializer 103A and the DAC devices 107-1 and 107-2 are on the sink side. Audio packets conforming to the I2S standard that store audio data of sounds to be output from the speakers 108-1 and 108-2 are stored in the A-Packet payload of an A-Packet and transmitted from the source side to the sink side.

[0138] The ECU 102A, like the ECU 102 in FIG. 2, has a function as an I2C and I2S master in the communication system 101A.

[0139] Similar to the A-PHY serializer 104 in FIG. 2, the A-PHY serializer 104A generates an A-Packet in which the audio data supplied from the ECU 102A is stored in the A-Packet payload, and transmits the A-Packet to the sink side via the A-PHY network.

[0140] Similar to the A-PHY deserializer 103 in FIG. 2, the A-PHY deserializer 103A receives an A-Packet containing an Audio packet transmitted from the source side via the A-PHY network, obtains audio data conforming to the I2S standard from the A-Packet, and supplies it to the DAC device 107-1 and the DAC device 107-2.

[0141] The DAC devices 107-1 and 107-2 have functions as I2C and I2S slaves, respectively, and perform DA conversion of audio data supplied from the A-PHY deserializer 103A into analog sound signals, which are supplied to the speakers 108-1 and 108-2, respectively. Note that the DAC devices 107-1 and 107-2 are configured in the same way, and when there is no need to distinguish between them, they will be simply referred to as the DAC device 107.

[0142] The speakers 108-1 and 108-2 output sounds in response to analog sound signals supplied from the DAC devices 107-1 and 107-2, respectively. Note that the speakers 108-1 and 108-2 have the same configuration, and when there is no need to distinguish between them, they will be simply referred to as the speakers 108.

[0143] In addition, in the communication system 101A, similar to the communication system 101 of FIG. 2, A-Packets storing I2C packets, CFS A-Packets storing frequency offsets, and the like are transmitted and received via the A-PHY network.

[0144] Fig. 22 is a block diagram showing an example configuration of an ECU 102A and an A-PHY serializer 104A. Note that in the ECU 102A shown in Fig. 22, components common to the ECU 102 in Fig. 3 are designated by the same reference numerals, and detailed descriptions thereof will be omitted. Also, in the A-PHY serializer 104A shown in Fig. 22, components common to the A-PHY deserializer 103 in Fig. 3 are designated by the same reference numerals, and detailed descriptions thereof will be omitted.

[0145] Furthermore, in the communication system 101A, audio packets are only transmitted in one direction from the source side to the sink side, and audio packets (I2S data) are not transmitted from the sink side to the source side as in the communication system 101 in Fig. 1. Therefore, in the A-PHY serializer 104A shown in Fig. 22, blocks that do not perform processing in the communication system 101A (blocks that perform processing to receive audio packets from the sink side) are indicated by dashed lines.

[0146] 22, the ECU 102A has a configuration similar to the ECU 102 in Fig. 3 in that it includes an I2C master 201 and an I2S master 202. The ECU 102A differs from the ECU 102 in that it is configured to supply an MCK (audio master clock signal), which is a clock signal required for transmitting SDATA, to an MCK divider 248 of the A-PHY serializer 104A. In the ECU 102A, SDATA for outputting sound from the speaker 108 is supplied from the I2S master 202 to the I2S slave 247.

[0147] As shown in Fig. 22, the A-PHY serializer 104A has a configuration common to the A-PHY deserializer 103 in Fig. 3 in that it is configured with a PAL-I2C 211 and a data link layer 213. The A-PHY serializer 104A has a configuration different from the A-PHY deserializer 103 in Fig. 3 in that it is configured with a PAL-Audio 212A and a PHY layer 214A.

[0148] The PAL-Audio 212A has a configuration common to the PAL-Audio 212 in Fig. 3 in that it includes an I2C slave 231, a PAL_I2S master-side register 232, and a controller 233. The PAL-Audio 212A has a configuration different from the PAL-Audio 212 in Fig. 3 in that it includes a PAL_I2S encoder 234A.

[0149] The PAL_I2S encoder 234A has a configuration in common with the PAL_I2S encoder 234 in Fig. 3 in that it has a PMC 242, an A-Packet constructor 243, an I2S encode FIFO 244, an I2S decode FIFO 245, an A-Packet deconstructor 246, and an I2S slave 247. The PAL_I2S encoder 234A has a configuration different from the PAL_I2S encoder 234 in Fig. 3 in that it includes an MCK divider 248.

[0150] The MCK divider 248 divides the MCK supplied from the ECU 102A in accordance with the N value supplied from the controller 233, and supplies MCK_Div obtained by this division to the PMC 242. For example, as shown in FIG. 23 , if the MCK is 24.576 MHz and the N value is 1536, the MCK divider 248 supplies 16 KHz (= 24.576 MHz / 1536) obtained as MCK_Div to the PMC 242.

[0151] Then, in the PAL_I2S encoder 234A, the I2S slave 247 supplies the SDATA supplied from the I2S master 202 to the A-Packet constructor 243. The A-Packet constructor 243 generates an audio packet (see FIG. 24 ) made up of an audio header and audio payload to be stored in the A-Packet payload in accordance with the RTBC supplied from the running time base counter 251 in the data link layer 213, the LRCLK and BCLK supplied from the I2S master 202, PMC_result(M) (=15625) supplied from the PMC 242, and parameters (Number of channels and SDBW) supplied from the controller 233, and writes the generated audio packet to the I2S encode FIFO 244.

[0152] 24, the Audio header includes Audio Type, CRC Type, Time Stamp Type, I2S Packet Type, and Audio Packet ID, and the Audio payload includes Data length, 3 Bytes of PMC_result[17:0], 125 Bytes of I2S data, and 4 Bytes of CRC32. As such, in the communication system 101A, since SDATA needs to be transmitted by Audio packets, (1) is set in the I2S Packet Type of the Audio header.

[0153] When storing a PAL_Audio A-Packet in the A-Packet payload (see FIG. 21 described above), the frame constructor 252 reads the Audio header and Audio payload from the I2S encoding FIFO 244 and stores them in the A-Packet payload.

[0154] The PHY layer 214A has an uplink 261A and a downlink 262A, and performs physical layer processing. In the communication system 101A, the uplink 261A is the receiving side (Rx), and the downlink 262A is the transmitting side (Tx). In the PHY layer 214A, the downlink 262A transmits the A-Packet provided from the frame constructor 252 to the A-PHY network.

[0155] The ECU 102A and the A-PHY serializer 104A are configured as described above.

[0156] The A-PHY serializer 104A divides the MCK required for transmitting SDATA according to the N value, counts the MCK_Div obtained by this division according to TxREFCK, and generates an Audio packet in which the count result PMC_result(M) and SDATA (I2S data) are stored in the Audio payload.The A-PHY serializer 104A can then store this Audio packet in an Audio packet conforming to the A-PHY standard and transmit it over the A-PHY network.

[0157] FIG. 25 shows a modified example of the PAL-Audio 212A.

[0158] In the PAL-Audio 212A of FIG. 22, MCK is supplied from the ECU 102A to the MCK divider 248, but, for example, MCK may be generated from BCLK within the PAL-Audio 212A.

[0159] That is, the PAL-Audio 212A' shown in FIG. 25 is different in configuration from the PAL-Audio 212A shown in FIG. 22 in that it is configured to include an MCK generator 235.

[0160] The MCK generator 235 generates an MCK (=BCLK×{K / (SDBW×ch)}) by multiplying the BCLK supplied from the ECU 102A in accordance with parameters (K value, SDBW, and number of channels) supplied from the controller 233, and supplies the MCK to the MCK divider 248. For example, if the K value is 512, the SDBW is 32, and the number of channels is 8, the MCK generator 235 generates an MCK of 24.576 MHz (=12.288 MHz×{512 / (32×8)}).

[0161] In this way, the PAL-Audio 212A' can generate MCK from BCLK.

[0162] Fig. 26 is a block diagram showing an example configuration of an A-PHY deserializer 103A. Note that in the A-PHY deserializer 103A shown in Fig. 26, components common to the A-PHY serializer 104 in Fig. 7 are assigned the same reference numerals, and detailed description thereof will be omitted. Also in the A-PHY deserializer 103A shown in Fig. 26, blocks that do not perform processing in the communication system 101A (blocks that perform processing to transmit Audio packets to the source side) are shown with dashed lines.

[0163] As shown in Fig. 26, the A-PHY deserializer 103A has a configuration common to the A-PHY serializer 104 in Fig. 7 in that it includes a data link layer 302 and a PAL-I2C 303. The A-PHY deserializer 103A has a configuration different from the A-PHY serializer 104 in Fig. 7 in that it includes a PHY layer 301A and a PAL-Audio 304A.

[0164] The PHY layer 301A has an uplink 311A ​​and a downlink 312A, and performs physical layer processing. In the communication system 101A, the uplink 311A ​​is the transmitting side (Tx), and the downlink 312 is the receiving side (Rx). In the PHY layer 301A, the downlink 312A receives an A-Packet transmitted from the A-PHY network and supplies it to a frame deconstructor 321 in the data link layer 302.

[0165] 7 in that it has an I2C slave 341, a PAL_I2S slave-side register 342, a slave-side controller 343, and a PAL_I2S encoder / decoder 345, and functions as, for example, an ISAS (see FIG. 1). The PAL-Audio 304A differs from the PAL-Audio 304 in that it has an MCK generator 346. In the communication system 101A, the I2S master 353 operates in a transmission mode in which it transmits SDATA to the DAC device 107, according to the setting value of the I2S master mode in FIG. 20.

[0166] The MCK generator 346 generates an MCK based on the RxREFCK supplied from the running time base counter 322, the PMC_result(M) (=15625) supplied from the A-Packet deconstructor 352, and parameters supplied from the slave-side controller 343. The MCK generator 346 then supplies the MCK to the I2S master 353, and may also transmit the MCK to the DAC device 107. Note that a detailed configuration of the MCK generator 346 will be described later with reference to FIG. 28 .

[0167] The A-PHY deserializer 103A is configured as described above.

[0168] The A-PHY deserializer 103A receives an Audio packet via the A-PHY network, obtains the PMC_result(M) stored in the Audio payload of the Audio packet, and can restore the MCK by referring to the RxREFCK based on the PMC_result(M).

[0169] Fig. 27 is a block diagram showing an example of the configuration of the DAC device 107. Note that in the DAC device 107 shown in Fig. 27, components common to those of the ADC device 105 in Fig. 8 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0170] As shown in Fig. 27, the DAC device 107 has a configuration in common with the ADC device 105 in Fig. 8 in that it includes an I2C slave 361 and an I2S slave 362. The DAC device 107 has a configuration different from the ADC device 105 in Fig. 8 in that it includes a DA converter 365 and a register 366.

[0171] In the DAC device 107, the I2C slave 361 can write DAC setting information to a register 366 under the control of the I2C master 333. Furthermore, the I2S slave 362 converts the SDATA transmitted from the I2S master 353 into audio data in accordance with the I2S standard, in accordance with the LRCLK, BCLK, and, if necessary, MCK transmitted from the I2S master 353, and supplies the SDATA to the DA converter 365. The SDATA is made up of audio data for two channels, the speaker 108-1 and the speaker 108-2.

[0172] The DA converter 365 performs DA conversion on the audio data supplied from the I2S slave 362 in accordance with the DAC setting information in the register 366 , and supplies the analog sound signal obtained by the DA conversion to the speaker 108 .

[0173] The DAC device 107 is configured as described above.

[0174] Fig. 28 is a block diagram showing an example of the configuration of the MCK generator 346. In the MCK generator 346 shown in Fig. 28, components common to those in the BCLK generator 344 in Fig. 10 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0175] 28, the MCK generator 346 has a configuration common to the BCLK generator 344 in Fig. 10 in that it includes a controller register 371, a TxREFCK generator 372, and a TxREFCK divider 373. The MCK generator 346 is configured to include an MCK generator core 376 and a BCLK / LRCLK generator 377.

[0176] In the MCK generator 346, the TxREFCK divider 373 restores MCK_Div (=TxREFCK / PMC_result(M)) in the same way as BCLK_Div, and supplies it to the MCK generator core 376. For example, as shown in FIG. 29, if TxREFCK is 250 MHz and PMC_result(M) is 15625, the TxREFCK divider 373 restores MCK_Div of 16 kHz (=250 MHz / 15625).

[0177] The MCK generator core 376 multiplies the MCK_Div supplied from the TxREFCK divider 373 by the N value supplied from the controller register 371 to restore MCK (=MCK_Div × N), and supplies this to the BCLK / LRCLK generator 377 and also outputs it to the outside. For example, as shown in Figure 29, if MCK_Div is 16 kHz and the N value is 1536, the MCK generator core 376 restores an MCK of 24.576 MHz (=16 kHz × 1536).

[0178] The BCLK / LRCLK generator 377 first calculates the division value (= K / (SDBW × ch)) by which to divide MCK to restore BCLK, based on the parameters (K value, SDBW, number of channels) supplied from the controller register 371. The BCLK / LRCLK generator 377 then multiplies the MCK supplied from the MCK generator core 376 by that division value to restore BCLK (= MCK / division value). Furthermore, the BCLK / LRCLK generator 377 divides BCLK based on BCLK and the parameters (SDBW and number of channels) supplied from the controller register 371 to restore LRCLK (= BCLK / (SDBW × ch)).

[0179] The MCK generator 346 is configured as described above.

[0180] The communication system 101A configured as described above utilizes RTBC that uses the time synchronization function of the A-PHY network, and can store SDATA (I2S data: audio data that conforms to the I2S standard) in A-Packets and transmit it via the A-PHY network.

[0181] The flow of data in the communication system 101A will be described.

[0182] First, DAC device 107-1 and DAC device 107-2 require DAC setting information for digital-to-analog conversion of analog sound signals to be output to speakers 108-1 and 108-2, respectively. Therefore, I2C master 201 of ECU 102A transmits the DAC setting information as I2C data to I2C slave 361-1 and I2C slave 361-2 via PAL-I2C 211 functioning as ICAM and PAL-I2C 303 functioning as ICAS. I2C slave 361-1 receives the I2C data and writes the DAC setting information to register 366-1, and I2C slave 361-2 receives the I2C data and writes the DAC setting information to register 366-2.

[0183] Before transmitting via I2S, the ECU 102A writes necessary information from the audio transmission setting information (see FIG. 20 described above) to the PAL_I2S master side register 232 and the PAL_I2S slave side register 342 via the PAL-I2C 211 functioning as ICAM and the PAL-I2C 303 functioning as ICAS. Note that the ECU 102A may write the audio transmission setting information via the PAL-I2C 211 and the PAL-I2C 303, or may use a method such as PAL-SPI.

[0184] The PAL-Audio 212 A measures the MCK received from the ECU 102 A using RTBC, converts it into an A-Packet together with SDATA, and supplies it to the frame constructor 252 .

[0185] When transmitting data received from the PAL-Audio 212A to the A-PHY deserializer 103A, the frame constructor 252 stores the received data in the A-Packet payload to construct an A-Packet, and supplies the A-Packet to the downlink 262A.

[0186] The downlink 262A of the PHY layer 214A transmits the A-Packet over the A-PHY network to the downlink 312A of the A-PHY deserializer 103A.

[0187] The downlink 312A of the PHY layer 301A receives an A-Packet transmitted from the downlink 262A of the A-PHY serializer 104A via the A-PHY network, and supplies the A-Packet to a frame deconstructor 321.

[0188] When the frame decoder 321 receives an A-Packet from the downlink 312A, it refers to the Adaptation Type in the A-Packet header, and if the Adaptation Type indicates (7), it supplies the Audio packet stored in the A-Packet payload to the PAL-Audio 304A, which functions as an ISAS.

[0189] The PAL-Audio 304A restores the I2S signal from the A-Packet supplied from the frame deconstructor 321, and transmits the I2S signal to the I2S slave 362-1 and the I2S slave 362-2.

[0190] The I2S slave 362-1 supplies the I2S data to a DA converter 365-1, which then supplies an analog sound signal obtained by DA converting the I2S data to the speaker 108-1, causing sound to be output from the speaker 108-1. Similarly, the I2S slave 362-2 supplies the I2S data to a DA converter 365-2, which then supplies an analog sound signal obtained by DA converting the I2S data to the speaker 108-2, causing sound to be output from the speaker 108-2.

[0191] In the communication system 101A, the above-described data flow enables audio transmission setting information to be transmitted using I2C via the A-PHY network, BCLK and MCK to be converted into A-Packets and transmitted, and SDATA (I2S Data) to be transmitted.

[0192] <Examples of Combinations of Configurations> The present technology can also be configured as follows: (1) A communication system comprising: a transmitting device that divides a clock signal required for transmitting audio data conforming to the I2S (Inter-IC Sound) standard according to a predetermined N value, counts the divided clock signal obtained by the division according to a predetermined transmission reference frequency, generates an audio packet having the count result stored in an audio payload, stores the audio packet in an audio packet conforming to the A-PHY (The Automotive PHY) standard, and transmits the audio packet via an A-PHY network; and a receiving device that receives the A-Packet via the A-PHY network, obtains the count result stored in the audio payload of the audio packet stored in the A-Packet, refers to the transmission reference frequency based on the count result, and restores the clock signal. (2) The communication system described in (1) above, wherein the clock signal is BCLK or MCK required for transmitting SDATA, which is audio data conforming to the I2S standard. (3) The communication system according to (1), further comprising: a control device connected to the first communication device in accordance with the I2S and I2C (Inter-Integrated Circuit) standards, the control device having an I2S master that controls communication via the I2S, and an I2C master that controls communication via the I2C, and a device connected to the second communication device in accordance with the I2S and I2C standards, the control device having an I2S slave that performs communication according to the I2S standard under communication control by the I2S master via the A-PHY network, and an I2C slave that performs communication according to the I2C standard under communication control by the I2C master. (4) The communication system according to (3), wherein the first communication device and the second communication device time-synchronize the clock signals using a CFS (Clock Forwarding Service) A-Packet that conforms to the A-PHY standard.(5) The communication system according to (4), wherein the I2C master writes audio transmission setting information, in which information necessary for transmitting SDATA, which is audio data conforming to the I2S standard, is set, into a first register possessed by the first communication device. (6) The communication system according to (5), wherein the first communication device functions as the I2S adaptation layer connected to the native I2S master and includes a first PAL-Audio having the first register, and the second communication device is the I2S adaptation layer connected to the native I2S slave and includes a second PAL-Audio having a second register into which the audio transmission setting information is written. (7) The communication system according to (6), wherein the device is an ADC (Analog to Digital Converter) device that acquires audio data by AD converting an analog sound signal of sound picked up by a microphone, and the I2S slave converts the audio data into SDATA and transmits it to the second communication device. (8) The communication system according to (7), wherein the first PAL-Audio has: a clock divider that divides the clock signal in accordance with the value N; a counter that counts the count result of the divided clock signal in accordance with the transmission reference frequency; and a first packet generator that generates the Audio packet having the count result stored in the Audio payload. (9) The communication system according to (7), wherein the second PAL-Audio has: a clock recovery unit that refers to the transmission reference frequency and recovers the clock signal based on the count result; a packet disassembly unit that acquires the count result from the Audio packet having the count result stored in the Audio payload based on the clock signal; and a second packet generator that stores the SDATA in the Audio payload based on the clock signal to generate the Audio packet.(10) The communication system according to (6), wherein the I2S slave converts the SDATA transmitted from the second communication device into audio data, and the device is a DAC (Digital to Analog Converter) device that performs DA conversion of the audio data into an analog sound signal and supplies the analog sound signal to a speaker that outputs sound in accordance with the sound signal. (11) The communication system according to (10), wherein the first PAL-Audio has: a clock divider that divides the clock signal in accordance with the N value, a counting unit that counts the count result of the divided clock signal in accordance with the transmission reference frequency, and a packet generator that generates the Audio packet having the count result and the SDATA stored in the Audio payload. (12) The communication system described in (11) above, wherein the second PAL-Audio includes: a clock recovery unit that refers to the transmission reference frequency based on the counting result and recovers the clock signal; and a packet disassembly unit that acquires the counting result and the SDATA from the Audio packet in which the SDATA is stored in the Audio payload based on the clock signal. (13) A communication method including: a communication system: dividing a clock signal required for transmitting audio data conforming to the I2S (Inter-IC Sound) standard according to a predetermined N value; counting the divided clock signal obtained by the division according to a predetermined transmission reference frequency; generating an Audio packet having the count result stored in the Audio payload; storing the Audio packet in an A-Packet conforming to the A-PHY (The Automotive PHY) standard; and transmitting the A-PHY network; receiving the A-Packet via the A-PHY network; obtaining the count result stored in the Audio payload of the Audio packet stored in the A-Packet; and restoring the clock signal by referring to the transmission reference frequency based on the count result.

[0193] It should be noted that the present embodiment is not limited to the above-described embodiment, and various modifications are possible within the scope of the gist of the present disclosure. Furthermore, the effects described in this specification are merely examples and are not intended to be limiting, and other effects may also be obtained.

[0194] 11 I2S bus, 21 I2S master, 22 ISAM, 23 ISAS, 24 I2S slave, 101 Communication system, 102 ECU, 103 A-PHY deserializer, 104 A-PHY serializer, 105 ADC device, 106 Microphone, 107 DAC device, 108 Speaker

Claims

1. A communication system comprising: a first communication device that divides a clock signal required for transmitting audio data in accordance with the I2S (Inter-IC Sound) standard in accordance with a predetermined N value, counts the divided clock signal obtained by the division in accordance with a predetermined transmission reference frequency, generates an Audio packet having the count result stored in the Audio payload, stores the Audio packet in an A-Packet that complies with the A-PHY (The Automotive PHY) standard, and transmits the A-PHY network; and a second communication device that receives the A-Packet via the A-PHY network, obtains the count result stored in the Audio payload of the Audio packet stored in the A-Packet, and restores the clock signal based on the count result by referring to a predetermined reception reference frequency.

2. The communication system according to claim 1, wherein the clock signal is BCLK or MCK required for transmitting SDATA, which is audio data conforming to the I2S standard.

3. The communication system according to claim 1, further comprising: a control device connected to the first communication device in accordance with the I2S and I2C (Inter-Integrated Circuit) standards, and having an I2S master that controls communication via the I2S, and an I2C master that controls communication via the I2C; and a device connected to the second communication device in accordance with the I2S and I2C standards, and having an I2S slave that communicates via the A-PHY network in accordance with communication control by the I2S master, and an I2C slave that communicates in accordance with the I2C standard in accordance with communication control by the I2C master.

4. The communication system according to claim 3, wherein the first communication device and the second communication device synchronize the time of the clock signals using a CFS (Clock Forwarding Service) A-Packet conforming to the A-PHY standard.

5. The communication system according to claim 4, wherein the I2C master writes audio transmission setting information, which contains information necessary for transmitting SDATA, which is audio data conforming to the I2S standard, into a first register possessed by the first communication device.

6. The communication system according to claim 5, wherein the first communication device functions as an adaptation layer of the I2S connected to the native I2S master and has a first PAL-Audio having the first register, and the second communication device is an adaptation layer of the I2S connected to the native I2S slave and has a second PAL-Audio having a second register into which the audio transmission setting information is written.

7. The communication system according to claim 6, wherein the device is an ADC (Analog to Digital Converter) device that acquires audio data by AD converting an analog sound signal of a sound picked up by a microphone, and the I2S slave converts the audio data into SDATA and transmits it to the second communication device.

8. The communication system according to claim 7, wherein the first PAL-Audio comprises: a clock divider that divides the clock signal in accordance with the N value; a counting unit that counts the count result of the divided clock signal in accordance with the transmission reference frequency; and a first packet generating unit that generates the Audio packet with the count result stored in the Audio payload.

9. The communication system of claim 7, wherein the second PAL-Audio comprises: a clock recovery unit that references the transmission reference frequency based on the counting result and recovers the clock signal; a packet disassembly unit that acquires the counting result from the Audio packet in which the counting result is stored in the Audio payload based on the clock signal; and a second packet generation unit that stores the SDATA in the Audio payload based on the clock signal to generate the Audio packet.

10. The communication system according to claim 6, wherein the I2S slave converts the SDATA transmitted from the second communication device into audio data, and the device is a DAC (Digital to Analog Converter) device that performs DA conversion of the audio data into an analog sound signal and supplies the sound signal to a speaker that outputs sound in accordance with the sound signal.

11. The communication system according to claim 10, wherein the first PAL-Audio comprises: a clock dividing unit that divides the clock signal in accordance with the N value; a counting unit that counts the count result of the divided clock signal in accordance with the transmission reference frequency; and a packet generating unit that generates the Audio packet in which the count result and the SDATA are stored in the Audio payload.

12. The communication system of claim 10, wherein the second PAL-Audio comprises: a clock recovery unit that references the transmission reference frequency based on the counting result and recovers the clock signal; and a packet disassembly unit that acquires the counting result and the SDATA from the Audio packet in which the SDATA is stored in the Audio payload based on the clock signal.

13. A communications method comprising: a communications system dividing a clock signal required for transmitting audio data in accordance with the I2S (Inter-IC Sound) standard in accordance with a predetermined N value, counting the divided clock signal obtained by the division in accordance with a predetermined transmission reference frequency, generating an Audio packet having the count result stored in the Audio payload, storing the Audio packet in an A-Packet in accordance with the A-PHY (The Automotive PHY) standard, and transmitting the A-PHY network; receiving the A-Packet via the A-PHY network, obtaining the count result stored in the Audio payload of the Audio packet stored in the A-Packet, and restoring the clock signal based on the count result by referring to a predetermined reception reference frequency.

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