Pixel circuit, driving method, display panel, and display device

Abstract

A pixel circuit, a driving method, a display panel, and a display device. The pixel circuit (10) comprises: a driving transistor (101) used for driving a light-emitting device (106'); a first light-emitting control unit (102), having one end electrically connected to a first constant voltage end, and the other end electrically connected to the driving transistor (101) by means of a first node, wherein the first light-emitting control unit (102) is used for controlling conduction or cutoff between the first constant voltage end and the first node under the action of a first light-emitting control signal; a first charge storage unit (103), having one end electrically connected to the first node, and the other end electrically connected to the driving transistor (101) by means of a second node; a data writing compensation unit (104) electrically connected to the driving transistor (101) by means of a third node and used for writing a data voltage signal to the third node under the action of a first driving signal; and a first charging unit (105) electrically connected to the second node and used for writing a first initial voltage signal to the second node under the action of a second driving signal.

Description

Pixel circuit, driving method, display panel and display device This application claims priority to Chinese Patent Application No. 202410467660.4, filed on April 18, 2024, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0001] The present disclosure relates to a pixel circuit, a driving method, a display panel and a display device. BACKGROUND

[0002] In the current OLED (Organic Light-Emitting Diode) or AMOLED (Active-matrix organic light-emitting diode) display panel technology, the switching characteristics of transistors are used to control the size of the driving current to make the display panel display different brightness.

[0003] However, due to the existence of transistor threshold voltage, it will increase the power consumption of the pixel circuit, and at the same time, due to the transistor threshold voltage drift and other situations, it will also affect the light emitting accuracy of the pixel circuit, so how to eliminate the influence of the transistor threshold voltage is particularly important for the development of display panel technology. SUMMARY

[0004] In a first aspect, the embodiments of the present disclosure provide a pixel circuit, comprising: a driving transistor configured to drive a light emitting device; a first light emitting control unit having one end electrically connected to a first constant voltage terminal and the other end electrically connected to a first electrode of the driving transistor through a first node, the first light emitting control unit configured to control conduction or cutoff between the first constant voltage terminal and the first node under the action of a first light emitting control signal; a first charge storage unit having one end electrically connected to the first node and the other end electrically connected to a gate of the driving transistor through a second node, the first charge storage unit configured to release charges to the first node and the second node to dynamically balance the potential of the first node and the potential of the second node; a data writing compensation unit electrically connected to a second electrode of the driving transistor through a third node, the data writing compensation unit configured to write a data voltage signal to the third node under the action of a first driving signal, the data voltage signal having a voltage value less than a voltage value of the first constant voltage terminal; and a first charging unit electrically connected to the second node, the first charging unit configured to write a first initial voltage signal to the second node under the action of a second driving signal, the first initial voltage signal having a voltage value capable of driving the driving transistor to conduct.

[0005] In some embodiments, the pixel circuit further comprises:

[0006] a second light emitting control unit having one end electrically connected to the third node and the other end electrically connected to the light emitting device through a fourth node, the second light emitting control unit configured to control conduction or cutoff between the third node and the fourth node under the action of a second light emitting control signal.

[0007] In some embodiments, the pixel circuit further comprises:

[0008] a reset unit electrically connected to the fourth node, the reset unit configured to write a second initial voltage signal to the fourth node under the action of a third driving signal.

[0009] In some embodiments, the pixel circuit further comprises:

[0010] a second charge storage unit, one end of the second charge storage unit being electrically connected with the second node, and the other end of the second charge storage unit being electrically connected with the fourth node, the second charge storage unit being configured to release charges to the second node and the fourth node to dynamically balance the potential of the second node and the potential of the fourth node.

[0011] In some embodiments, the starting time of the effective level of the third driving signal is the same as the starting time of the effective level of the second driving signal, and the ending time of the effective level of the third driving signal is the same as the ending time of the effective level of the first driving signal.

[0012] In some embodiments, the first charge storage unit comprises an access subunit and a charge storage subunit, one end of the charge storage subunit being electrically connected with the second node, and the other end of the charge storage subunit being electrically connected with the first node, the access subunit being connected in series between the charge storage subunit and the first node or the second node; wherein the access subunit is configured to control whether the charge storage subunit is connected between the first node and the second node under the action of a fourth driving signal, and the charge storage subunit is configured to release charges to the first node and the second node to dynamically balance the potential of the first node and the potential of the second node.

[0013] In some embodiments, the pixel circuit further comprises:

[0014] a second charging unit, the second charging unit being electrically connected with the other end of the charge storage subunit, and the second charging unit being configured to write a third initial voltage signal into the charge storage subunit under the action of a fifth driving signal;

[0015] wherein the starting time of the effective level of the second driving signal is the same as the starting time of the effective level of the fifth driving signal, and the ending time of the effective level of the second driving signal is the same as the ending time of the effective level of the fifth driving signal.

[0016] In some embodiments, the access subunit comprises a first transistor, and the charge storage subunit comprises a first capacitor.

[0017] wherein a gate of the first transistor is configured to receive the fourth driving signal, one end of the first capacitor is electrically connected with the second node, and the other end of the first capacitor is electrically connected with the first node, and the first transistor is connected in series between the first capacitor and the first node or the second node.

[0018] In a second aspect, the embodiments of the present disclosure provide another pixel circuit, comprising: a driving transistor, a first light-emitting control unit, a second light-emitting control unit, a first charge storage unit, a second charge storage unit, a data writing compensation unit, a reset unit, and a first charging unit; the driving transistor comprises a zeroth transistor, a first electrode, a second electrode and a gate of the zeroth transistor are electrically connected with a first node, a third node and a second node respectively; the first light-emitting control unit comprises a second transistor, a gate of the second transistor is used for receiving a first light-emitting control signal, a first electrode of the second transistor is electrically connected with a first constant voltage terminal, and a second electrode of the second transistor is electrically connected with the first node; the data writing compensation unit comprises a third transistor, a gate of the third transistor is used for receiving a first driving signal, a first electrode of the third transistor is used for receiving a data voltage signal, and a second electrode of the third transistor is electrically connected with the third node; the second light-emitting control unit comprises a fourth transistor, a gate of the fourth transistor is used for receiving a second light-emitting control signal, a first electrode of the fourth transistor is electrically connected with the third node, and a second electrode of the fourth transistor is electrically connected with a light-emitting device through a fourth node; the first charging unit comprises a fifth transistor, a gate of the fifth transistor is used for receiving a second driving signal, a first electrode of the fifth transistor is used for receiving a first initial voltage signal, and a second electrode of the fifth transistor is electrically connected with the second node; the reset unit comprises a sixth transistor, a gate of the sixth transistor is used for receiving a third driving signal, a first electrode of the sixth transistor is used for receiving a second initial voltage signal, and a second electrode of the sixth transistor is electrically connected with the fourth node; the first charge storage unit comprises an access subunit and a charge storage subunit, the access subunit comprises a first transistor, the charge storage subunit comprises a first capacitor, a gate of the first transistor is used for receiving a fourth driving signal, one end of the first capacitor is electrically connected with the second node, the other end of the first capacitor is electrically connected with the first node, and the first transistor is connected in series between the first capacitor and the first node or the second node; the second charge storage unit comprises a second capacitor, and the second capacitor is connected in series between the second node and the fourth node.

[0019] In some embodiments, the pixel circuit further comprises:

[0020] a second charging unit, the second charging unit comprising a seventh transistor, a gate of the seventh transistor being used for receiving a fifth driving signal, a first electrode of the seventh transistor being electrically connected with the other end of the first capacitor, and a second electrode of the seventh transistor being used for receiving a third initial voltage signal; wherein the effective level of the second driving signal and the fifth driving signal has the same starting time and ending time.

[0021] In some embodiments, the voltage value of the data voltage signal is less than the voltage value of the first constant voltage terminal; the voltage value of the first initial voltage signal is capable of driving the driving transistor to turn on; the starting time of the active level of the first driving signal is later than or equal to the ending time of the active level of the second driving signal; the starting times of the active levels of the second driving signal, the third driving signal and the fourth driving signal are all the same, and the ending times of the active levels of the first driving signal, the third driving signal and the fourth driving signal are the same.

[0022] In a third aspect, the embodiments of the present disclosure provide a display panel, comprising a plurality of pixel circuits as described in any one of the first aspect or the second aspect.

[0023] In some embodiments, the first driving signal received by the pixel circuit of the nth row is the same as the second driving signal received by the pixel circuit of the (n-1)th row, n being an integer greater than or equal to 2.

[0024] In a fourth aspect, the embodiments of the present disclosure provide a driving method of a pixel circuit, for driving a pixel circuit as described in any one of the first aspect or the second aspect, the driving method comprising: in a reset phase, controlling the first light emitting control unit to turn on to make the first constant voltage terminal and the first node conductive, and controlling the first charging unit to write a first initial voltage signal to the second node; in a write compensation phase, controlling the first light emitting control unit to turn off to make the first constant voltage terminal and the first node cut off, and controlling the data write compensation unit to write the data voltage signal to the third node; in a light emitting phase, controlling the first light emitting control unit to turn on to make the first constant voltage terminal and the first node conductive, so that the driving transistor drives the light emitting device to emit light.

[0025] In some embodiments, the pixel circuit further comprises a second light emitting control unit and a reset unit, one end of the second light emitting control unit is electrically connected with the third node, and the other end is electrically connected with the light emitting device through a fourth node, and the reset unit is electrically connected with the fourth node, and

[0026] The driving method further comprises:

[0027] In the reset phase, the second light emitting control unit is controlled to turn on to make the third node and the fourth node conductive, and the reset unit is controlled to write a second initial voltage signal to the fourth node.

[0028] In some embodiments, when the pixel circuit further comprises a second charge storage unit, one end of the second charge storage unit is electrically connected with the second node, and the other end of the second charge storage unit is electrically connected with the fourth node,

[0029] The driving method further comprises:

[0030] In the write compensation phase, the reset unit is controlled to write the second initial voltage signal to the fourth node.

[0031] In some embodiments, the first charge storage unit comprises an access subunit and a charge storage subunit, one end of the charge storage subunit is electrically connected with the second node, the other end of the charge storage subunit is electrically connected with the first node or the second node, and the access subunit is connected in series between the charge storage subunit and the first node or the second node,

[0032] The driving method further comprises:

[0033] In the light emitting phase, the access subunit is controlled to be closed, so that the access between the charge storage subunit and the access subunit is disconnected.

[0034] In a fifth aspect, the embodiments of the present disclosure provide a controller, comprising: a memory storing a computer program; and a processor configured to invoke the computer program in the memory, the computer program being configured to execute the driving method according to any one of the fourth aspect.

[0035] In a sixth aspect, the embodiments of the present disclosure provide a display device, comprising the display panel according to any one of the third aspect and / or the controller according to the fifth aspect.

[0036] In summary, according to the pixel circuit provided by the embodiment of the present disclosure, the first charging unit writes the first initial voltage signal and the first constant voltage into the two ends of the first charge storage unit under the action of the active level of the second driving signal and the action of the first light-emitting control unit under the action of the first light-emitting control signal, and stores the voltage by using the first charge storage unit. Subsequently, the first charging unit and the first light-emitting control unit are closed, and the data writing compensation unit writes the data voltage signal into the third node under the action of the first driving signal. Since the voltage value of the first initial voltage signal can make the driving transistor conduct, a path is formed between the first electrode and the second electrode of the driving transistor connected between the first node and the second node, therefore, the charges of the first node continuously flow into the second node, the potential of the first node decreases, and the first charge storage unit controls the dynamic balance between the potentials of the first node and the second node, so that the potential of the second node decreases with the potential of the first node, and the potential of the third node does not change under the action of the data voltage signal, therefore, the gate-source voltage of the driving transistor gradually decreases to the threshold voltage, that is, the gate potential of the driving transistor is the sum of the voltage value of the data voltage signal and the threshold voltage, so as to complete the compensation of the threshold voltage of the driving transistor. Compared with the related art, the threshold voltage of the driving transistor is written to compensate the threshold voltage, that is, the gate potential is increased to compensate the threshold voltage, and the embodiment of the present disclosure reduces the gate potential, so that the voltage between the gate and the source of the driving transistor is the threshold voltage, so that the threshold voltage compensation of the driving transistor can be completed even if the threshold voltage is negative. Therefore, the pixel circuit provided by the embodiment of the present disclosure can more comprehensively compensate the threshold voltage of the driving transistor. BRIEF DESCRIPTION OF DRAWINGS

[0037] Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are for purposes of illustration only and are not considered a limitation of the present application. Moreover, like reference numerals are used to designate like parts throughout the specification and the figures. In the drawings:

[0038] FIG. 1 is a schematic block diagram of a pixel circuit according to an embodiment of the present disclosure;

[0039] FIG. 2 is a schematic block diagram of another pixel circuit according to an embodiment of the present disclosure;

[0040] FIG. 3 is a schematic block diagram of another pixel circuit according to an embodiment of the present disclosure;

[0041] FIG. 4 is a schematic block diagram of another pixel circuit according to an embodiment of the present disclosure;

[0042] FIG. 5 is a schematic circuit structure diagram of a pixel circuit according to an embodiment of the present disclosure;

[0043] FIG. 6 is a schematic circuit structure diagram of another pixel circuit provided by an embodiment of the present disclosure;

[0044] FIG. 7 is a schematic circuit structure diagram of still another pixel circuit provided by an embodiment of the present disclosure;

[0045] FIG. 8 is a schematic circuit structure diagram of yet another pixel circuit provided by an embodiment of the present disclosure;

[0046] FIG. 9 is a schematic block diagram of a display panel provided by an embodiment of the present disclosure;

[0047] FIG. 10 is a schematic circuit structure diagram of still another pixel circuit provided by an embodiment of the present disclosure;

[0048] FIG. 11 is a schematic circuit structure diagram of yet another pixel circuit provided by an embodiment of the present disclosure;

[0049] FIG. 12 is a schematic flowchart of a driving method of a pixel circuit provided by an embodiment of the present disclosure;

[0050] FIG. 13 is a circuit timing diagram of a pixel circuit provided by an embodiment of the present disclosure;

[0051] FIG. 14 is a circuit timing diagram of another pixel circuit provided by an embodiment of the present disclosure;

[0052] FIG. 15 is a schematic block diagram of a display device provided by an embodiment of the present disclosure;

[0053] In FIGS. 1-11 and 15, the names and reference numerals of the components correspond as follows:

[0054] 1 display panel, 2 controller;

[0055] 10 pixel circuit, 20 gate drive circuit;

[0056] 101 drive transistor, 102 first light-emitting control unit, 103 first charge storage unit, 104 data write compensation unit, 105 first charging unit, 106' light-emitting device, 107 second light-emitting control unit, 108 reset unit, 109 second charge storage unit, 110 second charging unit;

[0057] 1031 access subunit, 1032 charge storage subunit. DETAILED DESCRIPTION

[0058] The terms "first", "second", "third", "fourth" and the like in the description and in the claims of the present disclosure and above-mentioned drawings, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the use of the terms so construed herein can be interchanged, such that the embodiments described herein can be carried out in another order than the one described here without departing from the scope of the embodiments described herein. Also, the terms "comprising", "having", "including" and "containing" are to be construed open-ended, i.e., meaning "including, but not limited to", for example, a process, method, system, product or apparatus that comprises a list of steps or units can not necessarily be limited to those steps or units which are expressly listed, but can include other steps or units that are not expressly listed or inherent to such process, method, product or apparatus.

[0059] In the present disclosure, "first node", "second node", "third node" and the like refer to the connection points of two or more conductors in a circuit, which are set for better description of the circuit structure, and are not actually present. In an ideal case, a node can be regarded as an ideal conductor without resistance, and current can be freely divided at the node.

[0060] In the embodiments of the present disclosure, the transistors used can all be thin film transistors or field effect transistors or other switching devices with the same characteristics. The source and drain of the transistors used herein can be symmetrical in structure, the first electrode is used to represent one of the source and drain, and the second electrode is used to represent the other of the source and drain.

[0061] In the related art, the compensation for the threshold voltage of the driving transistor is usually performed by writing the threshold voltage to the gate of the driving transistor, for example, in the compensation stage of the pixel circuit, the related art flows the input current from the outside through the driving transistor and writes the positive charge carrying the threshold voltage value of the driving transistor to the gate of the driving transistor, thereby completing the compensation for the threshold voltage. However, in some cases, the threshold voltage of the driving transistor is negative, for example, the gate potential of the N-type thin film transistor without gate tuning is often close to 0V or even negative, because the current direction is the same as the direction of the movement of the positive charge, the related art cannot write the negative threshold voltage to the gate, thereby failing to complete the compensation for the threshold voltage of the driving transistor.

[0062] Therefore, the present disclosure provides a pixel circuit to at least solve the above technical problems.

[0063] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all the embodiments.

[0064] Fig. 1 is a schematic block diagram of a pixel circuit according to an embodiment of the present disclosure, Fig. 2 is a schematic block diagram of another pixel circuit according to an embodiment of the present disclosure, Fig. 3 is a schematic block diagram of yet another pixel circuit according to an embodiment of the present disclosure, and Fig. 4 is a schematic block diagram of still another pixel circuit according to an embodiment of the present disclosure. As shown in Figs. 1 to 4, the pixel circuit 10 includes a driving transistor 101, a first light-emitting control unit 102, a first charge storage unit 103, a data write compensation unit 104, and a first charging unit 105.

[0065] For example, the pixel circuit 10 can be applied to an OLED or AMOLED display panel, and the light-emitting device 106' can be driven by the driving transistor 101 to emit light.

[0066] For example, as shown in Fig. 1, one end of the first light-emitting control unit 102 is electrically connected to the first constant voltage terminal ELVDD, and the other end is electrically connected to the first electrode of the driving transistor 101 through the first node N1. The first light-emitting control unit 102 is configured to control the conduction or cutoff between the first constant voltage terminal ELVDD and the first node N1 under the action of the first light-emitting control signal EM1.

[0067] One end of the first charge storage unit 103 is electrically connected to the first node N1, and the other end is electrically connected to the gate of the driving transistor 101 through the second node N2. The first charge storage unit 103 is configured to release charges to the first node N1 and the second node N2 to dynamically balance the potential of the first node N1 and the potential of the second node N2.

[0068] It should be noted that the first charge storage unit 103 can be a capacitor, and the two plates of the capacitor are respectively electrically connected to the first node N1 and the second node N2. The capacitor can store the charges of the first node N1 and the second node N2. In addition, since the voltage across the capacitor cannot change abruptly, when the potential of the first node N1 or the second node N2 changes, the potential of the second node N2 or the first node N1 will also change in the same trend under the action of the capacitor, for example, synchronously decrease or synchronously increase, so as to dynamically balance the potential of the first node N1 and the potential of the second node N2. The subsequent description of the dynamic balance is the same, and will not be repeated here.

[0069] The data write compensation unit 104 is electrically connected to the second electrode of the driving transistor 101 through the third node N3. The data write compensation unit 104 is configured to write the data voltage signal Vdata to the third node N3 under the action of the first driving signal Gate1, and the voltage value of the data voltage signal Vdata is less than the voltage value of the first constant voltage terminal ELVDD.

[0070] The first charging unit 105 is electrically connected to the second node N2, and the first charging unit 105 is configured to write the first initial voltage signal Vini1 to the second node N2 under the action of the second driving signal Gate2, and the voltage value of the first initial voltage signal Vini1 is capable of driving the driving transistor 101 to be turned on.

[0071] It should be noted that the first initial voltage signal Vini1 is written to the second node N2, and the second node N2 is electrically connected to the gate of the driving transistor 101, that is, when the voltage value of the first initial voltage signal Vini1 is equivalent to the gate potential of the driving transistor 101, the voltage value between the source or the base and the gate can drive the driving transistor 101 to be turned on.

[0072] It should be noted that the first light-emitting control unit 102, the data writing compensation unit 104, and the first charging unit 105 can be components with switching functions under the action of specific signals, such as transistors.

[0073] It should be noted that the pixel circuit 10 usually has different working stages, and different working stages control each circuit device based on different signals to achieve different functions.

[0074] For example, as shown in FIG. 1, in order to complete the compensation of the threshold voltage of the driving transistor 101, the pixel circuit 10 provided by the present disclosure is performed by two stages. In the first stage, the first driving signal Gate1 is written to the first charging unit 105, that is, the first charging unit 105 writes the first initial voltage signal Vini1 to the second node N2 under the action of the effective level of the first driving signal Gate1. At the same time, the first light-emitting control unit 102 controls the first constant voltage terminal ELVDD and the first node N1 to be turned on under the action of the first light-emitting control signal EM1, so that the first constant voltage is written to the first node N1. In this process, the first charge storage unit 103 stores the voltage values of the first constant voltage and the first initial voltage signal Vini1, respectively.

[0075] In the second stage, the effective level of the first driving signal Gate 1 is terminated, i.e. the first charging unit 105 stops under the action of the first driving signal Gate 1 and no longer writes the first initial voltage into the second node N2. At this time, the first light-emitting control unit 102 is also closed and no longer writes the first constant voltage into the first node N1. At this time, the second driving signal Gate 2 writes into the data writing compensation unit 104, i.e. the data writing compensation unit 104 writes the data voltage signal Vdata into the third node N3 under the action of the effective level of the second driving signal Gate 2. The potential of one end of the first charge storage unit 103, i.e. the first node N1, is the voltage value of the first constant voltage terminal ELVDD at this time, and the potential of the other end, i.e. the second node N2, is the voltage value of the first initial voltage signal Vini1. The driving transistor 101 is turned on under the action of the first initial voltage signal Vini1 and the data voltage signal Vdata, and since the voltage value of the first constant voltage terminal ELVDD is greater than the voltage value of the data voltage signal Vdata, the charge of the first node N1 flows into the third node N3 through the driving transistor 101, i.e. the potential of the first node N1 decreases, but the potential of the third node N3 does not change under the clamping of the data voltage signal Vdata. The first charge storage unit 103 is connected between the first node N1 and the second node N2, and the potential of the first node N1 decreases, and the potential of the second node N2 also decreases under the action of the first charge storage unit 103 to maintain the dynamic balance of the voltage across the first charge storage unit 103.

[0076] In the first stage, the driving transistor 101 is in a cut-off state since the third node N3 has no external signal written into it, and in the second stage, the driving transistor 101 is turned on under the action of the potential of the second node N2, i.e. the first initial voltage signal Vini1 and the data voltage signal Vdata. Since the potential of the first node N1 decreases under the action of the decrease of the potential of the second node N2, i.e. the gate potential of the driving transistor 101 decreases, the driving transistor 101 tends to be cut off, and the cut-off condition of the transistor, i.e. the absolute value of the gate-source voltage is less than or equal to the absolute value of the threshold voltage. Since the potential of the second electrode of the driving transistor 101, i.e. the third node N3, is unchanged and always the voltage value of the data voltage signal Vdata, the final gate potential value will decrease to (Vdata+Vth), where Vth represents the threshold voltage of the driving transistor 101, thereby completing the threshold voltage compensation of the driving transistor 101. When the driving transistor 101 controls the driving current subsequently, taking an N-type thin film transistor as an example, the driving current can be calculated according to the following formula (1): ds = K × (V gs -V th ) 2 (1)

[0077] wherein I ds represents the driving current, i.e. the source-drain current, K represents a structure constant of the driving transistor 101, V gs represents the gate-source voltage of the driving transistor 101, V th represents the threshold voltage of the driving transistor 101.

[0078] It should be noted that in the above equation, V gs represents the threshold voltage of the driving transistor 101. g -V s Since V g is written in V th , V gs may be approximated from (V th -V th ), and then, when the driving transistor 101 controls the driving current to make the light emitting device 106' emit light, the influence of the threshold voltage of the driving transistor 101 is reduced.

[0079] It should be noted that the opening of the first charging unit 105 should be earlier than the opening time of the data compensation voltage unit, i.e. the starting time of the effective level of the first driving signal Gate 1 should be later than or equal to the ending time of the effective level of the second driving signal Gate 2. The opening of the first charging unit 105 and the data compensation unit can leave a one-end blank time to prevent the simultaneous opening or closing of the electronic device due to the fast switching and connection.

[0080] In summary, the pixel circuit 10 provided by the embodiment of the present disclosure, under the action of the effective level of the second driving signal Gate2 and the action of the first light-emitting control signal EM1, the first initial voltage signal Vini1 and the first constant voltage are written into the two ends of the first charge storage unit 103 respectively, and are stored by using the first charge storage unit 103. Subsequently, the first charging unit 105 and the first light-emitting control unit 102 are closed, and the data writing compensation unit 104 writes the data voltage signal Vdata into the third node N3 under the action of the first driving signal Gate1. Since the voltage value of the first initial voltage signal Vini1 can make the driving transistor 101 conduct, a path is formed between the first electrode and the second electrode of the driving transistor 101 and the first node N1 and the second node N2 respectively, therefore, the charges of the first node N1 continuously flow into the second node N2, the potential of the first node N1 decreases, and the first charge storage unit 103 controls the dynamic balance between the potential of the first node N1 and the potential of the second node N2, so that the potential of the second node N2 decreases with the potential of the first node N1, and the potential of the third node N3 does not change under the action of the data voltage signal Vdata, therefore, the gate-source voltage of the driving transistor 101 gradually decreases to the value of the threshold voltage, that is, the gate potential of the driving transistor 101 is the sum of the voltage value of the data voltage signal Vdata and the threshold voltage, so as to complete the compensation of the threshold voltage of the driving transistor 101. Compared with the related art, the threshold voltage of the driving transistor 101 is written in the form of increasing the gate potential to achieve the purpose of compensating the threshold voltage, the present disclosure reduces the gate potential to make the voltage between the gate and the source of the driving transistor 101 be the threshold voltage, so that the threshold voltage compensation of the driving transistor 101 can be completed even if the threshold voltage is negative. Therefore, the pixel circuit 10 provided by the present disclosure can more comprehensively compensate the threshold voltage of the driving transistor 101.

[0081] In some examples, as shown in the pixel circuit 10 provided by FIG. 3 and FIG. 4, the first charge storage unit 103 includes an access sub-unit 1031 and a charge storage sub-unit 1032, one end of the charge storage sub-unit 1032 is electrically connected with the second node N2, and the other end is electrically connected with the first node N1.

[0082] For example, in the example of FIG. 3, the access sub-unit 1031 is connected in series between the charge storage sub-unit 1032 and the first node N1.

[0083] For example, in the example of FIG. 4, the access sub-unit 1031 is connected in series between the charge storage sub-unit 1032 and the second node N2.

[0084] It should be noted that the access sub-unit 1031 controls whether the charge storage sub-unit 1032 is connected between the first node N1 and the second node N2 under the action of the fourth driving signal Gate4. For example, the access sub-unit 1031 can achieve this by disconnecting the connection between the charge sub-unit and the first node N1 or the second node N2.

[0085] It should be noted that when the access sub-unit 1031 controls the charge storage sub-unit 1032 to be connected between the first node N1 and the second node N2 under the action of the fourth driving signal Gate4, the charge storage sub-unit 1032 can then dynamically balance the potential between the first node N1 and the second node N2 by releasing charges to the first node N1 and the second node N2. When the access sub-unit 1031 controls the charge storage sub-unit 1032 to be disconnected from one of the first node N1 and the second node N2 under the action of the fourth driving signal Gate4, the charge storage sub-unit 1032 can not balance the potential change of the second node N2 or the first node N1 according to the potential change of the first node N1 or the second node N2. Therefore, in the case where the driving transistor 101 of the pixel circuit 10 needs to stably control the driving current, by setting the control relationship between the access sub-unit 1031 and the charge storage sub-unit 1032, the interference to the driving transistor 101 can be reduced, thereby improving the light emission stability of the pixel circuit 10.

[0086] In some examples, FIG. 5 is a schematic circuit structure diagram of a pixel circuit provided by an embodiment of the present disclosure, and FIG. 6 is another schematic circuit structure diagram of a pixel circuit provided by an embodiment of the present disclosure. Both FIG. 5 and FIG. 6 are an example of the circuit structure of the pixel circuit 10 shown in FIG. 1, FIG. 2, FIG. 3 and FIG. 4. As shown in FIG. 5 and FIG. 6, the access sub-unit 1031 includes a first transistor T1, and the charge storage sub-unit 1032 includes a first capacitor C1, wherein the gate of the first transistor T1 receives the fourth driving signal Gate4, and the two ends of the first capacitor C1 are electrically connected with the first node N1 and the second node N2 respectively.

[0087] For example, the positions of the first transistor T1 and the first capacitor C1 at the first node N1 and the second node N2 are not unique. In the embodiment of FIG. 5, the first electrode of the first transistor T1 is electrically connected with the first node N1, the second electrode is electrically connected with one end of the first capacitor C1, and the other end of the first capacitor C1 is electrically connected with the second node N2. In the embodiment of FIG. 6, the second electrode of the first transistor T1 is electrically connected with the second node N2, the first electrode is electrically connected with one end of the first capacitor C1, and the other end of the first capacitor C1 is electrically connected with the first node N1.

[0088] It should be noted that when the driving transistor 101 controls the driving current to make the light emitting device 106' emit light, the stability of the gate potential of the driving transistor 101 is particularly important, and therefore, by arranging the first transistor T1, the first capacitor C1 can be disconnected from the path between the first node N1 and the second node N2 when the driving transistor 101 drives the light emitting device 106' to emit light, thereby reducing the interference of the first capacitor C1 releasing charges on the driving transistor 101, and improving the stability of the light emitting of the pixel circuit 10.

[0089] It should be noted that the capacitor has two plates, both of which store charges, and in the embodiment of FIG. 6, the first capacitor C1 has no plate directly electrically connected to the gate of the driving transistor 101 when the first transistor T1 is off, and therefore, compared with the embodiment of FIG. 5, the first capacitor C1 can further shield the interference on the driving transistor 101.

[0090] The pixel circuit 10 provided by the present disclosure is described below with respect to the embodiments of FIG. 5 and FIG. 6.

[0091] For example, in the embodiments of FIG. 5 and FIG. 6, the driving transistor 101 includes the zeroth transistor DT, the data write compensation unit 104 includes the third transistor T3, the first light emitting control unit 102 includes the second transistor T2, and the first charging unit 105 includes the fifth transistor T5.

[0092] The first electrode, the second electrode and the gate of the zeroth transistor DT are electrically connected to the first node N1, the third node N3 and the second node N2, respectively; the gate of the third transistor T3 receives the first driving signal Gate1, the first electrode receives the data voltage signal Vdata, and the second electrode is electrically connected to the third node N3; the gate of the second transistor T2 receives the first light emitting control signal EM1 and is connected in series between the first constant voltage terminal ELVDD and the first node N1; the gate of the fifth transistor T5 receives the second driving signal Gate2, the first electrode receives the first initial voltage signal Vini1, and the second electrode is electrically connected to the second node N2.

[0093] In the first stage, the first transistor T1 is turned on under the action of the fourth driving signal Gate4, the first capacitor C1 is connected between the first node N1 and the second node N2, and the fifth transistor T5 and the second transistor T2 are turned on under the action of the second driving signal Gate2 and the first light emitting control signal EM1, respectively, to charge the two ends of the first capacitor C1, one end writes the voltage value of the first constant voltage terminal ELVDD, and the other end writes the first initial voltage signal Vini1.

[0094] In the second stage, the third transistor T3 is turned on under the action of the first driving signal Gate1, and the data voltage signal Vdata is written to the third node N3; the second transistor T2 and the fifth transistor T5 are both turned off, the first capacitor C1 supplies power to the gate of the zeroth transistor DT through the second node N2, and drives the zeroth transistor DT to be turned on. Since the potential of the first node N1 is the voltage value of the first constant voltage terminal ELVDD, which is greater than the voltage value of the data voltage signal Vdata, the charge of the first node N1 flows to the third node N3, and therefore, under the action of the first capacitor C1, the potential of the second node N2 decreases until the potential difference between the second node N2 and the third node N3 is the threshold voltage of the zeroth transistor DT. Since the potential of the third node N3 is always the voltage value of the data voltage signal Vdata, the gate potential of the zeroth transistor DT at this time is the sum of the voltage value of the data voltage signal Vdata and the threshold voltage of the zeroth transistor DT, i.e. (Vdata+Vth), thereby completing the threshold voltage compensation of the zeroth transistor DT.

[0095] In some examples, as shown in the examples of FIGS. 3 and 4, the pixel circuit 10 described above further includes a second charging unit 110, which is configured to write a third initial voltage signal Vini3 to the charge storage sub-unit 1032 under the action of a fifth driving signal, wherein the second driving signal Gate2 has the same starting time as the effective level of the fifth driving signal, and the second driving signal Gate2 has the same ending time as the effective level of the fifth driving signal.

[0096] It should be noted that the second charging unit 110 can be connected to different positions based on the relative position relationship between the access sub-unit 1031 and the charge storage sub-unit 1032 between the first node N1 and the second node N2. For example, in the example of FIG. 3, the second charging unit 110 is connected to the fifth node N5, and in the example of FIG. 4, the second charging unit 110 is connected to the first node N1.

[0097] As shown in FIGS. 3 and 4, one end of the charge storage sub-unit 1032 is connected to the first charging unit 105, and the other end is connected to the second charging unit 110, i.e. the charge storage sub-unit 1032 is charged through the first charging unit 105 and the second charging unit 110 respectively.

[0098] It should be noted that the current display panel includes multiple rows of pixel circuits 10, and each row of pixel circuits 10 often shares a power line or a power terminal. Due to the influence of the wire resistance, the pixel circuits 10 close to the power supply and the pixel circuits 10 far away from the power supply receive different voltage values of the first constant voltage terminal ELVDD, and the pixel circuits 10 far away from the power supply are relatively low. Therefore, in the embodiment, the second charging unit 110 is arranged to write the third initial voltage signal Vini3 to one end of the charge storage unit under the action of the fifth driving signal to charge one end of the charge storage unit, instead of charging one end of the charge storage unit by writing the voltage value of the first constant voltage terminal ELVDD from the first light-emitting control unit 102, so that the influence of the IR drop of the first constant voltage terminal ELVDD can be eliminated.

[0099] It should be noted that since the first charging unit 105 and the second charging unit 110 are respectively used to charge the charge storage sub-unit 1032, they can be simultaneously turned on and simultaneously turned off, that is, the starting time of the effective level of the second driving signal Gate2 and the fifth driving signal is the same, and the termination time of the effective level of the second driving signal Gate2 and the fifth driving signal is the same.

[0100] For example, FIG. 7 is a schematic circuit structure diagram of another pixel circuit provided by the embodiment of the present disclosure, and FIG. 8 is a schematic circuit structure diagram of still another pixel circuit provided by the embodiment of the present disclosure. Both FIG. 7 and FIG. 8 are one circuit structure example of the pixel circuit 10 shown in FIG. 1, FIG. 2, FIG. 3 and FIG. 4, and FIG. 7 and FIG. 8 are improvements on the circuit structures of FIG. 5 and FIG. 6. As shown in FIG. 7 and FIG. 8, the second charging unit 110 includes a seventh transistor T7.

[0101] As shown in the embodiment of FIG. 7, the seventh transistor T7 is electrically connected with the fifth node N5, both ends of the first capacitor C1 are connected to the fifth node N5 and the second node N2 respectively, and the first transistor T1 is connected in series between the fifth node N5 and the first node N1.

[0102] As shown in the embodiment of FIG. 8, the seventh transistor T7 is electrically connected with the first node N1, the first transistor T1 is connected in series between the first capacitor C1 and the second node N2, and one end of the first capacitor C1 is electrically connected with the first node N1.

[0103] It should be noted that the fifth transistor T5 and the seventh transistor T7 are connected to the two poles of the first capacitor C1 respectively, so as to charge the two poles of the first capacitor C1 at the same time when the first transistor T1 is turned on. At the same time, in order to avoid short circuit, the second transistor T2 is in an off state when the fifth transistor T5 and the seventh transistor T7 charge the first capacitor C1.

[0104] In summary, in the pixel circuit 10 provided by the embodiment of the present disclosure, the first charge storage unit 103 includes an access subunit 1031 and a charge storage subunit 1032, the access subunit 1031 is used to control whether the charge storage subunit 1032 is connected between the first node N1 and the second node N2, so as to reduce the interference of the charge released by the charge storage subunit 1032 on the driving transistor 101 in the light-emitting stage of the pixel circuit 10; and the two ends of the charge storage subunit 1032 are charged by the first charging unit 105 and the second charging unit 110 respectively, instead of being charged by the first light-emitting control unit 102, so that the voltage value accuracy of the voltage of the first constant voltage terminal ELVDD for writing the charge storage subunit 1032 can be improved due to the voltage loss. Therefore, the pixel circuit 10 provided by the embodiment of the present disclosure can improve the stability and accuracy of the gate potential of the driving transistor 101, and then improve the accuracy of the light-emitting of the pixel circuit 10.

[0105] According to some embodiments, as shown in the pixel circuit 10 provided by the embodiments of FIG. 2, FIG. 3 and FIG. 4, the pixel circuit 10 further includes a second light-emitting control unit 107, one end of the second light-emitting control unit 107 is electrically connected with the third node N3, and the other end is electrically connected with the fourth node N4 and the light-emitting device 106', for controlling the conduction or cutoff between the third node N3 and the fourth node N4 under the action of a second light-emitting control signal EM2.

[0106] It should be noted that by setting the second light-emitting control unit 107 to control the connection between the third node N3 and the light-emitting device 106', the light-emitting device 106' can be prevented from being accidentally lighted in the non-light-emitting stage.

[0107] For example, as shown in the embodiments of FIG. 5 to FIG. 8, the second light-emitting control unit 107 includes a fourth transistor T4, the gate of the fourth transistor T4 receives the second light-emitting control signal EM2, the first electrode is electrically connected with the third node N3, and the second electrode is electrically connected with the fourth node N4 and the light-emitting device 106', the light-emitting device 106' can be an OLED, and the other end of the light-emitting device 106' is connected with a second constant voltage terminal ELVSS, which can be grounded. The fourth transistor T4 can be cut off or conductive under the action of the second light-emitting control signal EM2, so as to control whether the driving current can flow into the OLED.

[0108] In some examples, as shown in the pixel circuit 10 provided by the embodiments of FIG. 2, FIG. 3 and FIG. 4, the pixel circuit 10 further includes a reset unit 108, the reset unit 108 is electrically connected with the fourth node N4, for writing a second initial voltage signal Vini2 into the fourth node N4 under the action of a third driving signal Gate3. In some examples, as shown in the pixel circuit 10 provided by the embodiments of FIG. 2, FIG. 3 and FIG. 4, the pixel circuit 10 further includes a reset unit 108, the reset unit 108 is electrically connected with the fourth node N4, for writing a second initial voltage signal Vini2 into the fourth node N4 under the action of a third driving signal Gate3.

[0109] It should be noted that the reset unit 108 writes the second initial voltage signal Vini2 to the fourth node N4 connected to the light emitting device 106', so as to clear the residual charge in the light emitting device 106'.

[0110] For example, as shown in the embodiments of FIGS. 5-8, the reset unit 108 includes a sixth transistor T6, the gate electrode of the sixth transistor T6 is configured to receive the third driving signal Gate3, the first electrode is configured to receive the second initial voltage signal Vini2, and the second electrode is electrically connected to the fourth node N4.

[0111] In some examples, as shown in the pixel circuit 10 provided in FIGS. 2, 3 and 4, the pixel circuit 10 further includes a second charge storage unit 109, one end of the second charge storage unit 109 is electrically connected to the second node N2, and the other end is electrically connected to the fourth node N4, for releasing charges to the second node N2 and the fourth node N4 to dynamically balance the potential of the second node N2 and the potential of the fourth node N4.

[0112] For example, as shown in the embodiments of FIGS. 5-8, the second charge storage unit 109 includes a second capacitor C2, and the two plates of the second capacitor C2 are respectively connected to the second node N2 and the fourth node N4.

[0113] When the pixel circuit 10 is in the light emitting stage, the second transistor T2 and the fourth transistor T4 are both turned on, and the second capacitor C2 can clamp the potential of the second node N2 to improve the stability of the driving current.

[0114] In some examples, as shown in the pixel circuit 10 provided in FIGS. 2, 3 and 4, the first charge storage unit 103 and the second charge storage unit 109 are connected in series through the second node N2 and are connected between the first node N1 and the fourth node N4. At this time, since the second node N2 is controlled by the first charge storage unit 103 and the second charge storage unit 109 at the same time, the stability of the charge stored in the second node N2 can be improved, and the control of the driving transistor 101 is more accurate.

[0115] In some examples, the starting time of the effective level of the third driving signal Gate3 is the same as the starting time of the effective level of the second driving signal Gate2, and the ending time of the effective level of the third driving signal Gate3 is the same as the ending time of the effective level of the first driving signal Gate1.

[0116] It should be noted that, as shown in the pixel circuit 10 provided by the embodiments of FIG. 2, FIG. 3 and FIG. 4, the third driving signal Gate3 controls the reset unit 108, the second driving signal Gate2 controls the first charging unit 105, the first driving signal Gate1 controls the data write compensation unit 104, and the first charge storage unit 103 and the second charge storage unit 109 are connected in series between the first node N1 and the fourth node N4 through the second node N2.

[0117] The starting moment of the effective level of the third driving signal Gate3 is the same as that of the second driving signal Gate2, which means that the first initial voltage signal Vini1 and the second initial voltage signal Vini2 are written into the first charging unit 105 and the reset unit 108 respectively at the same time, and the second initial voltage signal Vini2 is used to clamp the second charge storage unit 109, thereby improving the stability of the voltage value written into the second node N2.

[0118] The ending moment of the effective level of the third driving signal Gate3 is the same as that of the first driving signal Gate1, which can prevent the reset unit 108 from being closed and the second charge storage unit 109 from causing the potential jump of the second node N2.

[0119] The embodiments of the present disclosure further provide a pixel circuit 10, as shown in the embodiments of FIG. 5 or FIG. 6, which comprises a driving transistor 101, a first light-emitting control unit 102, a second light-emitting control unit 107, a first charge storage unit 103, a second charge storage unit 109, a data write compensation unit 104, a reset unit 108 and a first charging unit 105,

[0120] The driving transistor 101 comprises a zeroth transistor DT, and the first electrode, the second electrode and the gate of the zeroth transistor DT are electrically connected with the first node N1, the third node N3 and the second node N2 respectively;

[0121] The first light-emitting control unit 102 comprises a second transistor T2, the gate of the second transistor T2 is used for receiving a first light-emitting control signal EM1, the first electrode of the second transistor T2 is electrically connected with a first constant voltage terminal ELVDD, and the second electrode of the second transistor T2 is electrically connected with the first node N1;

[0122] The data write compensation unit 104 comprises a third transistor T3, the gate of the third transistor T3 is used for receiving a first driving signal Gate1, the first electrode of the third transistor T3 is used for receiving a data voltage signal Vdata, and the second electrode of the third transistor T3 is electrically connected with the third node N3;

[0123] The second light emitting control unit 107 comprises a fourth transistor T4, a gate of the fourth transistor T4 is configured to receive a second light emitting control signal EM2, a first electrode of the fourth transistor T4 is electrically connected with the third node N3, and a second electrode of the fourth transistor T4 is electrically connected with the light emitting device 106' through a fourth node N4;

[0124] The first charging unit 105 comprises a fifth transistor T5, a gate of the fifth transistor T5 is configured to receive a second driving signal Gate2, a first electrode of the fifth transistor T5 is configured to receive a first initial voltage signal Vini1, and a second electrode of the fifth transistor T5 is electrically connected with the second node N2;

[0125] The reset unit 108 comprises a sixth transistor T6, a gate of the sixth transistor T6 is configured to receive a third driving signal Gate3, a first electrode of the sixth transistor T6 is configured to receive a second initial voltage signal Vini2, and a second electrode of the sixth transistor T6 is electrically connected with the fourth node N4;

[0126] The first charge storage unit 103 comprises an access subunit 1031 and a charge storage subunit 1032, the access subunit 1031 comprises a first transistor T1, the charge storage subunit 1032 comprises a first capacitor C1, a gate of the first transistor T1 is configured to receive a fourth driving signal Gate4, one end of the first capacitor C1 is electrically connected with the second node N2, the other end of the first capacitor C1 is electrically connected with the first node N1, and the first transistor T1 is connected in series between the first capacitor C1 and the first node N1 or the second node N2;

[0127] The second charge storage unit 109 comprises a second capacitor C2, the second capacitor C2 is connected in series between the second node N2 and the fourth node N4.

[0128] In some examples, as shown in the embodiments of FIGS. 7 and 8, the pixel circuit 10 further comprises a second charging unit 110, the second charging unit 110 comprises a seventh transistor T7, a gate of the seventh transistor T7 is configured to receive a fifth driving signal, a first electrode of the seventh transistor T7 is electrically connected with the other end of the first capacitor C1, and a second electrode of the seventh transistor T7 is configured to receive a third initial voltage signal Vini3; wherein the effective level start time and the effective level end time of the second driving signal Gate2 and the fifth driving signal are the same.

[0129] It should be noted that the above-mentioned zeroth transistor DT to seventh transistor T7 can be the same type of transistor, which can reduce the process complexity of preparing the pixel circuit 10. Meanwhile, the transistors in the figure can all be oxide transistors, which can reduce the leakage current and save the power consumption caused by the pixel circuit 10.

[0130] In some examples, the voltage value of the data voltage signal Vdata is less than the voltage value of the first constant voltage terminal ELVDD; the voltage value of the first initial voltage signal Vini1 can drive the driving transistor 101 to be turned on; the starting moment of the effective level of the first driving signal Gate1 is later than or equal to the ending moment of the effective level of the second driving signal Gate2; the starting moments of the effective levels of the second driving signal Gate2, the third driving signal Gate3 and the fourth driving signal Gate4 are all the same, and the ending moments of the effective levels of the first driving signal Gate1, the third driving signal Gate3 and the fourth driving signal Gate4 are the same.

[0131] For example, as shown in the embodiments of FIGS. 5 to 8, the first driving signal Gate1 controls the third transistor T3 of the data compensation writing unit, the second driving signal Gate2 controls the fifth transistor T5 of the first charging unit 105, the third driving signal Gate3 controls the sixth transistor T6 of the reset unit 108, and the fourth driving signal Gate4 controls the first transistor T1 of the access sub-unit 1031.

[0132] The fifth transistor T5, the sixth transistor T6 and the first transistor T1 are turned on at the same time under the actions of the second driving signal Gate2, the third driving signal Gate3 and the fourth driving signal Gate4, respectively, to charge the first capacitor C1;

[0133] The third transistor T3, the sixth transistor T6 and the first transistor T1 are turned off at the same time under the actions of the first driving signal Gate1, the third driving signal Gate3 and the fourth driving signal Gate4, respectively, and the pixel circuit 10 enters the light emitting stage

[0134] The display panel provided by the embodiments of the present disclosure also provides a display panel including a plurality of pixel circuits 10 as described in any of the above embodiments.

[0135] For example, FIG. 9 is a schematic block diagram of a display panel provided by the embodiments of the present disclosure, as shown in FIG. 9, the display panel 1 provided by the embodiments of the present disclosure can include a gate driving circuit 20, the gate driving circuit 20 can drive the pixel circuit 10 as described in any of the above embodiments, and different scanning modes of a plurality of pixel circuits 10 can be realized by controlling driving signals, so that the display panel 1 achieves different display effects.

[0136] It should be noted that the display panel 1 provided by the embodiments of the present disclosure can have various shapes, can have a touch function, and can also be installed on various electronic devices.

[0137] In some examples, in the display panel 1 described above, the first driving signal Gate1 received by the pixel circuit 10 of the nth row is the same as the second driving signal Gate2 received by the pixel circuit 10 of the (n-1)th row, where n is an integer greater than or equal to 2.

[0138] For example, FIG. 10 and FIG. 11 are schematic circuit structure diagrams of another pixel circuit provided by the embodiments of the present disclosure, and both of FIG. 10 and FIG. 11 are one circuit structure example of the pixel circuit 10 shown in FIG. 1 to FIG. 4.

[0139] As shown in the embodiment of FIG. 10, in each row of the pixel circuit 10 of the display panel 1 described above, the gate of the third transistor T3 in the data writing compensation unit 104 receives the first driving signal Gate1, the gate of the fifth transistor T5 in the first charging unit 105 receives the second driving signal Gate2, and the first driving signal Gate1 received by the third transistor T3 in the pixel circuit 10 of the nth row can be the same as the second driving signal Gate2 received by the fifth transistor T5 in the pixel circuit 10 of the (n-1)th row, that is, the timing corresponding to the first driving signal Gate1 received by the third transistor T3 in the pixel circuit 10 of the nth row is Gate1 <n>The second driving signal Gate2 received by the gate of the fifth transistor T5 of the nth row is the corresponding timing of Gate1 <n-1>That is, for each row of pixel circuits 10, the first driving signal Gate1 and the second driving signal Gate2 can be provided by the same signal line, thereby being able to reduce the width of the display panel 1 and save power consumption.

[0140] In some examples, as shown in the embodiments combining FIG. 10 and FIG. 11, in each row of pixel circuits 10 of the above display panel 1, a second charging unit 110 is further included, and the second charging unit 110 includes a seventh transistor T7, and the signal received by the gate of the seventh transistor T7 is the same as the signal received by the gate of the fifth transistor T5, that is, for the nth row of pixels, the timing of the driving signal received by the gates of the fifth transistor T5 and the seventh transistor T7 is Gate1 <n-1>.

[0141] It should be noted that since the first charging unit 105 and the second charging unit 110 are both used to charge the first charge storage unit 103, they can be simultaneously turned on and turned off, and thus can share the same signal timing.

[0142] It should be noted that in the embodiments of the present disclosure, the reference signs in FIGS. 1 to 8, 10 and 11, ELVDD, ELVSS, Gate1, Gate2, Gate3, Gate4, Gate5, Vdata, Vini1, Vini2, Vini3, EM1, EM2, can represent signal lines or signals on the signal lines.

[0143] The embodiments of the present disclosure also provide a driving method of a pixel circuit, which can be used to drive the pixel circuit 10 as described in any one of the embodiments of FIGS. 1 to 8, 10 and 11. FIG. 12 is a schematic flowchart of a driving method of a pixel circuit provided by an embodiment of the present disclosure, and FIG. 13 is a circuit timing diagram of a pixel circuit provided by an embodiment of the present disclosure, which can be applied to the pixel circuit 10 shown in FIG. 5 or FIG. 6. The driving method provided by an embodiment of the present disclosure will be described below in combination with FIG. 13.

[0144] It should be noted that the following embodiments are described by taking N-type thin film transistors as an example, the effective level of the N-type thin film transistor is high, the transistor is turned on, and the non-effective level is low, the transistor is turned off. In order to be brief, when the transistor is turned on or turned off, the high and low levels of the signal are not indicated.

[0145] As shown in FIG. 12, the above driving method comprises:

[0146] S110, in the reset stage, controlling the first light emitting control unit 102 to be turned on to make the first constant voltage terminal ELVDD and the first node N1 conductive, and controlling the first charging unit 105 to write the first initial voltage signal Vini1 to the second node N2.

[0147] For example, as shown in FIG. 13 in combination with FIG. 5 and FIG. 6, P1 represents the reset stage. In the P1 stage, the first light emitting control signal EM1 is transmitted to the second transistor T2 to make the first constant voltage terminal ELVDD and the first node N1 conductive, the second driving signal Gate2 is transmitted to the fifth transistor T5 to make the fifth transistor T5 conductive, and the first initial voltage signal Vini1 is transmitted to the second node N2 to charge the two plates of the first capacitor C1.

[0148] In some examples, the pixel circuit 10 further comprises a second light emitting control unit 107 and a reset unit 108, one end of the second light emitting control unit 107 is electrically connected with the third node N3, the other end is electrically connected with the light emitting device 106' through the fourth node N4, and the reset unit 108 is electrically connected with the fourth node N4.

[0149] The above driving method further comprises: in the reset stage, controlling the second light emitting control unit 107 to be turned on to make the third node N3 and the fourth node N4 conductive, and controlling the reset unit 108 to write the second initial voltage signal Vini2 to the fourth node N4.

[0150] For example, as shown in FIG. 13 in combination with FIGS. 5 and 6, the pixel circuit 10 further comprises a sixth transistor T6, a fourth transistor T4 and a second capacitor C2. In the P1 stage, the fourth transistor T4 is transmitted with the second light emitting control signal EM2 to make the third node N3 and the fourth node N4 conductive, and the sixth transistor T6 is transmitted with the third driving signal Gate3 to make the second initial voltage signal Vini2 written to the fourth node N4, so that the residual charge of the light emitting device 106' and the second capacitor C2 can be cleared, and since the fourth transistor T4 is in the conductive state, the residual charge of the output end of the zeroth transistor DT can also be cleared.

[0151] S120, in the write compensation stage, controlling the first light emitting control unit 102 to be turned off to make the first constant voltage end ELVDD and the first node N1 cut off, and controlling the data write compensation unit 104 to write the data voltage signal Vdata to the third node N3.

[0152] For example, as shown in FIG. 13 in combination with FIGS. 5 and 6, P2 represents the write compensation stage. In the P2 stage, the fifth transistor T5 and the second transistor T2 are in the cut-off state, and the third transistor T3 is transmitted with the first driving signal Gate1 to make the data voltage signal Vdata written to the third node N3.

[0153] After the P1 stage, at this time, the potential of the first node N1 is ELVDD, the potential of the third node N3 is Vdata, the potential of the second node N2 is Vini1, and the zeroth transistor DT is in the conductive state under the control of the potential of the second node N2. Since the potential of the first node N1 is higher than the potential of the third node N3, the charge of the first node N1 flows into the third node N3 through the zeroth transistor DT, and the first capacitor C1 drives the potential of the second node N2 to drop due to the loss of the charge of the first node N1, until the potential difference between the second node N2 and the third node N3 is the threshold difference of the zeroth transistor DT, and the zeroth transistor DT is cut off, then the potential of the second node N2 drops from Vini1 to Vdata+Vth.

[0154] In some examples, the pixel circuit 10 further comprises a second charge storage unit 109, one end of the second charge storage unit 109 is electrically connected with the second node N2, and the other end of the second charge storage unit 109 is electrically connected with the fourth node N4,

[0155] The driving method further comprises: in the write compensation phase, controlling the reset unit 108 to write the second initial voltage signal Vini2 to the fourth node N4.

[0156] For example, in the P2 phase, the sixth transistor is controlled to write the second initial voltage signal Vini2 to the fourth node N4. Since in the P2 phase, the potential of the second node N2 will be lowered under the control of the first capacitor C1, and the second capacitor C2 is connected between the second node N2 and the fourth node N4, by transmitting a constant voltage signal to the fourth node N4, the influence of the second capacitor C2 on the potential of the second node N2 can be reduced.

[0157] S130, in the light emitting phase, the first light emitting control unit 102 is controlled to be turned on to make the first constant voltage terminal ELVDD conduct with the first node N1, so that the driving transistor 101 drives the light emitting device 106' to emit light.

[0158] For example, as shown in FIG. 13 in combination with FIGS. 5 and 6, P3 represents the light emitting phase. The second transistor T2 is turned on under the action of the first light emitting control signal EM1, the first constant voltage terminal ELVDD conducts with the first node N1, the fourth transistor T4 is turned on under the action of the second light emitting control signal EM2, and the third transistor T3, the fifth transistor T5 and the sixth transistor T6 are turned off. The light emitting device 106' emits light under the action of the driving current controlled by the zeroth transistor DT.

[0159] In some examples, the first charge storage unit 103 comprises an access subunit 1031 and a charge storage subunit 1032, one end of the charge storage subunit 1032 is electrically connected with the second node N2, the other end of the charge storage subunit 1032 is electrically connected with the first node N1, and the access subunit 1031 is connected in series between the charge storage subunit 1032 and the first node N1 or the second node N2,

[0160] The driving method further comprises: in the light emitting phase, the access subunit 1031 is controlled to be turned off to disconnect the path formed by the charge storage subunit 1032 and the access subunit 1031.

[0161] For example, as shown in FIG. 13 in combination with FIGS. 5 and 6, in the P3 phase, the first transistor T1 is controlled to be turned off by sending the fourth driving signal Gate4, so that the first capacitor C1 is disconnected between the first node N1 and the fourth node N4, thereby reducing the interference of the capacitor on the gate potential of the driving transistor 101 in the light emitting phase.

[0162] In some examples, as shown in the embodiments of FIG. 7 and FIG. 8, when the pixel circuit 10 described above includes the second charging unit 110, the following method can also be used. FIG. 14 is a circuit timing diagram of another pixel circuit 10 provided in an embodiment of the present disclosure. The driving method provided in an embodiment of the present disclosure is described below in conjunction with FIG. 14.

[0163] It should be noted that the same control logic of the same devices in FIG. 14 and FIG. 13 is not described again.

[0164] For example, as shown in the embodiments of FIG. 7 and FIG. 8, in the P1 stage, the first light-emitting control signal EM1 is transmitted to the second transistor T2 to control it to be turned off, and the fifth driving signal is transmitted to the seventh transistor T7 to control it to be turned on, and the third initial voltage signal Vini3 is transmitted to the end of the first capacitor C1 that is not connected to the fifth transistor T5, so that the first capacitor C1 is charged by the seventh transistor T7 and the fifth transistor T5.

[0165] It should be noted that the second transistor T2 is controlled to be turned off to avoid short circuit.

[0166] In the P2 and P3 stages, the control logic of the pixel circuit 10 corresponding to FIG. 14 and FIG. 13 is the same, and is not described again.

[0167] An embodiment of the present disclosure further provides a controller, including: a first memory, which stores a computer program; and a first processor, which is configured to invoke the computer program in the first memory, and the computer program is configured to execute the driving method according to any one of the embodiments of FIG. 12.

[0168] For example, the controller can include a processor or a processing chip, and can also be a GPU (Graphics Processing Unit, graphics processor).

[0169] An embodiment of the present disclosure further provides a display device. FIG. 15 is a schematic block diagram of a display device provided in an embodiment of the present disclosure. As shown in FIG. 15, the display device includes the display panel 1 according to any one of the embodiments of FIG. 9 and / or the controller 2.

[0170] For example, the display device provided in an embodiment of the present disclosure can be applied to vehicle display, smart phone, computer, medical display, television, smart wearable display, and the like, which are not limited in the present disclosure.

[0171] The above examples are only used to illustrate the technical solutions of the present disclosure, rather than limit them; although the present disclosure has been described in detail with reference to the foregoing examples, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing examples, or make equivalent replacements for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure. < / n>

Claims

1. A pixel circuit comprising: a driving transistor for driving a light emitting device; a first light emitting control unit, one end of which is electrically connected with a first constant voltage terminal and the other end of which is electrically connected with a first electrode of the driving transistor through a first node, the first light emitting control unit being configured to control conduction or block between the first constant voltage terminal and the first node under the action of a first light emitting control signal; a first charge storage unit, one end of which is electrically connected with the first node and the other end of which is electrically connected with a gate of the driving transistor through a second node, the first charge storage unit being configured to release charges to the first node and the second node to dynamically balance between the potential of the first node and the potential of the second node; a data writing compensation unit, which is electrically connected with a second electrode of the driving transistor through a third node, the data writing compensation unit being configured to write a data voltage signal into the third node under the action of a first driving signal, the voltage value of the data voltage signal being less than the voltage value of the first constant voltage terminal; a first charging unit, which is electrically connected with the second node, the first charging unit being configured to write a first initial voltage signal into the second node under the action of a second driving signal, the voltage value of the first initial voltage signal being capable of driving the driving transistor to conduct; wherein the starting time of the effective level of the first driving signal is later than or equal to the ending time of the effective level of the second driving signal.

2. The pixel circuit according to claim 1, further comprising: a second light emitting control unit, one end of which is electrically connected with the third node and the other end of which is electrically connected with the light emitting device through a fourth node, the second light emitting control unit being configured to control conduction or block between the third node and the fourth node under the action of a second light emitting control signal.

3. The pixel circuit according to claim 2, further comprising: a reset unit, which is electrically connected with the fourth node, the reset unit being configured to write a second initial voltage signal into the fourth node under the action of a third driving signal.

4. The pixel circuit according to claim 3, further comprising: a second charge storage unit, one end of which is electrically connected with the second node and the other end of which is electrically connected with the fourth node, the second charge storage unit being configured to release charges to the second node and the fourth node to dynamically balance between the potential of the second node and the potential of the fourth node.

5. The pixel circuit of claim 4, wherein, the starting time of the effective level of the third driving signal is the same as the starting time of the effective level of the second driving signal, and the ending time of the effective level of the third driving signal is the same as the ending time of the effective level of the first driving signal.

6. The pixel circuit according to any one of claims 1 to 5, wherein the first charge storage unit comprises an access subunit and a charge storage subunit, One end of the charge storage subunit is electrically connected with the second node, and the other end of the charge storage subunit is electrically connected with the first node, and the access subunit is connected in series between the charge storage subunit and the first node or the second node; The access subunit is configured to control whether the charge storage subunit is connected between the first node and the second node under the action of a fourth driving signal, and the charge storage subunit is configured to release charges to the first node and the second node to dynamically balance the electric potential of the first node and the electric potential of the second node.

7. The pixel circuit of claim 6, further comprising: a second charging unit, the second charging unit being electrically connected with the other end of the charge storage subunit, and the second charging unit being configured to write a third initial voltage signal into the charge storage subunit under the action of a fifth driving signal; The starting moment of the effective level of the second driving signal is the same as the starting moment of the effective level of the fifth driving signal, and the termination moment of the effective level of the second driving signal is the same as the termination moment of the effective level of the fifth driving signal.

8. The pixel circuit of claim 6, wherein, The access subunit comprises a first transistor, and the charge storage subunit comprises a first capacitor; The gate of the first transistor is configured to receive the fourth driving signal, one end of the first capacitor is electrically connected with the second node, the other end of the first capacitor is electrically connected with the first node, and the first transistor is connected in series between the first capacitor and the first node or the second node.

9. A pixel circuit comprising: a driving transistor, a first light-emitting control unit, a second light-emitting control unit, a first charge storage unit, a second charge storage unit, a data writing compensation unit, a reset unit, and a first charging unit; The driving transistor comprises a zeroth transistor, and the first electrode, the second electrode, and the gate of the zeroth transistor are electrically connected with a first node, a third node, and a second node, respectively; The first light-emitting control unit comprises a second transistor, the gate of the second transistor is configured to receive a first light-emitting control signal, the first electrode of the second transistor is electrically connected with a first constant voltage terminal, and the second electrode of the second transistor is electrically connected with the first node; The data writing compensation unit comprises a third transistor, the gate of the third transistor is configured to receive a first driving signal, the first electrode of the third transistor is configured to receive a data voltage signal, and the second electrode of the third transistor is electrically connected with the third node; The second light-emitting control unit comprises a fourth transistor, the gate of the fourth transistor is configured to receive a second light-emitting control signal, the first electrode of the fourth transistor is electrically connected with the third node, and the second electrode of the fourth transistor is electrically connected with a light-emitting device through a fourth node; The first charging unit comprises a fifth transistor, the gate of the fifth transistor is configured to receive a second driving signal, the first electrode of the fifth transistor is configured to receive a first initial voltage signal, and the second electrode of the fifth transistor is electrically connected with the second node. The reset unit comprises a sixth transistor, a gate electrode of the sixth transistor is configured to receive a third driving signal, a first electrode of the sixth transistor is configured to receive a second initial voltage signal, and a second electrode of the sixth transistor is electrically connected with the fourth node; The first charge storage unit comprises an access subunit and a charge storage subunit, the access subunit comprises a first transistor, the charge storage subunit comprises a first capacitor, a gate electrode of the first transistor is configured to receive a fourth driving signal, one end of the first capacitor is electrically connected with the second node, the other end of the first capacitor is electrically connected with the first node, and the first transistor is connected in series between the first capacitor and the first node or the second node; The second charge storage unit comprises a second capacitor, and the second capacitor is connected in series between the second node and the fourth node.

10. The pixel circuit of claim 9, further comprising: a second charging unit, the second charging unit comprising a seventh transistor, a gate electrode of the seventh transistor is configured to receive a fifth driving signal, a first electrode of the seventh transistor is electrically connected with the other end of the first capacitor, and a second electrode of the seventh transistor is configured to receive a third initial voltage signal; wherein the starting time and the ending time of the active level of the second driving signal and the fifth driving signal are the same.

11. The pixel circuit of claim 9 or 10, wherein, The voltage value of the data voltage signal is less than the voltage value of the first constant voltage terminal; The voltage value of the first initial voltage signal is capable of driving the driving transistor to turn on; The starting time of the active level of the first driving signal is later than or equal to the ending time of the active level of the second driving signal; The starting time of the active level of the second driving signal, the third driving signal and the fourth driving signal are the same, and the ending time of the active level of the first driving signal, the third driving signal and the fourth driving signal are the same.

12. A display panel comprising a plurality of pixel circuits according to any one of claims 1 to 11.

13. The display panel of claim 12, wherein, The first driving signal received by the pixel circuit of the nth row is the same as the second driving signal received by the pixel circuit of the (n-1)th row, and n is an integer greater than or equal to 2.

14. A driving method of a pixel circuit, for driving a pixel circuit according to any one of claims 1 to 11, the driving method comprising: in a reset phase, controlling the first light emitting control unit to turn on to make the first constant voltage terminal and the first node conductive, and controlling the first charging unit to write a first initial voltage signal to the second node; in a write compensation phase, controlling the first light emitting control unit to turn off to make the first constant voltage terminal and the first node non-conductive, and controlling the data write compensation unit to write the data voltage signal to the third node; in a light emitting phase, controlling the first light emitting control unit to turn on to make the first constant voltage terminal and the first node conductive, so that the driving transistor drives the light emitting device to emit light.

15. The driving method according to claim 14, wherein the pixel circuit further comprises a second light emitting control unit and a reset unit, one end of the second light emitting control unit is electrically connected with the third node, and the other end is electrically connected with the light emitting device through a fourth node, the reset unit is electrically connected with the fourth node, and the driving method further comprises: in the reset stage, controlling the second light emitting control unit to be turned on to make the third node and the fourth node conductive, and controlling the reset unit to write a second initial voltage signal to the fourth node.

16. The driving method according to claim 15, wherein the pixel circuit further comprises a second charge storage unit, one end of the second charge storage unit is electrically connected with the second node, and the other end is electrically connected with the fourth node, and the driving method further comprises: in the write compensation stage, controlling the reset unit to write the second initial voltage signal to the fourth node.

17. The driving method according to any one of claims 14 to 16, wherein the first charge storage unit comprises an access subunit and a charge storage subunit, one end of the charge storage subunit is electrically connected with the second node, the other end of the charge storage subunit is electrically connected with the first node, and the access subunit is connected in series between the charge storage subunit and the first node or the second node, and the driving method further comprises: in the light emitting stage, controlling the access subunit to be turned off to make the access subunit and the charge storage subunit disconnected.

18. A controller, comprising: a memory storing a computer program; and a processor configured to invoke the computer program in the memory, the computer program being configured to perform the driving method according to any one of claims 14 to 17.

19. A display device, comprising the display panel according to claim 12 or 13 and / or the controller according to claim 18. ​ ​ ​ ​ ​ ​ ​ ​

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