Display substrate and driving method therefor, and display apparatus

Abstract

A display substrate and a driving method therefor, and a display apparatus. A driving circuit is disposed in a non-display area of the display substrate, and comprises shift registers, wherein each shift register comprises a driving output subcircuit that is configured to provide a signal to at least one row of pixel driving circuits under the control of a first masking signal (MS1) of a masking signal end (MS). In a display frame where adjacent sub-display areas (11, 12) have different refresh rates, signals of an output power supply end (V) and the masking signal end (MS) are controlled, such that a signal of the output power supply end (V) is a first power supply signal (VS1) for part of the time and a second power supply signal (VS2) for part of the time, and a signal of the masking signal end (MS) is the first masking signal (MS1) for part of the time and a second masking signal (MS2) for part of the time, wherein the voltage value of the first power supply signal (VS1) is different from the voltage value of the second power supply signal (VS2), and the time period during which the signal of the output power supply end (V) is the second power supply signal (VS2) at least partially overlaps with the time period during which the signal of the masking signal end (MS) is the second masking signal (MS2).

Description

Display substrate, driving method thereof and display device

[0001] The present application claims priority to the Chinese patent application No. 202410461428.X, filed on April 17, 2024, and entitled "Display substrate, driving method thereof and display device", the content of which should be understood as incorporated herein by reference. TECHNICAL FIELD

[0002] The present disclosure relates to the technical field of display, in particular to a display substrate, a driving method thereof and a display device. BACKGROUND

[0003] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diodes (QLED) are active light-emitting display devices, which have the advantages of self-emission, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility and low cost. With the continuous development of display technology, display devices using OLED or QLED as light-emitting devices and controlled by Thin Film Transistor (TFT) have become the mainstream products in the current display field. SUMMARY

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] In a first aspect, the present disclosure provides a display substrate having a display area and a non-display area, the display area comprising: at least two sub-display areas, the content displayed by the display substrate comprising: at least two display frames, the refresh rates of adjacent sub-display areas being different in at least one display frame;

[0006] The display area is provided with an array of pixel driving circuits, and the non-display area is provided with a driving circuit, the driving circuit comprising: a plurality of cascaded shift registers, at least one level of shift registers being electrically connected with at least one row of pixel driving circuits, the shift registers comprising: a driving output sub-circuit;

[0007] The driving output sub-circuit is electrically connected with an output power supply end, a masking signal end and at least one row of pixel driving circuits, respectively, and is configured to provide the signal of the output power supply end to at least one row of pixel driving circuits under the control of the first masking signal of the masking signal end;

[0008] The display substrate further comprises a controller electrically connected with the output power terminal and the masking signal terminal respectively, configured to control signals of the output power terminal and the masking signal terminal in display frames of adjacent sub-display areas with different refresh rates, so that the signal of the output power terminal is the first power signal in part of time and the second power signal in part of time, and the signal of the masking signal terminal is the first masking signal in part of time and the second masking signal in part of time, wherein the voltage value of the first power signal is different from the voltage value of the second power signal, the voltage value of the first masking signal is different from the voltage value of the second masking signal, and the time period when the signal of the output power terminal is the second power signal at least partially overlaps with the time period when the signal of the masking signal terminal is the second masking signal.

[0009] In an example embodiment, the pixel driving circuit comprises a driving transistor and a compensation transistor electrically connected with the control electrode of the driving transistor.

[0010] The driving output sub-circuit of the at least one stage of shift register is electrically connected with the compensation transistor of the at least one row of pixel driving circuits.

[0011] In an example embodiment, the shift register further comprises a cascade output sub-circuit.

[0012] The cascade output sub-circuit is electrically connected with the driving output sub-circuit and the cascade output sub-circuit of the previous stage of shift register respectively, and configured to provide signals by the driving output sub-circuit and the cascade output sub-circuit of the previous stage of shift register.

[0013] In display frames of adjacent sub-display areas with the same refresh rate, the signal output by the cascade output sub-circuit of the same shift register is the same as the signal output by the driving output sub-circuit.

[0014] In an example embodiment, in display frames of adjacent sub-display areas with the same refresh rate, the signal of the output power terminal is the first power signal, and the signal of the masking signal terminal is the first masking signal.

[0015] In an example embodiment, the time period when the signal of the output power terminal is the second power signal is within the time period when the signal of the masking signal terminal is the second masking signal.

[0016] In an example embodiment, the compensation transistor is an N-type transistor, the first power signal and the second power signal are positive voltage signals, and the voltage value of the first power signal is greater than the voltage value of the second power signal.

[0017] In an exemplary embodiment, a difference between the voltage value of the first power signal and the voltage value of the second power signal is within a range of 0.01 volt to 0.5 volt.

[0018] In an exemplary embodiment, the compensation transistor is a P-type transistor, the first power signal and the second power signal are negative voltage signals, and an absolute value of the voltage value of the first power signal is greater than an absolute value of the voltage value of the second power signal.

[0019] In an exemplary embodiment, a difference between the absolute value of the voltage value of the first power signal and the absolute value of the voltage value of the second power signal is within a range of 0.01 volt to 0.5 volt.

[0020] In an exemplary embodiment, the display area includes M first sub-display areas and N second sub-display areas, the M first sub-display areas and the N second sub-display areas are arranged alternately, and in a display frame in which refresh rates of adjacent sub-display areas are different, the refresh rate of the first sub-display area is greater than the refresh rate of the second sub-display area.

[0021] The signal of the output power terminal is the second power signal in N time periods, and the signal of the masking signal terminal is the second masking signal in N time periods.

[0022] The start time of the signal of the masking signal terminal being the second masking signal in the nth time period is earlier than or equal to the start time of the output signal of the cascade output sub-circuit of the shift register connected to the first row of pixel driving circuits in the nth second sub-display area and later than the start time of the output signal of the cascade output sub-circuit of the shift register connected to the last row of pixel driving circuits in the nth first sub-display area, and 1≤n≤N.

[0023] In an exemplary embodiment, M-N=1, the start time of the signal of the output power terminal being the second power signal in the nth time period is the start time of the signal of the masking signal terminal being the second masking signal in the nth time period.

[0024] The end time of the signal of the output power terminal being the second power signal in the nth time period is later than the end time of the output signal of the cascade output sub-circuit of the shift register connected to the last row of pixel driving circuits in the nth first sub-display area and earlier than the start time of the output signal of the cascade output sub-circuit of the shift register connected to the first row of pixel driving circuits in the nth+1 first sub-display area.

[0025] In an exemplary embodiment, N-M=1, the start time of the signal of the output power terminal being the second power signal in the nth time period is the start time of the signal of the masking signal terminal being the second masking signal in the nth time period.

[0026] The end time of the first time period of the signal at the output power end being the second power signal is earlier than the start time of the output signal of the cascade output sub-circuit of the shift register connected to the first row of pixel driving circuits located in the first first sub-display area; the end time of the kth time period of the signal at the output power end being the second power signal is later than the end time of the output signal of the cascade output sub-circuit of the shift register connected to the last row of pixel driving circuits located in the k-1th first sub-display area, and is earlier than the start time of the output signal of the cascade output sub-circuit of the shift register connected to the first row of pixel driving circuits located in the kth first sub-display area, 2≤k≤N.

[0027] In an exemplary embodiment, M=N, the start time of the nth time period in which the signal at the output power terminal is the second power signal is the start time of the nth time period in which the signal at the mask signal terminal is the second mask signal;

[0028] The end time of the mth time period of the signal at the output power terminal being the second power signal is later than the end time of the output signal of the cascade output sub-circuit of the shift register connected to the last row of pixel driving circuits located in the mth first sub-display area, and is earlier than the start time of the output signal of the cascade output sub-circuit of the shift register connected to the first row of pixel driving circuits located in the i+1th first sub-display area. The end time of the Nth time period of the signal at the output power terminal being the second power signal is earlier than the end time of the Nth time period of the signal at the masking signal terminal being the second masking signal, 1≤m≤N-1.

[0029] In an exemplary embodiment, the non-display area is further provided with a masking signal line, and the masking signal terminal of at least one stage of shift register in the driving circuit is electrically connected to the masking signal line.

[0030] In an exemplary embodiment, the drive circuit further includes: an output power line, to which the output power terminal of at least one stage of the shift register in the drive circuit is electrically connected;

[0031] The controller includes: a first control chip and a second control chip;

[0032] The first control chip is electrically connected to the output power line and is configured to provide a first power signal to the output power line for part of the time and a second power signal to the output power line for part of the time in display frames in which adjacent sub-display areas have different refresh rates, and to provide the first power signal to the output power line for display frames in which adjacent sub-display areas have the same refresh rate;

[0033] The second control chip is electrically connected with the masking signal line and is configured to provide the first masking signal to the masking signal line in part of time and provide the second masking signal to the masking signal line in part of time in a display frame in which the refresh rates of the adjacent sub-display areas are different, and provide the first masking signal to the masking signal line in a display frame in which the refresh rates of the adjacent sub-display areas are same.

[0034] In an example embodiment, the non-display area is further provided with an output power line, a signal conversion line and a signal conversion sub-circuit, an output power terminal of at least one stage of shift register in the driving circuit is electrically connected with the output power line, and the controller comprises a control chip;

[0035] The signal conversion sub-circuit is electrically connected with the masking signal line, the output power line and the signal conversion line respectively, and is configured to provide the signal of the signal conversion line to the output power line under the control of the second masking signal of the masking signal line, the signal of the output power line is a first power signal, and the signal of the signal conversion line is a second power signal.

[0036] The control chip is electrically connected with the masking signal line and is configured to provide the first masking signal to the masking signal line in part of time and provide the second masking signal to the masking signal line in part of time in a display frame in which the refresh rates of the adjacent sub-display areas are different, and provide the first masking signal to the masking signal line in a display frame in which the refresh rates of the adjacent sub-display areas are same.

[0037] In an example embodiment, the signal conversion sub-circuit comprises a conversion transistor.

[0038] The control electrode of the conversion transistor is electrically connected with the masking signal line, the first electrode of the conversion transistor is electrically connected with the output power line, and the second electrode of the conversion transistor is electrically connected with the signal conversion line.

[0039] In an example embodiment, the cascade output sub-circuit comprises a first transistor to a sixteenth transistor, a first capacitor, a second capacitor, a third capacitor and a fifth capacitor, and the driving output sub-circuit comprises a seventeenth transistor to a twenty-fourth transistor, a fourth capacitor.

[0040] The gate electrode of the first transistor is electrically connected with the first clock signal end, the first electrode of the first transistor is electrically connected with the signal input end, and the second electrode of the first transistor is electrically connected with the first node; the gate electrode of the second transistor is electrically connected with the first node, the first electrode of the second transistor is electrically connected with the first clock signal end, and the second electrode of the second transistor is electrically connected with the second node; the gate electrode of the third transistor is electrically connected with the first clock signal end, the first electrode of the third transistor is electrically connected with the second power supply end, and the second electrode of the third transistor is electrically connected with the second node; the gate electrode of the fourth transistor is electrically connected with the third node, the first electrode of the fourth transistor is electrically connected with the second clock signal end, and the second electrode of the fourth transistor is electrically connected with the fourth node; the gate electrode of the fifth transistor is electrically connected with the second node, the first electrode of the fifth transistor is electrically connected with the first power supply end, and the second electrode of the fifth transistor is electrically connected with the fourth node; the gate electrode of the sixth transistor is electrically connected with the fifth node, the first electrode of the sixth transistor is electrically connected with the second clock signal end, and the second electrode of the sixth transistor is electrically connected with the sixth node; the gate electrode of the seventh transistor is electrically connected with the second clock signal end, the first electrode of the seventh transistor is electrically connected with the sixth node, and the second electrode of the seventh transistor is electrically connected with the seventh node; the gate electrode of the eighth transistor is electrically connected with the first node, the first electrode of the eighth transistor is electrically connected with the first power supply end, and the second electrode of the eighth transistor is electrically connected with the seventh node; the gate electrode of the ninth transistor is electrically connected with the seventh node, the first electrode of the ninth transistor is electrically connected with the first power supply end, and the second electrode of the ninth transistor is electrically connected with the cascade signal output end; the gate electrode of the tenth transistor is electrically connected with the eighth node, the first electrode of the tenth transistor is electrically connected with the third power supply end, and the second electrode of the tenth transistor is electrically connected with the cascade signal output end; the gate electrode of the eleventh transistor is electrically connected with the second power supply end, the first electrode of the eleventh transistor is electrically connected with the second node, and the second electrode of the eleventh transistor is electrically connected with the fifth node; the gate electrode of the twelfth transistor is electrically connected with the third power supply end, the first electrode of the twelfth transistor is electrically connected with the first node, and the second electrode of the twelfth transistor is electrically connected with the eighth node; the gate electrode of the thirteenth transistor is electrically connected with the fourth power supply end, the first electrode of the thirteenth transistor is electrically connected with the first power supply end, and the second electrode of the thirteenth transistor is electrically connected with the first node; the gate electrode of the fourteenth transistor is electrically connected with the first clock signal end, the first electrode of the fourteenth transistor is electrically connected with the signal input end, and the second electrode of the fourteenth transistor is electrically connected with the first electrode of the fifteenth transistor; the gate electrode of the fifteenth transistor is electrically connected with the second power supply end, the second electrode of the fifteenth transistor is electrically connected with the third node; the gate electrode of the sixteenth transistor is electrically connected with the third node, the first electrode of the sixteenth transistor is electrically connected with the third node, and the second electrode of the sixteenth transistor is electrically connected with the eighth node;The gate electrode of the seventeenth transistor is electrically connected with the eighth node, the first electrode of the seventeenth transistor is electrically connected with the third power supply end, the second electrode of the seventeenth transistor is electrically connected with the driving signal output end, the gate electrode of the eighteenth transistor is electrically connected with the seventh node, the first electrode of the eighteenth transistor is electrically connected with the output power supply end, the second electrode of the eighteenth transistor is electrically connected with the first electrode of the nineteenth transistor, the gate electrode of the nineteenth transistor is electrically connected with the ninth node, the second electrode of the nineteenth transistor is electrically connected with the driving signal output end, the gate electrode of the twentieth transistor is electrically connected with the inverse signal output end of the previous stage shift register, the first electrode of the twentieth transistor is electrically connected with the ninth node, the second electrode of the twentieth transistor is electrically connected with the second electrode of the twenty-first transistor, the gate electrode of the twenty-first transistor is electrically connected with the cascade signal output end, the second electrode of the twenty-first transistor is electrically connected with the masking signal end, the gate electrode of the twenty-second transistor is electrically connected with the cascade signal output end, the first electrode of the twenty-second transistor is electrically connected with the third power supply end, the second electrode of the twenty-second transistor is electrically connected with the inverse signal output end, the gate electrode of the twenty-third transistor is electrically connected with the cascade signal output end, the first electrode of the twenty-third transistor is electrically connected with the first power supply end, the second electrode of the twenty-third transistor is electrically connected with the inverse signal output end, the gate electrode of the twenty-fourth transistor is electrically connected with the ninth node, the first electrode of the twenty-fourth transistor is electrically connected with the second power supply end, the second electrode of the twenty-fourth transistor is electrically connected with the driving signal output end, the first plate of the first capacitor is electrically connected with the fifth node, the second plate of the first capacitor is electrically connected with the sixth node, the first plate of the second capacitor is electrically connected with the seventh node, the second plate of the second capacitor is electrically connected with the first power supply end, the first plate of the third capacitor is electrically connected with the third node, the second plate of the third capacitor is electrically connected with the fourth node, the first plate of the fourth capacitor is electrically connected with the ninth node, the second plate of the fourth capacitor is electrically connected with the output power supply end, the first plate of the fifth capacitor is electrically connected with the second power supply end, and the second plate of the fifth capacitor is electrically connected with the cascade signal output end.

[0041] In a second aspect, the present disclosure also provides a display device, comprising the display substrate.

[0042] In a third aspect, the present disclosure also provides a driving method of a display substrate, configured to drive the display substrate, the method further comprising:

[0043] In the display frames with different refresh rates of adjacent sub-display areas, the signals of the output power supply end and the masking signal end are controlled, so that the signal of the output power supply end is the first power supply signal in part of the time and the second power supply signal in part of the time, and the signal of the masking signal end is the first masking signal in part of the time and the second masking signal in part of the time.

[0044] Other aspects can become apparent from the following drawings and detailed description.

[0045] Summary of the Figures

[0046] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0047] FIG1 is a schematic structural diagram of a display device;

[0048] FIG2 is a schematic diagram of a planar structure of a display substrate;

[0049] FIG3 is a second schematic diagram of a planar structure of a display substrate;

[0050] FIG4 is a third schematic diagram of a planar structure of a display substrate;

[0051] FIG5 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0052] FIG6 is a timing diagram of the operation of the pixel driving circuit provided in FIG5 ;

[0053] FIG7 is an equivalent circuit diagram of a shift register;

[0054] FIG8 is a schematic diagram of a cascade connection of shift registers;

[0055] FIG9 is a timing diagram of the operation of a portion of a shift register;

[0056] FIG10 is a schematic diagram of a signal terminal and a masking signal terminal of a driving signal output terminal of at least a portion of a shift register;

[0057] FIG11 is a schematic structural diagram of a display substrate provided in an embodiment of the present disclosure;

[0058] FIG12 is a schematic diagram of signals at an output power terminal and a masked signal terminal provided by an embodiment of the present disclosure;

[0059] FIG13 is a schematic diagram showing the arrangement of a display area of ​​a display substrate;

[0060] FIG14 is a second schematic diagram of the arrangement of the display area of ​​a display substrate;

[0061] FIG15 is a third schematic diagram of the arrangement of the display area of ​​a display substrate;

[0062] FIG16 is a schematic structural diagram of a display substrate;

[0063] FIG17 is an equivalent circuit diagram of the signal conversion subcircuit.

[0064] Details

[0065] In order to make the objects, technical solutions and advantages of the present disclosure clearer, the following will be used to specifically explain the embodiments of the present disclosure with reference to the drawings. It should be noted that the embodiments can be implemented in a variety of different forms. Those skilled in the art can easily understand that the modes and contents can be changed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be combined with each other arbitrarily without conflict.

[0066] The proportions of the drawings in the present disclosure can be used as a reference in the actual process, but are not limited thereto. For example, the width-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are also not limited to the number shown in the drawings. The drawings described in the present disclosure are only schematic structural diagrams, and one embodiment of the present disclosure is not limited to the shapes or values shown in the drawings.

[0067] In the present specification, ordinal numbers such as "first", "second", "third", and the like are provided to avoid confusion of constituent elements, and are not intended to be limited in terms of numbers.

[0068] In the present specification, for the convenience of explanation, words indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to explain the positional relationship of the constituent elements with reference to the drawings, and are only for the convenience of describing the present specification and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction of describing each constituent element. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0069] In the present specification, unless specifically defined and limited otherwise, the terms "mount", "connected", "connection" should be interpreted broadly. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate piece, or the communication inside two elements. Those skilled in the art can understand the specific meaning of the above terms in the present disclosure according to the specific circumstances.

[0070] In this specification, a transistor refers to an element including at least a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and a source electrode (a source electrode terminal, a source region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that, in this specification, the channel region refers to a region where current flows mainly.

[0071] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or the first electrode can be a source electrode and the second electrode can be a drain electrode. In the case of using a transistor having opposite polarity or in the case of changing the direction of current in circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Thus, in this specification, the "source electrode" and the "drain electrode" can be interchanged, and the "source terminal" and the "drain terminal" can be interchanged.

[0072] In this specification, "electrically connected" includes the case where components are connected through an element having some function of electricity. The element having some function of electricity is not particularly limited as long as electric signals can be transmitted and received between components to be connected. Examples of the element having some function of electricity include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, and another element having some function.

[0073] In this specification, "parallel" refers to a state where an angle formed between two straight lines is greater than or equal to -10° and less than or equal to 10°, and thus includes a state where the angle is greater than or equal to -5° and less than or equal to 5°. In addition, "perpendicular" refers to a state where an angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and thus includes a state where the angle is greater than or equal to 85° and less than or equal to 95°.

[0074] In this specification, "film" and "layer" can be interchanged with each other. For example, "a conductive layer" can be replaced with "a conductive film". Similarly, "an insulating film" can be replaced with "an insulating layer".

[0075] In this specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon is not necessarily a strict one, can be an approximate triangle, rectangle, trapezoid, pentagon, or hexagon, and can have some small deformation due to a tolerance, a rounded corner, a rounded side, or deformation.

[0076] FIG. 1 is a structural schematic diagram of a display device. As shown in FIG. 1, the display device can include a timing controller, a data driver, a gate driver, and a pixel array, the timing controller is connected with the data driver and the gate driver respectively, the data driver is connected with a plurality of data signal lines (D1 to Dn) respectively, and the gate driver is connected with a plurality of gate signal lines (G1 to Gm) respectively. The pixel array can include a plurality of sub-pixels Pxij, i and j can be natural numbers, at least one sub-pixel Pxij can include a circuit unit and a light emitting device connected with the circuit unit, the circuit unit can include a pixel driving circuit, and the pixel driving circuit can be connected with the gate signal line and the data signal line respectively.

[0077] In an exemplary embodiment, the timing controller can provide a gray scale value and a control signal suitable for the specification of the data driver to the data driver, can provide a clock signal, a scan start signal, and the like suitable for the specification of the scan driver to the scan driver, and can provide a clock signal, an emission stop signal, and the like suitable for the specification of the light emitting driver to the light emitting driver. The data driver can generate data voltages to be provided to the data signal lines D1, D2, D3, …, and Dn using the gray scale value and the control signal received from the timing controller. For example, the data driver can sample the gray scale value using the clock signal, and apply data voltages corresponding to the gray scale value to the data signal lines D1 to Dn in units of a pixel row, n can be a natural number.

[0078] In an exemplary embodiment, the gate driver can generate scan signals to be provided to the gate signal lines G1, G2, G3, …, to Gm by receiving a clock signal, a gate start signal, and the like from the timing controller. For example, the scan driver can sequentially provide the scan signals having a turn-on level pulse to the gate signal lines G1 to Gm. For example, the gate driver can be configured in the form of a shift register, and can generate the scan signals in a manner that sequentially transfers the scan start signal provided in the form of a turn-on level pulse to the next stage circuit under the control of the clock signal, m can be a natural number.

[0079] FIG. 2 is a schematic diagram of a planar structure of a display substrate, FIG. 3 is a schematic diagram of a planar structure of a display substrate, and FIG. 4 is a schematic diagram of a planar structure of a display substrate. As shown in FIGS. 2 to 4, the display substrate can include a plurality of pixel units P arranged in a matrix manner, at least one of the plurality of pixel units P including a first sub-pixel P1 emitting first color light, a second sub-pixel P2 emitting second color light, and a third sub-pixel P3 emitting third color light, the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 each including a pixel driving circuit and a light emitting device. The pixel driving circuits in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to a gate signal line and a data signal line, and the pixel driving circuits are configured to receive a data voltage transmitted by the data signal line under the control of the gate signal line and output a corresponding current to the light emitting device. The light emitting devices in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to the pixel driving circuit of the sub-pixel in which the light emitting device is located, and the light emitting devices are configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which the light emitting device is located.

[0080] In an example embodiment, the first sub-pixel P1 can be a red sub-pixel (R) emitting red light, the second sub-pixel P2 can be a blue sub-pixel (B) emitting blue light, and the third sub-pixel P3 can be a green sub-pixel (G) emitting green light.

[0081] In an example embodiment, the shape of the sub-pixel can be rectangular, diamond, pentagonal, or hexagonal, and the three sub-pixels can be arranged in a horizontal parallel, vertical parallel, or triangular manner, which is not limited in the present disclosure.

[0082] In an example embodiment, the pixel unit can include three sub-pixels, and the three sub-pixels can be arranged in a horizontal parallel, vertical parallel, or triangular manner, which is not limited in the present disclosure. FIGS. 2 and 3 are described by taking an example in which the pixel unit includes three sub-pixels. The three sub-pixels in FIG. 2 are arranged in a horizontal parallel manner, and the three sub-pixels in FIG. 3 are arranged in a triangular manner.

[0083] In an example embodiment, the pixel unit can include four sub-pixels, and the four sub-pixels can be arranged in a horizontal parallel, vertical parallel, or square manner, which is not limited in the present disclosure. FIG. 4 is described by taking an example in which the pixel unit includes four sub-pixels and the four sub-pixels are arranged in a square manner.

[0084] In the display market, the low temperature poly-silicon (LTPS) technology is used in most display substrates, and the LTPS technology has advantages of high resolution, high response speed, high brightness, high aperture ratio, etc. Although the LTPS technology is welcomed by the market, the LTPS technology also has some defects, such as high production cost, large power consumption, etc. At this time, the low temperature polycrystalline oxide (LTPO) technology scheme emerges as the times require. Compared with the LTPS technology, the LTPO technology has smaller leakage current, faster pixel point response, and the display substrate is additionally provided with an oxide layer, so that the energy consumption required for exciting the pixel point is reduced, thereby reducing the power consumption during screen display.

[0085] In an exemplary embodiment, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure.

[0086] Fig. 5 is an equivalent circuit schematic diagram of a pixel driving circuit. As shown in Fig. 5, the pixel driving circuit in the LTPO display substrate can include 8 transistors (first transistor M1 to eighth transistor M8) and 1 capacitor C. Among them, the gate electrode of the first transistor M1 is electrically connected with the first reset signal line Reset1, the first electrode of the first transistor M1 is electrically connected with the first initial signal line INIT1, and the second electrode of the first transistor M1 is electrically connected with the third node N3 or the first node N1; the gate electrode of the second transistor M2 is electrically connected with the second scan signal line Gate2, the first electrode of the second transistor M2 is electrically connected with the first node N1, and the second electrode of the second transistor M2 is electrically connected with the third node N3; the gate electrode of the third transistor M3 is electrically connected with the first node N1, the first electrode of the third transistor M3 is electrically connected with the second node N2, and the second electrode of the third transistor M3 is electrically connected with the third node N3; the gate electrode of the fourth transistor M4 is electrically connected with the first scan signal line Gate1, the first electrode of the fourth transistor M4 is electrically connected with the data signal line Data, and the second electrode of the fourth transistor M4 is electrically connected with the second node N2; the gate electrode of the fifth transistor M5 is electrically connected with the emission signal line EM, the first electrode of the fifth transistor M5 is electrically connected with the high-level power supply line VDD, and the second electrode of the fifth transistor M5 is electrically connected with the second node N2; the gate electrode of the sixth transistor M6 is electrically connected with the emission signal line EM, the first electrode of the sixth transistor M6 is electrically connected with the third node N3, and the second electrode of the sixth transistor M6 is electrically connected with the fourth node N4; the gate electrode of the seventh transistor M7 is electrically connected with the second reset signal line Reset2, the first electrode of the seventh transistor M7 is electrically connected with the second initial signal line INIT2, and the second electrode of the seventh transistor M7 is electrically connected with the fourth node N4; the gate electrode of the eighth transistor M8 is electrically connected with the second reset signal line Reset2, the first electrode of the eighth transistor M8 is electrically connected with the third initial signal line INIT3, and the second electrode of the eighth transistor M8 is electrically connected with the second node N2; the first plate of the capacitor C is electrically connected with the first node N1, and the second plate of the capacitor C is electrically connected with the high-level power supply line VDD. Fig. 5 is described by taking the second electrode of the first transistor M1 being electrically connected with the third node N3 as an example.

[0087] In the example embodiment, the first transistor M1 is referred to as a first node reset transistor, the second transistor M2 is referred to as a compensation transistor, the third transistor M3 is referred to as a driving transistor, the fourth transistor M4 is referred to as a data writing transistor, the fifth transistor M5 and the sixth transistor M6 are referred to as emission transistors, the seventh transistor M7 is referred to as an anode reset transistor, and the eighth transistor M8 is referred to as a second node reset transistor.

[0088] In an example embodiment, the signal of the second reset signal line Reset2 can be the same as the signal of the first scan signal line Gate1, or can also be the same as the signal of the first reset signal line Reset1.

[0089] In an example embodiment, the first transistor M1 to the eighth transistor M8 can adopt a low-temperature polysilicon thin film transistor, or can adopt an oxide thin film transistor, or can adopt a low-temperature polysilicon thin film transistor and an oxide thin film transistor. The active pattern of the low-temperature polysilicon thin film transistor adopts low-temperature polysilicon (LTPS), and the active pattern of the oxide thin film transistor adopts oxide semiconductor (Oxide). The low-temperature polysilicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantage of low leakage current. Integrating the low-temperature polysilicon thin film transistor and the oxide thin film transistor on one display substrate forms an LTPO display substrate, which can take advantage of both and can achieve low-frequency driving, reduce power consumption, and improve display quality.

[0090] In an example embodiment, the second transistor M2 can be an N-type transistor, and the first transistor M1, the third transistor M3 to the eighth transistor M8 can be P-type transistors.

[0091] In an example embodiment, as shown in FIG. 5, the light emitting device L can be electrically connected with the fourth node N4 and the low-level power supply line VSS, respectively.

[0092] In an example embodiment, the light emitting device L can include a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked. For example, the anode of the light emitting device L is electrically connected with the fourth node N4, and the cathode of the light emitting device L is electrically connected with the low-level power supply line VSS.

[0093] In an example embodiment, the light emitting device L can include any one of an organic light emitting diode (OLED), a quantum dot light emitting diode, and an inorganic light emitting diode. For example, the light emitting device can adopt a micron-level light emitting device, such as a micro light emitting diode (Micro LED), a mini light emitting diode (Mini LED), or a micro organic light emitting diode (Micro OLED), etc., which is not limited in the present disclosure. For example, taking the light emitting device L as an organic electroluminescent diode (OLED) as an example, the light emitting device can include a first electrode (for example, as an anode), an organic light emitting layer, and a second electrode (for example, as a cathode) stacked.

[0094] In an exemplary embodiment, the organic light-emitting layer can include a light-emitting layer (EML) and any one or more of a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, one or more of the hole injection layer, the hole transport layer, the electron blocking layer, the hole blocking layer, the electron transport layer, and the electron injection layer of all sub-pixels can be a common layer connected together, the light-emitting layers of adjacent sub-pixels can have a small amount of overlap, or can be isolated.

[0095] In an exemplary embodiment, the high-level power line VDD continuously provides a high-level signal, and the low-level power line VSS continuously provides a low-level signal.

[0096] FIG. 6 is a timing diagram of the pixel driving circuit provided in FIG. 5. The working process of the pixel driving circuit exemplified by FIG. 5 in the display stage is described below to illustrate the exemplary embodiment of the present disclosure.

[0097] In combination with FIGS. 5 and 6, the working process of the pixel driving circuit can include:

[0098] In the first stage P1, referred to as the initialization stage, the signals of the first reset signal line Reset1 and the second reset signal line Reset2 are high-level signals, the first transistor M1 is turned on, the signal of the first initial signal line INIT1 is written to the third node N3 through the turned-on first transistor M1, the third node N3 is initialized (reset), the pre-stored voltage in the third node N3 is emptied, the initialization is completed, the seventh transistor M7 is turned on, the signal of the second initial signal line INIT2 is written to the fourth node N4 through the turned-on seventh transistor M7, the first electrode of the light-emitting device L is initialized (reset), the pre-stored voltage in the first electrode of the light-emitting device L is emptied, the initialization is completed, the eighth transistor M8 is turned on, the signal of the third initial signal line INIT3 is written to the second node N2 through the turned-on eighth transistor M8, the second node N2 is initialized (reset), the pre-stored voltage in the second node N2 is emptied, the initialization is completed.

[0099] In the second stage P2, referred to as a data writing stage or threshold compensation stage, the signal of the first scan signal line Gate1 is a low level signal, the signal of the second scan signal line Gate2 is a high level signal, and the data signal line Data outputs a data voltage. In this stage, the first node N1 is a low level signal, so the third transistor M3 is turned on. The signal of the first scan signal line Gate1 is a low level signal, the fourth transistor M4 is turned on, the signal of the second scan signal line Gate2 is a high level signal, and the second transistor M2 is turned on. The data voltage output by the data signal line Data is provided to the first node N1 through the turned-on fourth transistor M4, the second node N2, the turned-on third transistor M3, the third node N3, and the turned-on second transistor M2, and the difference between the data voltage output by the data signal line Data and the threshold voltage of the third transistor M3 is charged to the capacitor C until the voltage of the first node N1 is Vd-|Vth|, where Vd is the data voltage output by the data signal line Data, and Vth is the threshold voltage of the third transistor M3.

[0100] In the third stage P3, referred to as a light emitting stage, the signal of the light emitting signal line EM is a low level signal, the fifth transistor M5 and the sixth transistor M6 are turned on, and the power voltage output by the high level power supply line VDD is provided to the first electrode of the light emitting device L through the turned-on fifth transistor M5, the third transistor M3, and the sixth transistor M6 to drive the light emitting device L to emit light.

[0101] In the driving process of the pixel driving circuit, the driving current flowing through the third transistor M3 (the driving transistor) is determined by the voltage difference between the gate electrode and the first electrode. Since the voltage of the first node N1 is Vd-|Vth|, the driving current of the third transistor M3 is I=K*(Vgs-Vth). 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*(Vdd-Vd) 2

[0102] where I is the driving current flowing through the third transistor M3, that is, the driving current driving the light emitting device L, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor M3, Vth is the threshold voltage of the third transistor M3, Vd is the data voltage output by the data signal line Data, and Vdd is the power voltage output by the high level power supply line VDD.

[0103] In the exemplary embodiment, the gate signal lines can include the first scan signal line, the second scan signal line, the light emitting signal line, the first reset signal line, and the second reset signal line.

[0104] In an example embodiment, the gate driver includes at least one driving circuit. The number of driving circuits depends on the number of gate signal lines. Taking a display substrate including the pixel driving circuit provided in FIG. 5 as an example, the gate driving circuit can include a first scan driving circuit, a second scan driving circuit, and a light-emitting driving circuit. The first scan driving circuit is electrically connected with a first scan signal line, a first reset signal line, and a second reset signal line. The second scan driving circuit is electrically connected with a second scan signal line. The light-emitting driving circuit is electrically connected with a light-emitting signal line.

[0105] In an example embodiment, any driving circuit in the gate driver can include a plurality of cascaded shift registers. FIG. 7 is an equivalent circuit diagram of a shift register. As shown in FIG. 7, the shift register can include a cascaded output sub-circuit and a driving output sub-circuit.

[0106] In an example embodiment, the cascaded output sub-circuit can be a circuit structure of 10T3C, 10T4C, 12T3C, 12T4C, 13T3C, 13T4C, 16T3C, or 16T4C, which is not limited in the present disclosure.

[0107] In the example embodiment, as shown in FIG. 7, the cascade output sub-circuit can include: first to sixteenth transistors T1-T16, a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fifth capacitor C5. Wherein, a gate electrode of the first transistor T1 is electrically connected with a first clock signal terminal CK1, a first electrode of the first transistor T1 is electrically connected with a signal input terminal IN, and a second electrode of the first transistor T1 is electrically connected with a first node N1; a gate electrode of the second transistor T2 is electrically connected with the first node N1, a first electrode of the second transistor T2 is electrically connected with the first clock signal terminal CK1, and a second electrode of the second transistor T2 is electrically connected with a second node N2; a gate electrode of the third transistor T3 is electrically connected with the first clock signal terminal CK1, a first electrode of the third transistor T3 is electrically connected with a second power supply terminal V2, and a second electrode of the third transistor T3 is electrically connected with the second node N2; a gate electrode of the fourth transistor T4 is electrically connected with a third node N3, a first electrode of the fourth transistor T4 is electrically connected with a second clock signal terminal CK2, and a second electrode of the fourth transistor T4 is electrically connected with a fourth node N4; a gate electrode of the fifth transistor T5 is electrically connected with the second node N2, a first electrode of the fifth transistor T5 is electrically connected with a first power supply terminal V1, and a second electrode of the fifth transistor T5 is electrically connected with the fourth node N4; a gate electrode of the sixth transistor T6 is electrically connected with a fifth node N5, a first electrode of the sixth transistor T6 is electrically connected with the second clock signal terminal CK2, and a second electrode of the sixth transistor T6 is electrically connected with a sixth node N6; a gate electrode of the seventh transistor T7 is electrically connected with the second clock signal terminal CK2, a first electrode of the seventh transistor T7 is electrically connected with the sixth node N6, and a second electrode of the seventh transistor T7 is electrically connected with a seventh node N7; a gate electrode of the eighth transistor T8 is electrically connected with the first node N1, a first electrode of the eighth transistor T8 is electrically connected with the first power supply terminal V1, and a second electrode of the eighth transistor T8 is electrically connected with the seventh node N7; a gate electrode of the ninth transistor T9 is electrically connected with the seventh node N7, a first electrode of the ninth transistor T9 is electrically connected with the first power supply terminal V1, and a second electrode of the ninth transistor T9 is electrically connected with a cascade signal output terminal GP(n); a gate electrode of the tenth transistor T10 is electrically connected with an eighth node N8, a first electrode of the tenth transistor T10 is electrically connected with a third power supply terminal V3, and a second electrode of the tenth transistor T10 is electrically connected with the cascade signal output terminal GP(n); a gate electrode of the eleventh transistor T11 is electrically connected with the second power supply terminal V2, a first electrode of the eleventh transistor T11 is electrically connected with the second node N2, and a second electrode of the eleventh transistor T11 is electrically connected with the fifth node N5; a gate electrode of the twelfth transistor T12 is electrically connected with the third power supply terminal V3, a first electrode of the twelfth transistor T12 is electrically connected with the first node N1, and a second electrode of the twelfth transistor T12 is electrically connected with the eighth node N8;A thirteenth transistor T13 has a gate electrode electrically connected to the fourth power supply terminal V4, a first electrode electrically connected to the first power supply terminal V1, and a second electrode electrically connected to the first node N1; a fourteenth transistor T14 has a gate electrode electrically connected to the first clock signal terminal CK1, a first electrode electrically connected to the signal input terminal IN, and a second electrode electrically connected to a first electrode of a fifteenth transistor T15; the fifteenth transistor T15 has a gate electrode electrically connected to the second power supply terminal V2 and a second electrode electrically connected to the third node N3; a sixteenth transistor T16 has a gate electrode electrically connected to the third node N3, a first electrode electrically connected to the third node N3, and a second electrode electrically connected to the eighth node N8; the first capacitor C1 has a first end electrically connected to the fifth node N5 and a second end electrically connected to the sixth node N6; the second capacitor C2 has a first end electrically connected to the seventh node N7 and a second end electrically connected to the first power supply terminal V1; the third capacitor C3 has a first end electrically connected to the third node N3 and a second end electrically connected to the fourth node N4; the fifth capacitor C5 has a first end electrically connected to the second power supply terminal V2 and a second end electrically connected to the cascade signal output terminal GP(n). FIG. 7 illustrates the case of 16T4C.

[0108] In an example embodiment, when the cascade output sub-circuit is of a 10T3C circuit structure, the cascade output sub-circuit comprises: first to tenth transistors T1-T10 and first to third capacitors C1-C3.

[0109] In an example embodiment, when the cascade output sub-circuit is of a 10T4C circuit structure, the cascade output sub-circuit comprises: first to tenth transistors T1-T10 and first to third capacitors C1-C3 and a fifth capacitor C5.

[0110] In an example embodiment, when the cascade output sub-circuit is of a 12T3C circuit structure, the cascade output sub-circuit comprises: first to twelfth transistors T1-T12 and first to third capacitors C1-C3.

[0111] In an example embodiment, when the cascade output sub-circuit is of a 12T4C circuit structure, the cascade output sub-circuit comprises: first to twelfth transistors T1-T12 and first to third capacitors C1-C3 and a fifth capacitor C5.

[0112] In an example embodiment, when the cascade output sub-circuit is of a 13T3C circuit structure, the cascade output sub-circuit comprises: first to thirteenth transistors T1-T13 and first to third capacitors C1-C3.

[0113] In an example embodiment, when the cascaded output sub-circuit is a circuit structure of 13T4C, the cascaded output sub-circuit comprises: first to thirteenth transistors T1-T13, and first to third capacitors C1-C3 and a fifth capacitor C5.

[0114] In an example embodiment, when the cascaded output sub-circuit is a circuit structure of 16T3C, the cascaded output sub-circuit comprises: first to sixteenth transistors T1-T16, and first to third capacitors C1-C3.

[0115] In an example embodiment, as shown in FIG. 7, the driving output sub-circuit can comprise: seventeenth to twenty-fourth transistors T17-T24 and a fourth capacitor C4. Wherein, a gate electrode of the seventeenth transistor T17 is electrically connected with the eighth node N8, a first electrode of the seventeenth transistor T17 is electrically connected with the third power supply end V3, a second electrode of the seventeenth transistor T17 is electrically connected with the driving signal output end OP(n), a gate electrode of the eighteenth transistor T18 is electrically connected with the seventh node N7, a first electrode of the eighteenth transistor T18 is electrically connected with the output power supply end V, a second electrode of the eighteenth transistor T18 is electrically connected with a first electrode of the nineteenth transistor T19, a gate electrode of the nineteenth transistor T19 is electrically connected with the ninth node N9, a second electrode of the nineteenth transistor T19 is electrically connected with the driving signal output end OP(n), a gate electrode of the twentieth transistor T20 is electrically connected with the inverse signal output end Anti-GP(n-1) of the previous stage shift register, a first electrode of the twentieth transistor T20 is electrically connected with the ninth node N9, a second electrode of the twentieth transistor T20 is electrically connected with a second electrode of the twenty-first transistor T21, a gate electrode of the twenty-first transistor T21 is electrically connected with the cascaded signal output end GP(n), a second electrode of the twenty-first transistor T21 is electrically connected with the masking signal end MS, a gate electrode of the twenty-second transistor T22 is electrically connected with the cascaded signal output end GP(n), a first electrode of the twenty-second transistor T22 is electrically connected with the third power supply end V3, a second electrode of the twenty-second transistor T22 is electrically connected with the inverse signal output end Anti-GP(n), a gate electrode of the twenty-third transistor T23 is electrically connected with the cascaded signal output end GP(n), a first electrode of the twenty-third transistor T23 is electrically connected with the first power supply end V1, a second electrode of the twenty-third transistor T23 is electrically connected with the inverse signal output end Anti-GP(n), a gate electrode of the twenty-fourth transistor T24 is electrically connected with the ninth node N9, a first electrode of the twenty-fourth transistor T24 is electrically connected with the second power supply end V2, a second electrode of the twenty-fourth transistor T24 is electrically connected with the driving signal output end OP(n), a first end of the fourth capacitor C4 is electrically connected with the ninth node N9, and a second end of the fourth capacitor C4 is electrically connected with the output power supply end V.

[0116] In an exemplary embodiment, the selection output sub-circuit can include the seventeenth transistor T17, the eighteenth transistor T18, the nineteenth transistor T19, the twenty-fourth transistor T24, and the fourth capacitor C4. The twenty-second transistor T22 and the twenty-third transistor T23 can be referred to as an inverting output sub-circuit. The twentieth transistor T20 and the twenty-first transistor T21 can be referred to as a latch sub-circuit.

[0117] The shift register provided by the present disclosure can lock the control signal of the corresponding masking signal end in the selection output sub-circuit according to the requirement of the display area refresh rate, can control the signal output by the driving signal output end, and can realize different refresh rates in different areas of the display substrate, that is, high and low refresh rates can coexist in the same frame of picture. The embodiments of the present disclosure are not limited to realizing different refresh rates in fixed areas of the display substrate, but can realize dynamic refresh in any area, so that the power consumption of the display substrate can be reduced. Meanwhile, the latch sub-circuit can use the phase difference between the cascade signals output by the front and rear stages of the cascade output sub-circuit to store the control signal of the masking signal end in each stage of the shift register, so that the shift register can continuously and correctly output.

[0118] In an exemplary embodiment, any of the first capacitor C1 to the fifth capacitor C5 can be a capacitor device made by a process, for example, a capacitor device can be realized by making a special capacitor electrode, and the plurality of capacitor electrodes of the capacitor can be realized by a metal layer, a semiconductor layer (for example, doped polysilicon), or the like. Alternatively, any of the first capacitor C1 to the fifth capacitor C5 can be a parasitic capacitor between a plurality of devices, which can be realized by a transistor itself and other devices or lines. The connection mode of any of the first capacitor C1 to the fifth capacitor C5 includes but is not limited to the above-described mode, and can be other applicable connection mode, which can store the level of the corresponding node. Here, the exemplary embodiments of the present disclosure do not limit this.

[0119] In an exemplary embodiment, the transistors can be divided into N-type transistors and P-type transistors according to the characteristics of the transistors. When the transistor is a P-type transistor, the on voltage is a low voltage (for example, 0V, -5V, -10V, or other suitable voltage), and the off voltage is a high voltage (for example, 5V, 10V, or other suitable voltage). When the transistor is an N-type transistor, the on voltage is a high voltage (for example, 5V, 10V, or other suitable voltage), and the off voltage is a low voltage (for example, 0V, -5V, -10V, or other suitable voltage).

[0120] In the example embodiment, the first transistor T1 to the twentieth transistor T21 and the twenty-third transistor T23 are P-type transistors, and the twentieth transistor T22 and the twenty-fourth transistor T24 are N-type transistors.

[0121] In the example embodiment, the signal of the masking signal terminal MS can be a low-level signal or a high-level signal. When the signal of the masking signal terminal MS is a low-level signal, it can be -20V to -5V, and when the signal of the masking signal terminal MS is a high-level signal, it can be 5V to 20V.

[0122] In the example embodiment, the signal of the first power supply terminal V1 can be a high-level signal, for example, 5V to 10V, and the signal of the second power supply terminal V2 can be a low-level signal, for example, -10V to -5V.

[0123] In the example embodiment, when the transistors in the pixel driving circuit connected to the shift register are P-type transistors, the output power supply terminal V is a low-level signal, and the third power supply terminal V3 is a high-level signal. When the transistors in the pixel driving circuit connected to the shift register are N-type transistors, the output power supply terminal V is a high-level signal, and the third power supply terminal V3 is a low-level signal.

[0124] In the example embodiment, the signal of any one of the first clock signal terminal CK1 and the second clock signal terminal CK2 is a square wave signal with repeated high voltage and low voltage. For example, the signal of the first clock signal terminal CK1 and the signal of the second clock signal terminal CK2 can have the same period and can be configured as phase-shifted signals. Here, compared with the signal of the first clock signal terminal CK1, the signal of the second clock signal terminal CK2 can be phase-shifted by half a period. The high voltage period of the signal of any one of the first clock signal terminal CK1 and the second clock signal terminal CK2 in each period can be set to be longer than the low voltage period.

[0125] In the example embodiment, the fourth power supply terminal V4 is a low-level signal in the boot initialization stage to prevent the ninth transistor T9 and the tenth transistor T10 for controlling the shift register in the last stage from being simultaneously turned on due to the delay of the output signal, or a low-level signal in the abnormal shutdown stage to prevent the ninth transistor T9 and the tenth transistor T10 from being simultaneously turned on. The third power supply terminal V3 continuously provides a high-level signal in the normal display stage, that is, the thirteenth transistor T13 is turned off in the normal display stage.

[0126] In the example embodiment, the driving signal outputted by the driving signal output terminal OP(n) of the shift register is mainly used to control at least one transistor (for example, the second transistor M2 or the fourth transistor M4) in the pixel driving circuit of the display substrate. When the display substrate is in a refresh frame, the driving signal output terminal OP(n) outputs a high level signal in a period of time and outputs a low level signal in the remaining period of time in a frame time, so as to control the second transistor M2 to be turned on and realize refresh of the data voltage. When the display substrate is not in a refresh frame, the driving signal output terminal OP(n) always outputs a low level signal, so that the second transistor M2 cannot be turned on.

[0127] FIG. 8 is a schematic diagram of the cascade of the shift register. As shown in FIG. 8, the cascade signal output terminals GP of the cascade output sub-circuit connected to at least one level of the shift register are respectively electrically connected to the signal input terminals IN of the driving output sub-circuit of the current level of the shift register and the cascade output sub-circuit of the next level of the shift register. The driving signal output terminals OP of at least one level of the shift register are electrically connected to at least one row of pixel driving circuits.

[0128] As shown in FIG. 8, the signals of the masking signal terminals MS connected to at least one level of the shift register in the same driving circuit are the same, that is, the masking signal terminals connected to at least one level of the shift register in the same driving circuit are connected to the same signal line, that is, the masking signal line MSL.

[0129] FIG. 9 is a working timing diagram of part of the shift register. In the following, the working principle of the above-mentioned shift register provided by the embodiment of the present disclosure for realizing different refresh rates in different areas of the display substrate is described by taking the shift register shown in FIG. 7 as an example in combination with the signal timing diagram shown in FIG. 9. FIG. 9 is described by taking the first four levels of the shift register as an example.

[0130] The signal timing diagram shown in FIG. 9 only takes the input (IN), output (OP(1), OP(2), OP(3), OP(4)) of the first four-stage shift register and the transistor in the pixel driving circuit connected with the shift register as an example. For example, when the area corresponding to the second row of sub-pixels and the third row of sub-pixels in the display substrate is a low refresh rate area, and the first row of sub-pixels and the fourth row of sub-pixels are high refresh rate areas, when the signals at the cascade signal output end GP(1) of the first-stage shift register and the signal at the previous-stage reverse signal output end Anti-GP(0) are both low-level signals (at time t1), the twentieth transistor T20 and the twenty-first transistor T21 are both turned on, that is, the low-level signal at the masking signal end MS is locked in the fourth capacitor C4 of the selection output sub-circuit at time t1, when the first-stage cascade signal output end GP(1) outputs a high-level signal (at time t11), the eighteenth transistor T18 is turned on, and since the fourth capacitor C4 maintains the low-level signal at the masking signal end MS at time t1, the nineteenth transistor T19 is turned on, and the twenty-fourth transistor T24 is cut off, so that at time t11, the driving signal output end OP(1) of the first-stage shift register outputs a high-level signal of the output power supply end V, realizing high refresh rate of the first row of sub-pixels in the display area; the maintenance time of the driving signal output end OP(1) of the first-stage shift register outputting a high-level signal of the output power supply end V can be set according to actual needs. For example: the duration of the driving signal output end OP(1) of the first-stage shift register outputting a high-level signal can overlap with the duration of the driving signal output end OP(4) of the fourth-stage shift register outputting a high-level signal, and the pixel driving circuit corresponding to the driving signal output end OP(4) of the fourth-stage shift register can be pre-charged. Similarly, the duration of the driving signal output end OP(n) of the other-stage shift register outputting a high-level signal is similar, which will not be described here.

[0131] As shown in FIG. 9, when the signal at the cascade signal output end GP(2) of the second-stage shift register and the signal at the previous-stage reverse signal output end Anti-GP(1) are both low-level signals (at time t2), the twentieth transistor T20 and the twenty-first transistor T21 are both turned on, that is, the high-level signal at the masking signal end MS is locked in the fourth capacitor C4 of the selection output sub-circuit at time t2; when the second-stage cascade signal output end GP(2) outputs a high-level signal (at time t21), the eighteenth transistor T18 is turned on, and since the fourth capacitor C4 maintains the high-level signal at the masking signal end MS at time t2, the nineteenth transistor T19 is cut off, and the twentieth transistor T20 is turned on, so that at time t21, the driving signal output end OP(2) of the second-stage shift register outputs a low-level signal of the third power supply end V3, realizing low refresh rate of the second row of sub-pixels in the display area.

[0132] When the signals of the cascade signal output end GP(3) of the third stage shift register and the signal of the previous stage reverse signal output end Anti-GP(2) are both low level signals (at time t3), the twentieth transistor T20 and the twenty-first transistor T21 are both turned on, that is, the high level signal of the masking signal end MS is locked in the fourth capacitor C4 of the selection output sub-circuit at time t3; when the third stage cascade signal output end GP(3) outputs a high level (at time t31), the eighteenth transistor T18 is turned on, and since the fourth capacitor C4 maintains the high level signal of the masking signal end MS at time t3, the nineteenth transistor T19 is cut off, and the twentieth transistor T20 is turned on, so that the driving signal output end OP(3) of the third stage shift register outputs a low level signal of the third power supply end V3 at time t31, realizing the low refresh rate of the third row of sub-pixels in the display area.

[0133] When the signals of the cascade signal output end GP(4) of the fourth stage shift register and the signal of the previous stage reverse signal output end Anti-GP(3) are both low level signals (at time t4), the twentieth transistor T20 and the twenty-first transistor T21 are both turned on, that is, the low level signal of the masking signal end MS is locked in the fourth capacitor C4 of the selection output sub-circuit at time t4, and when the fourth stage cascade signal output end GP(4) outputs a high level (at time t31), the eighteenth transistor T18 is turned on, and since the fourth capacitor C4 maintains the low level signal of the masking signal end MS at time t4, the nineteenth transistor T19 is turned on, and the twentieth transistor T20 is cut off, so that the driving signal output end OP(4) of the fourth stage shift register outputs a high level signal of the output power supply end V1 at time t31, realizing the high refresh rate of the fourth row of sub-pixels in the display area.

[0134] The content displayed by the display substrate can include a plurality of display frames. When there are different refresh rates under the same display screen in the display panel, the center of the display panel is used as a boundary, the upper half screen uses a 120Hz refresh rate, and the lower half screen uses a 10Hz refresh rate. In part of the display frame, the masking signal end is provided with a signal that can make the driving signal output end output a driving signal, at this time, all pixel driving circuits are refreshed, and in another part of the display frame, the masking signal end jumps in part of the time, so that the driving signal output end of part of the shift register cannot output a driving signal, that is, the pixel driving circuit located in the lower half screen is not refreshed, so as to achieve the purpose of using 120Hz refresh rate in the upper half screen and using 10Hz refresh rate in the lower half screen.

[0135] Fig. 10 is a schematic diagram of the signal end of the driving signal output end of the at least partially shifted register and the masking signal end. OP(n), OP(n+1) and OP(n+2) in Fig. 10 are signals of the driving signal output end connected with the last three shifted registers of the pixel driving circuit located in the upper half screen, and OP(n+3) is a signal of the driving signal output end connected with the first shifted register of the pixel driving circuit located in the lower half screen. Since the lower half screen is of low refresh rate, in some display frames, the driving signal output end connected with the first shifted register of the pixel driving circuit located in the lower half screen does not output a valid level signal.

[0136] Fig. 10 is a schematic diagram of the signal end of the driving signal output end of the at least partially shifted register and the masking signal end. OP(n), OP(n+1) and OP(n+2) in Fig. 10 are signals of the driving signal output end connected with the last three shifted registers of the pixel driving circuit located in the upper half screen, and OP(n+3) is a signal of the driving signal output end connected with the first shifted register of the pixel driving circuit located in the lower half screen. Since the lower half screen is of low refresh rate, in some display frames, the driving signal output end connected with the first shifted register of the pixel driving circuit located in the lower half screen does not output a valid level signal.

[0137] Fig. 11 is a schematic diagram of the structure of the display substrate provided by the embodiment of the present disclosure, and Fig. 12 is a schematic diagram of the signals of the output power supply end and the masking signal end provided by the embodiment of the present disclosure. As shown in Fig. 11 and Fig. 12, the embodiment of the present disclosure provides a display substrate having a display area AA and a non-display area. The display area AA includes at least two sub-display areas 10, and the display substrate displays content including at least two display frames. The refresh rates of adjacent sub-display areas are different in at least one display frame.

[0138] The display area AA is provided with pixel driving circuits arranged in an array, and the non-display area is provided with a driving circuit. The driving circuit includes a plurality of cascaded shifted registers, at least one shifted register is electrically connected with at least one row of pixel driving circuits, and the shifted register includes a driving output sub-circuit. The driving output sub-circuit is electrically connected with an output power supply end, a masking signal end and at least one row of pixel driving circuits respectively, and is configured to provide the signal of the output power supply end to at least one row of pixel driving circuits under the control of a first masking signal of the masking signal end. The shifted register can be the shifted register as described in Fig. 7.

[0139] As shown in FIGS. 11 and 12, the display substrate further comprises a controller electrically connected with the output power terminal V and the masking signal terminal MS respectively, configured to control the signals of the output power terminal V and the masking signal terminal MS in the display frame with different refresh rates of the adjacent sub-display areas, so that the signal of the output power terminal V is the first power signal VS1 in part of the time and the second power signal VS2 in part of the time, and the signal of the masking signal terminal MS is the first masking signal MS1 in part of the time and the second masking signal MS2 in part of the time, wherein the voltage value of the first power signal VS1 is different from the voltage value of the second power signal VS2, the voltage value of the first masking signal MS1 is different from the voltage value of the second masking signal MS2, and the time period when the signal of the output power terminal V is the second power signal VS2 at least partially overlaps with the time period when the signal of the masking signal terminal MS is the second masking signal MS2.

[0140] In the example embodiment, when the signal of the masking signal terminal MS is the first masking signal MS1, the driving output sub-circuit outputs the driving signal to make the pixel driving circuit connected with the shift register refresh data to achieve high refresh rate, and when the signal of the masking signal terminal MS is the second masking signal MS2, the driving output sub-circuit cannot output the driving signal to make the pixel driving circuit connected with the shift register not refresh data to achieve low refresh rate.

[0141] The dashed line part in OP(n), OP(n+1) and OP(n+2) in FIG. 12 refers to the signal of OP(n), OP(n+1) and OP(n+2) when the signal of the output power terminal V is continuously the first power signal VS1, and the solid line part refers to the signal of OP(n), OP(n+1) and OP(n+2) when the signal of the output power terminal V is the first power signal VS1 in part of the time and the second power signal VS2 in part of the time, as shown in FIG. 12, the voltage value of the signal of OP(n), OP(n+1) and OP(n+2) remains constant when the signal of the output power terminal V is the first power signal VS1 in part of the time and the second power signal VS2 in part of the time.

[0142] In the display frame with different refresh rates of the adjacent sub-display areas, the display substrate switches the refresh rates of the adjacent sub-display areas.

[0143] The present disclosure controls the signals of the output power terminal and the masking signal terminal by the controller in the display frame in which the refresh rates of the adjacent sub-display areas are different, so that the signal of the output power terminal is the first power signal in part of the time and the second power signal in part of the time, the signal of the masking signal terminal is the first masking signal in part of the time and the second masking signal in part of the time, and the time period in which the signal of the output power terminal is the second power signal at least partially overlaps with the time period in which the signal of the masking signal terminal is the second masking signal. When the display substrate switches the refresh rate of the adjacent sub-display areas, the present disclosure adjusts the output signal of the driving output sub-circuit of the shift register by the signal of the output power terminal to compensate, so that the voltage of the output signal of the driving output sub-circuit of the shift register connected to the part of the pixel driving circuit located in the sub-display area with high refresh rate remains uniform, and the display effect of the display substrate is improved.

[0144] In an example embodiment, the pixel driving circuit comprises a driving transistor and a compensation transistor, the compensation transistor being electrically connected to the control electrode of the driving transistor; and a driving output sub-circuit of at least one stage of shift register being electrically connected to the compensation transistor of at least one row of pixel driving circuits.

[0145] In an example embodiment, the shift register further comprises a cascade output sub-circuit, the cascade output sub-circuit being electrically connected to the driving output sub-circuit and the cascade output sub-circuit of the upper stage of shift register respectively and being configured to provide signals to the driving output sub-circuit and the cascade output sub-circuit of the upper stage of shift register.

[0146] In an example embodiment, in the display frame in which the refresh rates of the adjacent sub-display areas are the same, the signal output by the cascade output sub-circuit of the same shift register is the same as the signal output by the driving output sub-circuit.

[0147] In an example embodiment, in the display frame in which the refresh rates of the adjacent sub-display areas are the same, the signal of the output power terminal is the first power signal, and the signal of the masking signal terminal is the first masking signal.

[0148] In an example embodiment, as shown in FIG. 12, the time period in which the signal of the output power terminal V is the second power signal VS2 is within the time period in which the signal of the masking signal terminal MS is the second masking signal MS2.

[0149] In an example embodiment, the compensation transistor is an N-type transistor, the first power signal VS1 and the second power signal VS2 are positive voltage signals, and the voltage value of the first power signal VS1 is greater than the voltage value of the second power signal VS2. FIG. 12 is an example in which the compensation transistor is an N-type transistor.

[0150] In an exemplary embodiment, the difference between the voltage value of the first power signal and the voltage value of the second power signal is within the range of 0.01 volt to 0.5 volt.

[0151] In an exemplary embodiment, the compensation transistor is a P-type transistor, the first power signal and the second power signal are negative voltage signals, and the absolute value of the voltage value of the first power signal is greater than the absolute value of the voltage value of the second power signal.

[0152] In an exemplary embodiment, the difference between the absolute value of the voltage value of the first power signal and the absolute value of the voltage value of the second power signal is within the range of 0.01 volt to 0.5 volt.

[0153] In an exemplary embodiment, FIG. 13 is a schematic diagram of the arrangement of a display area of a display substrate, FIG. 14 is a schematic diagram of the arrangement of a display area of a display substrate, and FIG. 15 is a schematic diagram of the arrangement of a display area of a display substrate. As shown in FIGS. 13 to 15, the display area includes M first sub-display areas 11 and N second sub-display areas 12, the M first sub-display areas 11 and the N second sub-display areas 12 are arranged alternately, in the display frame with different refresh rates of adjacent sub-display areas, the refresh rate of the first sub-display area 11 is greater than the refresh rate of the second sub-display area 12, and the absolute value of the difference between M and N is equal to 0 or 1. FIG. 13 is an example with M-N=1, FIG. 14 is an example with N-M=1, and FIG. 15 is an example with M=N. FIG. 11 is an example with M=N=1.

[0154] As shown in FIG. 11, the signal of the output power terminal V is the second power signal in N time periods, and the signal of the mask signal terminal MS is the second mask signal in N time periods.

[0155] In an exemplary embodiment, as shown in FIG. 11, the start time of the n-th time period of the second mask signal of the mask signal terminal is earlier than or equal to the start time of the output signal of the cascade output sub-circuit of the shift register connected to the first row of pixel driving circuits in the n-th second sub-display area, and later than the start time of the output signal of the cascade output sub-circuit of the shift register connected to the last row of pixel driving circuits in the n-th first sub-display area, 1≤n≤N. The start time of the n-th time period of the second mask signal of the mask signal terminal is earlier than the start time of the output signal of the cascade output sub-circuit of the shift register connected to the first row of pixel driving circuits in the n-th second sub-display area, and later than the start time of the output signal of the cascade output sub-circuit of the shift register connected to the last row of pixel driving circuits in the n-th first sub-display area, which can ensure the high refresh rate of the first sub-display area and the low refresh rate of the second sub-display area.

[0156] In an example embodiment, M-N=1, the start time of the nth time period of the signal of the output power supply end as the second power supply signal is the start time of the nth time period of the signal of the mask signal end as the second mask signal; the end time of the first time period of the signal of the output power supply end as the second power supply signal is earlier than the start time of the output signal of the cascaded output sub-circuit of the shift register connected to the pixel driving circuit of the first row in the first display sub-area, and the end time of the kth time period of the signal of the output power supply end as the second power supply signal is later than the end time of the output signal of the cascaded output sub-circuit of the shift register connected to the pixel driving circuit of the last row in the k-1th display sub-area, and earlier than the start time of the output signal of the cascaded output sub-circuit of the shift register connected to the pixel driving circuit of the first row in the kth display sub-area, 2≤k≤N. In the present disclosure, the end time of the kth time period of the signal of the output power supply end as the second power supply signal is later than the end time of the output signal of the cascaded output sub-circuit of the shift register connected to the pixel driving circuit of the last row in the k-1th display sub-area, and earlier than the start time of the output signal of the cascaded output sub-circuit of the shift register connected to the pixel driving circuit of the first row in the kth display sub-area, which can ensure the normal display of the first display sub-area when the display substrate is switched in refresh rate.

[0157] In an example embodiment, N-M=1, the start time of the nth time period of the signal of the output power supply end as the second power supply signal is the start time of the nth time period of the signal of the mask signal end as the second mask signal; the end time of the first time period of the signal of the output power supply end as the second power supply signal is earlier than the start time of the output signal of the cascaded output sub-circuit of the shift register connected to the pixel driving circuit of the first row in the first display sub-area, and the end time of the kth time period of the signal of the output power supply end as the second power supply signal is later than the end time of the output signal of the cascaded output sub-circuit of the shift register connected to the pixel driving circuit of the last row in the k-1th display sub-area, and earlier than the start time of the output signal of the cascaded output sub-circuit of the shift register connected to the pixel driving circuit of the first row in the kth display sub-area, 2≤k≤N. In the present disclosure, the end time of the kth time period of the signal of the output power supply end as the second power supply signal is later than the end time of the output signal of the cascaded output sub-circuit of the shift register connected to the pixel driving circuit of the last row in the k-1th display sub-area, and earlier than the start time of the output signal of the cascaded output sub-circuit of the shift register connected to the pixel driving circuit of the first row in the kth display sub-area, which can ensure the normal display of the first display sub-area when the display substrate is switched in refresh rate.

[0158] In an example embodiment, M=N, the start time of the n-th time period of the second power signal at the output power terminal is the start time of the n-th time period of the second mask signal at the mask signal terminal; the end time of the m-th time period of the second power signal at the output power terminal is later than the end time of the output signal of the cascade output sub-circuit of the shift register connected to the last row of pixel driving circuits in the m-th first sub-display area, and is earlier than the start time of the output signal of the cascade output sub-circuit of the shift register connected to the first row of pixel driving circuits in the i+1-th first sub-display area, the end time of the N-th time period of the second power signal at the output power terminal is earlier than the end time of the N-th time period of the second mask signal at the mask signal terminal, 1≤m≤N-1. The end time of the m-th time period of the second power signal at the output power terminal being later than the end time of the output signal of the cascade output sub-circuit of the shift register connected to the last row of pixel driving circuits in the m-th first sub-display area, and being earlier than the start time of the output signal of the cascade output sub-circuit of the shift register connected to the first row of pixel driving circuits in the i+1-th first sub-display area in the present disclosure can ensure the normal display of the first sub-display area when the display substrate is performing refresh rate switching.

[0159] In an example embodiment, the non-display area is further provided with a mask signal line, and the mask signal terminal of at least one stage of shift registers in the driving circuit is electrically connected to the mask signal line.

[0160] In an example embodiment, the display substrate further comprises an output power line, and the output power terminal of at least one stage of shift registers in the driving circuit is electrically connected to the output power line.

[0161] In an example embodiment, the controller comprises a first control chip and a second control chip.

[0162] In an example embodiment, the first control chip is electrically connected to the output power line and is configured to provide the first power signal to the output power line in part of the time and provide the second power signal to the output power line in part of the time in the display frame in which the refresh rates of adjacent sub-display areas are different, and provide the first power signal to the output power line in the display frame in which the refresh rates of adjacent sub-display areas are the same.

[0163] In an example embodiment, the second control chip is electrically connected to the mask signal line and is configured to provide the first mask signal to the mask signal line in part of the time and provide the second mask signal to the mask signal line in part of the time in the display frame in which the refresh rates of adjacent sub-display areas are different, and provide the first mask signal to the mask signal line in the display frame in which the refresh rates of adjacent sub-display areas are the same.

[0164] In an example embodiment, FIG. 16 is a structural schematic diagram of a display substrate. The non-display area is further provided with an output power line VL, a signal conversion line CL and a signal conversion sub-circuit, an output power end of at least one stage of shift register in the driving circuit is electrically connected with the output power line, and the controller includes a control chip.

[0165] In an example embodiment, the signal conversion sub-circuit is electrically connected with the masking signal line MSL, the output power line VL and the signal conversion line CL respectively, and is configured to provide the signal of the signal conversion line CL to the output power line VL under the control of the second masking signal of the masking signal line MSL. The signal of the output power line VL is the first power signal, and the signal of the signal conversion line CL is the second power signal.

[0166] In an example embodiment, the signal conversion sub-circuit provides the signal of the signal conversion line CL to the output power line VL when the display substrate is switched from a high refresh rate to a low refresh rate, that is, compensates the output signal of the driving output sub-circuit of the part of the shift register of the sub-display area of the high refresh rate.

[0167] In an example embodiment, the control chip is electrically connected with the masking signal line, and is configured to provide the first masking signal to the masking signal line in part of the time and provide the second masking signal to the masking signal line in part of the time in the display frame in which the refresh rates of the adjacent sub-display areas are different, and provide the first masking signal to the masking signal line in the display frame in which the refresh rates of the adjacent sub-display areas are the same.

[0168] In an example embodiment, FIG. 17 is an equivalent circuit diagram of the signal conversion sub-circuit. As shown in FIG. 17, the signal conversion sub-circuit includes a conversion transistor STFT. The control electrode of the conversion transistor STFT is electrically connected with the masking signal line MSL, the first electrode of the conversion transistor STFT is electrically connected with the output power line VL, and the second electrode of the conversion transistor is electrically connected with the signal conversion line CL.

[0169] The display substrate provided by the embodiments of the present disclosure is also provided with a driving method. The display substrate provided by any one of the above embodiments is driven by the driving method. The driving method of the display substrate can further include the following steps.

[0170] In the display frame in which the refresh rates of the adjacent sub-display areas are different, the signals of the output power end and the masking signal end are controlled so that the signal of the output power end is the first power signal in part of the time and is the second power signal in part of the time, and the signal of the masking signal end is the first masking signal in part of the time and is the second masking signal in part of the time.

[0171] The display device provided by the embodiments of the present disclosure includes the display substrate provided by any one of the above embodiments.

[0172] In exemplary embodiments, the display device can be any product or component having a display function, such as a wearable device, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigation device, etc.

[0173] The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can be referred to the general design.

[0174] For clarity, the thickness and size of a layer or microstructure are exaggerated in the drawings used to describe embodiments of the present disclosure. It can be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly" on or under the other element, or an intermediate element can be present.

[0175] Although the embodiments disclosed by the present disclosure are as described above, the content described is only the embodiments adopted for the purpose of facilitating the understanding of the present disclosure, and is not intended to limit the present disclosure. Any person skilled in the art of the present disclosure can make any modification and change in the form and details without departing from the spirit and scope of the present disclosure, but the patent protection scope of the present disclosure shall be subject to the scope defined by the appended claims.

Claims

1. A display substrate, wherein, The display substrate has a display area and a non-display area, the display area includes at least two sub-display areas, and the display content of the display substrate includes at least two display frames, and the refresh rates of adjacent sub-display areas are different in at least one display frame; The display area is provided with pixel driving circuits arranged in an array, and the non-display area is provided with a driving circuit, the driving circuit includes a plurality of cascaded shift registers, at least one level of shift registers is electrically connected with at least one row of pixel driving circuits, and the shift register includes a driving output sub-circuit; The driving output sub-circuit is electrically connected with an output power supply end, a masking signal end and at least one row of pixel driving circuits respectively, and is configured to provide the signal of the output power supply end to at least one row of pixel driving circuits under the control of the first masking signal of the masking signal end; The display substrate further includes a controller, the controller is electrically connected with the output power supply end and the masking signal end respectively, and is configured to control the signals of the output power supply end and the masking signal end in the display frame in which the refresh rates of adjacent sub-display areas are different, so that the signal of the output power supply end is the first power supply signal in part of time and is the second power supply signal in part of time, and the signal of the masking signal end is the first masking signal in part of time and is the second masking signal in part of time, wherein the voltage value of the first power supply signal is different from the voltage value of the second power supply signal, the voltage value of the first masking signal is different from the voltage value of the second masking signal, and the time period in which the signal of the output power supply end is the second power supply signal at least partially overlaps with the time period in which the signal of the masking signal end is the second masking signal. 2.The display substrate of claim 1, wherein, The pixel driving circuit includes a driving transistor and a compensation transistor, and the compensation transistor is electrically connected with the control electrode of the driving transistor; The driving output sub-circuit of at least one level of shift registers is electrically connected with the compensation transistor of at least one row of pixel driving circuits. 3.The display substrate of claim 2, wherein, The shift register further includes a cascaded output sub-circuit; The cascaded output sub-circuit is electrically connected with the driving output sub-circuit and at least one level of shift registers of the cascaded output sub-circuit of the upper level shift register except the current level shift register, and is configured to provide signals by the driving output sub-circuit and at least one level of shift registers of the cascaded output sub-circuit of the upper level shift register except the current level shift register; In the display frame in which the refresh rates of adjacent sub-display areas are the same, the signal output by the cascaded output sub-circuit of the same shift register is the same as the signal output by the driving output sub-circuit. 4.The display substrate of claim 3, wherein, In the display frame in which the refresh rates of adjacent sub-display areas are the same, the signal of the output power supply end is the first power supply signal, and the signal of the masking signal end is the first masking signal. 5.The display substrate of claim 3, wherein, The time period in which the signal of the output power supply end is the second power supply signal is within the time period in which the signal of the masking signal end is the second masking signal. 6.The display substrate of claim 5, wherein, The compensation transistor is an N-type transistor, the first power supply signal and the second power supply signal are positive voltage signals, and the voltage value of the first power supply signal is greater than the voltage value of the second power supply signal. 7.The display substrate of claim 6, wherein, The difference between the voltage value of the first power signal and the voltage value of the second power signal is within the range of 0.01 volt to 0.5 volt. 8.The display substrate of claim 5, wherein, The compensation transistor is a P-type transistor, the first power signal and the second power signal are negative voltage signals, and the absolute value of the voltage value of the first power signal is greater than the absolute value of the voltage value of the second power signal. 9.The display substrate of claim 8, wherein, The difference between the absolute value of the voltage value of the first power signal and the absolute value of the voltage value of the second power signal is within the range of 0.01 volt to 0.5 volt.

10. The display substrate according to any one of claims 5 to 9, wherein, The display area includes M first sub-display areas and N second sub-display areas, the M first sub-display areas and the N second sub-display areas are arranged alternately, and in the display frame with different refresh rates of adjacent sub-display areas, the refresh rate of the first sub-display area is greater than the refresh rate of the second sub-display area. The signal of the output power terminal is the second power signal in N time periods, and the signal of the masking signal terminal is the second masking signal in N time periods. The start time of the n-th time period of the second masking signal of the masking signal terminal is earlier than or equal to the start time of the output signal of the cascade output sub-circuit of the shift register connected to the first row of pixel driving circuits in the n-th second sub-display area, and later than the start time of the output signal of the cascade output sub-circuit of the shift register connected to the last row of pixel driving circuits in the n-th first sub-display area, 1≤n≤N. 11.The display substrate of claim 10, wherein, M-N=1, the start time of the n-th time period of the second power signal of the output power terminal is the start time of the n-th time period of the second masking signal of the masking signal terminal. The end time of the n-th time period of the second power signal of the output power terminal is later than the end time of the output signal of the cascade output sub-circuit of the shift register connected to the last row of pixel driving circuits in the n-th first sub-display area, and earlier than the start time of the output signal of the cascade output sub-circuit of the shift register connected to the first row of pixel driving circuits in the n+1-th first sub-display area. 12.The display substrate of claim 10, wherein, N-M=1, the start time of the n-th time period of the second power signal of the output power terminal is the start time of the n-th time period of the second masking signal of the masking signal terminal. The end time of the first time period of the second power signal of the output power terminal is earlier than the start time of the output signal of the cascade output sub-circuit of the shift register connected to the first row of pixel driving circuits in the first first sub-display area, and the end time of the k-th time period of the second power signal of the output power terminal is later than the end time of the output signal of the cascade output sub-circuit of the shift register connected to the last row of pixel driving circuits in the k-1-th first sub-display area, and earlier than the start time of the output signal of the cascade output sub-circuit of the shift register connected to the first row of pixel driving circuits in the k-th first sub-display area, 2≤k≤N. 13.The display substrate of claim 10, wherein, M=N, the start time of the n-th time period of the second power signal of the signal of the output power terminal is the start time of the n-th time period of the second mask signal of the signal of the mask signal terminal; The end time of the m-th time period of the second power signal of the signal of the output power terminal is later than the end time of the output signal of the cascade output sub-circuit of the shift register connected to the last row of pixel driving circuit in the m-th first sub-display area, and earlier than the start time of the output signal of the cascade output sub-circuit of the shift register connected to the first row of pixel driving circuit in the i+1-th first sub-display area, the end time of the N-th time period of the signal of the output power terminal is earlier than the end time of the N-th time period of the signal of the mask signal terminal, 1≤m≤N-1. 14.The display substrate of claim 10, wherein, The non-display area is further provided with a mask signal line, and the mask signal terminal of at least one stage of shift register in the driving circuit is electrically connected with the mask signal line.

15. The display substrate of claim 14, further comprising: An output power line, and the output power terminal of at least one stage of shift register in the driving circuit is electrically connected with the output power line; The controller comprises a first control chip and a second control chip. The first control chip is electrically connected with the output power line and is configured to provide the first power signal to the output power line in part of time in the display frame with different refresh rates of adjacent sub-display areas, provide the second power signal to the output power line in part of time, and provide the first power signal to the output power line in the display frame with same refresh rates of adjacent sub-display areas. The second control chip is electrically connected with the mask signal line and is configured to provide the first mask signal to the mask signal line in part of time in the display frame with different refresh rates of adjacent sub-display areas, provide the second mask signal to the mask signal line in part of time, and provide the first mask signal to the mask signal line in the display frame with same refresh rates of adjacent sub-display areas. 16.The display substrate of claim 14, wherein, The non-display area is further provided with an output power line, a signal conversion line and a signal conversion sub-circuit, the output power terminal of at least one stage of shift register in the driving circuit is electrically connected with the output power line, and the controller comprises a control chip. The signal conversion sub-circuit is electrically connected with the mask signal line, the output power line and the signal conversion line respectively and is configured to provide the signal of the signal conversion line to the output power line under the control of the second mask signal of the mask signal line, the signal of the output power line is the first power signal, and the signal of the signal conversion line is the second power signal. The control chip is electrically connected with the mask signal line and is configured to provide the first mask signal to the mask signal line in part of time in the display frame with different refresh rates of adjacent sub-display areas, provide the second mask signal to the mask signal line in part of time, and provide the first mask signal to the mask signal line in the display frame with same refresh rates of adjacent sub-display areas. 17.The display substrate of claim 16, wherein, The signal conversion sub-circuit comprises a conversion transistor. The control electrode of the conversion transistor is electrically connected with the mask signal line, the first electrode of the conversion transistor is electrically connected with the output power line, and the second electrode of the conversion transistor is electrically connected with the signal conversion line. 18.The display substrate of claim 3, wherein, The cascade output sub-circuit comprises a first transistor to a sixteenth transistor, a first capacitor, a second capacitor, a third capacitor and a fifth capacitor, and the driving output sub-circuit comprises a seventeenth transistor to a twenty-fourth transistor and a fourth capacitor. The gate electrode of the first transistor is electrically connected with the first clock signal end, the first electrode of the first transistor is electrically connected with the signal input end, and the second electrode of the first transistor is electrically connected with the first node; the gate electrode of the second transistor is electrically connected with the first node, the first electrode of the second transistor is electrically connected with the first clock signal end, and the second electrode of the second transistor is electrically connected with the second node; the gate electrode of the third transistor is electrically connected with the first clock signal end, the first electrode of the third transistor is electrically connected with the second power supply end, and the second electrode of the third transistor is electrically connected with the second node; the gate electrode of the fourth transistor is electrically connected with the third node, the first electrode of the fourth transistor is electrically connected with the second clock signal end, and the second electrode of the fourth transistor is electrically connected with the fourth node; the gate electrode of the fifth transistor is electrically connected with the second node, the first electrode of the fifth transistor is electrically connected with the first power supply end, and the second electrode of the fifth transistor is electrically connected with the fourth node; the gate electrode of the sixth transistor is electrically connected with the fifth node, the first electrode of the sixth transistor is electrically connected with the second clock signal end, and the second electrode of the sixth transistor is electrically connected with the sixth node; the gate electrode of the seventh transistor is electrically connected with the second clock signal end, the first electrode of the seventh transistor is electrically connected with the sixth node, and the second electrode of the seventh transistor is electrically connected with the seventh node; the gate electrode of the eighth transistor is electrically connected with the first node, the first electrode of the eighth transistor is electrically connected with the first power supply end, and the second electrode of the eighth transistor is electrically connected with the seventh node; the gate electrode of the ninth transistor is electrically connected with the seventh node, the first electrode of the ninth transistor is electrically connected with the first power supply end, and the second electrode of the ninth transistor is electrically connected with the cascade signal output end; the gate electrode of the tenth transistor is electrically connected with the eighth node, the first electrode of the tenth transistor is electrically connected with the third power supply end, and the second electrode of the tenth transistor is electrically connected with the cascade signal output end; the gate electrode of the eleventh transistor is electrically connected with the second power supply end, the first electrode of the eleventh transistor is electrically connected with the second node, and the second electrode of the eleventh transistor is electrically connected with the fifth node; the gate electrode of the twelfth transistor is electrically connected with the third power supply end, the first electrode of the twelfth transistor is electrically connected with the first node, and the second electrode of the twelfth transistor is electrically connected with the eighth node; the gate electrode of the thirteenth transistor is electrically connected with the fourth power supply end, the first electrode of the thirteenth transistor is electrically connected with the first power supply end, and the second electrode of the thirteenth transistor is electrically connected with the first node; the gate electrode of the fourteenth transistor is electrically connected with the first clock signal end, the first electrode of the fourteenth transistor is electrically connected with the signal input end, and the second electrode of the fourteenth transistor is electrically connected with the first electrode of the fifteenth transistor; the gate electrode of the fifteenth transistor is electrically connected with the second power supply end, the second electrode of the fifteenth transistor is electrically connected with the third node; the gate electrode of the sixteenth transistor is electrically connected with the third node, the first electrode of the sixteenth transistor is electrically connected with the third node, and the second electrode of the sixteenth transistor is electrically connected with the eighth node.The gate electrode of the seventeenth transistor is electrically connected with the eighth node, the first electrode of the seventeenth transistor is electrically connected with the third power supply end, the second electrode of the seventeenth transistor is electrically connected with the driving signal output end, the gate electrode of the eighteenth transistor is electrically connected with the seventh node, the first electrode of the eighteenth transistor is electrically connected with the output power supply end, the second electrode of the eighteenth transistor is electrically connected with the first electrode of the nineteenth transistor, the gate electrode of the nineteenth transistor is electrically connected with the ninth node, the second electrode of the nineteenth transistor is electrically connected with the driving signal output end, the gate electrode of the twentieth transistor is electrically connected with the inverse signal output end of the previous stage shift register, the first electrode of the twentieth transistor is electrically connected with the ninth node, the second electrode of the twentieth transistor is electrically connected with the second electrode of the twenty-first transistor, the gate electrode of the twenty-first transistor is electrically connected with the cascade signal output end, the second electrode of the twenty-first transistor is electrically connected with the masking signal end, the gate electrode of the twenty-second transistor is electrically connected with the cascade signal output end, the first electrode of the twenty-second transistor is electrically connected with the third power supply end, the second electrode of the twenty-second transistor is electrically connected with the inverse signal output end, the gate electrode of the twenty-third transistor is electrically connected with the cascade signal output end, the first electrode of the twenty-third transistor is electrically connected with the first power supply end, the second electrode of the twenty-third transistor is electrically connected with the inverse signal output end, the gate electrode of the twenty-fourth transistor is electrically connected with the ninth node, the first electrode of the twenty-fourth transistor is electrically connected with the second power supply end, the second electrode of the twenty-fourth transistor is electrically connected with the driving signal output end, the first plate of the first capacitor is electrically connected with the fifth node, the second plate of the first capacitor is electrically connected with the sixth node, the first plate of the second capacitor is electrically connected with the seventh node, the second plate of the second capacitor is electrically connected with the first power supply end, the first plate of the third capacitor is electrically connected with the third node, the second plate of the third capacitor is electrically connected with the fourth node, the first plate of the fourth capacitor is electrically connected with the ninth node, the second plate of the fourth capacitor is electrically connected with the output power supply end, the first plate of the fifth capacitor is electrically connected with the second power supply end, and the second plate of the fifth capacitor is electrically connected with the cascade signal output end.

19. A display device comprising: The display substrate of any one of claims 1 to 18.

20. A driving method of a display substrate configured to drive the display substrate of any one of claims 1 to 18, the method further comprising: in a display frame in which the refresh rates of the adjacent sub-display areas are different, controlling signals of the output power supply end and the masking signal end such that the signal of the output power supply end is the first power supply signal in part of time and the second power supply signal in part of time, and the signal of the masking signal end is the first masking signal in part of time and the second masking signal in part of time.

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