Memory configuration method and multi-head single-logic device (MH-SLD)

Abstract

The present application provides a memory configuration method and a multi-head single-logic device (MH-SLD). The method is applied to an MH-SLD, and comprises: receiving a memory configuration request, wherein the memory configuration request comprises memory configuration information corresponding to at least two heads, and the memory configuration information corresponding to the at least two heads indicates that the at least two heads correspond to a same address range of a CXL expanded memory; parsing the memory configuration request to obtain memory mapping ranges corresponding to the at least two heads; and on the basis of the memory mapping ranges corresponding to the at least two heads, configuring memory mapping ranges corresponding to the at least two heads. The method enables configuration of memory mapping ranges for at least two heads, and the memory mapping ranges for the at least two heads have an overlapping region, so that the same CXL expanded memory segment can be accessed via the at least two heads, thereby enabling host nodes connected to the at least two heads to access the same CXL memory segment.

Description

Memory configuration method and multi-interface single-logic MH-SLD device

[0001] The present disclosure claims priority to the Chinese patent publication with the application number 202410487740.6 and the title "Memory configuration method and multi-interface single-logic MH-SLD device" filed on April 19, 2024 with the China National Intellectual Property Office, the entire content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of computers, and in particular to a memory configuration method and a multi-interface single-logic MH-SLD device. BACKGROUND

[0003] Compute Express Link (CXL) is an interconnection technology designed for memory expansion, heterogeneous computing, and computer resource decomposition. As an open interconnection protocol, CXL enables high-speed and efficient interconnection between CPUs (Central Processing Units) and GPUs (Graphics Processing Units), FPGAs (Field Programmable Gate Arrays), or other accelerators, thereby meeting the requirements of high-performance heterogeneous computing. CXL memory expansion devices can provide memory expansion, pooling, and large-scale data access performance in cloud scenarios, AI (Artificial Intelligence), and other fields.

[0004] Common CXL memory expansion devices include two categories: single-logic devices, which are CXL memory expansion devices with only one logic device; and multi-logic devices, which are CXL memory expansion devices with multiple logic devices. In current technology, in order to reduce the manufacturing cost and logical complexity of the entire system, multi-head single-logic devices are generally used to implement memory expansion. Multi-head single-logic devices are single-logic devices with multiple interfaces that can connect to multiple host nodes. Simply put, multiple single-logic devices are integrated into a multi-head single-logic device.

[0005] However, the multiple host nodes connected by the multi-head single-logic device can only access independent CXL memory segments and cannot access the same CXL memory segment. SUMMARY

[0006] The memory configuration method and the multi-interface single-logic MH-SLD device provided by the embodiments of the present application can enable access to the same CXL expansion memory segment through at least two interfaces of the multi-head single-logic device, i.e., the host nodes connected to the at least two interfaces can access the same CXL memory segment.

[0007] To achieve the above object, the embodiments of the present application adopt the following technical solutions:

[0008] In a first aspect, the embodiments of the present application provide a memory configuration method applied to a multi-interface single-logic MH-SLD device, including: receiving a memory configuration request, wherein the memory configuration request includes memory configuration information corresponding to at least two interfaces, and the memory configuration information corresponding to the at least two interfaces represents that the at least two interfaces correspond to the same address range of CXL extended memory; parsing the memory configuration request to obtain the memory mapping range corresponding to the at least two interfaces; and configuring the memory mapping range corresponding to the at least two interfaces based on the memory mapping range corresponding to the at least two interfaces. The embodiments of the present application realize the configuration of the memory mapping range of the at least two interfaces of the MH-SLD device, and the memory mapping range of the at least two interfaces has an overlapping area, that is, the same memory segment of the CXL extended memory can be accessed through the at least two interfaces, realizing that the host nodes connected with the at least two interfaces can access the same CXL memory segment. Further, the host nodes connected with the at least two interfaces can realize data transmission through the shared same CXL memory segment, without realizing cross-host node data transmission through the network, so that faster data transmission speed and lower data transmission delay can be realized.

[0009] In a possible implementation, based on the memory mapping range corresponding to the at least two interfaces, the memory mapping range corresponding to the at least two interfaces is configured through a memory mapping module running on a CXL controller of the MH-SLD device; and the memory mapping module corresponds to all CXL extended memory of the MH-SLD device. Since the CXL controller runs a memory mapping module corresponding to all CXL extended memory, any memory mapping range of the CXL extended memory can be configured to any interface of the MH-SLD device at will, so as to realize the configuration of the memory mapping range corresponding to the at least two interfaces, and the memory mapping range of the at least two interfaces has an overlapping area.

[0010] In a possible implementation, before the memory mapping range corresponding to the at least two interfaces is configured, the CXL extended memory of the MH-SLD device is divided based on the memory mapping range corresponding to the at least two interfaces. Thus, the memory configuration of the at least two interfaces is met.

[0011] In a possible implementation, after the memory mapping range corresponding to the at least two interfaces is configured, configuration completion information is returned to a management component to inform the management component that the memory mapping range configuration of the at least two interfaces in the MH-SLD device is completed.

[0012] In a possible implementation, after the memory mapping ranges corresponding to the at least two interfaces are configured, the correspondence between the at least two interfaces and the memory mapping ranges is stored. This is convenient for subsequent transmission of the correspondence between the at least two interfaces and the memory mapping ranges to a host node to which the at least two interfaces are connected, and helps to realize enumeration of the MH-SLD device by the host node.

[0013] In a possible implementation, in response to a start-up operation of the first server, the MH-SLD device reads the stored correspondence between the at least two interfaces and the memory mapping ranges, the first server is a server connected with any one of the at least two interfaces, and device information is reported to the first server, so that the first server realizes enumeration of the MH-SLD device in the start-up process. After the first server is started, the CXL memory segment corresponding to the memory mapping range corresponding to the connected interface can be normally used.

[0014] In a possible implementation, the start-up operation of the first server includes that the first server performs the start-up operation in response to a trigger operation of starting up the first server by a user, or that a restart request is returned to the first server when the configuration of the memory mapping ranges corresponding to the at least two interfaces is completed, and the first server performs the start-up operation in response to the restart request. It can be known that, in the embodiment of the application, the memory mapping ranges of the at least two interfaces can be configured in the initialization stage of the MH-SLD device, and the memory mapping ranges of the at least two interfaces can also be reconfigured in the process of using the MH-SLD device.

[0015] In a possible implementation, the memory configuration request is sent by the management component to the MH-SLD in response to a trigger operation of configuring the at least two interfaces by a user. This makes the memory mapping ranges of the at least two interfaces of the MH-SLD device meet the demand of the user on the memory mapping ranges of the at least two interfaces.

[0016] In a possible implementation, the memory mapping range is represented in the form of a start address and a memory capacity.

[0017] In a second aspect, the embodiments of the present application provide a multi-interface single-logic MH-SLD device, comprising at least two interfaces, a compute express link (CXL) controller connected with the at least two interfaces, and a memory connected with the CXL controller; the at least two interfaces are configured to connect host nodes; the memory comprises CXL extended memory; the CXL controller is configured to receive and analyze a memory configuration request, and configure memory mapping ranges corresponding to the at least two interfaces based on the memory mapping ranges corresponding to the at least two interfaces obtained by the analysis; wherein the memory configuration request comprises memory configuration information corresponding to the at least two interfaces, and the memory configuration information corresponding to the at least two interfaces represents address ranges of the same CXL extended memory corresponding to the at least two interfaces. The memory mapping ranges of the at least two interfaces of the MH-SLD device are configured, and the memory mapping ranges of the at least two interfaces have an overlapping area, that is, the same memory segment of the CXL extended memory can be accessed through the at least two interfaces, and the host nodes connected with the at least two interfaces can access the same CXL memory segment.

[0018] In a possible implementation, the CXL controller comprises a flash memory; the flash memory is configured to store a correspondence between the at least two interfaces and the memory mapping ranges. When a server connected with the at least two interfaces of the MH-SLD device is started, the MH-SLD device reads the correspondence between the at least two interfaces and the memory mapping ranges stored in the flash memory, and reports the correspondence between the at least two interfaces and the memory mapping ranges to the server through device information reporting, so as to realize enumeration of the MH-SLD device by the server based on the device information. BRIEF DESCRIPTION OF DRAWINGS

[0019] FIG. 1 is a structural schematic diagram of a MH-SLD device provided by the prior art;

[0020] FIG. 2 is a schematic diagram of memory space allocation of a MH-SLD device provided by the prior art;

[0021] FIG. 3 is a schematic diagram of internal logic components of a MH-SLD device provided by the embodiments of the present application;

[0022] FIG. 4 is a flow schematic diagram of a memory configuration method provided by the embodiments of the present application;

[0023] FIG. 5 is a structural schematic diagram of a MH-SLD device after memory configuration provided by the embodiments of the present application;

[0024] FIG. 6 is an application flow schematic diagram of a MH-SLD device after memory configuration provided by the embodiments of the present application;

[0025] FIG. 7 is a structural schematic diagram of a memory configuration device provided by the embodiments of the present application. DETAILED DESCRIPTION

[0026] The terms “first”, “second”, and “third” and the like in the specification and claims of this application and the summary of the application, are used for distinguishing between similar elements and not necessarily for describing a specific sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances and embodiments.

[0027] In the embodiments of this application, the words “specifically”, “illustrative” or “for example” are used to mean serving as an example, instance, or illustration, and not to imply any preference or superiority. In the embodiments of this application, any embodiment or design scheme described as “specifically”, “for example” or the like should not be interpreted as being more preferred or superior than other embodiments or design schemes. Rather, the use of “specifically”, “for example” or the like is intended to present relevant concepts in a specific manner.

[0028] For the sake of clear and concise description of each of the following embodiments, first give a brief introduction of the related art:

[0029] CXL switch (CXL Switch) is a special switch for high-performance computing and data center, which supports CXL bus protocol. CXL switch can connect processors, accelerators, storage devices, etc. to realize high-performance and low-latency data transmission.

[0030] CXL memory expansion device is a device that can communicate with a server through a CXL interface and is used to expand the memory capacity of the server. CXL memory expansion device can provide additional memory capacity to meet the demand for large data sets and high-performance computing. Through the CXL interface, the server can directly access the memory in the expansion device to achieve high-speed data transmission and low-latency access. The current common CXL memory expansion device is divided into two categories, which are single-logic device and multi-logic device.

[0031] Single-logic device (SLD) refers to a CXL memory expansion device with only one logical device in CXL technology. For SLD, one SLD can only be connected with one server, that is, one SLD can only be used for one server.

[0032] Multi-head single-logic device (MH-SLD) is a special type of single-logic device. It refers to a single-logic device with multiple interfaces, which can be physically connected with multiple host nodes (such as servers, CXL switches, etc.) at the same time. In a physical device, each interface (head) corresponds to a logical unit respectively, and the logical device includes multiple logical units.

[0033] Multiple Logical Devices (MLD) is a CXL memory expansion device including multiple logical devices in CXL technology, each of which can independently perform specific tasks or functions, and multiple logical devices can work in parallel. The multiple logical devices have multiple interfaces and can be connected to multiple host nodes at the same time.

[0034] Next, the advantages of the memory configuration method of the present application embodiment will be introduced in combination with the memory configuration method of the MH-SLD device in the current technology.

[0035] First, in combination with FIG. 1, the basic structure of the common MH-SLD device 100 in the current technology will be introduced.

[0036] As shown in FIG. 1, the MH-SLD device includes a CXL controller 110, a first interface 120, a second interface 130, and a CXL expansion memory 140. It should be noted that FIG. 1 only takes the MH-SLD device with two ports as an example for illustration.

[0037] The first interface 120 and the second interface 130 are interfaces for connecting with host nodes (for example, servers or computers), that is, the MH-SLD device 100 can be connected to two host nodes at the same time. In some embodiments, the first interface 120 and the second interface 130 can also be connected to two host nodes through a CXL switch. The host nodes are connected to the CXL controller 110 of the MH-SLD device 100 through the first interface 120 and the second interface 130, respectively. In the present application embodiment, the first interface 120 and the second interface 130 are both CXL interfaces supporting CXL.shared mode, which is a memory resource sharing mode. In this mode, the CXL expansion memory 140 of the MH-SLD device 100 can be directly accessed by the processors of the host nodes connected to the first interface 120 and the second interface 130, thereby improving the data transmission efficiency.

[0038] The CXL controller 110 refers to a controller chip implementing the CXL (Compute Express Link) interface specification. The main function of the CXL controller is to implement the physical layer and logical layer characteristics of the CXL interface standard, including signal electricity, transmission protocol, address mapping, error handling, etc. In the embodiments of the present application, the CXL controller 110 can also implement the function of address translation, that is, translating / mapping the physical address (Physical Host Address, PHA) of the host node into the memory address (Device Physical Address, DPA) of the MH-SLD device 100. Specifically, the CXL controller 110 receives the request sent by the host node carrying the physical address of the host node, for example, the read request sent by the server carrying the physical address of the host node, and then translates the physical address of the host node into the memory address of the MH-SLD device 100, so as to realize that the host node can access the memory resources of the CXL extended memory 140 in the MH-SLD device 100.

[0039] The physical address (Physical Host Address, PHA) of the host node refers to the address in the physical memory address space directly used by the host node. That is, the physical address of the host node is the physical memory address for the operating system of the host node.

[0040] The memory address (Device Physical Address, DPA) inside the device refers to the memory physical address inside the CXL memory expansion device (MH-SLD device 100) connected with the host node.

[0041] In a possible implementation, the CXL controller 110 implements the translation / mapping of PHA into DPA through the HDM Decoder on the CXL controller 110. The HMD Decoder can be translated into the decoder of the host-managed device memory (Host-Managed Device Memory, HDM) in the CXL protocol, which refers to the address decoding data decoding hardware related to the HDM in the CXL protocol.

[0042] Specifically, the first interface 120 and the second interface 130 in the MH-SLD device 100 correspond to separate HMD Decoders, that is, the first interface 120 and the second interface 130 are connected with the corresponding HMD Decoders on the CXL controller 110, so that the host nodes connected with the first interface 120 and the second node 130 can directly access the memory segments of the independent CXL extended memory 140.

[0043] The CXL extended memory 140 refers to the memory inside the MH-SLD device 100, which can be a memory module (Dual Inline Memory Modules, DIMMS) or a DRAM. Specifically, the CXL extended memory is the memory connected with the CXL controller 110, which can be a memory bank or a DRAM, providing additional memory capacity for the host node connected with the MH-SLD device 100, thereby meeting the demand for large data sets and high-performance computing.

[0044] As shown in FIG. 1, the CXL extended memory 140 includes a CXL memory segment 141 and a CXL memory segment 142. The CXL memory segment 141 is connected with the first interface 120 through the CXL controller 110, so that the host node connected with the first interface 120 can directly access / manage the CXL memory segment 141. The CXL memory segment 142 is connected with the second interface 130 through the CXL controller 110, so that the host node connected with the second interface 130 can directly access / manage the CXL memory segment 142.

[0045] As shown in FIG. 1, the MH-SLD device 100 can be simply understood as integrating two SLD devices, so that the host node connected with the first interface 120 can only access the corresponding CXL memory segment 141, and the host node connected with the first interface 120 cannot access the CXL memory segment 142. The host node connected with the second interface 130 can only access the corresponding CXL memory segment 142, and the host node connected with the second interface 130 cannot access the CXL memory segment 141. That is, the multiple host nodes connected with the MH-SLD device can only access the independent CXL memory segment, and cannot access the same CXL memory segment between the multiple host nodes.

[0046] The above briefly explains the technical problems existing in the current technology in combination with the basic structure of the MH-SLD device 100 shown in FIG. 1. Next, in combination with the memory allocation diagram of the MH-SLD device in the current technology shown in FIG. 2, the allocation of the memory space of the MH-SLD device in the current technology is exemplarily explained.

[0047] As shown in FIG. 2, the MH-SLD device includes N interfaces, which are interface 1, interface 2, interface 3 to interface N. Among them, N is an integer greater than 1, and each interface is connected with a CXL controller. The CXL controller runs a memory mapping module corresponding to each interface, which can be represented by memory mapping module 1, memory mapping module 2, memory mapping module 3 to memory mapping module N. The CXL controller realizes the translation / mapping of the PHA carried by the request received by the corresponding interface into the DPA of the corresponding MH-SLD device based on the memory mapping table corresponding to the memory mapping module corresponding to each interface, so that the host node connected with the interface can access the corresponding CXL memory segment in the CXL extended memory. That is, each interface of the MH-SLD device corresponds to an independent CXL memory segment, which can be represented by D1, D2, D3 to DN, that is, the host connected with the interface can access the CXL memory segment corresponding to the interface.

[0048] Among them, the memory mapping module is a module for realizing the memory mapping function. Specifically, the memory mapping module can realize the control and management of the memory mapping operation, and provides address translation / mapping service.

[0049] Memory mapping refers to mapping the CXL extended memory in the MH-SLD device (memory expansion device) to the memory address space in the host node, so that the host node can directly access and manage the CXL extended memory in the MH-SLD device through the mapped memory address space. For example, through memory mapping, the memory mapping table between the physical address of the host node connected with the interface of the MH-SLD device and the CXL extended memory address can be obtained, so that the CXL controller can realize address translation based on the memory mapping table, so that the interface connected with the interface of the MH-SLD device can directly access and manage the CXL extended memory in the MH-SLD device.

[0050] According to the description of the memory mapping module and the memory mapping, the memory mapping refers to mapping the CXL extended memory address in the MH-SLD device to the physical address of the connected host node. In the embodiment of the present application, the memory mapping can be simply understood as being used to obtain the mapping relationship between the interface of the MH-SLD device and the corresponding CXL memory segment. Correspondingly, the memory mapping module is used to manage the mapping relationship between the interface and the corresponding CXL memory segment, that is, the memory mapping module is used to manage the management between the interface and the corresponding memory mapping range. The memory mapping range is used to define the memory address range of the CXL extended memory that can be accessed by each interface.

[0051] As shown in FIG. 2, each interface corresponds to a separate memory mapping module, and each memory mapping module corresponds to an independent CXL memory segment, so each memory mapping module can only map the corresponding independent CXL memory segment in the MH-SLD device to the memory address space in the host node connected by the corresponding interface, that is, each memory mapping module can only configure the memory mapping range of the independent CXL memory segment in the MH-SLD device to the corresponding interface, thereby establishing a mapping relationship between the interface and the memory mapping range.

[0052] For example, interface 1 corresponds to memory mapping module 1, and memory mapping module 1 only corresponds to CXL memory segment D1, so memory mapping module 1 can only configure the memory mapping range of CXL memory segment D1 to interface 1, and interface 1 does not correspond to the remaining memory mapping modules, so the memory mapping ranges of the remaining CXL memory segments managed by the remaining memory mapping modules cannot be configured to interface 1.

[0053] Therefore, in the current technology, each interface (Host Attached Endpoint Device, head) of the MH-SLD device is isolated from each other, and each interface can access an independent CXL memory segment, and multiple interfaces cannot access the same CXL memory segment, so the host node connected by each interface can only access the independent CXL memory segment corresponding to the interface, and multiple host nodes cannot access the same CXL memory segment, that is, multiple host nodes cannot share the same CXL memory segment.

[0054] Further, since multiple host nodes connected to the MH-SLD device cannot share the same CXL memory segment, data transmission between the multiple host nodes needs to be implemented through a network (for example, a traditional network and an IB network), and data transmission between multiple host nodes depends on network performance, and cross-host node data transmission needs to be implemented through a network, which is slow and consumes a lot of transmission resources.

[0055] The memory configuration method provided in the embodiment of the application is applied to an MH-SLD device, and includes the following steps: receiving a memory configuration request, wherein the memory configuration request carries memory configuration information corresponding to at least two interfaces, and the memory configuration information corresponding to the at least two interfaces includes memory configuration information corresponding to at least two interfaces, which indicates that the at least two interfaces correspond to the same address range of CXL extended memory; obtaining memory mapping ranges corresponding to the at least two interfaces by analyzing the received memory configuration request, and configuring the memory mapping ranges of the at least two interfaces based on the memory mapping ranges of the at least two interfaces. According to the embodiment of the application, the global memory mapping module of the MH-SLD device can configure the memory mapping ranges of the at least two interfaces of the MH-SLD device based on the demand of a user for memory allocation, and the memory mapping ranges of the at least two interfaces have an overlapping area, that is, the same memory segment of CXL extended memory can be accessed through the at least two interfaces, so that the host nodes connected with the at least two interfaces can access the same CXL memory segment.

[0056] Further, the host nodes connected with the at least two interfaces can realize data transmission through the same shared CXL memory segment, without realizing cross-host-node data transmission through a network, so that faster data transmission speed and lower data transmission delay can be realized.

[0057] Embodiment one:

[0058] The memory configuration method provided in the embodiment of the application will be described in detail below with reference to FIGS. 3-6.

[0059] Before introducing the memory configuration method provided in the embodiment of the application, the internal logic components of the MH-SLD device involved in the embodiment of the application will be briefly introduced below with reference to FIG. 3.

[0060] As shown in FIG. 3, the MH-SLD device includes N interfaces, a CXL controller, and CXL extended memory, the N interfaces are represented by interface 1, interface 2, interface 3 to interface N respectively, where N is an integer greater than 1. The connection relationship among them is as follows: the N interfaces are connected to the CXL controller, the CXL controller is connected with the CXL extended memory, so that the N interfaces can access the CXL extended memory. In the embodiment of the present application, the CXL controller runs a memory mapping module 300, each interface of the MH-SLD device corresponds to the memory mapping module 300, that is, interface 1, interface 2, interface 3 to interface N all correspond to the memory mapping module 300, and the memory mapping module 300 also corresponds to all CXL extended memory of the MH-SLD device. Further, the CXL extended memory includes CXL memory segment 1, CXL memory segment 2, CXL memory segment 3 to CXL memory segment N, represented by Z1, Z2, Z3 to ZN, that is, the memory mapping module 300 corresponds to Z1, Z2, Z3-ZN.

[0061] Since the memory mapping module 300 corresponds to all CXL extended memory, that is, the memory mapping module corresponds to Z1, Z2, Z3-ZN; and interface 1, interface 2, interface 3-interface N correspond to the memory mapping module 300, that is, the memory mapping module 300 is a global memory mapping module, so through the memory mapping module 300, any memory address (DPA) in all CXL extended memory in the MH-SLD device can be mapped to the physical address (PHA) of the host node connected to any one or more interfaces in all interfaces, that is, through the memory mapping module 300, any memory mapping range in the CXL extended memory can be configured to one or more interfaces in all interfaces. Further, through the memory mapping module 300, the same memory mapping range can be assigned to different interfaces, so that the host nodes connected by the different interfaces can access and manage the same memory segment on the CXL extended memory.

[0062] For example, the memory mapping module 300 corresponds to all CXL extended memories, and the memory mapping module 300 corresponds to all interfaces of the MH-SLD device, so the memory mapping module 300 can configure the memory mapping range of the CXL memory segment Z1 and Z2 to the interface 1, and at the same time, the memory mapping module 300 can also configure the memory mapping range of the CXL memory segment Z1 and Z2 to the interface 2, so that the host node connected to the interface 1 and the host node connected to the interface 2 can share the CXL memory segment Z1 and the CXL memory segment Z2. Further, the memory mapping module 300 can also configure the memory mapping range of the CXL memory segment Z3 to the interface 3 alone, so that the host node connected to the interface 3 can access the CXL memory segment Z3 alone. The plurality of host nodes connected to the MH-SLD device in the embodiment of the application can not only access independent CXL memory segments alone, but also access the same CXL memory segment between the plurality of host nodes.

[0063] The above briefly describes the MH-SLD device and the basic reason for enabling multiple host nodes to access the same CXL memory segment in the embodiment of the application in combination with FIG. 3. Next, a memory configuration method provided by the embodiment of the application, that is, how to configure the memory mapping range of the plurality of interfaces of the MH-SLD device, will be introduced in detail in combination with FIG. 4.

[0064] As shown in FIG. 4, the memory configuration method provided by the embodiment of the application includes the following steps:

[0065] S401, the management component 410 sends a memory configuration request to the MH-SLD device 420.

[0066] Specifically, the management component 410 sends a memory configuration request to the configuration interface of the MH-SLD device 420. The configuration interface can be an interface independent of the interface connected to the host node in the MH-SLD device 420, can be an interface dedicated to receiving a memory configuration request, for example, an I2C interface. Of course, in other embodiments, the configuration interface can be the interface connected to the host node in the MH-SLD device 420.

[0067] The management component 410 is a component for configuring the memory mapping range of the interface of the MH-SLD device. For example, the management component 410 can be a server, a fabric manager (FM), a device with an I2C interface, etc.

[0068] The fabric manager (FM) is a component responsible for managing and controlling the structure and topology inside the device. It provides functions such as topology discovery, configuration management, routing control, etc., to ensure the effectiveness and reliability of communication and data transmission between devices.

[0069] For the memory configuration request sent by the management component 410 to the MH-SLD device 420:

[0070] In a possible implementation, the memory configuration request carries memory configuration information corresponding to at least two interfaces, and the memory configuration information corresponding to the at least two interfaces indicates that the at least two interfaces correspond to the same address range of the CXL extended memory. Specifically, the memory configuration information includes an interface identifier and a memory mapping range corresponding to the interface. The interface identifier can be an interface number, an interface ID, or any unique identifier that can represent the interface. The memory mapping range can be represented by a starting address (address) and a memory capacity (size) of the CXL extended memory.

[0071] For example, the memory configuration request carries memory configuration information corresponding to interface 1 and interface 2. The interface identifier in the memory configuration information corresponding to interface 1 is interface 1, and the memory mapping range is memory mapping range Q1. The interface identifier in the memory configuration information corresponding to interface 2 is interface 2, and the memory mapping range is memory mapping range Q1. At this time, the memory configuration information corresponding to interface 1 and interface 2 indicates that interface 1 and interface 2 correspond to the same address range of the CXL extended memory, that is, the host nodes connected by interface 1 and interface 2 share the same memory segment of the CXL extended memory.

[0072] In another possible implementation, the memory configuration request carries memory configuration information corresponding to all interfaces, and in the memory configuration information corresponding to all interfaces, there is at least two interface corresponding memory configuration information indicating that the at least two interfaces correspond to the same address range of the CXL extended memory.

[0073] For example, the MH-SLD device 420 includes three interfaces, namely interface 1, interface 2, and interface 3. The memory configuration request carries memory configuration information corresponding to interface 1, interface 2, and interface 3. The interface identifier in the memory configuration information corresponding to interface 1 is interface 1, and the memory mapping range is memory mapping range Q1. The interface identifier in the memory configuration information corresponding to interface 2 is interface 2, and the memory mapping range is memory mapping range Q1. The interface identifier in the memory configuration information corresponding to interface 3 is interface 3, and the memory mapping range is memory mapping range Q2. At this time, the memory configuration information corresponding to interface 1 and interface 2 indicates that interface 1 and interface 2 correspond to the same address range of the CXL extended memory, and the memory configuration information corresponding to interface 3 indicates that interface 3 corresponds to an independent address range of the CXL extended memory, that is, the host node connected by interface 3 accesses and manages a memory segment of the independent CXL extended memory.

[0074] Specifically, the memory configuration information of the interface is obtained by the user in advance according to the memory allocation requirement. That is, the user presets the memory configuration information corresponding to the plurality of interfaces according to the performance of the host node that the plurality of interfaces of the MH-SLD device are possibly required to be connected, whether there is a data transmission requirement between the host nodes connected by the plurality of interfaces, and the like.

[0075] Further, the management component 410 sends a memory configuration request to the MH-SLD device 420 in response to the user's triggering operation for interface configuration. For example, the user's triggering operation for interface configuration can be that the user generates the memory configuration information corresponding to the plurality of interfaces according to the memory configuration requirement of the plurality of interfaces, and inputs the memory configuration information corresponding to the plurality of interfaces into the management component 410.

[0076] For the management component 410 to send the memory configuration request to the MH-SLD device 420:

[0077] In a possible implementation, when the MH-SLD device 420 is initialized, the management component 410 sends a memory configuration request carrying the memory configuration information corresponding to all interfaces to the MH-SLD device, so as to subsequently complete the configuration of the memory mapping range of all interfaces of the MH-SLD device 420.

[0078] In another possible implementation, during the operation of the host node connected by the interface of the MH-SLD device 410, that is, after the initialization of the MH-SLD device 410 is completed, the management component 410 can send a memory configuration request carrying the memory configuration information corresponding to at least two interfaces to the MH-SLD device 410 in response to the user's triggering operation for interface configuration, so as to subsequently complete the reconfiguration of the memory mapping range of the at least two interfaces.

[0079] S402, the MH-SLD device 420 parses the received memory configuration request to obtain the memory mapping range corresponding to the plurality of interfaces.

[0080] Specifically, the CXL controller of the MH-SLD device 420 parses the memory configuration information of the plurality of interfaces carried by the memory configuration request to obtain the memory mapping range corresponding to the plurality of interfaces.

[0081] The CXL controller uniformly identifies and manages the CXL expansion memory in the MH-SLD device through the memory mapping module, so as to respond to the user's memory configuration for different interfaces.

[0082] In a possible implementation, the CXL controller divides the CXL extended memory of the MH-SLD device based on the memory configuration information of the plurality of interfaces, so as to meet the memory configuration of different interfaces by a user. For example, the interface configuration request received by the MH-SLD device 420 carries the memory configuration information of interface A and interface B. The memory mapping range in the memory configuration information of interface A is 0-1000000000; the memory mapping range in the memory configuration information of interface B is 0-800000000. It can be learned that interface A needs to independently access the CXL extended memory with a memory mapping range of 800000001-1000000000 in the CXL extended memory, and interface A and interface B share the access to the CXL extended memory with a memory mapping range of 0-800000000 in the CXL extended memory. Therefore, the CXL extended memory with a memory mapping range of 0-1000000000 is divided into a CXL memory segment with a memory mapping range of 0-800000000 and a CXL memory segment with a memory mapping range of 800000001-1000000000, so as to meet the memory configuration of interface A and interface B by the user.

[0083] S403. The MH-SLD device 420 configures the memory mapping ranges corresponding to the plurality of interfaces based on the memory mapping ranges corresponding to the plurality of interfaces obtained by the parsing.

[0084] Specifically, after the CXL controller of the MH-SLD device 420 obtains the memory mapping ranges of the plurality of interfaces, the CXL controller sends a configuration request to a global memory mapping module (for example, the memory mapping module 300 shown in FIG. 3) of the MH-SLD device 420, and the configuration request carries the memory mapping ranges corresponding to the plurality of interfaces. The memory mapping module configures the memory mapping ranges of the plurality of interfaces based on the memory mapping ranges corresponding to the plurality of interfaces carried in the configuration request in response to the configuration request. That is, in the embodiment of the present application, the memory mapping module is configured to configure the memory mapping ranges corresponding to the plurality of interfaces according to the memory mapping ranges of the plurality of interfaces obtained by the structure manager.

[0085] In a possible implementation, the memory mapping module can be a software module or a hardware module. Generally, the memory mapping module in the MH-SLD device is a software module, for example, a memory mapping module in the form of firmware (FW).

[0086] S404. The MH-SLD device 420 stores the correspondence between the plurality of interfaces and the memory mapping ranges.

[0087] In a possible implementation, the correspondence between the plurality of interfaces and the memory mapping ranges is stored in a flash memory. Flash is a non-volatile memory technology that can retain data storage after power off, and has higher density, lower power consumption and mechanical reliability compared with random access memory (RAM).

[0088] It should be noted that, in addition to storing the correspondence between the plurality of interfaces and the memory mapping ranges in the flash memory, it can also be stored in static random access memory (SRAM), dynamic random access memory (DRAM), non-volatile random access memory (NVRAM), etc., which can retain data storage after power off.

[0089] For example, taking the MH-SLD device shown in FIG. 3 as an example, it is assumed that the memory mapping range corresponding to interface 1 is the memory mapping range of CXL memory segment Z1 and the memory mapping range of CXL memory segment Z2; the memory mapping range corresponding to interface 2 is the memory mapping range of CXL memory segment Z2; and the memory mapping range corresponding to interface 3 is the memory mapping range of CXL memory segment Z3. At this time, the correspondence between interface 1, interface 2 and interface 3 and the memory mapping range can be stored in the form of a table, as shown in Table 1.

[0090] Table 1

[0091] S405, the MH-SLD device 420 returns configuration completion information to the management component 410.

[0092] Specifically, after the MH-SLD device 420 configures the memory mapping ranges corresponding to the plurality of interfaces based on the parsed memory mapping ranges (and the MH-SLD device 420 stores the correspondence between the plurality of interfaces and the corresponding memory mapping ranges), the interface configuration of the MH-SLD device 420 is completed, and the MH-SLD device 420 returns the configuration completion information to the management component 410. After the management component 410 receives the configuration completion information, it is determined that the memory mapping range configuration of the plurality of interfaces of the MH-SLD device is completed, and the memory mapping ranges configured by at least two interfaces of the plurality of interfaces have the same memory mapping range, so that the host nodes connected by the at least two interfaces share the same memory segment of the CXL extended memory.

[0093] The memory configuration method provided in the embodiment of the application comprises: receiving a memory configuration request sent by a management component, the memory configuration request carrying memory configuration information corresponding to at least two interfaces, and there being memory configuration information corresponding to at least two interfaces in the memory configuration information corresponding to the at least two interfaces, the memory configuration information corresponding to the at least two interfaces indicating that the at least two interfaces correspond to the same address range of CXL extended memory; parsing the received memory configuration request to obtain memory mapping ranges corresponding to the at least two interfaces, and based on the memory mapping ranges of the at least two interfaces, configuring the memory mapping ranges of the at least two interfaces, and storing the correspondence between the at least two interfaces and the corresponding memory mapping ranges, completing the configuration of the memory mapping ranges of the at least two interfaces of the MH-SLD device, and returning configuration completion information to the management component to prompt the management component that the memory mapping ranges of the at least two interfaces of the MH-SLD device have been configured. The embodiment of the application can configure the memory mapping ranges of the at least two interfaces of the MH-SLD device based on the demand of a user for memory allocation based on the global memory mapping module of the MH-SLD device, and the memory mapping ranges of the at least two interfaces have an overlapping area, that is, the same memory segment of CXL extended memory can be accessed through the at least two interfaces, and the host nodes connected to the at least two interfaces can access the same CXL memory segment.

[0094] Further, since the same CXL memory segment can be shared between the at least two host nodes connected to the at least two interfaces of the MH-SLD device, when there is a demand for data transmission between the at least two host nodes, the two host nodes are connected to the at least two interfaces of the MH-SLD device sharing the same CXL memory segment, so that the two host nodes share the same CXL memory segment, and data transmission between the two host nodes can be realized based on the shared same CXL memory segment.

[0095] Specifically, assuming that the host node H1 needs to transmit data A to the host node H2, the host node H1 writes the data A into the shared same CXL memory segment, and the host node H2 reads the data A from the shared same CXL memory segment, so that the data A is transmitted from the host node H1 to the host node H2. That is, data transmission between the multiple host nodes connected to the MH-SLD device in the embodiment of the application can be realized through the shared same CXL memory segment, and cross-host node data transmission through a network is not needed, so that faster data transmission speed and lower data transmission delay can be realized.

[0096] Further, in the embodiment of the present application, in the memory configuration information corresponding to the plurality of interfaces, the memory configuration information corresponding to one or more interfaces may indicate that the one or more interfaces correspond to independent CXL extended memory segments, and therefore, configuring the memory mapping range of the one or more interfaces can enable the host node connected to the one or more interfaces of the MH-SLD device to access the independent CXL memory segments. Therefore, the memory configuration method of the MH-SLD device provided in the embodiment of the present application can enable the host nodes connected to the plurality of interfaces to access the same CXL memory segments, and can also enable the host nodes connected to the interfaces to access independent CXL memory segments.

[0097] The memory configuration method of the MH-SLD device provided in the embodiment of the present application is described in detail above in combination with FIG. 3 and FIG. 4, and the basic structure of the MH-SLD device after memory configuration is described below in combination with FIG. 5. The MH-SLD device 420 has performed the memory configuration by using the memory configuration method shown in FIG. 4.

[0098] As shown in FIG. 5, the MH-SLD device 420 includes a plurality of interfaces, a CXL controller 510, a flash memory 530, and a CXL extended memory 540. The plurality of interfaces can be two or more interfaces, for example, three interfaces, including an interface 521, an interface 522, and an interface 523. The CXL controller 510 includes the flash memory 530, and the flash memory 530 is used to store the correspondence between the three interfaces and the memory mapping range. The CXL extended memory 540 of the MH-SLD device 420 is divided into four CXL memory segments, including a CXL memory segment 541, a CXL memory segment 542, a CXL memory segment 543, and a CXL memory segment 544. After the memory configuration is completed by using the memory configuration method shown in FIG. 4, the memory mapping range corresponding to the interface 521 is the memory mapping range of the CXL memory segment 541 and the CXL memory segment 542; the memory mapping range corresponding to the interface 522 is the memory mapping range of the CXL memory segment 541, the CXL memory segment 543, and the CXL memory segment 544; and the memory mapping range corresponding to the interface 523 is the memory mapping range of the CXL memory segment 544.

[0099] As shown in FIG. 5, the host node connected with the interface 521 can independently access the CXL memory segment 542 in the MH-SLD device 420, the host node connected with the interface 521 and the host node connected with the interface 522 can share the CXL memory segment 541 in the MH-SLD device 420, the host node connected with the interface 522 can independently access the CXL memory segment 543 in the MH-SLD device 420, the host node connected with the interface 522 and the host node connected with the interface 523 can share the CXL memory segment 544 in the MH-SLD device 420, and the host node connected with the interface 523 cannot independently access the CXL extended memory of the MH-SLD device 420.

[0100] The above describes in detail the memory configuration method of the MH-SLD device provided by the embodiment of the present application in combination with FIGS. 3-5. The application process of the MH-SLD device after the memory configuration is completed is described in detail below in combination with FIG. 6.

[0101] As shown in FIG. 6, a host node connected with one interface of the MH-SLD device 420 is taken as a server 610 for example.

[0102] S601, the server 610 starts up.

[0103] The server 610 starts up, which is actually that the basic input / output system (BIOS) of the server 610 starts up.

[0104] The basic input / output system (BIOS) is a firmware solidified on the motherboard of a computer (server), which is the earliest loaded software when the server starts up. The BIOS provides the most basic hardware control and initialization functions of the server system, and is responsible for starting the system, detecting hardware, loading an operating system, and the like. The operating system (OS) is a system software, which is a software layer between application software and hardware in the server system, is responsible for managing and coordinating hardware resources and software resources in the server system, and provides an efficient working environment for users and program systems.

[0105] In a possible implementation manner, when the server 610 is connected to the MH-SLD device 420 for the first time and has not yet been in the start-up running state, the user needs to manually trigger the start-up of the server 610, and at this time, the server 610 starts up for the first time.

[0106] In another possible implementation, when the server 610 has been connected to the MH-SLD device 420 and is in a running state, and the memory mapping range corresponding to the interface to which the server 610 is currently connected has been reconfigured, the MH-SLD device 420 returns a restart request to the server 610 at the same time of returning the configuration completion information to the management component 410, or the management component 410 returns a restart request to the server 610 after receiving the configuration completion information, and the server 610 restarts in response to the restart request returned by the MH-SLD device 420.

[0107] It should be noted that in a possible implementation, the server 610, also referred to as a first server, is a server connected to any one of at least two interfaces of the MH-SLD device sharing the same address range of the CXL extended memory (there is an overlapping area in the corresponding memory mapping range).

[0108] S602, the MH-SLD device 420 reads the correspondence between the plurality of interfaces and the memory mapping range in the storage in response to the startup operation of the server 610.

[0109] In a possible implementation, the correspondence between the interface to which the server 610 is connected and the memory mapping range corresponding to the interface is read in the storage, or the correspondence between all interfaces of the MH-SLD device 420 and the memory mapping range is read in the storage.

[0110] S603, the MH-SLD device 420 reports device information to the server 610.

[0111] Specifically, the MH-SLD device 420 reports the device information to the server 610 through an ACPI interface.

[0112] ACPI (Advanced Configuration and Power Interface) is a standard interface for communication between an operating system and hardware. ACPI defines how an operating system controls interaction with system hardware to achieve functions such as power management, hot plug device management, device configuration, etc.

[0113] The device information includes a unique identifier of the MH-SLD device 420, a device type, a device state, resource allocation, and a correspondence between an interface and a memory mapping range, etc.

[0114] S604, the server 610 enumerates the MH-SLD device 420 during the startup process.

[0115] Wherein, enumeration refers to the process of listing and identifying a series of objects or elements in a system. In the field of computer, enumeration is often used to identify and access hardware devices, files, processes, etc. in the system.

[0116] Specifically, the server 610 generates a device enumeration table during the startup process, and the BIOS enumerates the hardware devices in the system based on the device enumeration table, including the MH-SLD device 420. Further, after enumerating the hardware devices in the system, i.e. enumerating all hardware devices connected to the server 610 (including the MH-SLD device 420), the operating system of the server 610 loads the corresponding driver program for the hardware device, and when the corresponding driver program for the hardware device is successfully loaded, the operating system of the server 610 initializes the hardware device, allocates resources and configuration parameters for the hardware device, so that the hardware device can work normally and be used by the operating system of the server 610.

[0117] In one possible implementation, the device enumeration table includes a SART table and a CEDT table. Specifically, the SART table and the CEDT table are generated during the startup process of the server 610, and the BIOS enumerates the hardware devices in the system of the server 610 according to the device information in the SART table and the CEDT table.

[0118] SART (System Activity Reporter Tool) is a tool defined by ACPI specification, which is used to detect and record system activities. For example, SART can record various activity information of the system during running, including processor state, memory usage, device state and system time, etc.

[0119] CEDT (Common Event Diagnostic Tool) is also a tool defined by ACPI specification, which is used to analyze and diagnose system events. For example, CEDT can capture and record system events, including hardware failure, error and exception events, etc.

[0120] S605, after the server 610 is powered on and completes, the interface corresponding to the CXL memory segment of the connected MH-SLD device 420 can be normally used.

[0121] Specifically, after the server 610 is powered on and completes, based on the memory mapping range corresponding to the interface of the connected MH-SLD device 420, the CXL memory segment corresponding to the interface is determined, and the server 610 can perform read operation or write operation on the CXL memory segment corresponding to the interface.

[0122] Further, in a possible implementation, the server 610 can display the correspondence between the interfaces and the memory mapping ranges reported by the MH-SLD device 420. The correspondence between the interfaces and the memory mapping ranges can be the correspondence between all interfaces and memory mapping ranges of the MH-SLD device 420, or the correspondence between the interfaces and the memory mapping ranges of the MH-SLD device 420 connected to the server 610, which is not limited in the embodiments of the present application.

[0123] Through S601-S605, the host node connected to the MH-SLD device 420 can normally use the CXL memory segment corresponding to the interface after the memory configuration is completed.

[0124] Further, after the server 610 is enumerated and starts up, when the server 610 accesses the CXL extended memory of the MH-SLD device 420, the server 610 sends an access request to the MH-SLD device 420, the access request includes a read request or a write request, and the access request carries address information of the access target; the CXL controller in the MH-SLD device 420 translates the address information to obtain a CXL extended memory address corresponding to the address information; the CXL controller judges whether the CXL extended memory address region belongs to the CXL memory segment accessible by the interface connected to the server 610 according to the correspondence between the interfaces and the memory mapping ranges stored in the flash memory, and if yes, executes the corresponding access request, and if not, determines that the access request is invalid and makes a corresponding error response. Therefore, the correspondence between the interfaces and the memory mapping ranges stored in the flash memory of the CXL controller can ensure that the host node connected to the interface of the MH-SLD device can efficiently and safely access the CXL memory segment corresponding to the interface, thereby realizing efficient data interaction between the MH-SLD device and the host node.

[0125] Embodiment Two:

[0126] The following will be described in detail in combination with FIG. 7.

[0127] The memory configuration device provided in the embodiments of the present application is applied to the MH-SLD device, and specifically applied to the CXL controller of the MH-SLD device. As shown in FIG. 7, the memory configuration device provided in the embodiments of the present application includes the following modules:

[0128] The receiving module 701 is configured to receive a memory configuration request. The memory configuration request includes memory configuration information corresponding to at least two interfaces, and the memory configuration information corresponding to the at least two interfaces represents the same address range of the CXL extended memory corresponding to the at least two interfaces.

[0129] The parsing module 702 is configured to parse the memory configuration request to obtain memory mapping ranges corresponding to the at least two interfaces.

[0130] The configuration module 703 is configured to configure the memory mapping ranges corresponding to the at least two interfaces based on the memory mapping ranges corresponding to the at least two interfaces.

[0131] In a possible implementation, the parsing module 702 is specifically configured to configure the memory mapping ranges corresponding to the at least two interfaces by a memory mapping module running on a CXL controller of a computing high-speed interconnection link of the MH-SLD device based on the memory mapping ranges corresponding to the at least two interfaces; and the memory mapping module corresponds to all CXL extended memories of the MH-SLD device.

[0132] In a possible implementation, the memory configuration apparatus further includes a division module configured to perform division processing on the CXL extended memories of the MH-SLD device based on the memory mapping ranges corresponding to the at least two interfaces, so as to meet the memory configuration of the at least two interfaces.

[0133] In a possible implementation, the memory configuration apparatus further includes a completion returning module configured to return configuration completion information to the management component to inform the management component that the memory mapping range configuration of the at least two interfaces in the MH-SLD device is completed.

[0134] In a possible implementation, the memory configuration apparatus further includes a storage module configured to store the correspondence between the at least two interfaces and the memory mapping ranges, so as to subsequently send the correspondence between the at least two interfaces and the memory mapping ranges to host nodes connected with the at least two interfaces, and facilitate the enumeration of the MH-SLD device by the host nodes.

[0135] In a possible implementation, the memory configuration apparatus further includes a reading module and a reporting module. The reading module is configured to read the stored correspondence between the at least two interfaces and the memory mapping ranges in response to a start-up operation of a first server, the first server being a server connected with any one of the at least two interfaces; and the reporting module is configured to report device information to the first server, so as to facilitate the enumeration of the MH-SLD device by the first server during the start-up process; and the device information includes the correspondence between the at least two interfaces and the memory mapping ranges.

[0136] The memory configuration apparatus provided in the embodiment of the present application comprises: a receiving module 701 configured to receive a memory configuration request; the memory configuration request comprises memory configuration information corresponding to at least two interfaces, and the memory configuration information corresponding to the at least two interfaces represents address ranges of the same CXL extended memory corresponding to the at least two interfaces; a parsing module 702 configured to parse the memory configuration request to obtain memory mapping ranges corresponding to the at least two interfaces; and a configuration module 703 configured to configure the memory mapping ranges corresponding to the at least two interfaces based on the memory mapping ranges corresponding to the at least two interfaces. The memory mapping ranges of the at least two interfaces of the MH-SLD device are configured, and the memory mapping ranges of the at least two interfaces overlap, that is, the same memory segment of the CXL extended memory can be accessed through the at least two interfaces, and the host nodes connected to the at least two interfaces can access the same CXL memory segment.

[0137] Further, since the same CXL memory segment can be shared between the at least two host nodes connected to the at least two interfaces of the MH-SLD device, when there is a demand for data transmission between the at least two host nodes, the two host nodes are connected to the at least two interfaces of the MH-SLD device sharing the same CXL memory segment, so that the two host nodes share the same CXL memory segment, and the data transmission between the two host nodes can be implemented based on the shared same CXL memory segment.

[0138] In addition, the embodiment of the present application further provides a multi-interface single-logic MH-SLD device, comprising at least two interfaces, a computing express link (CXL) controller connected to the at least two interfaces, and a memory connected to the CXL controller. The at least two interfaces are configured to connect host nodes; the memory comprises CXL extended memory; and the CXL controller is configured to execute the memory configuration method in the above embodiment.

[0139] Specifically, the CXL controller is configured to receive and parse a memory configuration request, and configure memory mapping ranges corresponding to the at least two interfaces based on the memory mapping ranges corresponding to the at least two interfaces obtained by parsing; wherein the memory configuration request comprises memory configuration information corresponding to the at least two interfaces, and the memory configuration information corresponding to the at least two interfaces represents address ranges of the same CXL extended memory corresponding to the at least two interfaces.

[0140] The embodiment of the present application further provides a server, which comprises a processor and a memory. The processor is connected to the memory, and the memory stores computer execution instructions. When the processor executes the computer execution instructions, the steps performed by the server in the memory configuration method in the above embodiment are implemented.

[0141] Although the application has been described in connection with the embodiments thereof with reference to the various drawings, it will be understood that other variations and modifications of the details, and specific examples can be resorted to by those skilled in the art without departing from the spirit and scope of the application. In its broadest form, the application is directed to all new and useful processes, machines, articles of manufacture, compositions of matter, and methods that fall within the scope of the claims. The specification and drawings are, accordingly, to be regarded as illustrative rather than restrictive. It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application cover the modifications and variations of this application provided they come within the scope of the appended claims and their equivalents.

[0142] Although the application has been described in connection with the embodiments thereof with reference to the various drawings, it will be understood that other variations and modifications of the details, and specific examples can be resorted to by those skilled in the art without departing from the spirit and scope of the application. In its broadest form, the application is directed to all new and useful processes, machines, articles of manufacture, compositions of matter, and methods that fall within the scope of the claims. The specification and drawings are, accordingly, to be regarded as illustrative rather than restrictive. It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application cover the modifications and variations of this application provided they come within the scope of the appended claims and their equivalents.

Claims

1. A memory configuration method, characterized by, The method is applied to a multi-interface single-logic MH-SLD device, and the method comprises the following steps: receiving a memory configuration request; the memory configuration request comprises memory configuration information corresponding to at least two interfaces, and the memory configuration information corresponding to the at least two interfaces represents address ranges of the same CXL extended memory corresponding to the at least two interfaces; parsing the memory configuration request to obtain memory mapping ranges corresponding to the at least two interfaces; configuring the memory mapping ranges corresponding to the at least two interfaces based on the memory mapping ranges corresponding to the at least two interfaces.

2. The method of claim 1, wherein, The step of configuring the memory mapping ranges corresponding to the at least two interfaces based on the memory mapping ranges corresponding to the at least two interfaces comprises the following steps: configuring the memory mapping ranges corresponding to the at least two interfaces by a memory mapping module running on a CXL controller of a computing high-speed interconnection link of the MH-SLD device based on the memory mapping ranges corresponding to the at least two interfaces; the memory mapping module corresponds to all CXL extended memories of the MH-SLD device.

3. The method of claim 1, wherein, Before the step of configuring the memory mapping ranges corresponding to the at least two interfaces based on the memory mapping ranges corresponding to the at least two interfaces, the method further comprises the following step: dividing the CXL extended memories of the MH-SLD device based on the memory mapping ranges corresponding to the at least two interfaces.

4. The method of claim 1, wherein, After the step of configuring the memory mapping ranges corresponding to the at least two interfaces based on the memory mapping ranges corresponding to the at least two interfaces, the method further comprises the following step: returning configuration completion information to a management component to inform the management component that the memory mapping range configuration of the at least two interfaces in the MH-SLD device is completed.

5. The method of claim 1, wherein, After the step of configuring the memory mapping ranges corresponding to the at least two interfaces based on the memory mapping ranges corresponding to the at least two interfaces, the method further comprises the following step: storing the correspondence between the at least two interfaces and the memory mapping ranges.

6. The method of claim 5, wherein, The method further comprises the following steps: reading the stored correspondence between the at least two interfaces and the memory mapping ranges in response to a start-up operation of a first server; the first server is a server connected to any one of the at least two interfaces; reporting device information to the first server to facilitate the first server to implement enumeration of the MH-SLD device in a start-up process; the device information comprises the correspondence between the at least two interfaces and the memory mapping ranges.

7. The method of claim 6, wherein, The start-up operation of the first server comprises that the first server performs a start-up operation in response to a trigger operation of a user on the first server; or, when the MH-SLD device completes the configuration of the memory mapping ranges corresponding to the at least two interfaces, returning a restart request to the first server to facilitate the first server to perform a start-up operation in response to the restart request.

8. The method of claim 1, wherein, The memory configuration request is sent by a management component to the MH-SLD in response to a trigger operation of a user on the configuration of the at least two interfaces.

9. A multi-interface single-logic (MH-SLD) device, comprising: The memory includes a CXL extended memory. The at least two interfaces are configured to be connected to a host node. The CXL controller is configured to receive and parse a memory configuration request, and configure a memory mapping range corresponding to the at least two interfaces based on the parsed memory mapping range corresponding to the at least two interfaces; wherein the memory configuration request includes memory configuration information corresponding to the at least two interfaces, and the memory configuration information corresponding to the at least two interfaces represents an address range of the same CXL extended memory corresponding to the at least two interfaces. The CXL controller includes a flash memory.

10. The MH-SLD device of claim 9, wherein, The flash memory is configured to store a correspondence between the at least two interfaces and the memory mapping range. ​

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